booke_machdep.c revision 1.4.2.4
1 1.4.2.2 rmind /*- 2 1.4.2.2 rmind * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 3 1.4.2.2 rmind * All rights reserved. 4 1.4.2.2 rmind * 5 1.4.2.2 rmind * This code is derived from software contributed to The NetBSD Foundation 6 1.4.2.2 rmind * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 7 1.4.2.2 rmind * Agency and which was developed by Matt Thomas of 3am Software Foundry. 8 1.4.2.2 rmind * 9 1.4.2.2 rmind * This material is based upon work supported by the Defense Advanced Research 10 1.4.2.2 rmind * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 11 1.4.2.2 rmind * Contract No. N66001-09-C-2073. 12 1.4.2.2 rmind * Approved for Public Release, Distribution Unlimited 13 1.4.2.2 rmind * 14 1.4.2.2 rmind * Redistribution and use in source and binary forms, with or without 15 1.4.2.2 rmind * modification, are permitted provided that the following conditions 16 1.4.2.2 rmind * are met: 17 1.4.2.2 rmind * 1. Redistributions of source code must retain the above copyright 18 1.4.2.2 rmind * notice, this list of conditions and the following disclaimer. 19 1.4.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 20 1.4.2.2 rmind * notice, this list of conditions and the following disclaimer in the 21 1.4.2.2 rmind * documentation and/or other materials provided with the distribution. 22 1.4.2.2 rmind * 23 1.4.2.2 rmind * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 1.4.2.2 rmind * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 1.4.2.2 rmind * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 1.4.2.2 rmind * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 1.4.2.2 rmind * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 1.4.2.2 rmind * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 1.4.2.2 rmind * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 1.4.2.2 rmind * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 1.4.2.2 rmind * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 1.4.2.2 rmind * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 1.4.2.2 rmind * POSSIBILITY OF SUCH DAMAGE. 34 1.4.2.2 rmind */ 35 1.4.2.2 rmind 36 1.4.2.2 rmind #define __INTR_PRIVATE 37 1.4.2.2 rmind #define _POWERPC_BUS_DMA_PRIVATE 38 1.4.2.2 rmind 39 1.4.2.2 rmind #include <sys/cdefs.h> 40 1.4.2.2 rmind 41 1.4.2.2 rmind #include <sys/param.h> 42 1.4.2.2 rmind #include <sys/cpu.h> 43 1.4.2.2 rmind #include <sys/device.h> 44 1.4.2.2 rmind #include <sys/intr.h> 45 1.4.2.2 rmind #include <sys/mount.h> 46 1.4.2.2 rmind #include <sys/msgbuf.h> 47 1.4.2.2 rmind #include <sys/kernel.h> 48 1.4.2.2 rmind #include <sys/reboot.h> 49 1.4.2.2 rmind #include <sys/bus.h> 50 1.4.2.2 rmind 51 1.4.2.2 rmind #include <uvm/uvm_extern.h> 52 1.4.2.2 rmind 53 1.4.2.2 rmind #include <powerpc/spr.h> 54 1.4.2.2 rmind #include <powerpc/booke/spr.h> 55 1.4.2.2 rmind #include <powerpc/booke/cpuvar.h> 56 1.4.2.2 rmind 57 1.4.2.2 rmind /* 58 1.4.2.2 rmind * Global variables used here and there 59 1.4.2.2 rmind */ 60 1.4.2.2 rmind paddr_t msgbuf_paddr; 61 1.4.2.2 rmind psize_t pmemsize; 62 1.4.2.2 rmind struct vm_map *phys_map; 63 1.4.2.2 rmind 64 1.4.2.2 rmind static bus_addr_t booke_dma_phys_to_bus_mem(bus_dma_tag_t, bus_addr_t); 65 1.4.2.2 rmind static bus_addr_t booke_dma_bus_mem_to_phys(bus_dma_tag_t, bus_addr_t); 66 1.4.2.2 rmind 67 1.4.2.2 rmind 68 1.4.2.2 rmind struct powerpc_bus_dma_tag booke_bus_dma_tag = { 69 1.4.2.2 rmind ._dmamap_create = _bus_dmamap_create, 70 1.4.2.2 rmind ._dmamap_destroy = _bus_dmamap_destroy, 71 1.4.2.2 rmind ._dmamap_load = _bus_dmamap_load, 72 1.4.2.2 rmind ._dmamap_load_mbuf = _bus_dmamap_load_mbuf, 73 1.4.2.2 rmind ._dmamap_load_uio = _bus_dmamap_load_uio, 74 1.4.2.2 rmind ._dmamap_load_raw = _bus_dmamap_load_raw, 75 1.4.2.2 rmind ._dmamap_unload = _bus_dmamap_unload, 76 1.4.2.2 rmind ._dmamap_sync = _bus_dmamap_sync, 77 1.4.2.2 rmind ._dmamem_alloc = _bus_dmamem_alloc, 78 1.4.2.2 rmind ._dmamem_free = _bus_dmamem_free, 79 1.4.2.2 rmind ._dmamem_map = _bus_dmamem_map, 80 1.4.2.2 rmind ._dmamem_unmap = _bus_dmamem_unmap, 81 1.4.2.2 rmind ._dmamem_mmap = _bus_dmamem_mmap, 82 1.4.2.2 rmind ._dma_phys_to_bus_mem = booke_dma_phys_to_bus_mem, 83 1.4.2.2 rmind ._dma_bus_mem_to_phys = booke_dma_bus_mem_to_phys, 84 1.4.2.2 rmind }; 85 1.4.2.2 rmind 86 1.4.2.2 rmind static bus_addr_t 87 1.4.2.2 rmind booke_dma_phys_to_bus_mem(bus_dma_tag_t t, bus_addr_t a) 88 1.4.2.2 rmind { 89 1.4.2.2 rmind return a; 90 1.4.2.2 rmind } 91 1.4.2.2 rmind 92 1.4.2.2 rmind static bus_addr_t 93 1.4.2.2 rmind booke_dma_bus_mem_to_phys(bus_dma_tag_t t, bus_addr_t a) 94 1.4.2.2 rmind { 95 1.4.2.2 rmind return a; 96 1.4.2.2 rmind } 97 1.4.2.2 rmind 98 1.4.2.2 rmind static int 99 1.4.2.2 rmind null_splraise(int ipl) 100 1.4.2.2 rmind { 101 1.4.2.2 rmind int cpl = curcpu()->ci_cpl; 102 1.4.2.2 rmind curcpu()->ci_cpl = ipl; 103 1.4.2.2 rmind return cpl; 104 1.4.2.2 rmind } 105 1.4.2.2 rmind 106 1.4.2.2 rmind static void 107 1.4.2.2 rmind null_splx(int ipl) 108 1.4.2.2 rmind { 109 1.4.2.2 rmind curcpu()->ci_cpl = ipl; 110 1.4.2.2 rmind } 111 1.4.2.2 rmind 112 1.4.2.2 rmind static const struct intrsw null_intrsw = { 113 1.4.2.2 rmind .intrsw_splraise = null_splraise, 114 1.4.2.2 rmind .intrsw_splx = null_splx, 115 1.4.2.2 rmind }; 116 1.4.2.2 rmind 117 1.4.2.2 rmind const struct intrsw *powerpc_intrsw = &null_intrsw; 118 1.4.2.2 rmind struct cpu_md_ops cpu_md_ops; 119 1.4.2.2 rmind 120 1.4.2.4 rmind struct cpu_softc cpu_softc[] = { 121 1.4.2.2 rmind [0] = { 122 1.4.2.4 rmind .cpu_ci = &cpu_info[0], 123 1.4.2.4 rmind }, 124 1.4.2.4 rmind #ifdef MULTIPROCESSOR 125 1.4.2.4 rmind [CPU_MAXNUM-1] = { 126 1.4.2.4 rmind .cpu_ci = &cpu_info[CPU_MAXNUM-1], 127 1.4.2.2 rmind }, 128 1.4.2.4 rmind #endif 129 1.4.2.2 rmind }; 130 1.4.2.4 rmind struct cpu_info cpu_info[] = { 131 1.4.2.2 rmind [0] = { 132 1.4.2.2 rmind .ci_curlwp = &lwp0, 133 1.4.2.2 rmind .ci_tlb_info = &pmap_tlb0_info, 134 1.4.2.4 rmind .ci_softc = &cpu_softc[0], 135 1.4.2.4 rmind .ci_cpl = IPL_HIGH, 136 1.4.2.4 rmind }, 137 1.4.2.4 rmind #ifdef MULTIPROCESSOR 138 1.4.2.4 rmind [CPU_MAXNUM-1] = { 139 1.4.2.4 rmind .ci_curlwp = NULL, 140 1.4.2.4 rmind .ci_tlb_info = &pmap_tlb0_info, 141 1.4.2.4 rmind .ci_softc = &cpu_softc[CPU_MAXNUM-1], 142 1.4.2.2 rmind .ci_cpl = IPL_HIGH, 143 1.4.2.2 rmind }, 144 1.4.2.4 rmind #endif 145 1.4.2.2 rmind }; 146 1.4.2.2 rmind 147 1.4.2.2 rmind /* 148 1.4.2.2 rmind * This should probably be in autoconf! XXX 149 1.4.2.2 rmind */ 150 1.4.2.2 rmind char cpu_model[80]; 151 1.4.2.2 rmind char machine[] = MACHINE; /* from <machine/param.h> */ 152 1.4.2.2 rmind char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 153 1.4.2.2 rmind 154 1.4.2.2 rmind char bootpath[256]; 155 1.4.2.2 rmind 156 1.4.2.2 rmind #if NKSYMS || defined(DDB) || defined(MODULAR) 157 1.4.2.2 rmind void *startsym, *endsym; 158 1.4.2.2 rmind #endif 159 1.4.2.2 rmind 160 1.4.2.2 rmind int fake_mapiodev = 1; 161 1.4.2.2 rmind 162 1.4.2.2 rmind void lcsplx(int); 163 1.4.2.2 rmind 164 1.4.2.2 rmind void 165 1.4.2.2 rmind booke_cpu_startup(const char *model) 166 1.4.2.2 rmind { 167 1.4.2.2 rmind vaddr_t minaddr, maxaddr; 168 1.4.2.2 rmind char pbuf[9]; 169 1.4.2.2 rmind 170 1.4.2.2 rmind strlcpy(cpu_model, model, sizeof(cpu_model)); 171 1.4.2.2 rmind 172 1.4.2.2 rmind printf("%s%s", copyright, version); 173 1.4.2.2 rmind 174 1.4.2.3 rmind format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 175 1.4.2.2 rmind printf("total memory = %s\n", pbuf); 176 1.4.2.2 rmind 177 1.4.2.2 rmind minaddr = 0; 178 1.4.2.2 rmind /* 179 1.4.2.2 rmind * Allocate a submap for physio 180 1.4.2.2 rmind */ 181 1.4.2.2 rmind phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 182 1.4.2.2 rmind VM_PHYS_SIZE, 0, false, NULL); 183 1.4.2.2 rmind 184 1.4.2.2 rmind /* 185 1.4.2.2 rmind * No need to allocate an mbuf cluster submap. Mbuf clusters 186 1.4.2.2 rmind * are allocated via the pool allocator, and we use direct-mapped 187 1.4.2.2 rmind * pool pages. 188 1.4.2.2 rmind */ 189 1.4.2.2 rmind 190 1.4.2.2 rmind format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 191 1.4.2.2 rmind printf("avail memory = %s\n", pbuf); 192 1.4.2.2 rmind 193 1.4.2.2 rmind /* 194 1.4.2.2 rmind * Set up the board properties database. 195 1.4.2.2 rmind */ 196 1.4.2.2 rmind board_info_init(); 197 1.4.2.2 rmind 198 1.4.2.2 rmind /* 199 1.4.2.2 rmind * Now that we have VM, malloc()s are OK in bus_space. 200 1.4.2.2 rmind */ 201 1.4.2.2 rmind bus_space_mallocok(); 202 1.4.2.2 rmind fake_mapiodev = 0; 203 1.4.2.2 rmind } 204 1.4.2.2 rmind 205 1.4.2.2 rmind static void 206 1.4.2.2 rmind dumpsys(void) 207 1.4.2.2 rmind { 208 1.4.2.2 rmind 209 1.4.2.2 rmind printf("dumpsys: TBD\n"); 210 1.4.2.2 rmind } 211 1.4.2.2 rmind 212 1.4.2.2 rmind /* 213 1.4.2.2 rmind * Halt or reboot the machine after syncing/dumping according to howto. 214 1.4.2.2 rmind */ 215 1.4.2.2 rmind void 216 1.4.2.2 rmind cpu_reboot(int howto, char *what) 217 1.4.2.2 rmind { 218 1.4.2.2 rmind static int syncing; 219 1.4.2.2 rmind static char str[256]; 220 1.4.2.2 rmind char *ap = str, *ap1 = ap; 221 1.4.2.2 rmind 222 1.4.2.2 rmind boothowto = howto; 223 1.4.2.2 rmind if (!cold && !(howto & RB_NOSYNC) && !syncing) { 224 1.4.2.2 rmind syncing = 1; 225 1.4.2.2 rmind vfs_shutdown(); /* sync */ 226 1.4.2.2 rmind resettodr(); /* set wall clock */ 227 1.4.2.2 rmind } 228 1.4.2.2 rmind 229 1.4.2.2 rmind splhigh(); 230 1.4.2.2 rmind 231 1.4.2.2 rmind if (!cold && (howto & RB_DUMP)) 232 1.4.2.2 rmind dumpsys(); 233 1.4.2.2 rmind 234 1.4.2.2 rmind doshutdownhooks(); 235 1.4.2.2 rmind 236 1.4.2.2 rmind pmf_system_shutdown(boothowto); 237 1.4.2.2 rmind 238 1.4.2.2 rmind if ((howto & RB_POWERDOWN) == RB_POWERDOWN) { 239 1.4.2.2 rmind /* Power off here if we know how...*/ 240 1.4.2.2 rmind } 241 1.4.2.2 rmind 242 1.4.2.2 rmind if (howto & RB_HALT) { 243 1.4.2.2 rmind printf("halted\n\n"); 244 1.4.2.2 rmind 245 1.4.2.2 rmind goto reboot; /* XXX for now... */ 246 1.4.2.2 rmind 247 1.4.2.2 rmind #ifdef DDB 248 1.4.2.2 rmind printf("dropping to debugger\n"); 249 1.4.2.2 rmind while(1) 250 1.4.2.2 rmind Debugger(); 251 1.4.2.2 rmind #endif 252 1.4.2.2 rmind } 253 1.4.2.2 rmind 254 1.4.2.2 rmind printf("rebooting\n\n"); 255 1.4.2.2 rmind if (what && *what) { 256 1.4.2.2 rmind if (strlen(what) > sizeof str - 5) 257 1.4.2.2 rmind printf("boot string too large, ignored\n"); 258 1.4.2.2 rmind else { 259 1.4.2.2 rmind strcpy(str, what); 260 1.4.2.2 rmind ap1 = ap = str + strlen(str); 261 1.4.2.2 rmind *ap++ = ' '; 262 1.4.2.2 rmind } 263 1.4.2.2 rmind } 264 1.4.2.2 rmind *ap++ = '-'; 265 1.4.2.2 rmind if (howto & RB_SINGLE) 266 1.4.2.2 rmind *ap++ = 's'; 267 1.4.2.2 rmind if (howto & RB_KDB) 268 1.4.2.2 rmind *ap++ = 'd'; 269 1.4.2.2 rmind *ap++ = 0; 270 1.4.2.2 rmind if (ap[-2] == '-') 271 1.4.2.2 rmind *ap1 = 0; 272 1.4.2.2 rmind 273 1.4.2.2 rmind /* flush cache for msgbuf */ 274 1.4.2.2 rmind dcache_wb(msgbuf_paddr, round_page(MSGBUFSIZE)); 275 1.4.2.2 rmind 276 1.4.2.2 rmind reboot: 277 1.4.2.2 rmind __asm volatile("msync; isync"); 278 1.4.2.2 rmind (*cpu_md_ops.md_cpu_reset)(); 279 1.4.2.2 rmind 280 1.4.2.2 rmind printf("%s: md_cpu_reset() failed!\n", __func__); 281 1.4.2.2 rmind #ifdef DDB 282 1.4.2.2 rmind for (;;) 283 1.4.2.2 rmind Debugger(); 284 1.4.2.2 rmind #else 285 1.4.2.2 rmind for (;;) 286 1.4.2.2 rmind /* nothing */; 287 1.4.2.2 rmind #endif 288 1.4.2.2 rmind } 289 1.4.2.2 rmind void 290 1.4.2.2 rmind lcsplx(int spl) 291 1.4.2.2 rmind { 292 1.4.2.2 rmind splx(spl); 293 1.4.2.2 rmind } 294 1.4.2.2 rmind 295 1.4.2.2 rmind /* 296 1.4.2.2 rmind * mapiodev: 297 1.4.2.2 rmind * 298 1.4.2.2 rmind * Allocate vm space and mapin the I/O address. Use reserved TLB 299 1.4.2.2 rmind * mapping if one is found. 300 1.4.2.2 rmind */ 301 1.4.2.2 rmind void * 302 1.4.2.2 rmind mapiodev(paddr_t pa, psize_t len) 303 1.4.2.2 rmind { 304 1.4.2.2 rmind const vsize_t off = pa & PAGE_MASK; 305 1.4.2.2 rmind 306 1.4.2.2 rmind /* 307 1.4.2.2 rmind * See if we have reserved TLB entry for the pa. This needs to be 308 1.4.2.2 rmind * true for console as we can't use uvm during early bootstrap. 309 1.4.2.2 rmind */ 310 1.4.2.2 rmind void * const p = tlb_mapiodev(pa, len); 311 1.4.2.2 rmind if (p != NULL) 312 1.4.2.2 rmind return p; 313 1.4.2.2 rmind 314 1.4.2.2 rmind if (fake_mapiodev) 315 1.4.2.2 rmind panic("mapiodev: no TLB entry reserved for %llx+%llx", 316 1.4.2.2 rmind (long long)pa, (long long)len); 317 1.4.2.2 rmind 318 1.4.2.2 rmind pa = trunc_page(pa); 319 1.4.2.2 rmind len = round_page(off + len); 320 1.4.2.2 rmind vaddr_t va = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 321 1.4.2.2 rmind 322 1.4.2.2 rmind if (va == 0) 323 1.4.2.2 rmind return NULL; 324 1.4.2.2 rmind 325 1.4.2.2 rmind for (va += len, pa += len; len > 0; len -= PAGE_SIZE) { 326 1.4.2.2 rmind va -= PAGE_SIZE; 327 1.4.2.2 rmind pa -= PAGE_SIZE; 328 1.4.2.2 rmind pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE, 329 1.4.2.2 rmind PMAP_NOCACHE); 330 1.4.2.2 rmind } 331 1.4.2.2 rmind pmap_update(pmap_kernel()); 332 1.4.2.2 rmind return (void *)(va + off); 333 1.4.2.2 rmind } 334 1.4.2.2 rmind 335 1.4.2.2 rmind void 336 1.4.2.2 rmind unmapiodev(vaddr_t va, vsize_t len) 337 1.4.2.2 rmind { 338 1.4.2.2 rmind /* Nothing to do for reserved (ie. not uvm_km_alloc'd) mappings. */ 339 1.4.2.2 rmind if (va < VM_MIN_KERNEL_ADDRESS || va > VM_MAX_KERNEL_ADDRESS) { 340 1.4.2.2 rmind tlb_unmapiodev(va, len); 341 1.4.2.2 rmind return; 342 1.4.2.2 rmind } 343 1.4.2.2 rmind 344 1.4.2.2 rmind len = round_page((va & PAGE_MASK) + len); 345 1.4.2.2 rmind va = trunc_page(va); 346 1.4.2.2 rmind 347 1.4.2.2 rmind pmap_kremove(va, len); 348 1.4.2.2 rmind uvm_km_free(kernel_map, va, len, UVM_KMF_VAONLY); 349 1.4.2.2 rmind } 350 1.4.2.2 rmind 351 1.4.2.2 rmind void 352 1.4.2.2 rmind cpu_evcnt_attach(struct cpu_info *ci) 353 1.4.2.2 rmind { 354 1.4.2.2 rmind struct cpu_softc * const cpu = ci->ci_softc; 355 1.4.2.2 rmind const char * const xname = device_xname(ci->ci_dev); 356 1.4.2.2 rmind 357 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 358 1.4.2.2 rmind NULL, xname, "clock"); 359 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&cpu->cpu_ev_late_clock, EVCNT_TYPE_INTR, 360 1.4.2.2 rmind NULL, xname, "late clock"); 361 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&cpu->cpu_ev_exec_trap_sync, EVCNT_TYPE_TRAP, 362 1.4.2.2 rmind NULL, xname, "exec pages synced (trap)"); 363 1.4.2.2 rmind #ifndef __HAVE_FAST_SOFTINTS 364 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 365 1.4.2.2 rmind NULL, xname, "soft clock"); 366 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 367 1.4.2.2 rmind NULL, xname, "soft net"); 368 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 369 1.4.2.2 rmind NULL, xname, "soft serial"); 370 1.4.2.2 rmind #endif 371 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 372 1.4.2.2 rmind NULL, xname, "traps"); 373 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 374 1.4.2.2 rmind &ci->ci_ev_traps, xname, "kernel DSI traps"); 375 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 376 1.4.2.2 rmind &ci->ci_ev_traps, xname, "user DSI traps"); 377 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 378 1.4.2.2 rmind &ci->ci_ev_udsi, xname, "user DSI failures"); 379 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 380 1.4.2.2 rmind &ci->ci_ev_traps, xname, "kernel ISI traps"); 381 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 382 1.4.2.2 rmind &ci->ci_ev_traps, xname, "user ISI traps"); 383 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 384 1.4.2.2 rmind &ci->ci_ev_isi, xname, "user ISI failures"); 385 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 386 1.4.2.2 rmind &ci->ci_ev_traps, xname, "system call traps"); 387 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 388 1.4.2.2 rmind &ci->ci_ev_traps, xname, "PGM traps"); 389 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_debug, EVCNT_TYPE_TRAP, 390 1.4.2.2 rmind &ci->ci_ev_traps, xname, "debug traps"); 391 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 392 1.4.2.2 rmind &ci->ci_ev_traps, xname, "FPU unavailable traps"); 393 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_fpusw, EVCNT_TYPE_MISC, 394 1.4.2.2 rmind &ci->ci_ev_fpu, xname, "FPU context switches"); 395 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 396 1.4.2.2 rmind &ci->ci_ev_traps, xname, "user alignment traps"); 397 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 398 1.4.2.2 rmind &ci->ci_ev_ali, xname, "user alignment traps"); 399 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 400 1.4.2.2 rmind &ci->ci_ev_umchk, xname, "user MCHK failures"); 401 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 402 1.4.2.2 rmind &ci->ci_ev_traps, xname, "SPE unavailable"); 403 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_vecsw, EVCNT_TYPE_MISC, 404 1.4.2.2 rmind &ci->ci_ev_vec, xname, "SPE context switches"); 405 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 406 1.4.2.2 rmind NULL, xname, "IPIs"); 407 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_tlbmiss_soft, EVCNT_TYPE_TRAP, 408 1.4.2.2 rmind &ci->ci_ev_traps, xname, "soft tlb misses"); 409 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_dtlbmiss_hard, EVCNT_TYPE_TRAP, 410 1.4.2.2 rmind &ci->ci_ev_traps, xname, "data tlb misses"); 411 1.4.2.2 rmind evcnt_attach_dynamic_nozero(&ci->ci_ev_itlbmiss_hard, EVCNT_TYPE_TRAP, 412 1.4.2.2 rmind &ci->ci_ev_traps, xname, "inst tlb misses"); 413 1.4.2.2 rmind } 414 1.4.2.2 rmind 415 1.4.2.2 rmind uint32_t 416 1.4.2.2 rmind cpu_read_4(bus_addr_t a) 417 1.4.2.2 rmind { 418 1.4.2.2 rmind struct cpu_softc * const cpu = curcpu()->ci_softc; 419 1.4.2.2 rmind // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 420 1.4.2.2 rmind return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, a); 421 1.4.2.2 rmind } 422 1.4.2.2 rmind 423 1.4.2.2 rmind uint8_t 424 1.4.2.2 rmind cpu_read_1(bus_addr_t a) 425 1.4.2.2 rmind { 426 1.4.2.2 rmind struct cpu_softc * const cpu = curcpu()->ci_softc; 427 1.4.2.2 rmind // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 428 1.4.2.2 rmind return bus_space_read_1(cpu->cpu_bst, cpu->cpu_bsh, a); 429 1.4.2.2 rmind } 430 1.4.2.2 rmind 431 1.4.2.2 rmind void 432 1.4.2.2 rmind cpu_write_4(bus_addr_t a, uint32_t v) 433 1.4.2.2 rmind { 434 1.4.2.2 rmind struct cpu_softc * const cpu = curcpu()->ci_softc; 435 1.4.2.2 rmind bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, a, v); 436 1.4.2.2 rmind } 437 1.4.2.2 rmind 438 1.4.2.2 rmind void 439 1.4.2.2 rmind cpu_write_1(bus_addr_t a, uint8_t v) 440 1.4.2.2 rmind { 441 1.4.2.2 rmind struct cpu_softc * const cpu = curcpu()->ci_softc; 442 1.4.2.2 rmind bus_space_write_1(cpu->cpu_bst, cpu->cpu_bsh, a, v); 443 1.4.2.2 rmind } 444 1.4.2.2 rmind 445 1.4.2.2 rmind void 446 1.4.2.2 rmind booke_sstep(struct trapframe *tf) 447 1.4.2.2 rmind { 448 1.4.2.2 rmind KASSERT(tf->tf_srr1 & PSL_DE); 449 1.4.2.2 rmind const uint32_t insn = ufetch_32((const void *)tf->tf_srr0); 450 1.4.2.2 rmind register_t dbcr0 = DBCR0_IAC1 | DBCR0_IDM; 451 1.4.2.2 rmind register_t dbcr1 = DBCR1_IAC1US_USER | DBCR1_IAC1ER_DS1; 452 1.4.2.2 rmind if ((insn >> 28) == 4) { 453 1.4.2.2 rmind uint32_t iac2 = 0; 454 1.4.2.2 rmind if ((insn >> 26) == 0x12) { 455 1.4.2.2 rmind const int32_t off = (((int32_t)insn << 6) >> 6) & ~3; 456 1.4.2.2 rmind iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 457 1.4.2.2 rmind dbcr0 |= DBCR0_IAC2; 458 1.4.2.2 rmind } else if ((insn >> 26) == 0x10) { 459 1.4.2.2 rmind const int16_t off = insn & ~3; 460 1.4.2.2 rmind iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 461 1.4.2.2 rmind dbcr0 |= DBCR0_IAC2; 462 1.4.2.2 rmind } else if ((insn & 0xfc00ffde) == 0x4c000420) { 463 1.4.2.2 rmind iac2 = tf->tf_ctr; 464 1.4.2.2 rmind dbcr0 |= DBCR0_IAC2; 465 1.4.2.2 rmind } else if ((insn & 0xfc00ffde) == 0x4c000020) { 466 1.4.2.2 rmind iac2 = tf->tf_lr; 467 1.4.2.2 rmind dbcr0 |= DBCR0_IAC2; 468 1.4.2.2 rmind } 469 1.4.2.2 rmind if (dbcr0 & DBCR0_IAC2) { 470 1.4.2.2 rmind dbcr1 |= DBCR1_IAC2US_USER | DBCR1_IAC2ER_DS1; 471 1.4.2.2 rmind mtspr(SPR_IAC2, iac2); 472 1.4.2.2 rmind } 473 1.4.2.2 rmind } 474 1.4.2.2 rmind mtspr(SPR_IAC1, tf->tf_srr0 + 4); 475 1.4.2.2 rmind mtspr(SPR_DBCR1, dbcr1); 476 1.4.2.2 rmind mtspr(SPR_DBCR0, dbcr0); 477 1.4.2.2 rmind } 478
Indexes created Tue Oct 21 19:09:51 GMT 2025