booke_machdep.c revision 1.12
1 /*- 2 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 7 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 8 * 9 * This material is based upon work supported by the Defense Advanced Research 10 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 11 * Contract No. N66001-09-C-2073. 12 * Approved for Public Release, Distribution Unlimited 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #define __INTR_PRIVATE 37 #define _POWERPC_BUS_DMA_PRIVATE 38 39 #include <sys/cdefs.h> 40 41 #include "opt_modular.h" 42 43 #include <sys/param.h> 44 #include <sys/cpu.h> 45 #include <sys/device.h> 46 #include <sys/intr.h> 47 #include <sys/mount.h> 48 #include <sys/msgbuf.h> 49 #include <sys/kernel.h> 50 #include <sys/reboot.h> 51 #include <sys/bus.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <powerpc/cpuset.h> 56 #include <powerpc/pcb.h> 57 #include <powerpc/spr.h> 58 #include <powerpc/booke/spr.h> 59 #include <powerpc/booke/cpuvar.h> 60 61 /* 62 * Global variables used here and there 63 */ 64 paddr_t msgbuf_paddr; 65 psize_t pmemsize; 66 struct vm_map *phys_map; 67 68 #ifdef MODULAR 69 register_t cpu_psluserset = PSL_USERSET; 70 register_t cpu_pslusermod = PSL_USERMOD; 71 register_t cpu_pslusermask = PSL_USERMASK; 72 #endif 73 74 static bus_addr_t booke_dma_phys_to_bus_mem(bus_dma_tag_t, bus_addr_t); 75 static bus_addr_t booke_dma_bus_mem_to_phys(bus_dma_tag_t, bus_addr_t); 76 77 78 struct powerpc_bus_dma_tag booke_bus_dma_tag = { 79 ._dmamap_create = _bus_dmamap_create, 80 ._dmamap_destroy = _bus_dmamap_destroy, 81 ._dmamap_load = _bus_dmamap_load, 82 ._dmamap_load_mbuf = _bus_dmamap_load_mbuf, 83 ._dmamap_load_uio = _bus_dmamap_load_uio, 84 ._dmamap_load_raw = _bus_dmamap_load_raw, 85 ._dmamap_unload = _bus_dmamap_unload, 86 ._dmamap_sync = _bus_dmamap_sync, 87 ._dmamem_alloc = _bus_dmamem_alloc, 88 ._dmamem_free = _bus_dmamem_free, 89 ._dmamem_map = _bus_dmamem_map, 90 ._dmamem_unmap = _bus_dmamem_unmap, 91 ._dmamem_mmap = _bus_dmamem_mmap, 92 ._dma_phys_to_bus_mem = booke_dma_phys_to_bus_mem, 93 ._dma_bus_mem_to_phys = booke_dma_bus_mem_to_phys, 94 }; 95 96 static bus_addr_t 97 booke_dma_phys_to_bus_mem(bus_dma_tag_t t, bus_addr_t a) 98 { 99 return a; 100 } 101 102 static bus_addr_t 103 booke_dma_bus_mem_to_phys(bus_dma_tag_t t, bus_addr_t a) 104 { 105 return a; 106 } 107 108 struct cpu_md_ops cpu_md_ops; 109 110 struct cpu_softc cpu_softc[] = { 111 [0] = { 112 .cpu_ci = &cpu_info[0], 113 }, 114 #ifdef MULTIPROCESSOR 115 [CPU_MAXNUM-1] = { 116 .cpu_ci = &cpu_info[CPU_MAXNUM-1], 117 }, 118 #endif 119 }; 120 struct cpu_info cpu_info[] = { 121 [0] = { 122 .ci_curlwp = &lwp0, 123 .ci_tlb_info = &pmap_tlb0_info, 124 .ci_softc = &cpu_softc[0], 125 .ci_cpl = IPL_HIGH, 126 .ci_idepth = -1, 127 }, 128 #ifdef MULTIPROCESSOR 129 [CPU_MAXNUM-1] = { 130 .ci_curlwp = NULL, 131 .ci_tlb_info = &pmap_tlb0_info, 132 .ci_softc = &cpu_softc[CPU_MAXNUM-1], 133 .ci_cpl = IPL_HIGH, 134 .ci_idepth = -1, 135 }, 136 #endif 137 }; 138 __CTASSERT(__arraycount(cpu_info) == __arraycount(cpu_softc)); 139 140 /* 141 * This should probably be in autoconf! XXX 142 */ 143 char cpu_model[80]; 144 char machine[] = MACHINE; /* from <machine/param.h> */ 145 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 146 147 char bootpath[256]; 148 149 #if NKSYMS || defined(DDB) || defined(MODULAR) 150 void *startsym, *endsym; 151 #endif 152 153 #if defined(MULTIPROCESSOR) 154 volatile struct cpu_hatch_data cpu_hatch_data __cacheline_aligned; 155 #endif 156 157 int fake_mapiodev = 1; 158 159 void 160 booke_cpu_startup(const char *model) 161 { 162 vaddr_t minaddr, maxaddr; 163 char pbuf[9]; 164 165 strlcpy(cpu_model, model, sizeof(cpu_model)); 166 167 printf("%s%s", copyright, version); 168 169 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 170 printf("total memory = %s\n", pbuf); 171 172 minaddr = 0; 173 /* 174 * Allocate a submap for physio 175 */ 176 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 177 VM_PHYS_SIZE, 0, false, NULL); 178 179 /* 180 * No need to allocate an mbuf cluster submap. Mbuf clusters 181 * are allocated via the pool allocator, and we use direct-mapped 182 * pool pages. 183 */ 184 185 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 186 printf("avail memory = %s\n", pbuf); 187 188 /* 189 * Register the tlb's evcnts 190 */ 191 pmap_tlb_info_evcnt_attach(curcpu()->ci_tlb_info); 192 193 /* 194 * Set up the board properties database. 195 */ 196 board_info_init(); 197 198 /* 199 * Now that we have VM, malloc()s are OK in bus_space. 200 */ 201 bus_space_mallocok(); 202 fake_mapiodev = 0; 203 204 #ifdef MULTIPROCESSOR 205 for (size_t i = 1; i < __arraycount(cpu_info); i++) { 206 struct cpu_info * const ci = &cpu_info[i]; 207 struct cpu_softc * const cpu = &cpu_softc[i]; 208 cpu->cpu_ci = ci; 209 cpu->cpu_bst = cpu_softc[0].cpu_bst; 210 cpu->cpu_le_bst = cpu_softc[0].cpu_le_bst; 211 cpu->cpu_bsh = cpu_softc[0].cpu_bsh; 212 cpu->cpu_highmem = cpu_softc[0].cpu_highmem; 213 ci->ci_softc = cpu; 214 ci->ci_tlb_info = &pmap_tlb0_info; 215 ci->ci_cpl = IPL_HIGH; 216 ci->ci_idepth = -1; 217 ci->ci_pmap_kern_segtab = curcpu()->ci_pmap_kern_segtab; 218 } 219 #endif /* MULTIPROCESSOR */ 220 } 221 222 static void 223 dumpsys(void) 224 { 225 226 printf("dumpsys: TBD\n"); 227 } 228 229 /* 230 * Halt or reboot the machine after syncing/dumping according to howto. 231 */ 232 void 233 cpu_reboot(int howto, char *what) 234 { 235 static int syncing; 236 static char str[256]; 237 char *ap = str, *ap1 = ap; 238 239 boothowto = howto; 240 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 241 syncing = 1; 242 vfs_shutdown(); /* sync */ 243 resettodr(); /* set wall clock */ 244 } 245 246 splhigh(); 247 248 if (!cold && (howto & RB_DUMP)) 249 dumpsys(); 250 251 doshutdownhooks(); 252 253 pmf_system_shutdown(boothowto); 254 255 if ((howto & RB_POWERDOWN) == RB_POWERDOWN) { 256 /* Power off here if we know how...*/ 257 } 258 259 if (howto & RB_HALT) { 260 printf("halted\n\n"); 261 262 goto reboot; /* XXX for now... */ 263 264 #ifdef DDB 265 printf("dropping to debugger\n"); 266 while(1) 267 Debugger(); 268 #endif 269 } 270 271 printf("rebooting\n\n"); 272 if (what && *what) { 273 if (strlen(what) > sizeof str - 5) 274 printf("boot string too large, ignored\n"); 275 else { 276 strcpy(str, what); 277 ap1 = ap = str + strlen(str); 278 *ap++ = ' '; 279 } 280 } 281 *ap++ = '-'; 282 if (howto & RB_SINGLE) 283 *ap++ = 's'; 284 if (howto & RB_KDB) 285 *ap++ = 'd'; 286 *ap++ = 0; 287 if (ap[-2] == '-') 288 *ap1 = 0; 289 290 /* flush cache for msgbuf */ 291 dcache_wb(msgbuf_paddr, round_page(MSGBUFSIZE)); 292 293 reboot: 294 __asm volatile("msync; isync"); 295 (*cpu_md_ops.md_cpu_reset)(); 296 297 printf("%s: md_cpu_reset() failed!\n", __func__); 298 #ifdef DDB 299 for (;;) 300 Debugger(); 301 #else 302 for (;;) 303 /* nothing */; 304 #endif 305 } 306 307 /* 308 * mapiodev: 309 * 310 * Allocate vm space and mapin the I/O address. Use reserved TLB 311 * mapping if one is found. 312 */ 313 void * 314 mapiodev(paddr_t pa, psize_t len) 315 { 316 const vsize_t off = pa & PAGE_MASK; 317 318 /* 319 * See if we have reserved TLB entry for the pa. This needs to be 320 * true for console as we can't use uvm during early bootstrap. 321 */ 322 void * const p = tlb_mapiodev(pa, len); 323 if (p != NULL) 324 return p; 325 326 if (fake_mapiodev) 327 panic("mapiodev: no TLB entry reserved for %llx+%llx", 328 (long long)pa, (long long)len); 329 330 pa = trunc_page(pa); 331 len = round_page(off + len); 332 vaddr_t va = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 333 334 if (va == 0) 335 return NULL; 336 337 for (va += len, pa += len; len > 0; len -= PAGE_SIZE) { 338 va -= PAGE_SIZE; 339 pa -= PAGE_SIZE; 340 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE, 341 PMAP_NOCACHE); 342 } 343 pmap_update(pmap_kernel()); 344 return (void *)(va + off); 345 } 346 347 void 348 unmapiodev(vaddr_t va, vsize_t len) 349 { 350 /* Nothing to do for reserved (ie. not uvm_km_alloc'd) mappings. */ 351 if (va < VM_MIN_KERNEL_ADDRESS || va > VM_MAX_KERNEL_ADDRESS) { 352 tlb_unmapiodev(va, len); 353 return; 354 } 355 356 len = round_page((va & PAGE_MASK) + len); 357 va = trunc_page(va); 358 359 pmap_kremove(va, len); 360 uvm_km_free(kernel_map, va, len, UVM_KMF_VAONLY); 361 } 362 363 void 364 cpu_evcnt_attach(struct cpu_info *ci) 365 { 366 struct cpu_softc * const cpu = ci->ci_softc; 367 const char * const xname = ci->ci_data.cpu_name; 368 369 evcnt_attach_dynamic_nozero(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 370 NULL, xname, "clock"); 371 evcnt_attach_dynamic_nozero(&cpu->cpu_ev_late_clock, EVCNT_TYPE_INTR, 372 NULL, xname, "late clock"); 373 evcnt_attach_dynamic_nozero(&cpu->cpu_ev_exec_trap_sync, EVCNT_TYPE_TRAP, 374 NULL, xname, "exec pages synced (trap)"); 375 evcnt_attach_dynamic_nozero(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 376 NULL, xname, "traps"); 377 evcnt_attach_dynamic_nozero(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 378 &ci->ci_ev_traps, xname, "kernel DSI traps"); 379 evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 380 &ci->ci_ev_traps, xname, "user DSI traps"); 381 evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 382 &ci->ci_ev_udsi, xname, "user DSI failures"); 383 evcnt_attach_dynamic_nozero(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 384 &ci->ci_ev_traps, xname, "kernel ISI traps"); 385 evcnt_attach_dynamic_nozero(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 386 &ci->ci_ev_traps, xname, "user ISI traps"); 387 evcnt_attach_dynamic_nozero(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 388 &ci->ci_ev_isi, xname, "user ISI failures"); 389 evcnt_attach_dynamic_nozero(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 390 &ci->ci_ev_traps, xname, "system call traps"); 391 evcnt_attach_dynamic_nozero(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 392 &ci->ci_ev_traps, xname, "PGM traps"); 393 evcnt_attach_dynamic_nozero(&ci->ci_ev_debug, EVCNT_TYPE_TRAP, 394 &ci->ci_ev_traps, xname, "debug traps"); 395 evcnt_attach_dynamic_nozero(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 396 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 397 evcnt_attach_dynamic_nozero(&ci->ci_ev_fpusw, EVCNT_TYPE_MISC, 398 &ci->ci_ev_fpu, xname, "FPU context switches"); 399 evcnt_attach_dynamic_nozero(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 400 &ci->ci_ev_traps, xname, "user alignment traps"); 401 evcnt_attach_dynamic_nozero(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 402 &ci->ci_ev_ali, xname, "user alignment traps"); 403 evcnt_attach_dynamic_nozero(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 404 &ci->ci_ev_umchk, xname, "user MCHK failures"); 405 evcnt_attach_dynamic_nozero(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 406 &ci->ci_ev_traps, xname, "SPE unavailable"); 407 evcnt_attach_dynamic_nozero(&ci->ci_ev_vecsw, EVCNT_TYPE_MISC, 408 &ci->ci_ev_vec, xname, "SPE context switches"); 409 evcnt_attach_dynamic_nozero(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 410 NULL, xname, "IPIs"); 411 evcnt_attach_dynamic_nozero(&ci->ci_ev_tlbmiss_soft, EVCNT_TYPE_TRAP, 412 &ci->ci_ev_traps, xname, "soft tlb misses"); 413 evcnt_attach_dynamic_nozero(&ci->ci_ev_dtlbmiss_hard, EVCNT_TYPE_TRAP, 414 &ci->ci_ev_traps, xname, "data tlb misses"); 415 evcnt_attach_dynamic_nozero(&ci->ci_ev_itlbmiss_hard, EVCNT_TYPE_TRAP, 416 &ci->ci_ev_traps, xname, "inst tlb misses"); 417 } 418 419 #ifdef MULTIPROCESSOR 420 register_t 421 cpu_hatch(void) 422 { 423 volatile struct cpuset_info * const csi = &cpuset_info; 424 const size_t id = cpu_number(); 425 426 /* 427 * We've hatched so tell the spinup code. 428 */ 429 CPUSET_ADD(csi->cpus_hatched, id); 430 431 /* 432 * Loop until running bit for this cpu is set. 433 */ 434 while (!CPUSET_HAS_P(csi->cpus_running, id)) { 435 continue; 436 } 437 438 /* 439 * Now that we are active, start the clocks. 440 */ 441 cpu_initclocks(); 442 443 /* 444 * Return sp of the idlelwp. Which we should be already using but ... 445 */ 446 return curcpu()->ci_curpcb->pcb_sp; 447 } 448 449 void 450 cpu_boot_secondary_processors(void) 451 { 452 volatile struct cpuset_info * const csi = &cpuset_info; 453 CPU_INFO_ITERATOR cii; 454 struct cpu_info *ci; 455 __cpuset_t running = CPUSET_NULLSET; 456 457 for (CPU_INFO_FOREACH(cii, ci)) { 458 /* 459 * Skip this CPU if it didn't sucessfully hatch. 460 */ 461 if (! CPUSET_HAS_P(csi->cpus_hatched, cpu_index(ci))) 462 continue; 463 464 KASSERT(!CPU_IS_PRIMARY(ci)); 465 KASSERT(ci->ci_data.cpu_idlelwp); 466 467 CPUSET_ADD(running, cpu_index(ci)); 468 } 469 KASSERT(CPUSET_EQUAL_P(csi->cpus_hatched, running)); 470 if (!CPUSET_EMPTY_P(running)) { 471 CPUSET_ADDSET(csi->cpus_running, running); 472 } 473 } 474 #endif 475 476 uint32_t 477 cpu_read_4(bus_addr_t a) 478 { 479 struct cpu_softc * const cpu = curcpu()->ci_softc; 480 // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 481 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, a); 482 } 483 484 uint8_t 485 cpu_read_1(bus_addr_t a) 486 { 487 struct cpu_softc * const cpu = curcpu()->ci_softc; 488 // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 489 return bus_space_read_1(cpu->cpu_bst, cpu->cpu_bsh, a); 490 } 491 492 void 493 cpu_write_4(bus_addr_t a, uint32_t v) 494 { 495 struct cpu_softc * const cpu = curcpu()->ci_softc; 496 bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, a, v); 497 } 498 499 void 500 cpu_write_1(bus_addr_t a, uint8_t v) 501 { 502 struct cpu_softc * const cpu = curcpu()->ci_softc; 503 bus_space_write_1(cpu->cpu_bst, cpu->cpu_bsh, a, v); 504 } 505 506 void 507 booke_sstep(struct trapframe *tf) 508 { 509 KASSERT(tf->tf_srr1 & PSL_DE); 510 const uint32_t insn = ufetch_32((const void *)tf->tf_srr0); 511 register_t dbcr0 = DBCR0_IAC1 | DBCR0_IDM; 512 register_t dbcr1 = DBCR1_IAC1US_USER | DBCR1_IAC1ER_DS1; 513 if ((insn >> 28) == 4) { 514 uint32_t iac2 = 0; 515 if ((insn >> 26) == 0x12) { 516 const int32_t off = (((int32_t)insn << 6) >> 6) & ~3; 517 iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 518 dbcr0 |= DBCR0_IAC2; 519 } else if ((insn >> 26) == 0x10) { 520 const int16_t off = insn & ~3; 521 iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 522 dbcr0 |= DBCR0_IAC2; 523 } else if ((insn & 0xfc00ffde) == 0x4c000420) { 524 iac2 = tf->tf_ctr; 525 dbcr0 |= DBCR0_IAC2; 526 } else if ((insn & 0xfc00ffde) == 0x4c000020) { 527 iac2 = tf->tf_lr; 528 dbcr0 |= DBCR0_IAC2; 529 } 530 if (dbcr0 & DBCR0_IAC2) { 531 dbcr1 |= DBCR1_IAC2US_USER | DBCR1_IAC2ER_DS1; 532 mtspr(SPR_IAC2, iac2); 533 } 534 } 535 mtspr(SPR_IAC1, tf->tf_srr0 + 4); 536 mtspr(SPR_DBCR1, dbcr1); 537 mtspr(SPR_DBCR0, dbcr0); 538 } 539
Indexes created Tue Sep 30 11:09:46 GMT 2025