booke_machdep.c revision 1.15
1 /* $NetBSD: booke_machdep.c,v 1.15 2012/07/18 18:51:59 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #define __INTR_PRIVATE 38 #define _POWERPC_BUS_DMA_PRIVATE 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: booke_machdep.c,v 1.15 2012/07/18 18:51:59 matt Exp $"); 42 43 #include "opt_modular.h" 44 45 #include <sys/param.h> 46 #include <sys/cpu.h> 47 #include <sys/device.h> 48 #include <sys/intr.h> 49 #include <sys/mount.h> 50 #include <sys/msgbuf.h> 51 #include <sys/kernel.h> 52 #include <sys/reboot.h> 53 #include <sys/bus.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <powerpc/cpuset.h> 58 #include <powerpc/pcb.h> 59 #include <powerpc/spr.h> 60 #include <powerpc/booke/spr.h> 61 #include <powerpc/booke/cpuvar.h> 62 63 /* 64 * Global variables used here and there 65 */ 66 paddr_t msgbuf_paddr; 67 psize_t pmemsize; 68 struct vm_map *phys_map; 69 70 #ifdef MODULAR 71 register_t cpu_psluserset = PSL_USERSET; 72 register_t cpu_pslusermod = PSL_USERMOD; 73 register_t cpu_pslusermask = PSL_USERMASK; 74 #endif 75 76 static bus_addr_t booke_dma_phys_to_bus_mem(bus_dma_tag_t, bus_addr_t); 77 static bus_addr_t booke_dma_bus_mem_to_phys(bus_dma_tag_t, bus_addr_t); 78 79 80 struct powerpc_bus_dma_tag booke_bus_dma_tag = { 81 ._dmamap_create = _bus_dmamap_create, 82 ._dmamap_destroy = _bus_dmamap_destroy, 83 ._dmamap_load = _bus_dmamap_load, 84 ._dmamap_load_mbuf = _bus_dmamap_load_mbuf, 85 ._dmamap_load_uio = _bus_dmamap_load_uio, 86 ._dmamap_load_raw = _bus_dmamap_load_raw, 87 ._dmamap_unload = _bus_dmamap_unload, 88 ._dmamap_sync = _bus_dmamap_sync, 89 ._dmamem_alloc = _bus_dmamem_alloc, 90 ._dmamem_free = _bus_dmamem_free, 91 ._dmamem_map = _bus_dmamem_map, 92 ._dmamem_unmap = _bus_dmamem_unmap, 93 ._dmamem_mmap = _bus_dmamem_mmap, 94 ._dma_phys_to_bus_mem = booke_dma_phys_to_bus_mem, 95 ._dma_bus_mem_to_phys = booke_dma_bus_mem_to_phys, 96 }; 97 98 static bus_addr_t 99 booke_dma_phys_to_bus_mem(bus_dma_tag_t t, bus_addr_t a) 100 { 101 return a; 102 } 103 104 static bus_addr_t 105 booke_dma_bus_mem_to_phys(bus_dma_tag_t t, bus_addr_t a) 106 { 107 return a; 108 } 109 110 struct cpu_md_ops cpu_md_ops; 111 112 struct cpu_softc cpu_softc[] = { 113 [0] = { 114 .cpu_ci = &cpu_info[0], 115 }, 116 #ifdef MULTIPROCESSOR 117 [CPU_MAXNUM-1] = { 118 .cpu_ci = &cpu_info[CPU_MAXNUM-1], 119 }, 120 #endif 121 }; 122 struct cpu_info cpu_info[] = { 123 [0] = { 124 .ci_curlwp = &lwp0, 125 .ci_tlb_info = &pmap_tlb0_info, 126 .ci_softc = &cpu_softc[0], 127 .ci_cpl = IPL_HIGH, 128 .ci_idepth = -1, 129 }, 130 #ifdef MULTIPROCESSOR 131 [CPU_MAXNUM-1] = { 132 .ci_curlwp = NULL, 133 .ci_tlb_info = &pmap_tlb0_info, 134 .ci_softc = &cpu_softc[CPU_MAXNUM-1], 135 .ci_cpl = IPL_HIGH, 136 .ci_idepth = -1, 137 }, 138 #endif 139 }; 140 __CTASSERT(__arraycount(cpu_info) == __arraycount(cpu_softc)); 141 142 /* 143 * This should probably be in autoconf! XXX 144 */ 145 char cpu_model[80]; 146 char machine[] = MACHINE; /* from <machine/param.h> */ 147 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 148 149 char bootpath[256]; 150 151 #if NKSYMS || defined(DDB) || defined(MODULAR) 152 void *startsym, *endsym; 153 #endif 154 155 #if defined(MULTIPROCESSOR) 156 volatile struct cpu_hatch_data cpu_hatch_data __cacheline_aligned; 157 #endif 158 159 int fake_mapiodev = 1; 160 161 void 162 booke_cpu_startup(const char *model) 163 { 164 vaddr_t minaddr, maxaddr; 165 char pbuf[9]; 166 167 strlcpy(cpu_model, model, sizeof(cpu_model)); 168 169 printf("%s%s", copyright, version); 170 171 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 172 printf("total memory = %s\n", pbuf); 173 174 minaddr = 0; 175 /* 176 * Allocate a submap for physio 177 */ 178 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 179 VM_PHYS_SIZE, 0, false, NULL); 180 181 /* 182 * No need to allocate an mbuf cluster submap. Mbuf clusters 183 * are allocated via the pool allocator, and we use direct-mapped 184 * pool pages. 185 */ 186 187 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 188 printf("avail memory = %s\n", pbuf); 189 190 /* 191 * Register the tlb's evcnts 192 */ 193 pmap_tlb_info_evcnt_attach(curcpu()->ci_tlb_info); 194 195 /* 196 * Set up the board properties database. 197 */ 198 board_info_init(); 199 200 /* 201 * Now that we have VM, malloc()s are OK in bus_space. 202 */ 203 bus_space_mallocok(); 204 fake_mapiodev = 0; 205 206 #ifdef MULTIPROCESSOR 207 for (size_t i = 1; i < __arraycount(cpu_info); i++) { 208 struct cpu_info * const ci = &cpu_info[i]; 209 struct cpu_softc * const cpu = &cpu_softc[i]; 210 cpu->cpu_ci = ci; 211 cpu->cpu_bst = cpu_softc[0].cpu_bst; 212 cpu->cpu_le_bst = cpu_softc[0].cpu_le_bst; 213 cpu->cpu_bsh = cpu_softc[0].cpu_bsh; 214 cpu->cpu_highmem = cpu_softc[0].cpu_highmem; 215 ci->ci_softc = cpu; 216 ci->ci_tlb_info = &pmap_tlb0_info; 217 ci->ci_cpl = IPL_HIGH; 218 ci->ci_idepth = -1; 219 ci->ci_pmap_kern_segtab = curcpu()->ci_pmap_kern_segtab; 220 } 221 #endif /* MULTIPROCESSOR */ 222 } 223 224 static void 225 dumpsys(void) 226 { 227 228 printf("dumpsys: TBD\n"); 229 } 230 231 /* 232 * Halt or reboot the machine after syncing/dumping according to howto. 233 */ 234 void 235 cpu_reboot(int howto, char *what) 236 { 237 static int syncing; 238 static char str[256]; 239 char *ap = str, *ap1 = ap; 240 241 boothowto = howto; 242 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 243 syncing = 1; 244 vfs_shutdown(); /* sync */ 245 resettodr(); /* set wall clock */ 246 } 247 248 splhigh(); 249 250 if (!cold && (howto & RB_DUMP)) 251 dumpsys(); 252 253 doshutdownhooks(); 254 255 pmf_system_shutdown(boothowto); 256 257 if ((howto & RB_POWERDOWN) == RB_POWERDOWN) { 258 /* Power off here if we know how...*/ 259 } 260 261 if (howto & RB_HALT) { 262 printf("halted\n\n"); 263 264 goto reboot; /* XXX for now... */ 265 266 #ifdef DDB 267 printf("dropping to debugger\n"); 268 while(1) 269 Debugger(); 270 #endif 271 } 272 273 printf("rebooting\n\n"); 274 if (what && *what) { 275 if (strlen(what) > sizeof str - 5) 276 printf("boot string too large, ignored\n"); 277 else { 278 strcpy(str, what); 279 ap1 = ap = str + strlen(str); 280 *ap++ = ' '; 281 } 282 } 283 *ap++ = '-'; 284 if (howto & RB_SINGLE) 285 *ap++ = 's'; 286 if (howto & RB_KDB) 287 *ap++ = 'd'; 288 *ap++ = 0; 289 if (ap[-2] == '-') 290 *ap1 = 0; 291 292 /* flush cache for msgbuf */ 293 dcache_wb(msgbuf_paddr, round_page(MSGBUFSIZE)); 294 295 reboot: 296 __asm volatile("msync; isync"); 297 (*cpu_md_ops.md_cpu_reset)(); 298 299 printf("%s: md_cpu_reset() failed!\n", __func__); 300 #ifdef DDB 301 for (;;) 302 Debugger(); 303 #else 304 for (;;) 305 /* nothing */; 306 #endif 307 } 308 309 /* 310 * mapiodev: 311 * 312 * Allocate vm space and mapin the I/O address. Use reserved TLB 313 * mapping if one is found. 314 */ 315 void * 316 mapiodev(paddr_t pa, psize_t len, bool prefetchable) 317 { 318 const vsize_t off = pa & PAGE_MASK; 319 320 /* 321 * See if we have reserved TLB entry for the pa. This needs to be 322 * true for console as we can't use uvm during early bootstrap. 323 */ 324 void * const p = tlb_mapiodev(pa, len, prefetchable); 325 if (p != NULL) 326 return p; 327 328 if (fake_mapiodev) 329 panic("mapiodev: no TLB entry reserved for %llx+%llx", 330 (long long)pa, (long long)len); 331 332 const paddr_t orig_pa = pa; 333 const psize_t orig_len = len; 334 vsize_t align = 0; 335 pa = trunc_page(pa); 336 len = round_page(off + len); 337 /* 338 * If we are allocating a large amount (>= 1MB) try to get an 339 * aligned VA region for it so try to do a large mapping for it. 340 */ 341 if ((len & (len - 1)) == 0 && len >= 0x100000) 342 align = len; 343 344 vaddr_t va = uvm_km_alloc(kernel_map, len, align, UVM_KMF_VAONLY); 345 346 if (va == 0 && align > 0) { 347 /* 348 * Large aligned request failed. Let's just get anything. 349 */ 350 align = 0; 351 va = uvm_km_alloc(kernel_map, len, align, UVM_KMF_VAONLY); 352 } 353 if (va == 0) 354 return NULL; 355 356 if (align) { 357 /* 358 * Now try to map that via one big TLB entry. 359 */ 360 pt_entry_t pte = pte_make_kenter_pa(pa, NULL, 361 VM_PROT_READ|VM_PROT_WRITE, 362 prefetchable ? 0 : PMAP_NOCACHE); 363 if (!tlb_ioreserve(va, len, pte)) { 364 void * const p0 = tlb_mapiodev(orig_pa, orig_len, 365 prefetchable); 366 KASSERT(p0 != NULL); 367 return p0; 368 } 369 } 370 371 for (va += len, pa += len; len > 0; len -= PAGE_SIZE) { 372 va -= PAGE_SIZE; 373 pa -= PAGE_SIZE; 374 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE, 375 prefetchable ? 0 : PMAP_NOCACHE); 376 } 377 pmap_update(pmap_kernel()); 378 return (void *)(va + off); 379 } 380 381 void 382 unmapiodev(vaddr_t va, vsize_t len) 383 { 384 /* Nothing to do for reserved (ie. not uvm_km_alloc'd) mappings. */ 385 if (va < VM_MIN_KERNEL_ADDRESS || va > VM_MAX_KERNEL_ADDRESS) { 386 tlb_unmapiodev(va, len); 387 return; 388 } 389 390 len = round_page((va & PAGE_MASK) + len); 391 va = trunc_page(va); 392 393 pmap_kremove(va, len); 394 uvm_km_free(kernel_map, va, len, UVM_KMF_VAONLY); 395 } 396 397 void 398 cpu_evcnt_attach(struct cpu_info *ci) 399 { 400 struct cpu_softc * const cpu = ci->ci_softc; 401 const char * const xname = ci->ci_data.cpu_name; 402 403 evcnt_attach_dynamic_nozero(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 404 NULL, xname, "clock"); 405 evcnt_attach_dynamic_nozero(&cpu->cpu_ev_late_clock, EVCNT_TYPE_INTR, 406 NULL, xname, "late clock"); 407 evcnt_attach_dynamic_nozero(&cpu->cpu_ev_exec_trap_sync, EVCNT_TYPE_TRAP, 408 NULL, xname, "exec pages synced (trap)"); 409 evcnt_attach_dynamic_nozero(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 410 NULL, xname, "traps"); 411 evcnt_attach_dynamic_nozero(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 412 &ci->ci_ev_traps, xname, "kernel DSI traps"); 413 evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 414 &ci->ci_ev_traps, xname, "user DSI traps"); 415 evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 416 &ci->ci_ev_udsi, xname, "user DSI failures"); 417 evcnt_attach_dynamic_nozero(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 418 &ci->ci_ev_traps, xname, "kernel ISI traps"); 419 evcnt_attach_dynamic_nozero(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 420 &ci->ci_ev_traps, xname, "user ISI traps"); 421 evcnt_attach_dynamic_nozero(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 422 &ci->ci_ev_isi, xname, "user ISI failures"); 423 evcnt_attach_dynamic_nozero(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 424 &ci->ci_ev_traps, xname, "system call traps"); 425 evcnt_attach_dynamic_nozero(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 426 &ci->ci_ev_traps, xname, "PGM traps"); 427 evcnt_attach_dynamic_nozero(&ci->ci_ev_debug, EVCNT_TYPE_TRAP, 428 &ci->ci_ev_traps, xname, "debug traps"); 429 evcnt_attach_dynamic_nozero(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 430 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 431 evcnt_attach_dynamic_nozero(&ci->ci_ev_fpusw, EVCNT_TYPE_MISC, 432 &ci->ci_ev_fpu, xname, "FPU context switches"); 433 evcnt_attach_dynamic_nozero(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 434 &ci->ci_ev_traps, xname, "user alignment traps"); 435 evcnt_attach_dynamic_nozero(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 436 &ci->ci_ev_ali, xname, "user alignment traps"); 437 evcnt_attach_dynamic_nozero(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 438 &ci->ci_ev_umchk, xname, "user MCHK failures"); 439 evcnt_attach_dynamic_nozero(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 440 &ci->ci_ev_traps, xname, "SPE unavailable"); 441 evcnt_attach_dynamic_nozero(&ci->ci_ev_vecsw, EVCNT_TYPE_MISC, 442 &ci->ci_ev_vec, xname, "SPE context switches"); 443 evcnt_attach_dynamic_nozero(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 444 NULL, xname, "IPIs"); 445 evcnt_attach_dynamic_nozero(&ci->ci_ev_tlbmiss_soft, EVCNT_TYPE_TRAP, 446 &ci->ci_ev_traps, xname, "soft tlb misses"); 447 evcnt_attach_dynamic_nozero(&ci->ci_ev_dtlbmiss_hard, EVCNT_TYPE_TRAP, 448 &ci->ci_ev_traps, xname, "data tlb misses"); 449 evcnt_attach_dynamic_nozero(&ci->ci_ev_itlbmiss_hard, EVCNT_TYPE_TRAP, 450 &ci->ci_ev_traps, xname, "inst tlb misses"); 451 } 452 453 #ifdef MULTIPROCESSOR 454 register_t 455 cpu_hatch(void) 456 { 457 volatile struct cpuset_info * const csi = &cpuset_info; 458 const size_t id = cpu_number(); 459 460 /* 461 * We've hatched so tell the spinup code. 462 */ 463 CPUSET_ADD(csi->cpus_hatched, id); 464 465 /* 466 * Loop until running bit for this cpu is set. 467 */ 468 while (!CPUSET_HAS_P(csi->cpus_running, id)) { 469 continue; 470 } 471 472 /* 473 * Now that we are active, start the clocks. 474 */ 475 cpu_initclocks(); 476 477 /* 478 * Return sp of the idlelwp. Which we should be already using but ... 479 */ 480 return curcpu()->ci_curpcb->pcb_sp; 481 } 482 483 void 484 cpu_boot_secondary_processors(void) 485 { 486 volatile struct cpuset_info * const csi = &cpuset_info; 487 CPU_INFO_ITERATOR cii; 488 struct cpu_info *ci; 489 __cpuset_t running = CPUSET_NULLSET; 490 491 for (CPU_INFO_FOREACH(cii, ci)) { 492 /* 493 * Skip this CPU if it didn't sucessfully hatch. 494 */ 495 if (! CPUSET_HAS_P(csi->cpus_hatched, cpu_index(ci))) 496 continue; 497 498 KASSERT(!CPU_IS_PRIMARY(ci)); 499 KASSERT(ci->ci_data.cpu_idlelwp); 500 501 CPUSET_ADD(running, cpu_index(ci)); 502 } 503 KASSERT(CPUSET_EQUAL_P(csi->cpus_hatched, running)); 504 if (!CPUSET_EMPTY_P(running)) { 505 CPUSET_ADDSET(csi->cpus_running, running); 506 } 507 } 508 #endif 509 510 uint32_t 511 cpu_read_4(bus_addr_t a) 512 { 513 struct cpu_softc * const cpu = curcpu()->ci_softc; 514 // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 515 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, a); 516 } 517 518 uint8_t 519 cpu_read_1(bus_addr_t a) 520 { 521 struct cpu_softc * const cpu = curcpu()->ci_softc; 522 // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 523 return bus_space_read_1(cpu->cpu_bst, cpu->cpu_bsh, a); 524 } 525 526 void 527 cpu_write_4(bus_addr_t a, uint32_t v) 528 { 529 struct cpu_softc * const cpu = curcpu()->ci_softc; 530 bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, a, v); 531 } 532 533 void 534 cpu_write_1(bus_addr_t a, uint8_t v) 535 { 536 struct cpu_softc * const cpu = curcpu()->ci_softc; 537 bus_space_write_1(cpu->cpu_bst, cpu->cpu_bsh, a, v); 538 } 539 540 void 541 booke_sstep(struct trapframe *tf) 542 { 543 KASSERT(tf->tf_srr1 & PSL_DE); 544 const uint32_t insn = ufetch_32((const void *)tf->tf_srr0); 545 register_t dbcr0 = DBCR0_IAC1 | DBCR0_IDM; 546 register_t dbcr1 = DBCR1_IAC1US_USER | DBCR1_IAC1ER_DS1; 547 if ((insn >> 28) == 4) { 548 uint32_t iac2 = 0; 549 if ((insn >> 26) == 0x12) { 550 const int32_t off = (((int32_t)insn << 6) >> 6) & ~3; 551 iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 552 dbcr0 |= DBCR0_IAC2; 553 } else if ((insn >> 26) == 0x10) { 554 const int16_t off = insn & ~3; 555 iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 556 dbcr0 |= DBCR0_IAC2; 557 } else if ((insn & 0xfc00ffde) == 0x4c000420) { 558 iac2 = tf->tf_ctr; 559 dbcr0 |= DBCR0_IAC2; 560 } else if ((insn & 0xfc00ffde) == 0x4c000020) { 561 iac2 = tf->tf_lr; 562 dbcr0 |= DBCR0_IAC2; 563 } 564 if (dbcr0 & DBCR0_IAC2) { 565 dbcr1 |= DBCR1_IAC2US_USER | DBCR1_IAC2ER_DS1; 566 mtspr(SPR_IAC2, iac2); 567 } 568 } 569 mtspr(SPR_IAC1, tf->tf_srr0 + 4); 570 mtspr(SPR_DBCR1, dbcr1); 571 mtspr(SPR_DBCR0, dbcr0); 572 } 573
Indexes created Tue Sep 30 11:09:46 GMT 2025