booke_machdep.c revision 1.17
1 /* $NetBSD: booke_machdep.c,v 1.17 2012/10/29 05:23:44 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #define __INTR_PRIVATE 38 #define _POWERPC_BUS_DMA_PRIVATE 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: booke_machdep.c,v 1.17 2012/10/29 05:23:44 matt Exp $"); 42 43 #include "opt_modular.h" 44 45 #include <sys/param.h> 46 #include <sys/cpu.h> 47 #include <sys/device.h> 48 #include <sys/intr.h> 49 #include <sys/mount.h> 50 #include <sys/msgbuf.h> 51 #include <sys/kernel.h> 52 #include <sys/reboot.h> 53 #include <sys/bus.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <powerpc/cpuset.h> 58 #include <powerpc/pcb.h> 59 #include <powerpc/spr.h> 60 #include <powerpc/booke/spr.h> 61 #include <powerpc/booke/cpuvar.h> 62 63 /* 64 * Global variables used here and there 65 */ 66 paddr_t msgbuf_paddr; 67 psize_t pmemsize; 68 struct vm_map *phys_map; 69 70 #ifdef MODULAR 71 register_t cpu_psluserset = PSL_USERSET; 72 register_t cpu_pslusermod = PSL_USERMOD; 73 register_t cpu_pslusermask = PSL_USERMASK; 74 #endif 75 76 static bus_addr_t booke_dma_phys_to_bus_mem(bus_dma_tag_t, bus_addr_t); 77 static bus_addr_t booke_dma_bus_mem_to_phys(bus_dma_tag_t, bus_addr_t); 78 79 80 struct powerpc_bus_dma_tag booke_bus_dma_tag = { 81 ._dmamap_create = _bus_dmamap_create, 82 ._dmamap_destroy = _bus_dmamap_destroy, 83 ._dmamap_load = _bus_dmamap_load, 84 ._dmamap_load_mbuf = _bus_dmamap_load_mbuf, 85 ._dmamap_load_uio = _bus_dmamap_load_uio, 86 ._dmamap_load_raw = _bus_dmamap_load_raw, 87 ._dmamap_unload = _bus_dmamap_unload, 88 /* 89 * The caches on BookE are coherent so we don't need to do any special 90 * cache synchronization. 91 */ 92 //._dmamap_sync = _bus_dmamap_sync, 93 ._dmamem_alloc = _bus_dmamem_alloc, 94 ._dmamem_free = _bus_dmamem_free, 95 ._dmamem_map = _bus_dmamem_map, 96 ._dmamem_unmap = _bus_dmamem_unmap, 97 ._dmamem_mmap = _bus_dmamem_mmap, 98 ._dma_phys_to_bus_mem = booke_dma_phys_to_bus_mem, 99 ._dma_bus_mem_to_phys = booke_dma_bus_mem_to_phys, 100 }; 101 102 static bus_addr_t 103 booke_dma_phys_to_bus_mem(bus_dma_tag_t t, bus_addr_t a) 104 { 105 return a; 106 } 107 108 static bus_addr_t 109 booke_dma_bus_mem_to_phys(bus_dma_tag_t t, bus_addr_t a) 110 { 111 return a; 112 } 113 114 struct cpu_md_ops cpu_md_ops; 115 116 struct cpu_softc cpu_softc[] = { 117 [0] = { 118 .cpu_ci = &cpu_info[0], 119 }, 120 #ifdef MULTIPROCESSOR 121 [CPU_MAXNUM-1] = { 122 .cpu_ci = &cpu_info[CPU_MAXNUM-1], 123 }, 124 #endif 125 }; 126 struct cpu_info cpu_info[] = { 127 [0] = { 128 .ci_curlwp = &lwp0, 129 .ci_tlb_info = &pmap_tlb0_info, 130 .ci_softc = &cpu_softc[0], 131 .ci_cpl = IPL_HIGH, 132 .ci_idepth = -1, 133 }, 134 #ifdef MULTIPROCESSOR 135 [CPU_MAXNUM-1] = { 136 .ci_curlwp = NULL, 137 .ci_tlb_info = &pmap_tlb0_info, 138 .ci_softc = &cpu_softc[CPU_MAXNUM-1], 139 .ci_cpl = IPL_HIGH, 140 .ci_idepth = -1, 141 }, 142 #endif 143 }; 144 __CTASSERT(__arraycount(cpu_info) == __arraycount(cpu_softc)); 145 146 /* 147 * This should probably be in autoconf! XXX 148 */ 149 char cpu_model[80]; 150 char machine[] = MACHINE; /* from <machine/param.h> */ 151 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 152 153 char bootpath[256]; 154 155 #if NKSYMS || defined(DDB) || defined(MODULAR) 156 void *startsym, *endsym; 157 #endif 158 159 #if defined(MULTIPROCESSOR) 160 volatile struct cpu_hatch_data cpu_hatch_data __cacheline_aligned; 161 #endif 162 163 int fake_mapiodev = 1; 164 165 void 166 booke_cpu_startup(const char *model) 167 { 168 vaddr_t minaddr, maxaddr; 169 char pbuf[9]; 170 171 strlcpy(cpu_model, model, sizeof(cpu_model)); 172 173 printf("%s%s", copyright, version); 174 175 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 176 printf("total memory = %s\n", pbuf); 177 178 minaddr = 0; 179 /* 180 * Allocate a submap for physio 181 */ 182 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 183 VM_PHYS_SIZE, 0, false, NULL); 184 185 /* 186 * No need to allocate an mbuf cluster submap. Mbuf clusters 187 * are allocated via the pool allocator, and we use direct-mapped 188 * pool pages. 189 */ 190 191 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 192 printf("avail memory = %s\n", pbuf); 193 194 /* 195 * Register the tlb's evcnts 196 */ 197 pmap_tlb_info_evcnt_attach(curcpu()->ci_tlb_info); 198 199 /* 200 * Set up the board properties database. 201 */ 202 board_info_init(); 203 204 /* 205 * Now that we have VM, malloc()s are OK in bus_space. 206 */ 207 bus_space_mallocok(); 208 fake_mapiodev = 0; 209 210 #ifdef MULTIPROCESSOR 211 for (size_t i = 1; i < __arraycount(cpu_info); i++) { 212 struct cpu_info * const ci = &cpu_info[i]; 213 struct cpu_softc * const cpu = &cpu_softc[i]; 214 cpu->cpu_ci = ci; 215 cpu->cpu_bst = cpu_softc[0].cpu_bst; 216 cpu->cpu_le_bst = cpu_softc[0].cpu_le_bst; 217 cpu->cpu_bsh = cpu_softc[0].cpu_bsh; 218 cpu->cpu_highmem = cpu_softc[0].cpu_highmem; 219 ci->ci_softc = cpu; 220 ci->ci_tlb_info = &pmap_tlb0_info; 221 ci->ci_cpl = IPL_HIGH; 222 ci->ci_idepth = -1; 223 ci->ci_pmap_kern_segtab = curcpu()->ci_pmap_kern_segtab; 224 } 225 #endif /* MULTIPROCESSOR */ 226 } 227 228 static void 229 dumpsys(void) 230 { 231 232 printf("dumpsys: TBD\n"); 233 } 234 235 /* 236 * Halt or reboot the machine after syncing/dumping according to howto. 237 */ 238 void 239 cpu_reboot(int howto, char *what) 240 { 241 static int syncing; 242 static char str[256]; 243 char *ap = str, *ap1 = ap; 244 245 boothowto = howto; 246 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 247 syncing = 1; 248 vfs_shutdown(); /* sync */ 249 resettodr(); /* set wall clock */ 250 } 251 252 splhigh(); 253 254 if (!cold && (howto & RB_DUMP)) 255 dumpsys(); 256 257 doshutdownhooks(); 258 259 pmf_system_shutdown(boothowto); 260 261 if ((howto & RB_POWERDOWN) == RB_POWERDOWN) { 262 /* Power off here if we know how...*/ 263 } 264 265 if (howto & RB_HALT) { 266 printf("halted\n\n"); 267 268 goto reboot; /* XXX for now... */ 269 270 #ifdef DDB 271 printf("dropping to debugger\n"); 272 while(1) 273 Debugger(); 274 #endif 275 } 276 277 printf("rebooting\n\n"); 278 if (what && *what) { 279 if (strlen(what) > sizeof str - 5) 280 printf("boot string too large, ignored\n"); 281 else { 282 strcpy(str, what); 283 ap1 = ap = str + strlen(str); 284 *ap++ = ' '; 285 } 286 } 287 *ap++ = '-'; 288 if (howto & RB_SINGLE) 289 *ap++ = 's'; 290 if (howto & RB_KDB) 291 *ap++ = 'd'; 292 *ap++ = 0; 293 if (ap[-2] == '-') 294 *ap1 = 0; 295 296 /* flush cache for msgbuf */ 297 dcache_wb(msgbuf_paddr, round_page(MSGBUFSIZE)); 298 299 reboot: 300 __asm volatile("msync; isync"); 301 (*cpu_md_ops.md_cpu_reset)(); 302 303 printf("%s: md_cpu_reset() failed!\n", __func__); 304 #ifdef DDB 305 for (;;) 306 Debugger(); 307 #else 308 for (;;) 309 /* nothing */; 310 #endif 311 } 312 313 /* 314 * mapiodev: 315 * 316 * Allocate vm space and mapin the I/O address. Use reserved TLB 317 * mapping if one is found. 318 */ 319 void * 320 mapiodev(paddr_t pa, psize_t len, bool prefetchable) 321 { 322 const vsize_t off = pa & PAGE_MASK; 323 324 /* 325 * See if we have reserved TLB entry for the pa. This needs to be 326 * true for console as we can't use uvm during early bootstrap. 327 */ 328 void * const p = tlb_mapiodev(pa, len, prefetchable); 329 if (p != NULL) 330 return p; 331 332 if (fake_mapiodev) 333 panic("mapiodev: no TLB entry reserved for %llx+%llx", 334 (long long)pa, (long long)len); 335 336 const paddr_t orig_pa = pa; 337 const psize_t orig_len = len; 338 vsize_t align = 0; 339 pa = trunc_page(pa); 340 len = round_page(off + len); 341 /* 342 * If we are allocating a large amount (>= 1MB) try to get an 343 * aligned VA region for it so try to do a large mapping for it. 344 */ 345 if ((len & (len - 1)) == 0 && len >= 0x100000) 346 align = len; 347 348 vaddr_t va = uvm_km_alloc(kernel_map, len, align, UVM_KMF_VAONLY); 349 350 if (va == 0 && align > 0) { 351 /* 352 * Large aligned request failed. Let's just get anything. 353 */ 354 align = 0; 355 va = uvm_km_alloc(kernel_map, len, align, UVM_KMF_VAONLY); 356 } 357 if (va == 0) 358 return NULL; 359 360 if (align) { 361 /* 362 * Now try to map that via one big TLB entry. 363 */ 364 pt_entry_t pte = pte_make_kenter_pa(pa, NULL, 365 VM_PROT_READ|VM_PROT_WRITE, 366 prefetchable ? 0 : PMAP_NOCACHE); 367 if (!tlb_ioreserve(va, len, pte)) { 368 void * const p0 = tlb_mapiodev(orig_pa, orig_len, 369 prefetchable); 370 KASSERT(p0 != NULL); 371 return p0; 372 } 373 } 374 375 for (va += len, pa += len; len > 0; len -= PAGE_SIZE) { 376 va -= PAGE_SIZE; 377 pa -= PAGE_SIZE; 378 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE, 379 prefetchable ? 0 : PMAP_NOCACHE); 380 } 381 pmap_update(pmap_kernel()); 382 return (void *)(va + off); 383 } 384 385 void 386 unmapiodev(vaddr_t va, vsize_t len) 387 { 388 /* Nothing to do for reserved (ie. not uvm_km_alloc'd) mappings. */ 389 if (va < VM_MIN_KERNEL_ADDRESS || va > VM_MAX_KERNEL_ADDRESS) { 390 tlb_unmapiodev(va, len); 391 return; 392 } 393 394 len = round_page((va & PAGE_MASK) + len); 395 va = trunc_page(va); 396 397 pmap_kremove(va, len); 398 uvm_km_free(kernel_map, va, len, UVM_KMF_VAONLY); 399 } 400 401 void 402 cpu_evcnt_attach(struct cpu_info *ci) 403 { 404 struct cpu_softc * const cpu = ci->ci_softc; 405 const char * const xname = ci->ci_data.cpu_name; 406 407 evcnt_attach_dynamic_nozero(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 408 NULL, xname, "clock"); 409 evcnt_attach_dynamic_nozero(&cpu->cpu_ev_late_clock, EVCNT_TYPE_INTR, 410 NULL, xname, "late clock"); 411 evcnt_attach_dynamic_nozero(&cpu->cpu_ev_exec_trap_sync, EVCNT_TYPE_TRAP, 412 NULL, xname, "exec pages synced (trap)"); 413 evcnt_attach_dynamic_nozero(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 414 NULL, xname, "traps"); 415 evcnt_attach_dynamic_nozero(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 416 &ci->ci_ev_traps, xname, "kernel DSI traps"); 417 evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 418 &ci->ci_ev_traps, xname, "user DSI traps"); 419 evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 420 &ci->ci_ev_udsi, xname, "user DSI failures"); 421 evcnt_attach_dynamic_nozero(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 422 &ci->ci_ev_traps, xname, "kernel ISI traps"); 423 evcnt_attach_dynamic_nozero(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 424 &ci->ci_ev_traps, xname, "user ISI traps"); 425 evcnt_attach_dynamic_nozero(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 426 &ci->ci_ev_isi, xname, "user ISI failures"); 427 evcnt_attach_dynamic_nozero(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 428 &ci->ci_ev_traps, xname, "system call traps"); 429 evcnt_attach_dynamic_nozero(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 430 &ci->ci_ev_traps, xname, "PGM traps"); 431 evcnt_attach_dynamic_nozero(&ci->ci_ev_debug, EVCNT_TYPE_TRAP, 432 &ci->ci_ev_traps, xname, "debug traps"); 433 evcnt_attach_dynamic_nozero(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 434 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 435 evcnt_attach_dynamic_nozero(&ci->ci_ev_fpusw, EVCNT_TYPE_MISC, 436 &ci->ci_ev_fpu, xname, "FPU context switches"); 437 evcnt_attach_dynamic_nozero(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 438 &ci->ci_ev_traps, xname, "user alignment traps"); 439 evcnt_attach_dynamic_nozero(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 440 &ci->ci_ev_ali, xname, "user alignment traps"); 441 evcnt_attach_dynamic_nozero(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 442 &ci->ci_ev_umchk, xname, "user MCHK failures"); 443 evcnt_attach_dynamic_nozero(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 444 &ci->ci_ev_traps, xname, "SPE unavailable"); 445 evcnt_attach_dynamic_nozero(&ci->ci_ev_vecsw, EVCNT_TYPE_MISC, 446 &ci->ci_ev_vec, xname, "SPE context switches"); 447 evcnt_attach_dynamic_nozero(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 448 NULL, xname, "IPIs"); 449 evcnt_attach_dynamic_nozero(&ci->ci_ev_tlbmiss_soft, EVCNT_TYPE_TRAP, 450 &ci->ci_ev_traps, xname, "soft tlb misses"); 451 evcnt_attach_dynamic_nozero(&ci->ci_ev_dtlbmiss_hard, EVCNT_TYPE_TRAP, 452 &ci->ci_ev_traps, xname, "data tlb misses"); 453 evcnt_attach_dynamic_nozero(&ci->ci_ev_itlbmiss_hard, EVCNT_TYPE_TRAP, 454 &ci->ci_ev_traps, xname, "inst tlb misses"); 455 } 456 457 #ifdef MULTIPROCESSOR 458 register_t 459 cpu_hatch(void) 460 { 461 volatile struct cpuset_info * const csi = &cpuset_info; 462 const size_t id = cpu_number(); 463 464 /* 465 * We've hatched so tell the spinup code. 466 */ 467 CPUSET_ADD(csi->cpus_hatched, id); 468 469 /* 470 * Loop until running bit for this cpu is set. 471 */ 472 while (!CPUSET_HAS_P(csi->cpus_running, id)) { 473 continue; 474 } 475 476 /* 477 * Now that we are active, start the clocks. 478 */ 479 cpu_initclocks(); 480 481 /* 482 * Return sp of the idlelwp. Which we should be already using but ... 483 */ 484 return curcpu()->ci_curpcb->pcb_sp; 485 } 486 487 void 488 cpu_boot_secondary_processors(void) 489 { 490 volatile struct cpuset_info * const csi = &cpuset_info; 491 CPU_INFO_ITERATOR cii; 492 struct cpu_info *ci; 493 __cpuset_t running = CPUSET_NULLSET; 494 495 for (CPU_INFO_FOREACH(cii, ci)) { 496 /* 497 * Skip this CPU if it didn't sucessfully hatch. 498 */ 499 if (! CPUSET_HAS_P(csi->cpus_hatched, cpu_index(ci))) 500 continue; 501 502 KASSERT(!CPU_IS_PRIMARY(ci)); 503 KASSERT(ci->ci_data.cpu_idlelwp); 504 505 CPUSET_ADD(running, cpu_index(ci)); 506 } 507 KASSERT(CPUSET_EQUAL_P(csi->cpus_hatched, running)); 508 if (!CPUSET_EMPTY_P(running)) { 509 CPUSET_ADDSET(csi->cpus_running, running); 510 } 511 } 512 #endif 513 514 uint32_t 515 cpu_read_4(bus_addr_t a) 516 { 517 struct cpu_softc * const cpu = curcpu()->ci_softc; 518 // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 519 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, a); 520 } 521 522 uint8_t 523 cpu_read_1(bus_addr_t a) 524 { 525 struct cpu_softc * const cpu = curcpu()->ci_softc; 526 // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 527 return bus_space_read_1(cpu->cpu_bst, cpu->cpu_bsh, a); 528 } 529 530 void 531 cpu_write_4(bus_addr_t a, uint32_t v) 532 { 533 struct cpu_softc * const cpu = curcpu()->ci_softc; 534 bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, a, v); 535 } 536 537 void 538 cpu_write_1(bus_addr_t a, uint8_t v) 539 { 540 struct cpu_softc * const cpu = curcpu()->ci_softc; 541 bus_space_write_1(cpu->cpu_bst, cpu->cpu_bsh, a, v); 542 } 543 544 void 545 booke_sstep(struct trapframe *tf) 546 { 547 KASSERT(tf->tf_srr1 & PSL_DE); 548 const uint32_t insn = ufetch_32((const void *)tf->tf_srr0); 549 register_t dbcr0 = DBCR0_IAC1 | DBCR0_IDM; 550 register_t dbcr1 = DBCR1_IAC1US_USER | DBCR1_IAC1ER_DS1; 551 if ((insn >> 28) == 4) { 552 uint32_t iac2 = 0; 553 if ((insn >> 26) == 0x12) { 554 const int32_t off = (((int32_t)insn << 6) >> 6) & ~3; 555 iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 556 dbcr0 |= DBCR0_IAC2; 557 } else if ((insn >> 26) == 0x10) { 558 const int16_t off = insn & ~3; 559 iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 560 dbcr0 |= DBCR0_IAC2; 561 } else if ((insn & 0xfc00ffde) == 0x4c000420) { 562 iac2 = tf->tf_ctr; 563 dbcr0 |= DBCR0_IAC2; 564 } else if ((insn & 0xfc00ffde) == 0x4c000020) { 565 iac2 = tf->tf_lr; 566 dbcr0 |= DBCR0_IAC2; 567 } 568 if (dbcr0 & DBCR0_IAC2) { 569 dbcr1 |= DBCR1_IAC2US_USER | DBCR1_IAC2ER_DS1; 570 mtspr(SPR_IAC2, iac2); 571 } 572 } 573 mtspr(SPR_IAC1, tf->tf_srr0 + 4); 574 mtspr(SPR_DBCR1, dbcr1); 575 mtspr(SPR_DBCR0, dbcr0); 576 } 577 578 #ifdef DIAGNOSTIC 579 static inline void 580 swap_data(uint64_t *data, size_t a, size_t b) 581 { 582 uint64_t swap = data[a]; 583 data[a] = data[b]; 584 data[b] = swap; 585 } 586 587 static void 588 sort_data(uint64_t *data, size_t count) 589 { 590 #if 0 591 /* 592 * Mostly classic bubble sort 593 */ 594 do { 595 size_t new_count = 0; 596 for (size_t i = 1; i < count; i++) { 597 if (tbs[i - 1] > tbs[i]) { 598 swap_tbs(tbs, i - 1, i); 599 new_count = i; 600 } 601 } 602 count = new_count; 603 } while (count > 0); 604 #else 605 /* 606 * Comb sort 607 */ 608 size_t gap = count; 609 bool swapped = false; 610 while (gap > 1 || swapped) { 611 if (gap > 1) { 612 /* 613 * phi = (1 + sqrt(5)) / 2 [golden ratio] 614 * N = 1 / (1 - e^-phi)) = 1.247330950103979 615 * 616 * We want to but can't use floating point to calculate 617 * gap = (size_t)((double)gap / N) 618 * 619 * So we will use the multicative inverse of N 620 * (module 65536) to achieve the division. 621 * 622 * iN = 2^16 / 1.24733... = 52540 623 * x / N == (x * iN) / 65536 624 */ 625 gap = (gap * 52540) / 65536; 626 } 627 628 swapped = false; 629 630 for (size_t i = 0; gap + i < count; i++) { 631 if (data[i] > data[i + gap]) { 632 swap_data(data, i, i + gap); 633 swapped = true; 634 } 635 } 636 } 637 #endif 638 } 639 #endif 640 641 void 642 dump_splhist(struct cpu_info *ci, void (*pr)(const char *, ...)) 643 { 644 #ifdef DIAGNOSTIC 645 struct cpu_softc * const cpu = ci->ci_softc; 646 uint64_t tbs[NIPL*NIPL]; 647 size_t ntbs = 0; 648 for (size_t to = 0; to < NIPL; to++) { 649 for (size_t from = 0; from < NIPL; from++) { 650 uint64_t tb = cpu->cpu_spl_tb[to][from]; 651 if (tb == 0) 652 continue; 653 tbs[ntbs++] = (tb << 8) | (to << 4) | from; 654 } 655 } 656 sort_data(tbs, ntbs); 657 658 if (pr == NULL) 659 pr = printf; 660 uint64_t last_tb = 0; 661 for (size_t i = 0; i < ntbs; i++) { 662 uint64_t tb = tbs[i]; 663 size_t from = tb & 15; 664 size_t to = (tb >> 4) & 15; 665 tb >>= 8; 666 (*pr)("%s(%zu) from %zu at %"PRId64"", 667 from < to ? "splraise" : "splx", 668 to, from, tb); 669 if (last_tb && from != IPL_NONE) 670 (*pr)(" (+%"PRId64")", tb - last_tb); 671 (*pr)("\n"); 672 last_tb = tb; 673 } 674 #endif 675 } 676
Indexes created Tue Sep 30 11:09:46 GMT 2025