booke_machdep.c revision 1.21
1 /* $NetBSD: booke_machdep.c,v 1.21 2014/09/22 21:35:15 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #define __INTR_PRIVATE 38 #define _POWERPC_BUS_DMA_PRIVATE 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: booke_machdep.c,v 1.21 2014/09/22 21:35:15 matt Exp $"); 42 43 #include "opt_modular.h" 44 45 #include <sys/param.h> 46 #include <sys/cpu.h> 47 #include <sys/device.h> 48 #include <sys/intr.h> 49 #include <sys/mount.h> 50 #include <sys/msgbuf.h> 51 #include <sys/kernel.h> 52 #include <sys/reboot.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <powerpc/pcb.h> 59 #include <powerpc/spr.h> 60 #include <powerpc/booke/spr.h> 61 #include <powerpc/booke/cpuvar.h> 62 63 /* 64 * Global variables used here and there 65 */ 66 paddr_t msgbuf_paddr; 67 psize_t pmemsize; 68 struct vm_map *phys_map; 69 70 #ifdef MODULAR 71 register_t cpu_psluserset = PSL_USERSET; 72 register_t cpu_pslusermod = PSL_USERMOD; 73 register_t cpu_pslusermask = PSL_USERMASK; 74 #endif 75 76 static bus_addr_t booke_dma_phys_to_bus_mem(bus_dma_tag_t, bus_addr_t); 77 static bus_addr_t booke_dma_bus_mem_to_phys(bus_dma_tag_t, bus_addr_t); 78 79 80 struct powerpc_bus_dma_tag booke_bus_dma_tag = { 81 ._dmamap_create = _bus_dmamap_create, 82 ._dmamap_destroy = _bus_dmamap_destroy, 83 ._dmamap_load = _bus_dmamap_load, 84 ._dmamap_load_mbuf = _bus_dmamap_load_mbuf, 85 ._dmamap_load_uio = _bus_dmamap_load_uio, 86 ._dmamap_load_raw = _bus_dmamap_load_raw, 87 ._dmamap_unload = _bus_dmamap_unload, 88 /* 89 * The caches on BookE are coherent so we don't need to do any special 90 * cache synchronization. 91 */ 92 //._dmamap_sync = _bus_dmamap_sync, 93 ._dmamem_alloc = _bus_dmamem_alloc, 94 ._dmamem_free = _bus_dmamem_free, 95 ._dmamem_map = _bus_dmamem_map, 96 ._dmamem_unmap = _bus_dmamem_unmap, 97 ._dmamem_mmap = _bus_dmamem_mmap, 98 ._dma_phys_to_bus_mem = booke_dma_phys_to_bus_mem, 99 ._dma_bus_mem_to_phys = booke_dma_bus_mem_to_phys, 100 }; 101 102 static bus_addr_t 103 booke_dma_phys_to_bus_mem(bus_dma_tag_t t, bus_addr_t a) 104 { 105 return a; 106 } 107 108 static bus_addr_t 109 booke_dma_bus_mem_to_phys(bus_dma_tag_t t, bus_addr_t a) 110 { 111 return a; 112 } 113 114 struct cpu_md_ops cpu_md_ops; 115 116 struct cpu_softc cpu_softc[] = { 117 [0] = { 118 .cpu_ci = &cpu_info[0], 119 }, 120 #ifdef MULTIPROCESSOR 121 [CPU_MAXNUM-1] = { 122 .cpu_ci = &cpu_info[CPU_MAXNUM-1], 123 }, 124 #endif 125 }; 126 struct cpu_info cpu_info[] = { 127 [0] = { 128 .ci_curlwp = &lwp0, 129 .ci_tlb_info = &pmap_tlb0_info, 130 .ci_softc = &cpu_softc[0], 131 .ci_cpl = IPL_HIGH, 132 .ci_idepth = -1, 133 }, 134 #ifdef MULTIPROCESSOR 135 [CPU_MAXNUM-1] = { 136 .ci_curlwp = NULL, 137 .ci_tlb_info = &pmap_tlb0_info, 138 .ci_softc = &cpu_softc[CPU_MAXNUM-1], 139 .ci_cpl = IPL_HIGH, 140 .ci_idepth = -1, 141 }, 142 #endif 143 }; 144 __CTASSERT(__arraycount(cpu_info) == __arraycount(cpu_softc)); 145 146 /* 147 * This should probably be in autoconf! XXX 148 */ 149 char machine[] = MACHINE; /* from <machine/param.h> */ 150 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 151 152 char bootpath[256]; 153 154 #if NKSYMS || defined(DDB) || defined(MODULAR) 155 void *startsym, *endsym; 156 #endif 157 158 #if defined(MULTIPROCESSOR) 159 volatile struct cpu_hatch_data cpu_hatch_data __cacheline_aligned; 160 #endif 161 162 int fake_mapiodev = 1; 163 164 void 165 booke_cpu_startup(const char *model) 166 { 167 vaddr_t minaddr, maxaddr; 168 char pbuf[9]; 169 170 cpu_setmodel("%s", model); 171 172 printf("%s%s", copyright, version); 173 174 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 175 printf("total memory = %s\n", pbuf); 176 177 minaddr = 0; 178 /* 179 * Allocate a submap for physio 180 */ 181 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 182 VM_PHYS_SIZE, 0, false, NULL); 183 184 /* 185 * No need to allocate an mbuf cluster submap. Mbuf clusters 186 * are allocated via the pool allocator, and we use direct-mapped 187 * pool pages. 188 */ 189 190 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 191 printf("avail memory = %s\n", pbuf); 192 193 /* 194 * Register the tlb's evcnts 195 */ 196 pmap_tlb_info_evcnt_attach(curcpu()->ci_tlb_info); 197 198 /* 199 * Set up the board properties database. 200 */ 201 board_info_init(); 202 203 /* 204 * Now that we have VM, malloc()s are OK in bus_space. 205 */ 206 bus_space_mallocok(); 207 fake_mapiodev = 0; 208 209 #ifdef MULTIPROCESSOR 210 for (size_t i = 1; i < __arraycount(cpu_info); i++) { 211 struct cpu_info * const ci = &cpu_info[i]; 212 struct cpu_softc * const cpu = &cpu_softc[i]; 213 cpu->cpu_ci = ci; 214 cpu->cpu_bst = cpu_softc[0].cpu_bst; 215 cpu->cpu_le_bst = cpu_softc[0].cpu_le_bst; 216 cpu->cpu_bsh = cpu_softc[0].cpu_bsh; 217 cpu->cpu_highmem = cpu_softc[0].cpu_highmem; 218 ci->ci_softc = cpu; 219 ci->ci_tlb_info = &pmap_tlb0_info; 220 ci->ci_cpl = IPL_HIGH; 221 ci->ci_idepth = -1; 222 ci->ci_pmap_kern_segtab = curcpu()->ci_pmap_kern_segtab; 223 } 224 225 kcpuset_create(&cpuset_info.cpus_running, true); 226 kcpuset_create(&cpuset_info.cpus_hatched, true); 227 kcpuset_create(&cpuset_info.cpus_paused, true); 228 kcpuset_create(&cpuset_info.cpus_resumed, true); 229 kcpuset_create(&cpuset_info.cpus_halted, true); 230 #endif /* MULTIPROCESSOR */ 231 } 232 233 static void 234 dumpsys(void) 235 { 236 237 printf("dumpsys: TBD\n"); 238 } 239 240 /* 241 * Halt or reboot the machine after syncing/dumping according to howto. 242 */ 243 void 244 cpu_reboot(int howto, char *what) 245 { 246 static int syncing; 247 static char str[256]; 248 char *ap = str, *ap1 = ap; 249 250 boothowto = howto; 251 if (!cold && !(howto & RB_NOSYNC) && !syncing) { 252 syncing = 1; 253 vfs_shutdown(); /* sync */ 254 resettodr(); /* set wall clock */ 255 } 256 257 splhigh(); 258 259 if (!cold && (howto & RB_DUMP)) 260 dumpsys(); 261 262 doshutdownhooks(); 263 264 pmf_system_shutdown(boothowto); 265 266 if ((howto & RB_POWERDOWN) == RB_POWERDOWN) { 267 /* Power off here if we know how...*/ 268 } 269 270 if (howto & RB_HALT) { 271 printf("halted\n\n"); 272 273 goto reboot; /* XXX for now... */ 274 275 #ifdef DDB 276 printf("dropping to debugger\n"); 277 while(1) 278 Debugger(); 279 #endif 280 } 281 282 printf("rebooting\n\n"); 283 if (what && *what) { 284 if (strlen(what) > sizeof str - 5) 285 printf("boot string too large, ignored\n"); 286 else { 287 strcpy(str, what); 288 ap1 = ap = str + strlen(str); 289 *ap++ = ' '; 290 } 291 } 292 *ap++ = '-'; 293 if (howto & RB_SINGLE) 294 *ap++ = 's'; 295 if (howto & RB_KDB) 296 *ap++ = 'd'; 297 *ap++ = 0; 298 if (ap[-2] == '-') 299 *ap1 = 0; 300 301 /* flush cache for msgbuf */ 302 dcache_wb(msgbuf_paddr, round_page(MSGBUFSIZE)); 303 304 reboot: 305 __asm volatile("msync; isync"); 306 (*cpu_md_ops.md_cpu_reset)(); 307 308 printf("%s: md_cpu_reset() failed!\n", __func__); 309 #ifdef DDB 310 for (;;) 311 Debugger(); 312 #else 313 for (;;) 314 /* nothing */; 315 #endif 316 } 317 318 /* 319 * mapiodev: 320 * 321 * Allocate vm space and mapin the I/O address. Use reserved TLB 322 * mapping if one is found. 323 */ 324 void * 325 mapiodev(paddr_t pa, psize_t len, bool prefetchable) 326 { 327 const vsize_t off = pa & PAGE_MASK; 328 329 /* 330 * See if we have reserved TLB entry for the pa. This needs to be 331 * true for console as we can't use uvm during early bootstrap. 332 */ 333 void * const p = tlb_mapiodev(pa, len, prefetchable); 334 if (p != NULL) 335 return p; 336 337 if (fake_mapiodev) 338 panic("mapiodev: no TLB entry reserved for %llx+%llx", 339 (long long)pa, (long long)len); 340 341 const paddr_t orig_pa = pa; 342 const psize_t orig_len = len; 343 vsize_t align = 0; 344 pa = trunc_page(pa); 345 len = round_page(off + len); 346 /* 347 * If we are allocating a large amount (>= 1MB) try to get an 348 * aligned VA region for it so try to do a large mapping for it. 349 */ 350 if ((len & (len - 1)) == 0 && len >= 0x100000) 351 align = len; 352 353 vaddr_t va = uvm_km_alloc(kernel_map, len, align, UVM_KMF_VAONLY); 354 355 if (va == 0 && align > 0) { 356 /* 357 * Large aligned request failed. Let's just get anything. 358 */ 359 align = 0; 360 va = uvm_km_alloc(kernel_map, len, align, UVM_KMF_VAONLY); 361 } 362 if (va == 0) 363 return NULL; 364 365 if (align) { 366 /* 367 * Now try to map that via one big TLB entry. 368 */ 369 pt_entry_t pte = pte_make_kenter_pa(pa, NULL, 370 VM_PROT_READ|VM_PROT_WRITE, 371 prefetchable ? 0 : PMAP_NOCACHE); 372 if (!tlb_ioreserve(va, len, pte)) { 373 void * const p0 = tlb_mapiodev(orig_pa, orig_len, 374 prefetchable); 375 KASSERT(p0 != NULL); 376 return p0; 377 } 378 } 379 380 for (va += len, pa += len; len > 0; len -= PAGE_SIZE) { 381 va -= PAGE_SIZE; 382 pa -= PAGE_SIZE; 383 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE, 384 prefetchable ? 0 : PMAP_NOCACHE); 385 } 386 pmap_update(pmap_kernel()); 387 return (void *)(va + off); 388 } 389 390 void 391 unmapiodev(vaddr_t va, vsize_t len) 392 { 393 /* Nothing to do for reserved (ie. not uvm_km_alloc'd) mappings. */ 394 if (va < VM_MIN_KERNEL_ADDRESS || va > VM_MAX_KERNEL_ADDRESS) { 395 tlb_unmapiodev(va, len); 396 return; 397 } 398 399 len = round_page((va & PAGE_MASK) + len); 400 va = trunc_page(va); 401 402 pmap_kremove(va, len); 403 uvm_km_free(kernel_map, va, len, UVM_KMF_VAONLY); 404 } 405 406 void 407 cpu_evcnt_attach(struct cpu_info *ci) 408 { 409 struct cpu_softc * const cpu = ci->ci_softc; 410 const char * const xname = ci->ci_data.cpu_name; 411 412 evcnt_attach_dynamic_nozero(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 413 NULL, xname, "clock"); 414 evcnt_attach_dynamic_nozero(&cpu->cpu_ev_late_clock, EVCNT_TYPE_INTR, 415 NULL, xname, "late clock"); 416 evcnt_attach_dynamic_nozero(&cpu->cpu_ev_exec_trap_sync, EVCNT_TYPE_TRAP, 417 NULL, xname, "exec pages synced (trap)"); 418 evcnt_attach_dynamic_nozero(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 419 NULL, xname, "traps"); 420 evcnt_attach_dynamic_nozero(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 421 &ci->ci_ev_traps, xname, "kernel DSI traps"); 422 evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 423 &ci->ci_ev_traps, xname, "user DSI traps"); 424 evcnt_attach_dynamic_nozero(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 425 &ci->ci_ev_udsi, xname, "user DSI failures"); 426 evcnt_attach_dynamic_nozero(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 427 &ci->ci_ev_traps, xname, "kernel ISI traps"); 428 evcnt_attach_dynamic_nozero(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 429 &ci->ci_ev_traps, xname, "user ISI traps"); 430 evcnt_attach_dynamic_nozero(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 431 &ci->ci_ev_isi, xname, "user ISI failures"); 432 evcnt_attach_dynamic_nozero(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 433 &ci->ci_ev_traps, xname, "system call traps"); 434 evcnt_attach_dynamic_nozero(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 435 &ci->ci_ev_traps, xname, "PGM traps"); 436 evcnt_attach_dynamic_nozero(&ci->ci_ev_debug, EVCNT_TYPE_TRAP, 437 &ci->ci_ev_traps, xname, "debug traps"); 438 evcnt_attach_dynamic_nozero(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 439 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 440 evcnt_attach_dynamic_nozero(&ci->ci_ev_fpusw, EVCNT_TYPE_MISC, 441 &ci->ci_ev_fpu, xname, "FPU context switches"); 442 evcnt_attach_dynamic_nozero(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 443 &ci->ci_ev_traps, xname, "user alignment traps"); 444 evcnt_attach_dynamic_nozero(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 445 &ci->ci_ev_ali, xname, "user alignment traps"); 446 evcnt_attach_dynamic_nozero(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 447 &ci->ci_ev_umchk, xname, "user MCHK failures"); 448 evcnt_attach_dynamic_nozero(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 449 &ci->ci_ev_traps, xname, "SPE unavailable"); 450 evcnt_attach_dynamic_nozero(&ci->ci_ev_vecsw, EVCNT_TYPE_MISC, 451 &ci->ci_ev_vec, xname, "SPE context switches"); 452 evcnt_attach_dynamic_nozero(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 453 NULL, xname, "IPIs"); 454 evcnt_attach_dynamic_nozero(&ci->ci_ev_tlbmiss_soft, EVCNT_TYPE_TRAP, 455 &ci->ci_ev_traps, xname, "soft tlb misses"); 456 evcnt_attach_dynamic_nozero(&ci->ci_ev_dtlbmiss_hard, EVCNT_TYPE_TRAP, 457 &ci->ci_ev_traps, xname, "data tlb misses"); 458 evcnt_attach_dynamic_nozero(&ci->ci_ev_itlbmiss_hard, EVCNT_TYPE_TRAP, 459 &ci->ci_ev_traps, xname, "inst tlb misses"); 460 } 461 462 #ifdef MULTIPROCESSOR 463 register_t 464 cpu_hatch(void) 465 { 466 struct cpuset_info * const csi = &cpuset_info; 467 const size_t id = cpu_number(); 468 469 /* 470 * We've hatched so tell the spinup code. 471 */ 472 kcpuset_set(csi->cpus_hatched, id); 473 474 /* 475 * Loop until running bit for this cpu is set. 476 */ 477 while (!kcpuset_isset(csi->cpus_running, id)) { 478 continue; 479 } 480 481 /* 482 * Now that we are active, start the clocks. 483 */ 484 cpu_initclocks(); 485 486 /* 487 * Return sp of the idlelwp. Which we should be already using but ... 488 */ 489 return curcpu()->ci_curpcb->pcb_sp; 490 } 491 492 void 493 cpu_boot_secondary_processors(void) 494 { 495 volatile struct cpuset_info * const csi = &cpuset_info; 496 CPU_INFO_ITERATOR cii; 497 struct cpu_info *ci; 498 kcpuset_t *running; 499 500 kcpuset_create(&running, true); 501 502 for (CPU_INFO_FOREACH(cii, ci)) { 503 /* 504 * Skip this CPU if it didn't sucessfully hatch. 505 */ 506 if (!kcpuset_isset(csi->cpus_hatched, cpu_index(ci))) 507 continue; 508 509 KASSERT(!CPU_IS_PRIMARY(ci)); 510 KASSERT(ci->ci_data.cpu_idlelwp); 511 512 kcpuset_set(running, cpu_index(ci)); 513 } 514 KASSERT(kcpuset_match(csi->cpus_hatched, running)); 515 if (!kcpuset_iszero(running)) { 516 kcpuset_merge(csi->cpus_running, running); 517 } 518 kcpuset_destroy(running); 519 } 520 #endif 521 522 uint32_t 523 cpu_read_4(bus_addr_t a) 524 { 525 struct cpu_softc * const cpu = curcpu()->ci_softc; 526 // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 527 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, a); 528 } 529 530 uint8_t 531 cpu_read_1(bus_addr_t a) 532 { 533 struct cpu_softc * const cpu = curcpu()->ci_softc; 534 // printf(" %s(%p, %x, %x)", __func__, cpu->cpu_bst, cpu->cpu_bsh, a); 535 return bus_space_read_1(cpu->cpu_bst, cpu->cpu_bsh, a); 536 } 537 538 void 539 cpu_write_4(bus_addr_t a, uint32_t v) 540 { 541 struct cpu_softc * const cpu = curcpu()->ci_softc; 542 bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, a, v); 543 } 544 545 void 546 cpu_write_1(bus_addr_t a, uint8_t v) 547 { 548 struct cpu_softc * const cpu = curcpu()->ci_softc; 549 bus_space_write_1(cpu->cpu_bst, cpu->cpu_bsh, a, v); 550 } 551 552 void 553 booke_sstep(struct trapframe *tf) 554 { 555 KASSERT(tf->tf_srr1 & PSL_DE); 556 const uint32_t insn = ufetch_32((const void *)tf->tf_srr0); 557 register_t dbcr0 = DBCR0_IAC1 | DBCR0_IDM; 558 register_t dbcr1 = DBCR1_IAC1US_USER | DBCR1_IAC1ER_DS1; 559 if ((insn >> 28) == 4) { 560 uint32_t iac2 = 0; 561 if ((insn >> 26) == 0x12) { 562 const int32_t off = (((int32_t)insn << 6) >> 6) & ~3; 563 iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 564 dbcr0 |= DBCR0_IAC2; 565 } else if ((insn >> 26) == 0x10) { 566 const int16_t off = insn & ~3; 567 iac2 = ((insn & 2) ? 0 : tf->tf_srr0) + off; 568 dbcr0 |= DBCR0_IAC2; 569 } else if ((insn & 0xfc00fffe) == 0x4c000420) { 570 iac2 = tf->tf_ctr; 571 dbcr0 |= DBCR0_IAC2; 572 } else if ((insn & 0xfc00fffe) == 0x4c000020) { 573 iac2 = tf->tf_lr; 574 dbcr0 |= DBCR0_IAC2; 575 } 576 if (dbcr0 & DBCR0_IAC2) { 577 dbcr1 |= DBCR1_IAC2US_USER | DBCR1_IAC2ER_DS1; 578 mtspr(SPR_IAC2, iac2); 579 } 580 } 581 mtspr(SPR_IAC1, tf->tf_srr0 + 4); 582 mtspr(SPR_DBCR1, dbcr1); 583 mtspr(SPR_DBCR0, dbcr0); 584 } 585 586 #ifdef DIAGNOSTIC 587 static inline void 588 swap_data(uint64_t *data, size_t a, size_t b) 589 { 590 uint64_t swap = data[a]; 591 data[a] = data[b]; 592 data[b] = swap; 593 } 594 595 static void 596 sort_data(uint64_t *data, size_t count) 597 { 598 #if 0 599 /* 600 * Mostly classic bubble sort 601 */ 602 do { 603 size_t new_count = 0; 604 for (size_t i = 1; i < count; i++) { 605 if (tbs[i - 1] > tbs[i]) { 606 swap_tbs(tbs, i - 1, i); 607 new_count = i; 608 } 609 } 610 count = new_count; 611 } while (count > 0); 612 #else 613 /* 614 * Comb sort 615 */ 616 size_t gap = count; 617 bool swapped = false; 618 while (gap > 1 || swapped) { 619 if (gap > 1) { 620 /* 621 * phi = (1 + sqrt(5)) / 2 [golden ratio] 622 * N = 1 / (1 - e^-phi)) = 1.247330950103979 623 * 624 * We want to but can't use floating point to calculate 625 * gap = (size_t)((double)gap / N) 626 * 627 * So we will use the multicative inverse of N 628 * (module 65536) to achieve the division. 629 * 630 * iN = 2^16 / 1.24733... = 52540 631 * x / N == (x * iN) / 65536 632 */ 633 gap = (gap * 52540) / 65536; 634 } 635 636 swapped = false; 637 638 for (size_t i = 0; gap + i < count; i++) { 639 if (data[i] > data[i + gap]) { 640 swap_data(data, i, i + gap); 641 swapped = true; 642 } 643 } 644 } 645 #endif 646 } 647 #endif 648 649 void 650 dump_splhist(struct cpu_info *ci, void (*pr)(const char *, ...)) 651 { 652 #ifdef DIAGNOSTIC 653 struct cpu_softc * const cpu = ci->ci_softc; 654 uint64_t tbs[NIPL*NIPL]; 655 size_t ntbs = 0; 656 for (size_t to = 0; to < NIPL; to++) { 657 for (size_t from = 0; from < NIPL; from++) { 658 uint64_t tb = cpu->cpu_spl_tb[to][from]; 659 if (tb == 0) 660 continue; 661 tbs[ntbs++] = (tb << 8) | (to << 4) | from; 662 } 663 } 664 sort_data(tbs, ntbs); 665 666 if (pr == NULL) 667 pr = printf; 668 uint64_t last_tb = 0; 669 for (size_t i = 0; i < ntbs; i++) { 670 uint64_t tb = tbs[i]; 671 size_t from = tb & 15; 672 size_t to = (tb >> 4) & 15; 673 tb >>= 8; 674 (*pr)("%s(%zu) from %zu at %"PRId64"", 675 from < to ? "splraise" : "splx", 676 to, from, tb); 677 if (last_tb && from != IPL_NONE) 678 (*pr)(" (+%"PRId64")", tb - last_tb); 679 (*pr)("\n"); 680 last_tb = tb; 681 } 682 #endif 683 } 684
Indexes created Mon Sep 29 21:09:56 GMT 2025