booke_pmap.c revision 1.30 1 /* $NetBSD: booke_pmap.c,v 1.30 2020/12/20 16:38:25 skrll Exp $ */
2 /*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 *
10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #define __PMAP_PRIVATE
38
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: booke_pmap.c,v 1.30 2020/12/20 16:38:25 skrll Exp $");
41
42 #ifdef _KERNEL_OPT
43 #include "opt_multiprocessor.h"
44 #include "opt_pmap.h"
45 #endif
46
47 #include <sys/param.h>
48 #include <sys/kcore.h>
49 #include <sys/buf.h>
50 #include <sys/mutex.h>
51
52 #include <uvm/uvm.h>
53
54 #include <machine/pmap.h>
55
56 PMAP_COUNTER(zeroed_pages, "pages zeroed");
57 PMAP_COUNTER(copied_pages, "pages copied");
58
59 CTASSERT(sizeof(pmap_segtab_t) == NBPG);
60
61 void
62 pmap_procwr(struct proc *p, vaddr_t va, size_t len)
63 {
64 struct pmap * const pmap = p->p_vmspace->vm_map.pmap;
65 vsize_t off = va & PAGE_SIZE;
66
67 kpreempt_disable();
68 for (const vaddr_t eva = va + len; va < eva; off = 0) {
69 const vaddr_t segeva = uimin(va + len, va - off + PAGE_SIZE);
70 pt_entry_t * const ptep = pmap_pte_lookup(pmap, va);
71 if (ptep == NULL) {
72 va = segeva;
73 continue;
74 }
75 pt_entry_t pt_entry = *ptep;
76 if (!pte_valid_p(pt_entry) || !pte_exec_p(pt_entry)) {
77 va = segeva;
78 continue;
79 }
80 kpreempt_enable();
81 dcache_wb(pte_to_paddr(pt_entry), segeva - va);
82 icache_inv(pte_to_paddr(pt_entry), segeva - va);
83 kpreempt_disable();
84 va = segeva;
85 }
86 kpreempt_enable();
87 }
88
89 void
90 pmap_md_page_syncicache(struct vm_page_md *mdpg, const kcpuset_t *onproc)
91 {
92 KASSERT(VM_PAGEMD_VMPAGE_P(mdpg));
93
94 struct vm_page * const pg = VM_MD_TO_PAGE(mdpg);
95
96 /*
97 * If onproc is empty, we could do a
98 * pmap_page_protect(pg, VM_PROT_NONE) and remove all
99 * mappings of the page and clear its execness. Then
100 * the next time page is faulted, it will get icache
101 * synched. But this is easier. :)
102 */
103 paddr_t pa = VM_PAGE_TO_PHYS(pg);
104 dcache_wb_page(pa);
105 icache_inv_page(pa);
106 }
107
108 vaddr_t
109 pmap_md_direct_map_paddr(paddr_t pa)
110 {
111 return (vaddr_t) pa;
112 }
113
114 bool
115 pmap_md_direct_mapped_vaddr_p(vaddr_t va)
116 {
117 return va < VM_MIN_KERNEL_ADDRESS || VM_MAX_KERNEL_ADDRESS <= va;
118 }
119
120 paddr_t
121 pmap_md_direct_mapped_vaddr_to_paddr(vaddr_t va)
122 {
123 return (paddr_t) va;
124 }
125
126 #ifdef PMAP_MINIMALTLB
127 static pt_entry_t *
128 kvtopte(const pmap_segtab_t *stp, vaddr_t va)
129 {
130 pt_entry_t * const ptep = stp->seg_tab[va >> SEGSHIFT];
131 if (ptep == NULL)
132 return NULL;
133 return &ptep[(va & SEGOFSET) >> PAGE_SHIFT];
134 }
135
136 vaddr_t
137 pmap_kvptefill(vaddr_t sva, vaddr_t eva, pt_entry_t pt_entry)
138 {
139 pmap_segtab_t * const stp = &pmap_kern_segtab;
140 KASSERT(sva == trunc_page(sva));
141 pt_entry_t *ptep = kvtopte(stp, sva);
142 for (; sva < eva; sva += NBPG) {
143 *ptep++ = pt_entry ? (sva | pt_entry) : 0;
144 }
145 return sva;
146 }
147 #endif
148
149 /*
150 * Bootstrap the system enough to run with virtual memory.
151 * firstaddr is the first unused kseg0 address (not page aligned).
152 */
153 vaddr_t
154 pmap_bootstrap(vaddr_t startkernel, vaddr_t endkernel,
155 phys_ram_seg_t *avail, size_t cnt)
156 {
157 pmap_segtab_t * const stp = &pmap_kern_segtab;
158
159 KASSERT(endkernel == trunc_page(endkernel));
160
161 /* common initialization */
162 pmap_bootstrap_common();
163
164 /* init the lock */
165 pmap_tlb_info_init(&pmap_tlb0_info);
166
167 /*
168 * Compute the number of pages kmem_arena will have.
169 */
170 kmeminit_nkmempages();
171
172 /*
173 * Figure out how many PTE's are necessary to map the kernel.
174 * We also reserve space for kmem_alloc_pageable() for vm_fork().
175 */
176
177 /* Get size of buffer cache and set an upper limit */
178 buf_setvalimit((VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS) / 8);
179 vsize_t bufsz = buf_memcalc();
180 buf_setvalimit(bufsz);
181
182 vsize_t kv_nsegtabs = pmap_round_seg(VM_PHYS_SIZE
183 + (ubc_nwins << ubc_winshift)
184 + bufsz
185 + 16 * NCARGS
186 + pager_map_size
187 + maxproc * USPACE
188 + NBPG * nkmempages) >> SEGSHIFT;
189
190 /*
191 * Initialize `FYI' variables. Note we're relying on
192 * the fact that BSEARCH sorts the vm_physmem[] array
193 * for us. Must do this before uvm_pageboot_alloc()
194 * can be called.
195 */
196 pmap_limits.avail_start = uvm_physseg_get_start(uvm_physseg_get_first()) << PGSHIFT;
197 pmap_limits.avail_end = uvm_physseg_get_end(uvm_physseg_get_last()) << PGSHIFT;
198 const size_t max_nsegtabs =
199 (pmap_round_seg(VM_MAX_KERNEL_ADDRESS)
200 - pmap_trunc_seg(VM_MIN_KERNEL_ADDRESS)) / NBSEG;
201 if (kv_nsegtabs >= max_nsegtabs) {
202 pmap_limits.virtual_end = VM_MAX_KERNEL_ADDRESS;
203 kv_nsegtabs = max_nsegtabs;
204 } else {
205 pmap_limits.virtual_end = VM_MIN_KERNEL_ADDRESS
206 + kv_nsegtabs * NBSEG;
207 }
208
209 /*
210 * Now actually allocate the kernel PTE array (must be done
211 * after virtual_end is initialized).
212 */
213 const vaddr_t kv_segtabs = avail[0].start;
214 KASSERT(kv_segtabs == endkernel);
215 KASSERT(avail[0].size >= NBPG * kv_nsegtabs);
216 printf(" kv_nsegtabs=%#"PRIxVSIZE, kv_nsegtabs);
217 printf(" kv_segtabs=%#"PRIxVADDR, kv_segtabs);
218 avail[0].start += NBPG * kv_nsegtabs;
219 avail[0].size -= NBPG * kv_nsegtabs;
220 endkernel += NBPG * kv_nsegtabs;
221
222 /*
223 * Initialize the kernel's two-level page level. This only wastes
224 * an extra page for the segment table and allows the user/kernel
225 * access to be common.
226 */
227 pt_entry_t **ptp = &stp->seg_tab[VM_MIN_KERNEL_ADDRESS >> SEGSHIFT];
228 pt_entry_t *ptep = (void *)kv_segtabs;
229 memset(ptep, 0, NBPG * kv_nsegtabs);
230 for (size_t i = 0; i < kv_nsegtabs; i++, ptep += NPTEPG) {
231 *ptp++ = ptep;
232 }
233
234 #if PMAP_MINIMALTLB
235 const vsize_t dm_nsegtabs = (physmem + NPTEPG - 1) / NPTEPG;
236 const vaddr_t dm_segtabs = avail[0].start;
237 printf(" dm_nsegtabs=%#"PRIxVSIZE, dm_nsegtabs);
238 printf(" dm_segtabs=%#"PRIxVADDR, dm_segtabs);
239 KASSERT(dm_segtabs == endkernel);
240 KASSERT(avail[0].size >= NBPG * dm_nsegtabs);
241 avail[0].start += NBPG * dm_nsegtabs;
242 avail[0].size -= NBPG * dm_nsegtabs;
243 endkernel += NBPG * dm_nsegtabs;
244
245 ptp = stp->seg_tab;
246 ptep = (void *)dm_segtabs;
247 memset(ptep, 0, NBPG * dm_nsegtabs);
248 for (size_t i = 0; i < dm_nsegtabs; i++, ptp++, ptep += NPTEPG) {
249 *ptp = ptep;
250 }
251
252 /*
253 */
254 extern uint32_t _fdata[], _etext[];
255 vaddr_t va;
256
257 /* Now make everything before the kernel inaccessible. */
258 va = pmap_kvptefill(NBPG, startkernel, 0);
259
260 /* Kernel text is readonly & executable */
261 va = pmap_kvptefill(va, round_page((vaddr_t)_etext),
262 PTE_M | PTE_xR | PTE_xX);
263
264 /* Kernel .rdata is readonly */
265 va = pmap_kvptefill(va, trunc_page((vaddr_t)_fdata), PTE_M | PTE_xR);
266
267 /* Kernel .data/.bss + page tables are read-write */
268 va = pmap_kvptefill(va, round_page(endkernel), PTE_M | PTE_xR | PTE_xW);
269
270 /* message buffer page table pages are read-write */
271 (void) pmap_kvptefill(msgbuf_paddr, msgbuf_paddr+round_page(MSGBUFSIZE),
272 PTE_M | PTE_xR | PTE_xW);
273 #endif
274
275 for (size_t i = 0; i < cnt; i++) {
276 printf(" uvm_page_physload(%#lx,%#lx,%#lx,%#lx,%d)",
277 atop(avail[i].start),
278 atop(avail[i].start + avail[i].size) - 1,
279 atop(avail[i].start),
280 atop(avail[i].start + avail[i].size) - 1,
281 VM_FREELIST_DEFAULT);
282 uvm_page_physload(
283 atop(avail[i].start),
284 atop(avail[i].start + avail[i].size) - 1,
285 atop(avail[i].start),
286 atop(avail[i].start + avail[i].size) - 1,
287 VM_FREELIST_DEFAULT);
288 }
289
290 pmap_pvlist_lock_init(curcpu()->ci_ci.dcache_line_size);
291
292 /*
293 * Initialize the pools.
294 */
295 pool_init(&pmap_pmap_pool, PMAP_SIZE, 0, 0, 0, "pmappl",
296 &pool_allocator_nointr, IPL_NONE);
297 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvpl",
298 &pmap_pv_page_allocator, IPL_NONE);
299
300 tlb_set_asid(0);
301
302 return endkernel;
303 }
304
305 struct vm_page *
306 pmap_md_alloc_poolpage(int flags)
307 {
308 /*
309 * Any managed page works for us.
310 */
311 return uvm_pagealloc(NULL, 0, NULL, flags);
312 }
313
314 vaddr_t
315 pmap_md_map_poolpage(paddr_t pa, vsize_t size)
316 {
317 const vaddr_t sva = (vaddr_t) pa;
318 #ifdef PMAP_MINIMALTLB
319 const vaddr_t eva = sva + size;
320 pmap_kvptefill(sva, eva, PTE_M | PTE_xR | PTE_xW);
321 #endif
322 return sva;
323 }
324
325 void
326 pmap_md_unmap_poolpage(vaddr_t va, vsize_t size)
327 {
328 #ifdef PMAP_MINIMALTLB
329 struct pmap * const pm = pmap_kernel();
330 const vaddr_t eva = va + size;
331 pmap_kvptefill(va, eva, 0);
332 for (;va < eva; va += NBPG) {
333 pmap_tlb_invalidate_addr(pm, va);
334 }
335 pmap_update(pm);
336 #endif
337 }
338
339 void
340 pmap_zero_page(paddr_t pa)
341 {
342 PMAP_COUNT(zeroed_pages);
343 vaddr_t va = pmap_md_map_poolpage(pa, NBPG);
344 dcache_zero_page(va);
345
346 KASSERT(!VM_PAGEMD_EXECPAGE_P(VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(va))));
347 pmap_md_unmap_poolpage(va, NBPG);
348 }
349
350 void
351 pmap_copy_page(paddr_t src, paddr_t dst)
352 {
353 const size_t line_size = curcpu()->ci_ci.dcache_line_size;
354 vaddr_t src_va = pmap_md_map_poolpage(src, NBPG);
355 vaddr_t dst_va = pmap_md_map_poolpage(dst, NBPG);
356 const vaddr_t end = src_va + PAGE_SIZE;
357
358 PMAP_COUNT(copied_pages);
359
360 while (src_va < end) {
361 __asm __volatile(
362 "dcbt %2,%0" "\n\t" /* touch next src cacheline */
363 "dcba 0,%1" "\n\t" /* don't fetch dst cacheline */
364 :: "b"(src_va), "b"(dst_va), "b"(line_size));
365 for (u_int i = 0;
366 i < line_size;
367 src_va += 32, dst_va += 32, i += 32) {
368 register_t tmp;
369 __asm __volatile(
370 "mr %[tmp],31" "\n\t"
371 "lmw 24,0(%[src])" "\n\t"
372 "stmw 24,0(%[dst])" "\n\t"
373 "mr 31,%[tmp]" "\n\t"
374 : [tmp] "=&r"(tmp)
375 : [src] "b"(src_va), [dst] "b"(dst_va)
376 : "r24", "r25", "r26", "r27",
377 "r28", "r29", "r30", "memory");
378 }
379 }
380 pmap_md_unmap_poolpage(src_va, NBPG);
381 pmap_md_unmap_poolpage(dst_va, NBPG);
382
383 KASSERT(!VM_PAGEMD_EXECPAGE_P(VM_PAGE_TO_MD(PHYS_TO_VM_PAGE(dst))));
384 }
385
386 void
387 pmap_md_init(void)
388 {
389
390 /* nothing for now */
391 }
392
393 bool
394 pmap_md_io_vaddr_p(vaddr_t va)
395 {
396 return va >= pmap_limits.avail_end
397 && !(VM_MIN_KERNEL_ADDRESS <= va && va < VM_MAX_KERNEL_ADDRESS);
398 }
399
400 bool
401 pmap_md_tlb_check_entry(void *ctx, vaddr_t va, tlb_asid_t asid, pt_entry_t pte)
402 {
403 pmap_t pm = ctx;
404 struct pmap_asid_info * const pai = PMAP_PAI(pm, curcpu()->ci_tlb_info);
405
406 if (asid != pai->pai_asid)
407 return true;
408
409 const pt_entry_t * const ptep = pmap_pte_lookup(pm, va);
410 KASSERT(ptep != NULL);
411 pt_entry_t xpte = *ptep;
412 xpte &= ~((xpte & (PTE_UNSYNCED|PTE_UNMODIFIED)) << 1);
413 xpte ^= xpte & (PTE_UNSYNCED|PTE_UNMODIFIED|PTE_WIRED);
414
415 KASSERTMSG(pte == xpte,
416 "pm=%p va=%#"PRIxVADDR" asid=%u: TLB pte (%#x) != real pte (%#x/%#x)",
417 pm, va, asid, pte, xpte, *ptep);
418
419 return true;
420 }
421
422 #ifdef MULTIPROCESSOR
423 void
424 pmap_md_tlb_info_attach(struct pmap_tlb_info *ti, struct cpu_info *ci)
425 {
426 /* nothing */
427 }
428 #endif /* MULTIPROCESSOR */
429