pq3etsec.c revision 1.1.2.2
1 /* $NetBSD: pq3etsec.c,v 1.1.2.2 2011/01/11 03:45:29 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_inet.h" 38 #include "bpfilter.h" 39 40 #include <sys/cdefs.h> 41 42 #include <sys/param.h> 43 #include <sys/cpu.h> 44 #include <sys/device.h> 45 #include <sys/mbuf.h> 46 #include <sys/ioctl.h> 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/proc.h> 52 #include <sys/atomic.h> 53 #include <sys/callout.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 60 #include <dev/mii/miivar.h> 61 62 #include "ioconf.h" 63 64 #include <net/bpf.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/ip.h> 70 #include <netinet/in_offload.h> 71 #endif /* INET */ 72 #ifdef INET6 73 #include <netinet6/in6.h> 74 #include <netinet/ip6.h> 75 #endif 76 #include <netinet6/in6_offload.h> 77 78 79 #include <powerpc/spr.h> 80 #include <powerpc/booke/spr.h> 81 82 #include <powerpc/booke/cpuvar.h> 83 #include <powerpc/booke/e500var.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/etsecreg.h> 86 87 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 88 89 #define ETSEC_MAXTXMBUFS 30 90 #define ETSEC_NTXSEGS 30 91 #define ETSEC_MAXRXMBUFS 511 92 #define ETSEC_MINRXMBUFS 32 93 #define ETSEC_NRXSEGS 1 94 95 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 96 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx\ 97 |IFCAP_CSUM_UDPv4_Rx\ 98 |IFCAP_CSUM_TCPv6_Rx\ 99 |IFCAP_CSUM_UDPv6_Rx) 100 101 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 102 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx\ 103 |IFCAP_CSUM_UDPv4_Tx\ 104 |IFCAP_CSUM_TCPv6_Tx\ 105 |IFCAP_CSUM_UDPv6_Tx) 106 107 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN|IFCAP_RCTRL_TUCSEN\ 108 |IFCAP_TCTRL_IPCSEN|IFCAP_TCTRL_TUCSEN) 109 110 #define M_CSUM_IP (M_CSUM_CIP|M_CSUM_CTU) 111 #define M_CSUM_IP6 (M_CSUM_TCPv6|M_CSUM_UDPv6) 112 #define M_CSUM_TUP (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 113 #define M_CSUM_UDP (M_CSUM_UDPv4|M_CSUM_UDPv6) 114 #define M_CSUM_IP4 (M_CSUM_IPv4|M_CSUM_UDPv4|M_CSUM_TCPv4) 115 #define M_CSUM_CIP (M_CSUM_IPv4) 116 #define M_CSUM_CTU (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 117 118 struct pq3etsec_txqueue { 119 bus_dmamap_t txq_descmap; 120 volatile struct txbd *txq_consumer; 121 volatile struct txbd *txq_producer; 122 volatile struct txbd *txq_first; 123 volatile struct txbd *txq_last; 124 struct ifqueue txq_mbufs; 125 struct mbuf *txq_next; 126 #ifdef ETSEC_DEBUG 127 struct mbuf *txq_lmbufs[512]; 128 #endif 129 uint32_t txq_qmask; 130 uint32_t txq_free; 131 uint32_t txq_threshold; 132 uint32_t txq_lastintr; 133 bus_size_t txq_reg_tbase; 134 bus_dma_segment_t txq_descmap_seg; 135 }; 136 137 struct pq3etsec_rxqueue { 138 bus_dmamap_t rxq_descmap; 139 volatile struct rxbd *rxq_consumer; 140 volatile struct rxbd *rxq_producer; 141 volatile struct rxbd *rxq_first; 142 volatile struct rxbd *rxq_last; 143 struct mbuf *rxq_mhead; 144 struct mbuf **rxq_mtail; 145 struct mbuf *rxq_mconsumer; 146 #ifdef ETSEC_DEBUG 147 struct mbuf *rxq_mbufs[512]; 148 #endif 149 uint32_t rxq_qmask; 150 uint32_t rxq_inuse; 151 uint32_t rxq_threshold; 152 bus_size_t rxq_reg_rbase; 153 bus_size_t rxq_reg_rbptr; 154 bus_dma_segment_t rxq_descmap_seg; 155 }; 156 157 struct pq3etsec_mapcache { 158 u_int dmc_nmaps; 159 u_int dmc_maxseg; 160 u_int dmc_maxmaps; 161 u_int dmc_maxmapsize; 162 bus_dmamap_t dmc_maps[0]; 163 }; 164 165 struct pq3etsec_softc { 166 device_t sc_dev; 167 struct ethercom sc_ec; 168 #define sc_if sc_ec.ec_if 169 struct mii_data sc_mii; 170 bus_space_tag_t sc_bst; 171 bus_space_handle_t sc_bsh; 172 bus_dma_tag_t sc_dmat; 173 int sc_phy_addr; 174 prop_dictionary_t sc_intrmap; 175 uint32_t sc_intrmask; 176 177 uint32_t sc_soft_flags; 178 #define SOFT_RESET 0x0001 179 #define SOFT_RXINTR 0x0010 180 #define SOFT_RXBSY 0x0020 181 #define SOFT_TXINTR 0x0100 182 #define SOFT_TXERROR 0x0200 183 184 struct pq3etsec_txqueue sc_txq; 185 struct pq3etsec_rxqueue sc_rxq; 186 uint32_t sc_txerrors; 187 uint32_t sc_rxerrors; 188 189 size_t sc_rx_adjlen; 190 191 /* 192 * Copies of various ETSEC registers. 193 */ 194 uint32_t sc_imask; 195 uint32_t sc_maccfg1; 196 uint32_t sc_maccfg2; 197 uint32_t sc_maxfrm; 198 uint32_t sc_ecntrl; 199 uint32_t sc_dmactrl; 200 uint32_t sc_macstnaddr1; 201 uint32_t sc_macstnaddr2; 202 uint32_t sc_tctrl; 203 uint32_t sc_rctrl; 204 uint32_t sc_gaddr[16]; 205 uint64_t sc_macaddrs[15]; 206 207 void *sc_tx_ih; 208 void *sc_rx_ih; 209 void *sc_error_ih; 210 void *sc_soft_ih; 211 212 kmutex_t *sc_lock; 213 214 struct evcnt sc_ev_tx_stall; 215 struct evcnt sc_ev_tx_intr; 216 struct evcnt sc_ev_rx_stall; 217 struct evcnt sc_ev_rx_intr; 218 struct evcnt sc_ev_error_intr; 219 struct evcnt sc_ev_soft_intr; 220 struct evcnt sc_ev_tx_pause; 221 struct evcnt sc_ev_rx_pause; 222 struct evcnt sc_ev_mii_ticks; 223 224 struct callout sc_mii_callout; 225 uint64_t sc_mii_last_tick; 226 227 struct ifqueue sc_rx_bufcache; 228 struct pq3etsec_mapcache *sc_rx_mapcache; 229 struct pq3etsec_mapcache *sc_tx_mapcache; 230 }; 231 232 static int pq3etsec_match(device_t, cfdata_t, void *); 233 static void pq3etsec_attach(device_t, device_t, void *); 234 235 static void pq3etsec_ifstart(struct ifnet *); 236 static void pq3etsec_ifwatchdog(struct ifnet *); 237 static int pq3etsec_ifinit(struct ifnet *); 238 static void pq3etsec_ifstop(struct ifnet *, int); 239 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 240 241 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 242 struct pq3etsec_mapcache **, size_t, size_t, size_t, size_t); 243 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 244 struct pq3etsec_mapcache *); 245 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 246 struct pq3etsec_mapcache *); 247 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 248 struct pq3etsec_mapcache *, bus_dmamap_t); 249 250 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 251 struct pq3etsec_txqueue *, u_int); 252 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 253 struct pq3etsec_txqueue *); 254 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 255 struct pq3etsec_txqueue *); 256 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 257 struct pq3etsec_txqueue *); 258 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 259 struct pq3etsec_txqueue *, struct mbuf *m); 260 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 261 struct pq3etsec_txqueue *); 262 263 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 264 struct pq3etsec_rxqueue *, u_int); 265 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 266 struct pq3etsec_rxqueue *); 267 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 268 struct pq3etsec_rxqueue *, bool); 269 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 270 struct pq3etsec_rxqueue *); 271 272 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 273 274 static void pq3etsec_mii_tick(void *); 275 static int pq3etsec_rx_intr(void *); 276 static int pq3etsec_tx_intr(void *); 277 static int pq3etsec_error_intr(void *); 278 static void pq3etsec_soft_intr(void *); 279 280 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 281 pq3etsec_match, pq3etsec_attach, NULL, NULL); 282 283 static int 284 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 285 { 286 287 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 288 return 0; 289 290 return 1; 291 } 292 293 static inline uint32_t 294 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 295 { 296 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 297 } 298 299 static inline void 300 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 301 { 302 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 303 } 304 305 static int 306 pq3etsec_mii_readreg(device_t self, int phy, int reg) 307 { 308 struct pq3etsec_softc * const sc = device_private(self); 309 uint32_t miimcom = etsec_read(sc, MIIMCOM); 310 311 // int s = splnet(); 312 313 etsec_write(sc, MIIMADD, 314 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 315 316 etsec_write(sc, IEVENT, IEVENT_MMRD); 317 etsec_write(sc, MIIMCOM, 0); /* clear any past bits */ 318 etsec_write(sc, MIIMCOM, MIIMCOM_READ); 319 #if 0 320 sc->sc_imask |= IEVENT_MMRD; 321 etsec_write(sc, IMASK, sc->sc_imask); 322 #endif 323 324 while (etsec_read(sc, MIIMIND) != 0) { 325 delay(1); 326 } 327 int data = etsec_read(sc, MIIMSTAT); 328 329 if (miimcom == MIIMCOM_SCAN) 330 etsec_write(sc, MIIMCOM, miimcom); 331 332 #if 0 333 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 334 __func__, phy, reg, data); 335 #endif 336 etsec_write(sc, IEVENT, IEVENT_MMRD); 337 // splx(s); 338 return data; 339 } 340 341 static void 342 pq3etsec_mii_writereg(device_t self, int phy, int reg, int data) 343 { 344 struct pq3etsec_softc * const sc = device_private(self); 345 uint32_t miimcom = etsec_read(sc, MIIMCOM); 346 347 #if 0 348 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 349 __func__, phy, reg, data); 350 #endif 351 352 // int s = splnet(); 353 etsec_write(sc, IEVENT, IEVENT_MMWR); 354 etsec_write(sc, MIIMADD, 355 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 356 etsec_write(sc, MIIMCOM, 0); /* clear any past bits */ 357 etsec_write(sc, MIIMCON, data); 358 359 #if 0 360 sc->sc_imask |= IEVENT_MMWR; 361 etsec_write(sc, IMASK, sc->sc_imask); 362 #endif 363 364 int timo = 1000; /* 1ms */ 365 while ((etsec_read(sc, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 366 delay(1); 367 } 368 369 if (miimcom == MIIMCOM_SCAN) 370 etsec_write(sc, MIIMCOM, miimcom); 371 etsec_write(sc, IEVENT, IEVENT_MMWR); 372 // splx(s); 373 } 374 375 static void 376 pq3etsec_mii_statchg(device_t self) 377 { 378 struct pq3etsec_softc * const sc = device_private(self); 379 struct mii_data * const mii = &sc->sc_mii; 380 381 uint32_t maccfg1 = sc->sc_maccfg1; 382 uint32_t maccfg2 = sc->sc_maccfg2; 383 uint32_t ecntrl = sc->sc_ecntrl; 384 385 maccfg1 &= ~(MACCFG1_TX_FLOW|MACCFG1_RX_FLOW); 386 maccfg2 &= ~(MACCFG2_IFMODE|MACCFG2_FD); 387 388 if (sc->sc_mii.mii_media_active & IFM_FDX) { 389 maccfg2 |= MACCFG2_FD; 390 } 391 392 /* 393 * Now deal with the flow control bits. 394 */ 395 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 396 && (mii->mii_media_active & IFM_ETH_FMASK)) { 397 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 398 maccfg1 |= MACCFG1_RX_FLOW; 399 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 400 maccfg1 |= MACCFG1_TX_FLOW; 401 } 402 403 /* 404 * Now deal with the speed. 405 */ 406 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 407 maccfg2 |= MACCFG2_IFMODE_GMII; 408 } else { 409 maccfg2 |= MACCFG2_IFMODE_MII; 410 ecntrl &= ~ECNTRL_R100M; 411 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 412 ecntrl |= ECNTRL_R100M; 413 } 414 } 415 416 /* 417 * If things are different, re-init things. 418 */ 419 if (maccfg1 != sc->sc_maccfg1 420 || maccfg2 != sc->sc_maccfg2 421 || ecntrl != sc->sc_ecntrl) { 422 if (sc->sc_if.if_flags & IFF_RUNNING) 423 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 424 sc->sc_maccfg1 = maccfg1; 425 sc->sc_maccfg2 = maccfg2; 426 sc->sc_ecntrl = ecntrl; 427 } 428 } 429 430 #if 0 431 static void 432 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 433 { 434 struct pq3etsec_softc * const sc = ifp->if_softc; 435 436 mii_pollstat(&sc->sc_mii); 437 ether_mediastatus(ifp, ifmr); 438 ifmr->ifm_status = sc->sc_mii.mii_media_status; 439 ifmr->ifm_active = sc->sc_mii.mii_media_active; 440 } 441 442 static int 443 pq3etsec_mediachange(struct ifnet *ifp) 444 { 445 struct pq3etsec_softc * const sc = ifp->if_softc; 446 447 if ((ifp->if_flags & IFF_UP) == 0) 448 return 0; 449 450 int rv = mii_mediachg(&sc->sc_mii); 451 return (rv == ENXIO) ? 0 : rv; 452 } 453 #endif 454 455 static void 456 pq3etsec_attach(device_t parent, device_t self, void *aux) 457 { 458 struct cpunode_softc * const psc = device_private(parent); 459 struct pq3etsec_softc * const sc = device_private(self); 460 struct cpunode_attach_args * const cna = aux; 461 struct cpunode_locators * const cnl = &cna->cna_locs; 462 int error; 463 464 psc->sc_children |= cna->cna_childmask; 465 sc->sc_dev = self; 466 sc->sc_bst = cna->cna_memt; 467 sc->sc_dmat = &booke_bus_dma_tag; 468 469 /* 470 * If we have a common MDIO bus, if all off instance 1. 471 */ 472 device_t miiself = (self->dv_cfdata->cf_flags & 0x100) 473 ? tsec_cd.cd_devs[0] 474 : self; 475 476 /* 477 * See if the phy is in the config file... 478 */ 479 if (self->dv_cfdata->cf_flags & 0x3f) { 480 sc->sc_phy_addr = (self->dv_cfdata->cf_flags & 0x3f) - 1; 481 } else { 482 unsigned char prop_name[20]; 483 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 484 cnl->cnl_instance); 485 sc->sc_phy_addr = board_info_get_number(prop_name); 486 } 487 aprint_normal(" phy %d", sc->sc_phy_addr); 488 489 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 490 &sc->sc_bsh); 491 if (error) { 492 aprint_error(": error mapping registers: %d\n", error); 493 return; 494 } 495 496 /* 497 * Assume firmware has aready set the mac address and fetch it 498 * before we reinit it. 499 */ 500 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 501 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 502 sc->sc_rctrl = RCTRL_DEFAULT; 503 sc->sc_maccfg2 = MACCFG2_DEFAULT; 504 505 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 506 size_t len; 507 const uint8_t *mac_addr = 508 board_info_get_data("tsec-mac-addr-base", &len); 509 KASSERT(len == ETHER_ADDR_LEN); 510 sc->sc_macstnaddr2 = 511 (mac_addr[1] << 24) 512 | (mac_addr[0] << 16); 513 sc->sc_macstnaddr1 = 514 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 515 | (mac_addr[4] << 16) 516 | (mac_addr[3] << 8) 517 | (mac_addr[2] << 0); 518 #if 0 519 aprint_error(": mac-address unknown\n"); 520 return; 521 #endif 522 } 523 524 char enaddr[ETHER_ADDR_LEN] = { 525 [0] = sc->sc_macstnaddr2 >> 16, 526 [1] = sc->sc_macstnaddr2 >> 24, 527 [2] = sc->sc_macstnaddr1 >> 0, 528 [3] = sc->sc_macstnaddr1 >> 8, 529 [4] = sc->sc_macstnaddr1 >> 16, 530 [5] = sc->sc_macstnaddr1 >> 24, 531 }; 532 533 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 534 if (error) { 535 aprint_error(": failed to init rxq: %d\n", error); 536 return; 537 } 538 539 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 540 if (error) { 541 aprint_error(": failed to init txq: %d\n", error); 542 return; 543 } 544 545 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 546 ETSEC_MAXRXMBUFS, ETSEC_MINRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 547 if (error) { 548 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 549 return; 550 } 551 552 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 553 ETSEC_MAXTXMBUFS, ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 554 if (error) { 555 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 556 return; 557 } 558 559 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 560 pq3etsec_tx_intr, sc); 561 if (sc->sc_tx_ih == NULL) { 562 aprint_error(": failed to establish tx interrupt: %d\n", 563 cnl->cnl_intrs[0]); 564 return; 565 } 566 567 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 568 pq3etsec_rx_intr, sc); 569 if (sc->sc_rx_ih == NULL) { 570 aprint_error(": failed to establish rx interrupt: %d\n", 571 cnl->cnl_intrs[1]); 572 return; 573 } 574 575 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 576 pq3etsec_error_intr, sc); 577 if (sc->sc_error_ih == NULL) { 578 aprint_error(": failed to establish error interrupt: %d\n", 579 cnl->cnl_intrs[2]); 580 return; 581 } 582 583 sc->sc_soft_ih = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 584 pq3etsec_soft_intr, sc); 585 if (sc->sc_soft_ih == NULL) { 586 aprint_error(": failed to establish soft interrupt\n"); 587 return; 588 } 589 590 aprint_normal("\n"); 591 592 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 593 594 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 595 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 596 597 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 598 ether_sprintf(enaddr)); 599 600 const char * const xname = device_xname(sc->sc_dev); 601 struct ethercom * const ec = &sc->sc_ec; 602 struct ifnet * const ifp = &ec->ec_if; 603 604 ec->ec_mii = &sc->sc_mii; 605 606 sc->sc_mii.mii_ifp = ifp; 607 sc->sc_mii.mii_readreg = pq3etsec_mii_readreg; 608 sc->sc_mii.mii_writereg = pq3etsec_mii_writereg; 609 sc->sc_mii.mii_statchg = pq3etsec_mii_statchg; 610 611 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 612 ether_mediastatus); 613 614 mii_attach(miiself, &sc->sc_mii, 0xffffffff, 615 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 616 617 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 618 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 619 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 620 } else { 621 callout_schedule(&sc->sc_mii_callout, hz); 622 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 623 } 624 625 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 626 | ETHERCAP_JUMBO_MTU; 627 628 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 629 ifp->if_softc = sc; 630 ifp->if_capabilities = IFCAP_ETSEC; 631 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 632 ifp->if_ioctl = pq3etsec_ifioctl; 633 ifp->if_start = pq3etsec_ifstart; 634 ifp->if_watchdog = pq3etsec_ifwatchdog; 635 ifp->if_init = pq3etsec_ifinit; 636 ifp->if_stop = pq3etsec_ifstop; 637 IFQ_SET_READY(&ifp->if_snd); 638 639 pq3etsec_ifstop(ifp, true); 640 641 /* 642 * Attach the interface. 643 */ 644 if_attach(ifp); 645 ether_ifattach(ifp, enaddr); 646 647 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 648 NULL, xname, "rx stall"); 649 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 650 NULL, xname, "tx stall"); 651 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 652 NULL, xname, "tx intr"); 653 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 654 NULL, xname, "rx intr"); 655 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 656 NULL, xname, "error intr"); 657 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 658 NULL, xname, "soft intr"); 659 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 660 NULL, xname, "tx pause"); 661 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 662 NULL, xname, "rx pause"); 663 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 664 NULL, xname, "mii ticks"); 665 } 666 667 static uint64_t 668 pq3etsec_macaddr_create(const uint8_t *lladdr) 669 { 670 uint64_t macaddr = 0; 671 672 lladdr += ETHER_ADDR_LEN; 673 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 674 macaddr = (macaddr << 8) | *--lladdr; 675 } 676 return macaddr << 16; 677 } 678 679 static int 680 pq3etsec_ifinit(struct ifnet *ifp) 681 { 682 struct pq3etsec_softc * const sc = ifp->if_softc; 683 int error = 0; 684 685 sc->sc_maxfrm = max(ifp->if_mtu + 32, MCLBYTES); 686 if (ifp->if_mtu > ETHERMTU_JUMBO) 687 return error; 688 689 KASSERT(ifp->if_flags & IFF_UP); 690 691 /* 692 * Stop the interface (steps 1 to 4 in the Soft Reset and 693 * Reconfigurating Procedure. 694 */ 695 pq3etsec_ifstop(ifp, 0); 696 697 /* 698 * If our frame size has changed (or it's our first time through) 699 * destroy the existing transmit mapcache. 700 */ 701 if (sc->sc_tx_mapcache != NULL 702 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 703 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 704 sc->sc_tx_mapcache = NULL; 705 } 706 707 if (sc->sc_tx_mapcache == NULL) { 708 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 709 ETSEC_MAXTXMBUFS, ETSEC_MAXTXMBUFS, sc->sc_maxfrm, 710 ETSEC_NTXSEGS); 711 if (error) 712 return error; 713 } 714 715 sc->sc_ev_mii_ticks.ev_count++; 716 mii_tick(&sc->sc_mii); 717 718 if (ifp->if_flags & IFF_PROMISC) { 719 sc->sc_rctrl |= RCTRL_PROM; 720 } else { 721 sc->sc_rctrl &= ~RCTRL_PROM; 722 } 723 724 uint32_t rctrl_prsdep = 0; 725 sc->sc_rctrl &= ~(RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP); 726 if (VLAN_ATTACHED(&sc->sc_ec)) { 727 sc->sc_rctrl |= RCTRL_VLEX; 728 rctrl_prsdep = RCTRL_PRSDEP_L2; 729 } 730 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 731 sc->sc_rctrl |= RCTRL_IPCSEN; 732 rctrl_prsdep = RCTRL_PRSDEP_L3; 733 } 734 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 735 sc->sc_rctrl |= RCTRL_TUCSEN; 736 rctrl_prsdep = RCTRL_PRSDEP_L4; 737 } 738 sc->sc_rctrl |= rctrl_prsdep; 739 #if 0 740 if (sc->sc_rctrl & (RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP)) 741 aprint_normal_dev(sc->sc_dev, 742 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 743 sc->sc_rctrl, 744 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 745 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 746 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 747 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 748 #endif 749 750 sc->sc_tctrl &= ~(TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS); 751 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 752 sc->sc_tctrl |= TCTRL_VLINS; 753 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 754 sc->sc_tctrl |= TCTRL_IPCSEN; 755 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 756 sc->sc_tctrl |= TCTRL_TUCSEN; 757 #if 0 758 if (sc->sc_tctrl & (TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS)) 759 aprint_normal_dev(sc->sc_dev, 760 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 761 sc->sc_tctrl, 762 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 763 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 764 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 765 #endif 766 767 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN|MACCFG1_RX_EN); 768 769 const uint64_t macstnaddr = 770 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 771 772 sc->sc_imask = IEVENT_DPE; 773 774 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 775 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 776 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 777 778 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 779 pq3etsec_txq_reset(sc, &sc->sc_txq); 780 781 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 782 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 783 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 784 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 785 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 786 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 787 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 788 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 789 790 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 791 pq3etsec_mc_setup(sc); 792 793 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 794 etsec_write(sc, MRBLR, MCLBYTES); 795 796 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 797 sc->sc_dmactrl |= DMACTRL_DEFAULT; 798 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 799 800 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 801 etsec_write(sc, TQUEUE, TQUEUE_EN0); 802 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE|IEVENT_TXC; 803 804 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 805 806 /* 12. Enable receive queues in RQUEUE, */ 807 etsec_write(sc, RQUEUE, RQUEUE_EN0|RQUEUE_EX0); 808 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY|IEVENT_RXC; 809 810 /* and optionally set TOE functionality in RCTRL. */ 811 etsec_write(sc, RCTRL, sc->sc_rctrl); 812 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 813 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 814 sc->sc_rx_adjlen += sizeof(struct rxfcb); 815 816 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 817 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 818 819 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 820 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 821 822 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 823 sc->sc_dmactrl &= ~(DMACTRL_GRS|DMACTRL_GTS); 824 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 825 826 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 827 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 828 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 829 830 sc->sc_soft_flags = 0; 831 832 etsec_write(sc, IMASK, sc->sc_imask); 833 834 ifp->if_flags |= IFF_RUNNING; 835 836 return error; 837 } 838 839 static void 840 pq3etsec_ifstop(struct ifnet *ifp, int disable) 841 { 842 struct pq3etsec_softc * const sc = ifp->if_softc; 843 844 KASSERT(!cpu_intr_p()); 845 const uint32_t imask_gsc_mask = IEVENT_GTSC|IEVENT_GRSC; 846 /* 847 * Clear the GTSC and GRSC from the interrupt mask until 848 * we are ready for them. Then clear them from IEVENT, 849 * request the graceful shutdown, and then enable the 850 * GTSC and GRSC bits in the mask. This should cause the 851 * error interrupt to fire which will issue a wakeup to 852 * allow us to resume. 853 */ 854 855 /* 856 * 1. Set GRS/GTS bits in DMACTRL register 857 */ 858 sc->sc_dmactrl |= DMACTRL_GRS|DMACTRL_GTS; 859 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 860 etsec_write(sc, IEVENT, imask_gsc_mask); 861 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 862 863 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN|MACCFG1_RX_EN)) { 864 /* 865 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 866 */ 867 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 868 869 u_int timo = 1000; 870 uint32_t ievent = etsec_read(sc, IEVENT); 871 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 872 if (--timo == 0) { 873 aprint_error_dev(sc->sc_dev, 874 "WARNING: " 875 "request to stop failed (IEVENT=%#x)\n", 876 ievent); 877 break; 878 } 879 delay(10); 880 ievent = etsec_read(sc, IEVENT); 881 } 882 } 883 884 /* 885 * Now reset the controller. 886 * 887 * 3. Set SOFT_RESET bit in MACCFG1 register 888 * 4. Clear SOFT_RESET bit in MACCFG1 register 889 */ 890 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 891 etsec_write(sc, MACCFG1, 0); 892 etsec_write(sc, IMASK, 0); 893 etsec_write(sc, IEVENT, ~0); 894 sc->sc_imask = 0; 895 ifp->if_flags &= ~IFF_RUNNING; 896 897 uint32_t tbipa = etsec_read(sc, TBIPA); 898 if (tbipa == sc->sc_phy_addr) { 899 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 900 etsec_write(sc, TBIPA, 0x1f); 901 } 902 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 903 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 904 etsec_write(sc, MIIMCFG, miimcfg); 905 906 /* 907 * Let's consume any remaing transmitted packets. And if we are 908 * disabling the interface, purge ourselves of any untransmitted 909 * packets. But don't consume any received packets, just drop them. 910 * If we aren't disabling the interface, save the mbufs in the 911 * receive queue for reuse. 912 */ 913 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 914 pq3etsec_txq_consume(sc, &sc->sc_txq); 915 if (disable) { 916 pq3etsec_txq_purge(sc, &sc->sc_txq); 917 IF_PURGE(&ifp->if_snd); 918 } 919 } 920 921 static void 922 pq3etsec_ifwatchdog(struct ifnet *ifp) 923 { 924 } 925 926 static void 927 pq3etsec_mc_setup( 928 struct pq3etsec_softc *sc) 929 { 930 struct ethercom * const ec = &sc->sc_ec; 931 struct ifnet * const ifp = &sc->sc_if; 932 struct ether_multi *enm; 933 struct ether_multistep step; 934 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 935 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 936 937 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 938 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 939 940 ifp->if_flags &= ~IFF_ALLMULTI; 941 942 ETHER_FIRST_MULTI(step, ec, enm); 943 for (u_int i = 0; enm != NULL; ) { 944 const char *addr = enm->enm_addrlo; 945 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 946 ifp->if_flags |= IFF_ALLMULTI; 947 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 948 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 949 break; 950 } 951 if ((sc->sc_rctrl & RCTRL_EMEN) 952 && i < __arraycount(sc->sc_macaddrs)) { 953 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 954 } else { 955 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 956 #if 0 957 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 958 ether_sprintf(addr), crc, 959 crc >> crc_shift, 960 crc >> (crc_shift + 5), 961 (crc >> crc_shift) & 31, 962 1 << (((crc >> crc_shift) & 31) ^ 31)); 963 #endif 964 /* 965 * The documentation doesn't completely follow PowerPC 966 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 967 * is 0x7fa32d9b. By empirical testing, the 968 * corresponding hash bit is word 3, bit 31 (ppc bit 969 * order). Since 3 << 31 | 31 is 0x7f, we deduce 970 * H[0:2] selects the register while H[3:7] selects 971 * the bit (ppc bit order). 972 */ 973 crc >>= crc_shift; 974 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 975 } 976 ETHER_NEXT_MULTI(step, enm); 977 } 978 for (u_int i = 0; i < 8; i++) { 979 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 980 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 981 #if 0 982 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 983 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 984 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 985 i, GADDR(i), etsec_read(sc, GADDR(i))); 986 #endif 987 } 988 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 989 uint64_t macaddr = sc->sc_macaddrs[i]; 990 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 991 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 992 #if 0 993 if (macaddr) 994 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 995 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 996 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 997 #endif 998 } 999 } 1000 1001 static int 1002 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1003 { 1004 struct pq3etsec_softc *sc = ifp->if_softc; 1005 struct ifreq * const ifr = data; 1006 const int s = splnet(); 1007 int error; 1008 1009 switch (cmd) { 1010 case SIOCSIFMEDIA: 1011 case SIOCGIFMEDIA: 1012 /* Flow control requires full-duplex mode. */ 1013 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1014 (ifr->ifr_media & IFM_FDX) == 0) 1015 ifr->ifr_media &= ~IFM_ETH_FMASK; 1016 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1017 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1018 /* We can do both TXPAUSE and RXPAUSE. */ 1019 ifr->ifr_media |= 1020 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1021 } 1022 } 1023 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1024 break; 1025 1026 default: 1027 error = ether_ioctl(ifp, cmd, data); 1028 if (error != ENETRESET) 1029 break; 1030 1031 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1032 error = 0; 1033 if (ifp->if_flags & IFF_RUNNING) 1034 pq3etsec_mc_setup(sc); 1035 break; 1036 } 1037 error = pq3etsec_ifinit(ifp); 1038 break; 1039 } 1040 1041 splx(s); 1042 return error; 1043 } 1044 1045 static void 1046 pq3etsec_rxq_desc_presync( 1047 struct pq3etsec_softc *sc, 1048 struct pq3etsec_rxqueue *rxq, 1049 volatile struct rxbd *rxbd, 1050 size_t count) 1051 { 1052 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1053 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1054 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1055 } 1056 1057 static void 1058 pq3etsec_rxq_desc_postsync( 1059 struct pq3etsec_softc *sc, 1060 struct pq3etsec_rxqueue *rxq, 1061 volatile struct rxbd *rxbd, 1062 size_t count) 1063 { 1064 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1065 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1066 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1067 } 1068 1069 static void 1070 pq3etsec_txq_desc_presync( 1071 struct pq3etsec_softc *sc, 1072 struct pq3etsec_txqueue *txq, 1073 volatile struct txbd *txbd, 1074 size_t count) 1075 { 1076 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1077 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1078 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1079 } 1080 1081 static void 1082 pq3etsec_txq_desc_postsync( 1083 struct pq3etsec_softc *sc, 1084 struct pq3etsec_txqueue *txq, 1085 volatile struct txbd *txbd, 1086 size_t count) 1087 { 1088 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1089 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1090 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1091 } 1092 1093 static bus_dmamap_t 1094 pq3etsec_mapcache_get( 1095 struct pq3etsec_softc *sc, 1096 struct pq3etsec_mapcache *dmc) 1097 { 1098 if (dmc->dmc_nmaps == 0) { 1099 bus_dmamap_t map; 1100 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1101 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1102 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &map); 1103 if (error) { 1104 aprint_error_dev(sc->sc_dev, 1105 "failed to allocate a %zuB map: %d\n", 1106 dmc->dmc_maxmapsize, error); 1107 return NULL; 1108 } 1109 return map; 1110 } 1111 1112 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1113 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1114 } 1115 1116 static void 1117 pq3etsec_mapcache_put( 1118 struct pq3etsec_softc *sc, 1119 struct pq3etsec_mapcache *dmc, 1120 bus_dmamap_t map) 1121 { 1122 KASSERT(map != NULL); 1123 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1124 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1125 } 1126 1127 static void 1128 pq3etsec_mapcache_destroy( 1129 struct pq3etsec_softc *sc, 1130 struct pq3etsec_mapcache *dmc) 1131 { 1132 const size_t dmc_size = 1133 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1134 1135 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1136 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1137 } 1138 kmem_free(dmc, dmc_size); 1139 } 1140 1141 static int 1142 pq3etsec_mapcache_create( 1143 struct pq3etsec_softc *sc, 1144 struct pq3etsec_mapcache **dmc_p, 1145 size_t maxmaps, 1146 size_t minmaps, 1147 size_t maxmapsize, 1148 size_t maxseg) 1149 { 1150 const size_t dmc_size = 1151 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1152 struct pq3etsec_mapcache * const dmc = kmem_zalloc(dmc_size, KM_SLEEP); 1153 1154 dmc->dmc_maxmaps = maxmaps; 1155 dmc->dmc_nmaps = minmaps; 1156 dmc->dmc_maxmapsize = maxmapsize; 1157 dmc->dmc_maxseg = maxseg; 1158 1159 for (u_int i = 0; i < minmaps; i++) { 1160 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1161 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1162 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1163 if (error) { 1164 aprint_error_dev(sc->sc_dev, 1165 "failed to creat dma map cache " 1166 "entry %u of %zu (max %zu): %d\n", 1167 i, minmaps, maxmaps, error); 1168 while (i-- > 0) { 1169 bus_dmamap_destroy(sc->sc_dmat, 1170 dmc->dmc_maps[i]); 1171 } 1172 kmem_free(dmc, dmc_size); 1173 return error; 1174 } 1175 KASSERT(dmc->dmc_maps[i] != NULL); 1176 } 1177 1178 *dmc_p = dmc; 1179 1180 return 0; 1181 } 1182 1183 #if 0 1184 static void 1185 pq3etsec_dmamem_free( 1186 bus_dma_tag_t dmat, 1187 size_t map_size, 1188 bus_dma_segment_t *seg, 1189 bus_dmamap_t map, 1190 void *kvap) 1191 { 1192 bus_dmamap_destroy(dmat, map); 1193 bus_dmamem_unmap(dmat, kvap, map_size); 1194 bus_dmamem_free(dmat, seg, 1); 1195 } 1196 #endif 1197 1198 static int 1199 pq3etsec_dmamem_alloc( 1200 bus_dma_tag_t dmat, 1201 size_t map_size, 1202 bus_dma_segment_t *seg, 1203 bus_dmamap_t *map, 1204 void **kvap) 1205 { 1206 int error; 1207 int nseg; 1208 1209 *kvap = NULL; 1210 *map = NULL; 1211 1212 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1213 seg, 1, &nseg, 0); 1214 if (error) 1215 return error; 1216 1217 KASSERT(nseg == 1); 1218 1219 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1220 BUS_DMA_COHERENT); 1221 if (error == 0) { 1222 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1223 map); 1224 if (error == 0) { 1225 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1226 NULL, 0); 1227 if (error == 0) 1228 return 0; 1229 bus_dmamap_destroy(dmat, *map); 1230 *map = NULL; 1231 } 1232 bus_dmamem_unmap(dmat, *kvap, map_size); 1233 *kvap = NULL; 1234 } 1235 bus_dmamem_free(dmat, seg, nseg); 1236 return 0; 1237 } 1238 1239 static struct mbuf * 1240 pq3etsec_rx_buf_alloc( 1241 struct pq3etsec_softc *sc) 1242 { 1243 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1244 if (m == NULL) { 1245 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1246 return NULL; 1247 } 1248 MCLGET(m, M_DONTWAIT); 1249 if ((m->m_flags & M_EXT) == 0) { 1250 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1251 m_freem(m); 1252 return NULL; 1253 } 1254 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1255 1256 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1257 if (map == NULL) { 1258 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1259 m_freem(m); 1260 return NULL; 1261 } 1262 M_SETCTX(m, map); 1263 m->m_len = m->m_pkthdr.len = MCLBYTES; 1264 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1265 BUS_DMA_READ|BUS_DMA_NOWAIT); 1266 if (error) { 1267 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1268 error); 1269 M_SETCTX(m, NULL); 1270 m_freem(m); 1271 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1272 return NULL; 1273 } 1274 KASSERT(map->dm_mapsize == MCLBYTES); 1275 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1276 BUS_DMASYNC_PREREAD); 1277 1278 return m; 1279 } 1280 1281 static void 1282 pq3etsec_rx_map_unload( 1283 struct pq3etsec_softc *sc, 1284 struct mbuf *m) 1285 { 1286 KASSERT(m); 1287 for (; m != NULL; m = m->m_next) { 1288 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1289 KASSERT(map); 1290 KASSERT(map->dm_mapsize == MCLBYTES); 1291 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1292 BUS_DMASYNC_POSTREAD); 1293 bus_dmamap_unload(sc->sc_dmat, map); 1294 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1295 M_SETCTX(m, NULL); 1296 } 1297 } 1298 1299 static bool 1300 pq3etsec_rxq_produce( 1301 struct pq3etsec_softc *sc, 1302 struct pq3etsec_rxqueue *rxq) 1303 { 1304 volatile struct rxbd *producer = rxq->rxq_producer; 1305 #if 0 1306 size_t inuse = rxq->rxq_inuse; 1307 #endif 1308 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1309 struct mbuf *m; 1310 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1311 if (m == NULL) { 1312 m = pq3etsec_rx_buf_alloc(sc); 1313 if (m == NULL) { 1314 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1315 break; 1316 } 1317 } 1318 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1319 KASSERT(map); 1320 1321 #ifdef ETSEC_DEBUG 1322 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1323 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1324 #endif 1325 1326 /* rxbd_len is write-only by the ETSEC */ 1327 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1328 membar_producer(); 1329 producer->rxbd_flags |= RXBD_E; 1330 if (__predict_false(rxq->rxq_mhead == NULL)) { 1331 KASSERT(producer == rxq->rxq_consumer); 1332 rxq->rxq_mconsumer = m; 1333 } 1334 *rxq->rxq_mtail = m; 1335 rxq->rxq_mtail = &m->m_next; 1336 m->m_len = MCLBYTES; 1337 m->m_next = NULL; 1338 rxq->rxq_inuse++; 1339 if (++producer == rxq->rxq_last) { 1340 membar_producer(); 1341 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1342 rxq->rxq_last - rxq->rxq_producer); 1343 producer = rxq->rxq_producer = rxq->rxq_first; 1344 } 1345 } 1346 if (producer != rxq->rxq_producer) { 1347 membar_producer(); 1348 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1349 producer - rxq->rxq_producer); 1350 rxq->rxq_producer = producer; 1351 } 1352 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1353 if (qhlt) { 1354 KASSERT(qhlt & rxq->rxq_qmask); 1355 sc->sc_ev_rx_stall.ev_count++; 1356 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1357 } 1358 #if 0 1359 aprint_normal_dev(sc->sc_dev, 1360 "%s: buffers inuse went from %zu to %zu\n", 1361 __func__, inuse, rxq->rxq_inuse); 1362 #endif 1363 return true; 1364 } 1365 1366 static bool 1367 pq3etsec_rx_offload( 1368 struct pq3etsec_softc *sc, 1369 struct mbuf *m, 1370 const struct rxfcb *fcb) 1371 { 1372 if (fcb->rxfcb_flags & RXFCB_VLN) { 1373 VLAN_INPUT_TAG(&sc->sc_if, m, fcb->rxfcb_vlctl, 1374 m_freem(m); return false); 1375 } 1376 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1377 || (fcb->rxfcb_flags & (RXFCB_CIP|RXFCB_CTU)) == 0) 1378 return true; 1379 int csum_flags = 0; 1380 if ((fcb->rxfcb_flags & (RXFCB_IP6|RXFCB_CIP)) == RXFCB_CIP) { 1381 csum_flags |= M_CSUM_IPv4; 1382 if (fcb->rxfcb_flags & RXFCB_EIP) 1383 csum_flags |= M_CSUM_IPv4_BAD; 1384 } 1385 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1386 int ipv_flags; 1387 if (fcb->rxfcb_flags & RXFCB_IP6) 1388 ipv_flags = M_CSUM_TCPv6|M_CSUM_UDPv6; 1389 else 1390 ipv_flags = M_CSUM_TCPv4|M_CSUM_UDPv4; 1391 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1392 csum_flags |= (M_CSUM_TCPv4|M_CSUM_TCPv6) & ipv_flags; 1393 } else { 1394 csum_flags |= (M_CSUM_UDPv4|M_CSUM_UDPv6) & ipv_flags; 1395 } 1396 if (fcb->rxfcb_flags & RXFCB_ETU) 1397 csum_flags |= M_CSUM_TCP_UDP_BAD; 1398 } 1399 1400 m->m_pkthdr.csum_flags = csum_flags; 1401 return true; 1402 } 1403 1404 static void 1405 pq3etsec_rx_input( 1406 struct pq3etsec_softc *sc, 1407 struct mbuf *m, 1408 uint16_t rxbd_flags) 1409 { 1410 struct ifnet * const ifp = &sc->sc_if; 1411 1412 pq3etsec_rx_map_unload(sc, m); 1413 1414 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1415 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1416 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1417 return; 1418 } 1419 m_adj(m, sc->sc_rx_adjlen); 1420 1421 if (rxbd_flags & RXBD_M) 1422 m->m_flags |= M_PROMISC; 1423 if (rxbd_flags & RXBD_BC) 1424 m->m_flags |= M_BCAST; 1425 if (rxbd_flags & RXBD_MC) 1426 m->m_flags |= M_MCAST; 1427 m->m_flags |= M_HASFCS; 1428 m->m_pkthdr.rcvif = &sc->sc_if; 1429 1430 ifp->if_ipackets++; 1431 ifp->if_ibytes += m->m_pkthdr.len; 1432 1433 /* 1434 * Let's give it to the network subsystm to deal with. 1435 */ 1436 int s = splnet(); 1437 #if NBPFILTER > 0 1438 if (ifp->if_bpf) 1439 bpf_mtap(ifp->if_bpf, m); 1440 #endif 1441 (*ifp->if_input)(ifp, m); 1442 splx(s); 1443 } 1444 1445 static void 1446 pq3etsec_rxq_consume( 1447 struct pq3etsec_softc *sc, 1448 struct pq3etsec_rxqueue *rxq) 1449 { 1450 struct ifnet * const ifp = &sc->sc_if; 1451 volatile struct rxbd *consumer = rxq->rxq_consumer; 1452 size_t rxconsumed = 0; 1453 1454 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1455 1456 for (;;) { 1457 if (consumer == rxq->rxq_producer) { 1458 rxq->rxq_consumer = consumer; 1459 rxq->rxq_inuse -= rxconsumed; 1460 return; 1461 } 1462 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1463 const uint16_t rxbd_flags = consumer->rxbd_flags; 1464 if (rxbd_flags & RXBD_E) { 1465 rxq->rxq_consumer = consumer; 1466 rxq->rxq_inuse -= rxconsumed; 1467 return; 1468 } 1469 KASSERT(rxq->rxq_mconsumer != NULL); 1470 #ifdef ETSEC_DEBUG 1471 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1472 #endif 1473 #if 0 1474 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1475 __func__, 1476 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1477 mtod(rxq->rxq_mconsumer, int *)[0], 1478 mtod(rxq->rxq_mconsumer, int *)[1], 1479 mtod(rxq->rxq_mconsumer, int *)[2], 1480 mtod(rxq->rxq_mconsumer, int *)[3]); 1481 #endif 1482 /* 1483 * We own this packet again. Clear all flags except wrap. 1484 */ 1485 rxconsumed++; 1486 consumer->rxbd_flags = rxbd_flags & (RXBD_W|RXBD_I); 1487 1488 /* 1489 * If this descriptor has the LAST bit set and no errors, 1490 * it's a valid input packet. 1491 */ 1492 if ((rxbd_flags & (RXBD_L|RXBD_ERRORS)) == RXBD_L) { 1493 size_t rxbd_len = consumer->rxbd_len; 1494 struct mbuf *m = rxq->rxq_mhead; 1495 struct mbuf *m_last = rxq->rxq_mconsumer; 1496 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1497 rxq->rxq_mtail = &rxq->rxq_mhead; 1498 rxq->rxq_mconsumer = rxq->rxq_mhead; 1499 m_last->m_next = NULL; 1500 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1501 m->m_pkthdr.len = rxbd_len; 1502 pq3etsec_rx_input(sc, m, rxbd_flags); 1503 } else if (rxbd_flags & RXBD_L) { 1504 KASSERT(rxbd_flags & RXBD_ERRORS); 1505 struct mbuf *m; 1506 /* 1507 * We encountered an error, take the mbufs and add 1508 * then to the rx bufcache so we can reuse them. 1509 */ 1510 ifp->if_ierrors++; 1511 for (m = rxq->rxq_mhead; 1512 m != rxq->rxq_mconsumer; 1513 m = m->m_next) { 1514 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1515 } 1516 m = rxq->rxq_mconsumer; 1517 if ((rxq->rxq_mhead = m->m_next) == NULL) 1518 rxq->rxq_mtail = &rxq->rxq_mhead; 1519 rxq->rxq_mconsumer = m->m_next; 1520 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1521 } else { 1522 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1523 } 1524 #ifdef ETSEC_DEBUG 1525 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1526 #endif 1527 1528 /* 1529 * Wrap at the last entry! 1530 */ 1531 if (rxbd_flags & RXBD_W) { 1532 KASSERT(consumer + 1 == rxq->rxq_last); 1533 consumer = rxq->rxq_first; 1534 } else { 1535 consumer++; 1536 } 1537 #ifdef ETSEC_DEBUG 1538 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1539 #endif 1540 } 1541 } 1542 1543 static void 1544 pq3etsec_rxq_purge( 1545 struct pq3etsec_softc *sc, 1546 struct pq3etsec_rxqueue *rxq, 1547 bool discard) 1548 { 1549 struct mbuf *m; 1550 1551 if ((m = rxq->rxq_mhead) != NULL) { 1552 #ifdef ETSEC_DEBUG 1553 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1554 #endif 1555 1556 if (discard) { 1557 pq3etsec_rx_map_unload(sc, m); 1558 m_freem(m); 1559 } else { 1560 while (m != NULL) { 1561 struct mbuf *m0 = m->m_next; 1562 m->m_next = NULL; 1563 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1564 m = m0; 1565 } 1566 } 1567 1568 } 1569 1570 rxq->rxq_mconsumer = NULL; 1571 rxq->rxq_mhead = NULL; 1572 rxq->rxq_mtail = &rxq->rxq_mhead; 1573 rxq->rxq_inuse = 0; 1574 } 1575 1576 static void 1577 pq3etsec_rxq_reset( 1578 struct pq3etsec_softc *sc, 1579 struct pq3etsec_rxqueue *rxq) 1580 { 1581 /* 1582 * sync all the descriptors 1583 */ 1584 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1585 rxq->rxq_last - rxq->rxq_first); 1586 1587 /* 1588 * Make sure we own all descriptors in the ring. 1589 */ 1590 volatile struct rxbd *rxbd; 1591 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1592 rxbd->rxbd_flags = RXBD_I; 1593 } 1594 1595 /* 1596 * Last descriptor has the wrap flag. 1597 */ 1598 rxbd->rxbd_flags = RXBD_W|RXBD_I; 1599 1600 /* 1601 * Reset the producer consumer indexes. 1602 */ 1603 rxq->rxq_consumer = rxq->rxq_first; 1604 rxq->rxq_producer = rxq->rxq_first; 1605 rxq->rxq_inuse = 0; 1606 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1607 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1608 1609 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY; 1610 1611 /* 1612 * Restart the transmit at the first descriptor 1613 */ 1614 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1615 } 1616 1617 static int 1618 pq3etsec_rxq_attach( 1619 struct pq3etsec_softc *sc, 1620 struct pq3etsec_rxqueue *rxq, 1621 u_int qno) 1622 { 1623 size_t map_size = PAGE_SIZE; 1624 size_t desc_count = map_size / sizeof(struct rxbd); 1625 int error; 1626 void *descs; 1627 1628 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1629 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1630 if (error) 1631 return error; 1632 1633 memset(descs, 0, map_size); 1634 rxq->rxq_first = descs; 1635 rxq->rxq_last = rxq->rxq_first + desc_count; 1636 rxq->rxq_consumer = descs; 1637 rxq->rxq_producer = descs; 1638 1639 pq3etsec_rxq_purge(sc, rxq, true); 1640 pq3etsec_rxq_reset(sc, rxq); 1641 1642 rxq->rxq_reg_rbase = RBASEn(qno); 1643 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1644 1645 return 0; 1646 } 1647 1648 static bool 1649 pq3etsec_txq_active_p( 1650 struct pq3etsec_softc * const sc, 1651 struct pq3etsec_txqueue *txq) 1652 { 1653 return !IF_IS_EMPTY(&txq->txq_mbufs); 1654 } 1655 1656 static bool 1657 pq3etsec_txq_fillable_p( 1658 struct pq3etsec_softc * const sc, 1659 struct pq3etsec_txqueue *txq) 1660 { 1661 return txq->txq_free >= txq->txq_threshold; 1662 } 1663 1664 static int 1665 pq3etsec_txq_attach( 1666 struct pq3etsec_softc *sc, 1667 struct pq3etsec_txqueue *txq, 1668 u_int qno) 1669 { 1670 size_t map_size = PAGE_SIZE; 1671 size_t desc_count = map_size / sizeof(struct txbd); 1672 int error; 1673 void *descs; 1674 1675 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1676 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1677 if (error) 1678 return error; 1679 1680 memset(descs, 0, map_size); 1681 txq->txq_first = descs; 1682 txq->txq_last = txq->txq_first + desc_count; 1683 txq->txq_consumer = descs; 1684 txq->txq_producer = descs; 1685 1686 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1687 1688 txq->txq_reg_tbase = TBASEn(qno); 1689 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1690 1691 pq3etsec_txq_reset(sc, txq); 1692 1693 return 0; 1694 } 1695 1696 static int 1697 pq3etsec_txq_map_load( 1698 struct pq3etsec_softc *sc, 1699 struct pq3etsec_txqueue *txq, 1700 struct mbuf *m) 1701 { 1702 bus_dmamap_t map; 1703 int error; 1704 1705 map = M_GETCTX(m, bus_dmamap_t); 1706 if (map != NULL) 1707 return 0; 1708 1709 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1710 if (map == NULL) 1711 return ENOMEM; 1712 1713 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1714 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1715 if (error) 1716 return error; 1717 1718 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1719 BUS_DMASYNC_PREWRITE); 1720 M_SETCTX(m, map); 1721 return 0; 1722 } 1723 1724 static void 1725 pq3etsec_txq_map_unload( 1726 struct pq3etsec_softc *sc, 1727 struct pq3etsec_txqueue *txq, 1728 struct mbuf *m) 1729 { 1730 KASSERT(m); 1731 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1732 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1733 BUS_DMASYNC_POSTWRITE); 1734 bus_dmamap_unload(sc->sc_dmat, map); 1735 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1736 } 1737 1738 static bool 1739 pq3etsec_txq_produce( 1740 struct pq3etsec_softc *sc, 1741 struct pq3etsec_txqueue *txq, 1742 struct mbuf *m) 1743 { 1744 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1745 1746 if (map->dm_nsegs > txq->txq_free) 1747 return false; 1748 1749 /* 1750 * TCP Offload flag must be set in the first descriptor. 1751 */ 1752 volatile struct txbd *producer = txq->txq_producer; 1753 uint16_t last_flags = TXBD_L; 1754 uint16_t first_flags = TXBD_R 1755 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1756 1757 /* 1758 * If we've produced enough descriptors without consuming any 1759 * we need to ask for an interrupt to reclaim some. 1760 */ 1761 txq->txq_lastintr += map->dm_nsegs; 1762 if (txq->txq_lastintr >= txq->txq_threshold 1763 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1764 txq->txq_lastintr = 0; 1765 last_flags |= TXBD_I; 1766 } 1767 1768 #ifdef ETSEC_DEBUG 1769 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1770 #endif 1771 KASSERT(producer != txq->txq_last); 1772 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1773 producer->txbd_len = map->dm_segs[0].ds_len; 1774 1775 if (map->dm_nsegs > 1) { 1776 volatile struct txbd *start = producer + 1; 1777 size_t count = map->dm_nsegs - 1; 1778 for (u_int i = 1; i < map->dm_nsegs; i++) { 1779 if (__predict_false(++producer == txq->txq_last)) { 1780 producer = txq->txq_first; 1781 if (start < txq->txq_last) { 1782 pq3etsec_txq_desc_presync(sc, txq, 1783 start, txq->txq_last - start); 1784 count -= txq->txq_last - start; 1785 } 1786 start = txq->txq_first; 1787 } 1788 #ifdef ETSEC_DEBUG 1789 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1790 #endif 1791 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1792 producer->txbd_len = map->dm_segs[i].ds_len; 1793 producer->txbd_flags = TXBD_R 1794 | (producer->txbd_flags & TXBD_W) 1795 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1796 #if 0 1797 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1798 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1799 #endif 1800 } 1801 pq3etsec_txq_desc_presync(sc, txq, start, count); 1802 } else { 1803 first_flags |= last_flags; 1804 } 1805 1806 membar_producer(); 1807 txq->txq_producer->txbd_flags = 1808 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1809 #if 0 1810 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1811 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1812 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1813 #endif 1814 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1815 1816 /* 1817 * Reduce free count by the number of segments we consumed. 1818 */ 1819 txq->txq_free -= map->dm_nsegs; 1820 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 1821 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 1822 KASSERT(producer->txbd_flags & TXBD_L); 1823 #ifdef ETSEC_DEBUG 1824 txq->txq_lmbufs[producer - txq->txq_first] = m; 1825 #endif 1826 1827 #if 0 1828 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 1829 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 1830 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 1831 #endif 1832 1833 if (++producer == txq->txq_last) 1834 txq->txq_producer = txq->txq_first; 1835 else 1836 txq->txq_producer = producer; 1837 IF_ENQUEUE(&txq->txq_mbufs, m); 1838 1839 /* 1840 * Restart the transmitter. 1841 */ 1842 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 1843 1844 return true; 1845 } 1846 1847 static void 1848 pq3etsec_tx_offload( 1849 struct pq3etsec_softc *sc, 1850 struct pq3etsec_txqueue *txq, 1851 struct mbuf **mp) 1852 { 1853 struct mbuf *m = *mp; 1854 u_int csum_flags = m->m_pkthdr.csum_flags; 1855 struct m_tag *vtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m); 1856 1857 KASSERT(m->m_flags & M_PKTHDR); 1858 1859 /* 1860 * Let see if we are doing any offload first. 1861 */ 1862 if (csum_flags == 0 && vtag == 0) { 1863 m->m_flags &= ~M_HASFCB; 1864 return; 1865 } 1866 1867 uint16_t flags = 0; 1868 if (csum_flags & M_CSUM_IP) { 1869 flags |= TXFCB_IP 1870 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 1871 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 1872 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 1873 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 1874 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 1875 } 1876 if (vtag) { 1877 flags |= TXFCB_VLN; 1878 } 1879 if (flags == 0) { 1880 m->m_flags &= ~M_HASFCB; 1881 return; 1882 } 1883 1884 struct txfcb fcb; 1885 fcb.txfcb_flags = flags; 1886 if (csum_flags & M_CSUM_IPv4) 1887 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 1888 else 1889 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 1890 fcb.txfcb_l3os = ETHER_HDR_LEN; 1891 fcb.txfcb_phcs = 0; 1892 fcb.txfcb_vlctl = vtag ? VLAN_TAG_VALUE(vtag) & 0xffff : 0; 1893 1894 #if 0 1895 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 1896 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 1897 fcb.txfcb_phcs, fcb.txfcb_vlctl); 1898 #endif 1899 1900 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 1901 m->m_data -= sizeof(fcb); 1902 m->m_len += sizeof(fcb); 1903 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 1904 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 1905 m->m_data = m->m_pktdat; 1906 m->m_len += sizeof(fcb); 1907 } else { 1908 struct mbuf *mn; 1909 MGET(mn, M_DONTWAIT, m->m_type); 1910 if (mn == NULL) { 1911 if (csum_flags & M_CSUM_IP4) { 1912 #ifdef INET 1913 ip_undefer_csum(m, ETHER_HDR_LEN, 1914 csum_flags & M_CSUM_IP4); 1915 #else 1916 panic("%s: impossible M_CSUM flags %#x", 1917 device_xname(sc->sc_dev), csum_flags); 1918 #endif 1919 } else if (csum_flags & M_CSUM_IP6) { 1920 #ifdef INET6 1921 ip6_undefer_csum(m, ETHER_HDR_LEN, 1922 csum_flags & M_CSUM_IP6); 1923 #else 1924 panic("%s: impossible M_CSUM flags %#x", 1925 device_xname(sc->sc_dev), csum_flags); 1926 #endif 1927 } else if (vtag) { 1928 } 1929 1930 m->m_flags &= ~M_HASFCB; 1931 return; 1932 } 1933 1934 M_MOVE_PKTHDR(mn, m); 1935 mn->m_next = m; 1936 m = mn; 1937 MH_ALIGN(m, sizeof(fcb)); 1938 m->m_len = sizeof(fcb); 1939 *mp = m; 1940 } 1941 m->m_pkthdr.len += sizeof(fcb); 1942 m->m_flags |= M_HASFCB; 1943 *mtod(m, struct txfcb *) = fcb; 1944 return; 1945 } 1946 1947 static bool 1948 pq3etsec_txq_enqueue( 1949 struct pq3etsec_softc *sc, 1950 struct pq3etsec_txqueue *txq) 1951 { 1952 for (;;) { 1953 if (IF_QFULL(&txq->txq_mbufs)) 1954 return false; 1955 struct mbuf *m = txq->txq_next; 1956 if (m == NULL) { 1957 int s = splnet(); 1958 IF_DEQUEUE(&sc->sc_if.if_snd, m); 1959 splx(s); 1960 if (m == NULL) 1961 return true; 1962 M_SETCTX(m, NULL); 1963 pq3etsec_tx_offload(sc, txq, &m); 1964 } else { 1965 txq->txq_next = NULL; 1966 } 1967 int error = pq3etsec_txq_map_load(sc, txq, m); 1968 if (error) { 1969 aprint_error_dev(sc->sc_dev, 1970 "discarded packet due to " 1971 "dmamap load failure: %d\n", error); 1972 m_freem(m); 1973 continue; 1974 } 1975 KASSERT(txq->txq_next == NULL); 1976 if (!pq3etsec_txq_produce(sc, txq, m)) { 1977 txq->txq_next = m; 1978 return false; 1979 } 1980 KASSERT(txq->txq_next == NULL); 1981 } 1982 } 1983 1984 static bool 1985 pq3etsec_txq_consume( 1986 struct pq3etsec_softc *sc, 1987 struct pq3etsec_txqueue *txq) 1988 { 1989 struct ifnet * const ifp = &sc->sc_if; 1990 volatile struct txbd *consumer = txq->txq_consumer; 1991 size_t txfree = 0; 1992 1993 #if 0 1994 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 1995 #endif 1996 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 1997 1998 for (;;) { 1999 if (consumer == txq->txq_producer) { 2000 txq->txq_consumer = consumer; 2001 txq->txq_free += txfree; 2002 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2003 #if 0 2004 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2005 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2006 #endif 2007 KASSERT(txq->txq_lastintr == 0); 2008 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2009 return true; 2010 } 2011 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2012 const uint16_t txbd_flags = consumer->txbd_flags; 2013 if (txbd_flags & TXBD_R) { 2014 txq->txq_consumer = consumer; 2015 txq->txq_free += txfree; 2016 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2017 #if 0 2018 printf("%s: freed %zu descriptors\n", 2019 __func__, txfree); 2020 #endif 2021 return pq3etsec_txq_fillable_p(sc, txq); 2022 } 2023 2024 /* 2025 * If this is the last descriptor in the chain, get the 2026 * mbuf, free its dmamap, and free the mbuf chain itself. 2027 */ 2028 if (txbd_flags & TXBD_L) { 2029 struct mbuf *m; 2030 2031 IF_DEQUEUE(&txq->txq_mbufs, m); 2032 #ifdef ETSEC_DEBUG 2033 KASSERTMSG(m == txq->txq_lmbufs[consumer-txq->txq_first], 2034 ("%s: %p [%u]: flags %#x m (%p) != %p (%p)", __func__, 2035 consumer, consumer - txq->txq_first, txbd_flags, 2036 m, &txq->txq_lmbufs[consumer-txq->txq_first], 2037 txq->txq_lmbufs[consumer-txq->txq_first])); 2038 #endif 2039 KASSERT(m); 2040 pq3etsec_txq_map_unload(sc, txq, m); 2041 #if 0 2042 printf("%s: mbuf %p: consumed a %u byte packet\n", 2043 __func__, m, m->m_pkthdr.len); 2044 #endif 2045 if (m->m_flags & M_HASFCB) 2046 m_adj(m, sizeof(struct txfcb)); 2047 ifp->if_opackets++; 2048 ifp->if_obytes += m->m_pkthdr.len; 2049 if (m->m_flags & M_MCAST) 2050 ifp->if_omcasts++; 2051 if (txbd_flags & TXBD_ERRORS) 2052 ifp->if_oerrors++; 2053 m_freem(m); 2054 #ifdef ETSEC_DEBUG 2055 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2056 #endif 2057 } else { 2058 #ifdef ETSEC_DEBUG 2059 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2060 #endif 2061 } 2062 2063 /* 2064 * We own this packet again. Clear all flags except wrap. 2065 */ 2066 txfree++; 2067 //consumer->txbd_flags = txbd_flags & TXBD_W; 2068 2069 /* 2070 * Wrap at the last entry! 2071 */ 2072 if (txbd_flags & TXBD_W) { 2073 KASSERT(consumer + 1 == txq->txq_last); 2074 consumer = txq->txq_first; 2075 } else { 2076 consumer++; 2077 KASSERT(consumer < txq->txq_last); 2078 } 2079 } 2080 } 2081 2082 static void 2083 pq3etsec_txq_purge( 2084 struct pq3etsec_softc *sc, 2085 struct pq3etsec_txqueue *txq) 2086 { 2087 struct mbuf *m; 2088 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2089 2090 for (;;) { 2091 IF_DEQUEUE(&txq->txq_mbufs, m); 2092 if (m == NULL) 2093 break; 2094 pq3etsec_txq_map_unload(sc, txq, m); 2095 m_freem(m); 2096 } 2097 if ((m = txq->txq_next) != NULL) { 2098 txq->txq_next = NULL; 2099 pq3etsec_txq_map_unload(sc, txq, m); 2100 m_freem(m); 2101 } 2102 #ifdef ETSEC_DEBUG 2103 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2104 #endif 2105 } 2106 2107 static void 2108 pq3etsec_txq_reset( 2109 struct pq3etsec_softc *sc, 2110 struct pq3etsec_txqueue *txq) 2111 { 2112 /* 2113 * sync all the descriptors 2114 */ 2115 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2116 txq->txq_last - txq->txq_first); 2117 2118 /* 2119 * Make sure we own all descriptors in the ring. 2120 */ 2121 volatile struct txbd *txbd; 2122 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2123 txbd->txbd_flags = 0; 2124 } 2125 2126 /* 2127 * Last descriptor has the wrap flag. 2128 */ 2129 txbd->txbd_flags = TXBD_W; 2130 2131 /* 2132 * Reset the producer consumer indexes. 2133 */ 2134 txq->txq_consumer = txq->txq_first; 2135 txq->txq_producer = txq->txq_first; 2136 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2137 txq->txq_threshold = txq->txq_free / 2; 2138 txq->txq_lastintr = 0; 2139 2140 /* 2141 * What do we want to get interrupted on? 2142 */ 2143 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE; 2144 2145 /* 2146 * Restart the transmit at the first descriptor 2147 */ 2148 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2149 } 2150 2151 static void 2152 pq3etsec_ifstart(struct ifnet *ifp) 2153 { 2154 struct pq3etsec_softc * const sc = ifp->if_softc; 2155 2156 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2157 softint_schedule(sc->sc_soft_ih); 2158 } 2159 2160 static void 2161 pq3etsec_tx_error( 2162 struct pq3etsec_softc * const sc) 2163 { 2164 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2165 2166 pq3etsec_txq_consume(sc, txq); 2167 2168 if (pq3etsec_txq_fillable_p(sc, txq)) 2169 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2170 if (sc->sc_txerrors & (IEVENT_LC|IEVENT_CRL|IEVENT_XFUN|IEVENT_BABT)) { 2171 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2172 } 2173 2174 if (pq3etsec_txq_active_p(sc, txq)) 2175 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2176 if (!pq3etsec_txq_enqueue(sc, txq)) { 2177 sc->sc_ev_tx_stall.ev_count++; 2178 sc->sc_if.if_flags |= IFF_OACTIVE; 2179 } 2180 2181 sc->sc_txerrors = 0; 2182 } 2183 2184 int 2185 pq3etsec_tx_intr(void *arg) 2186 { 2187 struct pq3etsec_softc * const sc = arg; 2188 2189 sc->sc_ev_tx_intr.ev_count++; 2190 2191 uint32_t ievent = etsec_read(sc, IEVENT); 2192 ievent &= IEVENT_TXF|IEVENT_TXB; 2193 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2194 2195 #if 0 2196 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2197 __func__, ievent, etsec_read(sc, IMASK)); 2198 #endif 2199 2200 if (ievent == 0) 2201 return 0; 2202 2203 sc->sc_imask &= ~(IEVENT_TXF|IEVENT_TXB); 2204 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2205 etsec_write(sc, IMASK, sc->sc_imask); 2206 softint_schedule(sc->sc_soft_ih); 2207 return 1; 2208 } 2209 2210 int 2211 pq3etsec_rx_intr(void *arg) 2212 { 2213 struct pq3etsec_softc * const sc = arg; 2214 2215 sc->sc_ev_rx_intr.ev_count++; 2216 2217 uint32_t ievent = etsec_read(sc, IEVENT); 2218 ievent &= IEVENT_RXF|IEVENT_RXB; 2219 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2220 if (ievent == 0) 2221 return 0; 2222 2223 #if 0 2224 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2225 #endif 2226 2227 sc->sc_imask &= ~(IEVENT_RXF|IEVENT_RXB); 2228 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2229 etsec_write(sc, IMASK, sc->sc_imask); 2230 softint_schedule(sc->sc_soft_ih); 2231 return 1; 2232 } 2233 2234 int 2235 pq3etsec_error_intr(void *arg) 2236 { 2237 struct pq3etsec_softc * const sc = arg; 2238 2239 sc->sc_ev_error_intr.ev_count++; 2240 2241 for (int rv = 0, soft_flags = 0;; rv = 1) { 2242 uint32_t ievent = etsec_read(sc, IEVENT); 2243 ievent &= ~(IEVENT_RXF|IEVENT_RXB|IEVENT_TXF|IEVENT_TXB); 2244 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2245 if (ievent == 0) { 2246 if (soft_flags) { 2247 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2248 softint_schedule(sc->sc_soft_ih); 2249 } 2250 return rv; 2251 } 2252 #if 0 2253 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2254 __func__, ievent, etsec_read(sc, IMASK)); 2255 #endif 2256 2257 if (ievent & (IEVENT_GRSC|IEVENT_GTSC)) { 2258 sc->sc_imask &= ~(IEVENT_GRSC|IEVENT_GTSC); 2259 etsec_write(sc, IMASK, sc->sc_imask); 2260 wakeup(sc); 2261 } 2262 if (ievent & (IEVENT_MMRD|IEVENT_MMWR)) { 2263 sc->sc_imask &= ~(IEVENT_MMRD|IEVENT_MMWR); 2264 etsec_write(sc, IMASK, sc->sc_imask); 2265 wakeup(&sc->sc_mii); 2266 } 2267 if (ievent & IEVENT_BSY) { 2268 soft_flags |= SOFT_RXBSY; 2269 sc->sc_imask &= ~IEVENT_BSY; 2270 etsec_write(sc, IMASK, sc->sc_imask); 2271 } 2272 if (ievent & IEVENT_TXE) { 2273 soft_flags |= SOFT_TXERROR; 2274 sc->sc_imask &= ~IEVENT_TXE; 2275 sc->sc_txerrors |= ievent; 2276 } 2277 if (ievent & IEVENT_TXC) { 2278 sc->sc_ev_tx_pause.ev_count++; 2279 } 2280 if (ievent & IEVENT_RXC) { 2281 sc->sc_ev_rx_pause.ev_count++; 2282 } 2283 if (ievent & IEVENT_DPE) { 2284 soft_flags |= SOFT_RESET; 2285 sc->sc_imask &= ~IEVENT_DPE; 2286 etsec_write(sc, IMASK, sc->sc_imask); 2287 } 2288 } 2289 } 2290 2291 void 2292 pq3etsec_soft_intr(void *arg) 2293 { 2294 struct pq3etsec_softc * const sc = arg; 2295 struct ifnet * const ifp = &sc->sc_if; 2296 2297 mutex_enter(sc->sc_lock); 2298 2299 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2300 2301 sc->sc_ev_soft_intr.ev_count++; 2302 2303 if (soft_flags & SOFT_RESET) { 2304 int s = splnet(); 2305 pq3etsec_ifinit(ifp); 2306 splx(s); 2307 soft_flags = 0; 2308 } 2309 2310 if (soft_flags & SOFT_RXBSY) { 2311 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2312 size_t threshold = 5 * rxq->rxq_threshold / 4; 2313 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2314 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2315 } else { 2316 sc->sc_imask |= IEVENT_BSY; 2317 } 2318 aprint_normal_dev(sc->sc_dev, 2319 "increasing receive buffers from %zu to %zu\n", 2320 rxq->rxq_threshold, threshold); 2321 rxq->rxq_threshold = threshold; 2322 } 2323 2324 if ((soft_flags & SOFT_TXINTR) 2325 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2326 /* 2327 * Let's do what we came here for. Consume transmitted 2328 * packets off the the transmit ring. 2329 */ 2330 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2331 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2332 sc->sc_ev_tx_stall.ev_count++; 2333 ifp->if_flags |= IFF_OACTIVE; 2334 } else { 2335 ifp->if_flags &= ~IFF_OACTIVE; 2336 } 2337 sc->sc_imask |= IEVENT_TXF; 2338 } 2339 2340 if (soft_flags & (SOFT_RXINTR|SOFT_RXBSY)) { 2341 /* 2342 * Let's consume 2343 */ 2344 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2345 sc->sc_imask |= IEVENT_RXF; 2346 } 2347 2348 if (soft_flags & SOFT_TXERROR) { 2349 pq3etsec_tx_error(sc); 2350 sc->sc_imask |= IEVENT_TXE; 2351 } 2352 2353 if (ifp->if_flags & IFF_RUNNING) { 2354 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2355 etsec_write(sc, IMASK, sc->sc_imask); 2356 } else { 2357 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2358 } 2359 2360 mutex_exit(sc->sc_lock); 2361 } 2362 2363 static void 2364 pq3etsec_mii_tick(void *arg) 2365 { 2366 struct pq3etsec_softc * const sc = arg; 2367 mutex_enter(sc->sc_lock); 2368 callout_ack(&sc->sc_mii_callout); 2369 sc->sc_ev_mii_ticks.ev_count++; 2370 #ifdef DEBUG 2371 uint64_t now = mftb(); 2372 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2373 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2374 __func__, now - sc->sc_mii_last_tick); 2375 callout_stop(&sc->sc_mii_callout); 2376 } 2377 #endif 2378 mii_tick(&sc->sc_mii); 2379 int s = splnet(); 2380 if (sc->sc_soft_flags & SOFT_RESET) 2381 softint_schedule(sc->sc_soft_ih); 2382 splx(s); 2383 callout_schedule(&sc->sc_mii_callout, hz); 2384 #ifdef DEBUG 2385 sc->sc_mii_last_tick = now; 2386 #endif 2387 mutex_exit(sc->sc_lock); 2388 } 2389
Indexes created Thu Oct 02 14:10:14 GMT 2025