pq3etsec.c revision 1.1.4.1
1 /* $NetBSD: pq3etsec.c,v 1.1.4.1 2011/06/06 09:06:26 jruoho Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_inet.h" 38 39 #include <sys/cdefs.h> 40 41 #include <sys/param.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 #include <sys/mbuf.h> 45 #include <sys/ioctl.h> 46 #include <sys/intr.h> 47 #include <sys/bus.h> 48 #include <sys/kernel.h> 49 #include <sys/kmem.h> 50 #include <sys/proc.h> 51 #include <sys/atomic.h> 52 #include <sys/callout.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_ether.h> 57 #include <net/if_media.h> 58 59 #include <dev/mii/miivar.h> 60 61 #include "ioconf.h" 62 63 #include <net/bpf.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <netinet/in_offload.h> 70 #endif /* INET */ 71 #ifdef INET6 72 #include <netinet6/in6.h> 73 #include <netinet/ip6.h> 74 #endif 75 #include <netinet6/in6_offload.h> 76 77 78 #include <powerpc/spr.h> 79 #include <powerpc/booke/spr.h> 80 81 #include <powerpc/booke/cpuvar.h> 82 #include <powerpc/booke/e500var.h> 83 #include <powerpc/booke/e500reg.h> 84 #include <powerpc/booke/etsecreg.h> 85 86 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 87 88 #define ETSEC_MAXTXMBUFS 30 89 #define ETSEC_NTXSEGS 30 90 #define ETSEC_MAXRXMBUFS 511 91 #define ETSEC_MINRXMBUFS 32 92 #define ETSEC_NRXSEGS 1 93 94 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 95 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx\ 96 |IFCAP_CSUM_UDPv4_Rx\ 97 |IFCAP_CSUM_TCPv6_Rx\ 98 |IFCAP_CSUM_UDPv6_Rx) 99 100 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 101 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx\ 102 |IFCAP_CSUM_UDPv4_Tx\ 103 |IFCAP_CSUM_TCPv6_Tx\ 104 |IFCAP_CSUM_UDPv6_Tx) 105 106 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN|IFCAP_RCTRL_TUCSEN\ 107 |IFCAP_TCTRL_IPCSEN|IFCAP_TCTRL_TUCSEN) 108 109 #define M_CSUM_IP (M_CSUM_CIP|M_CSUM_CTU) 110 #define M_CSUM_IP6 (M_CSUM_TCPv6|M_CSUM_UDPv6) 111 #define M_CSUM_TUP (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 112 #define M_CSUM_UDP (M_CSUM_UDPv4|M_CSUM_UDPv6) 113 #define M_CSUM_IP4 (M_CSUM_IPv4|M_CSUM_UDPv4|M_CSUM_TCPv4) 114 #define M_CSUM_CIP (M_CSUM_IPv4) 115 #define M_CSUM_CTU (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 116 117 struct pq3etsec_txqueue { 118 bus_dmamap_t txq_descmap; 119 volatile struct txbd *txq_consumer; 120 volatile struct txbd *txq_producer; 121 volatile struct txbd *txq_first; 122 volatile struct txbd *txq_last; 123 struct ifqueue txq_mbufs; 124 struct mbuf *txq_next; 125 #ifdef ETSEC_DEBUG 126 struct mbuf *txq_lmbufs[512]; 127 #endif 128 uint32_t txq_qmask; 129 uint32_t txq_free; 130 uint32_t txq_threshold; 131 uint32_t txq_lastintr; 132 bus_size_t txq_reg_tbase; 133 bus_dma_segment_t txq_descmap_seg; 134 }; 135 136 struct pq3etsec_rxqueue { 137 bus_dmamap_t rxq_descmap; 138 volatile struct rxbd *rxq_consumer; 139 volatile struct rxbd *rxq_producer; 140 volatile struct rxbd *rxq_first; 141 volatile struct rxbd *rxq_last; 142 struct mbuf *rxq_mhead; 143 struct mbuf **rxq_mtail; 144 struct mbuf *rxq_mconsumer; 145 #ifdef ETSEC_DEBUG 146 struct mbuf *rxq_mbufs[512]; 147 #endif 148 uint32_t rxq_qmask; 149 uint32_t rxq_inuse; 150 uint32_t rxq_threshold; 151 bus_size_t rxq_reg_rbase; 152 bus_size_t rxq_reg_rbptr; 153 bus_dma_segment_t rxq_descmap_seg; 154 }; 155 156 struct pq3etsec_mapcache { 157 u_int dmc_nmaps; 158 u_int dmc_maxseg; 159 u_int dmc_maxmaps; 160 u_int dmc_maxmapsize; 161 bus_dmamap_t dmc_maps[0]; 162 }; 163 164 struct pq3etsec_softc { 165 device_t sc_dev; 166 struct ethercom sc_ec; 167 #define sc_if sc_ec.ec_if 168 struct mii_data sc_mii; 169 bus_space_tag_t sc_bst; 170 bus_space_handle_t sc_bsh; 171 bus_dma_tag_t sc_dmat; 172 int sc_phy_addr; 173 prop_dictionary_t sc_intrmap; 174 uint32_t sc_intrmask; 175 176 uint32_t sc_soft_flags; 177 #define SOFT_RESET 0x0001 178 #define SOFT_RXINTR 0x0010 179 #define SOFT_RXBSY 0x0020 180 #define SOFT_TXINTR 0x0100 181 #define SOFT_TXERROR 0x0200 182 183 struct pq3etsec_txqueue sc_txq; 184 struct pq3etsec_rxqueue sc_rxq; 185 uint32_t sc_txerrors; 186 uint32_t sc_rxerrors; 187 188 size_t sc_rx_adjlen; 189 190 /* 191 * Copies of various ETSEC registers. 192 */ 193 uint32_t sc_imask; 194 uint32_t sc_maccfg1; 195 uint32_t sc_maccfg2; 196 uint32_t sc_maxfrm; 197 uint32_t sc_ecntrl; 198 uint32_t sc_dmactrl; 199 uint32_t sc_macstnaddr1; 200 uint32_t sc_macstnaddr2; 201 uint32_t sc_tctrl; 202 uint32_t sc_rctrl; 203 uint32_t sc_gaddr[16]; 204 uint64_t sc_macaddrs[15]; 205 206 void *sc_tx_ih; 207 void *sc_rx_ih; 208 void *sc_error_ih; 209 void *sc_soft_ih; 210 211 kmutex_t *sc_lock; 212 213 struct evcnt sc_ev_tx_stall; 214 struct evcnt sc_ev_tx_intr; 215 struct evcnt sc_ev_rx_stall; 216 struct evcnt sc_ev_rx_intr; 217 struct evcnt sc_ev_error_intr; 218 struct evcnt sc_ev_soft_intr; 219 struct evcnt sc_ev_tx_pause; 220 struct evcnt sc_ev_rx_pause; 221 struct evcnt sc_ev_mii_ticks; 222 223 struct callout sc_mii_callout; 224 uint64_t sc_mii_last_tick; 225 226 struct ifqueue sc_rx_bufcache; 227 struct pq3etsec_mapcache *sc_rx_mapcache; 228 struct pq3etsec_mapcache *sc_tx_mapcache; 229 }; 230 231 static int pq3etsec_match(device_t, cfdata_t, void *); 232 static void pq3etsec_attach(device_t, device_t, void *); 233 234 static void pq3etsec_ifstart(struct ifnet *); 235 static void pq3etsec_ifwatchdog(struct ifnet *); 236 static int pq3etsec_ifinit(struct ifnet *); 237 static void pq3etsec_ifstop(struct ifnet *, int); 238 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 239 240 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 241 struct pq3etsec_mapcache **, size_t, size_t, size_t, size_t); 242 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 243 struct pq3etsec_mapcache *); 244 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 245 struct pq3etsec_mapcache *); 246 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 247 struct pq3etsec_mapcache *, bus_dmamap_t); 248 249 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 250 struct pq3etsec_txqueue *, u_int); 251 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 252 struct pq3etsec_txqueue *); 253 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 254 struct pq3etsec_txqueue *); 255 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 256 struct pq3etsec_txqueue *); 257 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 258 struct pq3etsec_txqueue *, struct mbuf *m); 259 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 260 struct pq3etsec_txqueue *); 261 262 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 263 struct pq3etsec_rxqueue *, u_int); 264 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 265 struct pq3etsec_rxqueue *); 266 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 267 struct pq3etsec_rxqueue *, bool); 268 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 269 struct pq3etsec_rxqueue *); 270 271 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 272 273 static void pq3etsec_mii_tick(void *); 274 static int pq3etsec_rx_intr(void *); 275 static int pq3etsec_tx_intr(void *); 276 static int pq3etsec_error_intr(void *); 277 static void pq3etsec_soft_intr(void *); 278 279 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 280 pq3etsec_match, pq3etsec_attach, NULL, NULL); 281 282 static int 283 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 284 { 285 286 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 287 return 0; 288 289 return 1; 290 } 291 292 static inline uint32_t 293 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 294 { 295 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 296 } 297 298 static inline void 299 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 300 { 301 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 302 } 303 304 static int 305 pq3etsec_mii_readreg(device_t self, int phy, int reg) 306 { 307 struct pq3etsec_softc * const sc = device_private(self); 308 uint32_t miimcom = etsec_read(sc, MIIMCOM); 309 310 // int s = splnet(); 311 312 etsec_write(sc, MIIMADD, 313 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 314 315 etsec_write(sc, IEVENT, IEVENT_MMRD); 316 etsec_write(sc, MIIMCOM, 0); /* clear any past bits */ 317 etsec_write(sc, MIIMCOM, MIIMCOM_READ); 318 #if 0 319 sc->sc_imask |= IEVENT_MMRD; 320 etsec_write(sc, IMASK, sc->sc_imask); 321 #endif 322 323 while (etsec_read(sc, MIIMIND) != 0) { 324 delay(1); 325 } 326 int data = etsec_read(sc, MIIMSTAT); 327 328 if (miimcom == MIIMCOM_SCAN) 329 etsec_write(sc, MIIMCOM, miimcom); 330 331 #if 0 332 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 333 __func__, phy, reg, data); 334 #endif 335 etsec_write(sc, IEVENT, IEVENT_MMRD); 336 // splx(s); 337 return data; 338 } 339 340 static void 341 pq3etsec_mii_writereg(device_t self, int phy, int reg, int data) 342 { 343 struct pq3etsec_softc * const sc = device_private(self); 344 uint32_t miimcom = etsec_read(sc, MIIMCOM); 345 346 #if 0 347 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 348 __func__, phy, reg, data); 349 #endif 350 351 // int s = splnet(); 352 etsec_write(sc, IEVENT, IEVENT_MMWR); 353 etsec_write(sc, MIIMADD, 354 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 355 etsec_write(sc, MIIMCOM, 0); /* clear any past bits */ 356 etsec_write(sc, MIIMCON, data); 357 358 #if 0 359 sc->sc_imask |= IEVENT_MMWR; 360 etsec_write(sc, IMASK, sc->sc_imask); 361 #endif 362 363 int timo = 1000; /* 1ms */ 364 while ((etsec_read(sc, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 365 delay(1); 366 } 367 368 if (miimcom == MIIMCOM_SCAN) 369 etsec_write(sc, MIIMCOM, miimcom); 370 etsec_write(sc, IEVENT, IEVENT_MMWR); 371 // splx(s); 372 } 373 374 static void 375 pq3etsec_mii_statchg(device_t self) 376 { 377 struct pq3etsec_softc * const sc = device_private(self); 378 struct mii_data * const mii = &sc->sc_mii; 379 380 uint32_t maccfg1 = sc->sc_maccfg1; 381 uint32_t maccfg2 = sc->sc_maccfg2; 382 uint32_t ecntrl = sc->sc_ecntrl; 383 384 maccfg1 &= ~(MACCFG1_TX_FLOW|MACCFG1_RX_FLOW); 385 maccfg2 &= ~(MACCFG2_IFMODE|MACCFG2_FD); 386 387 if (sc->sc_mii.mii_media_active & IFM_FDX) { 388 maccfg2 |= MACCFG2_FD; 389 } 390 391 /* 392 * Now deal with the flow control bits. 393 */ 394 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 395 && (mii->mii_media_active & IFM_ETH_FMASK)) { 396 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 397 maccfg1 |= MACCFG1_RX_FLOW; 398 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 399 maccfg1 |= MACCFG1_TX_FLOW; 400 } 401 402 /* 403 * Now deal with the speed. 404 */ 405 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 406 maccfg2 |= MACCFG2_IFMODE_GMII; 407 } else { 408 maccfg2 |= MACCFG2_IFMODE_MII; 409 ecntrl &= ~ECNTRL_R100M; 410 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 411 ecntrl |= ECNTRL_R100M; 412 } 413 } 414 415 /* 416 * If things are different, re-init things. 417 */ 418 if (maccfg1 != sc->sc_maccfg1 419 || maccfg2 != sc->sc_maccfg2 420 || ecntrl != sc->sc_ecntrl) { 421 if (sc->sc_if.if_flags & IFF_RUNNING) 422 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 423 sc->sc_maccfg1 = maccfg1; 424 sc->sc_maccfg2 = maccfg2; 425 sc->sc_ecntrl = ecntrl; 426 } 427 } 428 429 #if 0 430 static void 431 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 432 { 433 struct pq3etsec_softc * const sc = ifp->if_softc; 434 435 mii_pollstat(&sc->sc_mii); 436 ether_mediastatus(ifp, ifmr); 437 ifmr->ifm_status = sc->sc_mii.mii_media_status; 438 ifmr->ifm_active = sc->sc_mii.mii_media_active; 439 } 440 441 static int 442 pq3etsec_mediachange(struct ifnet *ifp) 443 { 444 struct pq3etsec_softc * const sc = ifp->if_softc; 445 446 if ((ifp->if_flags & IFF_UP) == 0) 447 return 0; 448 449 int rv = mii_mediachg(&sc->sc_mii); 450 return (rv == ENXIO) ? 0 : rv; 451 } 452 #endif 453 454 static void 455 pq3etsec_attach(device_t parent, device_t self, void *aux) 456 { 457 struct cpunode_softc * const psc = device_private(parent); 458 struct pq3etsec_softc * const sc = device_private(self); 459 struct cpunode_attach_args * const cna = aux; 460 struct cpunode_locators * const cnl = &cna->cna_locs; 461 int error; 462 463 psc->sc_children |= cna->cna_childmask; 464 sc->sc_dev = self; 465 sc->sc_bst = cna->cna_memt; 466 sc->sc_dmat = &booke_bus_dma_tag; 467 468 /* 469 * If we have a common MDIO bus, if all off instance 1. 470 */ 471 device_t miiself = (self->dv_cfdata->cf_flags & 0x100) 472 ? tsec_cd.cd_devs[0] 473 : self; 474 475 /* 476 * See if the phy is in the config file... 477 */ 478 if (self->dv_cfdata->cf_flags & 0x3f) { 479 sc->sc_phy_addr = (self->dv_cfdata->cf_flags & 0x3f) - 1; 480 } else { 481 unsigned char prop_name[20]; 482 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 483 cnl->cnl_instance); 484 sc->sc_phy_addr = board_info_get_number(prop_name); 485 } 486 aprint_normal(" phy %d", sc->sc_phy_addr); 487 488 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 489 &sc->sc_bsh); 490 if (error) { 491 aprint_error(": error mapping registers: %d\n", error); 492 return; 493 } 494 495 /* 496 * Assume firmware has aready set the mac address and fetch it 497 * before we reinit it. 498 */ 499 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 500 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 501 sc->sc_rctrl = RCTRL_DEFAULT; 502 sc->sc_maccfg2 = MACCFG2_DEFAULT; 503 504 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 505 size_t len; 506 const uint8_t *mac_addr = 507 board_info_get_data("tsec-mac-addr-base", &len); 508 KASSERT(len == ETHER_ADDR_LEN); 509 sc->sc_macstnaddr2 = 510 (mac_addr[1] << 24) 511 | (mac_addr[0] << 16); 512 sc->sc_macstnaddr1 = 513 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 514 | (mac_addr[4] << 16) 515 | (mac_addr[3] << 8) 516 | (mac_addr[2] << 0); 517 #if 0 518 aprint_error(": mac-address unknown\n"); 519 return; 520 #endif 521 } 522 523 char enaddr[ETHER_ADDR_LEN] = { 524 [0] = sc->sc_macstnaddr2 >> 16, 525 [1] = sc->sc_macstnaddr2 >> 24, 526 [2] = sc->sc_macstnaddr1 >> 0, 527 [3] = sc->sc_macstnaddr1 >> 8, 528 [4] = sc->sc_macstnaddr1 >> 16, 529 [5] = sc->sc_macstnaddr1 >> 24, 530 }; 531 532 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 533 if (error) { 534 aprint_error(": failed to init rxq: %d\n", error); 535 return; 536 } 537 538 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 539 if (error) { 540 aprint_error(": failed to init txq: %d\n", error); 541 return; 542 } 543 544 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 545 ETSEC_MAXRXMBUFS, ETSEC_MINRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 546 if (error) { 547 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 548 return; 549 } 550 551 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 552 ETSEC_MAXTXMBUFS, ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 553 if (error) { 554 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 555 return; 556 } 557 558 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 559 pq3etsec_tx_intr, sc); 560 if (sc->sc_tx_ih == NULL) { 561 aprint_error(": failed to establish tx interrupt: %d\n", 562 cnl->cnl_intrs[0]); 563 return; 564 } 565 566 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 567 pq3etsec_rx_intr, sc); 568 if (sc->sc_rx_ih == NULL) { 569 aprint_error(": failed to establish rx interrupt: %d\n", 570 cnl->cnl_intrs[1]); 571 return; 572 } 573 574 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 575 pq3etsec_error_intr, sc); 576 if (sc->sc_error_ih == NULL) { 577 aprint_error(": failed to establish error interrupt: %d\n", 578 cnl->cnl_intrs[2]); 579 return; 580 } 581 582 sc->sc_soft_ih = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 583 pq3etsec_soft_intr, sc); 584 if (sc->sc_soft_ih == NULL) { 585 aprint_error(": failed to establish soft interrupt\n"); 586 return; 587 } 588 589 aprint_normal("\n"); 590 591 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 592 593 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 594 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 595 596 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 597 ether_sprintf(enaddr)); 598 599 const char * const xname = device_xname(sc->sc_dev); 600 struct ethercom * const ec = &sc->sc_ec; 601 struct ifnet * const ifp = &ec->ec_if; 602 603 ec->ec_mii = &sc->sc_mii; 604 605 sc->sc_mii.mii_ifp = ifp; 606 sc->sc_mii.mii_readreg = pq3etsec_mii_readreg; 607 sc->sc_mii.mii_writereg = pq3etsec_mii_writereg; 608 sc->sc_mii.mii_statchg = pq3etsec_mii_statchg; 609 610 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 611 ether_mediastatus); 612 613 if (sc->sc_phy_addr < 32) { 614 mii_attach(miiself, &sc->sc_mii, 0xffffffff, 615 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 616 617 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 618 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 619 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 620 } else { 621 callout_schedule(&sc->sc_mii_callout, hz); 622 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 623 } 624 } else { 625 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 626 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX); 627 } 628 629 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 630 | ETHERCAP_JUMBO_MTU; 631 632 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 633 ifp->if_softc = sc; 634 ifp->if_capabilities = IFCAP_ETSEC; 635 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 636 ifp->if_ioctl = pq3etsec_ifioctl; 637 ifp->if_start = pq3etsec_ifstart; 638 ifp->if_watchdog = pq3etsec_ifwatchdog; 639 ifp->if_init = pq3etsec_ifinit; 640 ifp->if_stop = pq3etsec_ifstop; 641 IFQ_SET_READY(&ifp->if_snd); 642 643 pq3etsec_ifstop(ifp, true); 644 645 /* 646 * Attach the interface. 647 */ 648 if_attach(ifp); 649 ether_ifattach(ifp, enaddr); 650 651 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 652 NULL, xname, "rx stall"); 653 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 654 NULL, xname, "tx stall"); 655 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 656 NULL, xname, "tx intr"); 657 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 658 NULL, xname, "rx intr"); 659 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 660 NULL, xname, "error intr"); 661 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 662 NULL, xname, "soft intr"); 663 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 664 NULL, xname, "tx pause"); 665 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 666 NULL, xname, "rx pause"); 667 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 668 NULL, xname, "mii ticks"); 669 } 670 671 static uint64_t 672 pq3etsec_macaddr_create(const uint8_t *lladdr) 673 { 674 uint64_t macaddr = 0; 675 676 lladdr += ETHER_ADDR_LEN; 677 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 678 macaddr = (macaddr << 8) | *--lladdr; 679 } 680 return macaddr << 16; 681 } 682 683 static int 684 pq3etsec_ifinit(struct ifnet *ifp) 685 { 686 struct pq3etsec_softc * const sc = ifp->if_softc; 687 int error = 0; 688 689 sc->sc_maxfrm = max(ifp->if_mtu + 32, MCLBYTES); 690 if (ifp->if_mtu > ETHERMTU_JUMBO) 691 return error; 692 693 KASSERT(ifp->if_flags & IFF_UP); 694 695 /* 696 * Stop the interface (steps 1 to 4 in the Soft Reset and 697 * Reconfigurating Procedure. 698 */ 699 pq3etsec_ifstop(ifp, 0); 700 701 /* 702 * If our frame size has changed (or it's our first time through) 703 * destroy the existing transmit mapcache. 704 */ 705 if (sc->sc_tx_mapcache != NULL 706 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 707 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 708 sc->sc_tx_mapcache = NULL; 709 } 710 711 if (sc->sc_tx_mapcache == NULL) { 712 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 713 ETSEC_MAXTXMBUFS, ETSEC_MAXTXMBUFS, sc->sc_maxfrm, 714 ETSEC_NTXSEGS); 715 if (error) 716 return error; 717 } 718 719 sc->sc_ev_mii_ticks.ev_count++; 720 mii_tick(&sc->sc_mii); 721 722 if (ifp->if_flags & IFF_PROMISC) { 723 sc->sc_rctrl |= RCTRL_PROM; 724 } else { 725 sc->sc_rctrl &= ~RCTRL_PROM; 726 } 727 728 uint32_t rctrl_prsdep = 0; 729 sc->sc_rctrl &= ~(RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP); 730 if (VLAN_ATTACHED(&sc->sc_ec)) { 731 sc->sc_rctrl |= RCTRL_VLEX; 732 rctrl_prsdep = RCTRL_PRSDEP_L2; 733 } 734 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 735 sc->sc_rctrl |= RCTRL_IPCSEN; 736 rctrl_prsdep = RCTRL_PRSDEP_L3; 737 } 738 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 739 sc->sc_rctrl |= RCTRL_TUCSEN; 740 rctrl_prsdep = RCTRL_PRSDEP_L4; 741 } 742 sc->sc_rctrl |= rctrl_prsdep; 743 #if 0 744 if (sc->sc_rctrl & (RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP)) 745 aprint_normal_dev(sc->sc_dev, 746 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 747 sc->sc_rctrl, 748 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 749 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 750 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 751 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 752 #endif 753 754 sc->sc_tctrl &= ~(TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS); 755 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 756 sc->sc_tctrl |= TCTRL_VLINS; 757 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 758 sc->sc_tctrl |= TCTRL_IPCSEN; 759 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 760 sc->sc_tctrl |= TCTRL_TUCSEN; 761 #if 0 762 if (sc->sc_tctrl & (TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS)) 763 aprint_normal_dev(sc->sc_dev, 764 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 765 sc->sc_tctrl, 766 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 767 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 768 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 769 #endif 770 771 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN|MACCFG1_RX_EN); 772 773 const uint64_t macstnaddr = 774 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 775 776 sc->sc_imask = IEVENT_DPE; 777 778 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 779 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 780 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 781 782 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 783 pq3etsec_txq_reset(sc, &sc->sc_txq); 784 785 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 786 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 787 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 788 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 789 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 790 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 791 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 792 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 793 794 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 795 pq3etsec_mc_setup(sc); 796 797 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 798 etsec_write(sc, MRBLR, MCLBYTES); 799 800 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 801 sc->sc_dmactrl |= DMACTRL_DEFAULT; 802 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 803 804 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 805 etsec_write(sc, TQUEUE, TQUEUE_EN0); 806 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE|IEVENT_TXC; 807 808 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 809 810 /* 12. Enable receive queues in RQUEUE, */ 811 etsec_write(sc, RQUEUE, RQUEUE_EN0|RQUEUE_EX0); 812 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY|IEVENT_RXC; 813 814 /* and optionally set TOE functionality in RCTRL. */ 815 etsec_write(sc, RCTRL, sc->sc_rctrl); 816 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 817 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 818 sc->sc_rx_adjlen += sizeof(struct rxfcb); 819 820 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 821 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 822 823 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 824 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 825 826 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 827 sc->sc_dmactrl &= ~(DMACTRL_GRS|DMACTRL_GTS); 828 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 829 830 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 831 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 832 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 833 834 sc->sc_soft_flags = 0; 835 836 etsec_write(sc, IMASK, sc->sc_imask); 837 838 ifp->if_flags |= IFF_RUNNING; 839 840 return error; 841 } 842 843 static void 844 pq3etsec_ifstop(struct ifnet *ifp, int disable) 845 { 846 struct pq3etsec_softc * const sc = ifp->if_softc; 847 848 KASSERT(!cpu_intr_p()); 849 const uint32_t imask_gsc_mask = IEVENT_GTSC|IEVENT_GRSC; 850 /* 851 * Clear the GTSC and GRSC from the interrupt mask until 852 * we are ready for them. Then clear them from IEVENT, 853 * request the graceful shutdown, and then enable the 854 * GTSC and GRSC bits in the mask. This should cause the 855 * error interrupt to fire which will issue a wakeup to 856 * allow us to resume. 857 */ 858 859 /* 860 * 1. Set GRS/GTS bits in DMACTRL register 861 */ 862 sc->sc_dmactrl |= DMACTRL_GRS|DMACTRL_GTS; 863 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 864 etsec_write(sc, IEVENT, imask_gsc_mask); 865 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 866 867 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN|MACCFG1_RX_EN)) { 868 /* 869 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 870 */ 871 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 872 873 u_int timo = 1000; 874 uint32_t ievent = etsec_read(sc, IEVENT); 875 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 876 if (--timo == 0) { 877 aprint_error_dev(sc->sc_dev, 878 "WARNING: " 879 "request to stop failed (IEVENT=%#x)\n", 880 ievent); 881 break; 882 } 883 delay(10); 884 ievent = etsec_read(sc, IEVENT); 885 } 886 } 887 888 /* 889 * Now reset the controller. 890 * 891 * 3. Set SOFT_RESET bit in MACCFG1 register 892 * 4. Clear SOFT_RESET bit in MACCFG1 register 893 */ 894 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 895 etsec_write(sc, MACCFG1, 0); 896 etsec_write(sc, IMASK, 0); 897 etsec_write(sc, IEVENT, ~0); 898 sc->sc_imask = 0; 899 ifp->if_flags &= ~IFF_RUNNING; 900 901 uint32_t tbipa = etsec_read(sc, TBIPA); 902 if (tbipa == sc->sc_phy_addr) { 903 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 904 etsec_write(sc, TBIPA, 0x1f); 905 } 906 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 907 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 908 etsec_write(sc, MIIMCFG, miimcfg); 909 910 /* 911 * Let's consume any remaing transmitted packets. And if we are 912 * disabling the interface, purge ourselves of any untransmitted 913 * packets. But don't consume any received packets, just drop them. 914 * If we aren't disabling the interface, save the mbufs in the 915 * receive queue for reuse. 916 */ 917 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 918 pq3etsec_txq_consume(sc, &sc->sc_txq); 919 if (disable) { 920 pq3etsec_txq_purge(sc, &sc->sc_txq); 921 IF_PURGE(&ifp->if_snd); 922 } 923 } 924 925 static void 926 pq3etsec_ifwatchdog(struct ifnet *ifp) 927 { 928 } 929 930 static void 931 pq3etsec_mc_setup( 932 struct pq3etsec_softc *sc) 933 { 934 struct ethercom * const ec = &sc->sc_ec; 935 struct ifnet * const ifp = &sc->sc_if; 936 struct ether_multi *enm; 937 struct ether_multistep step; 938 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 939 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 940 941 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 942 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 943 944 ifp->if_flags &= ~IFF_ALLMULTI; 945 946 ETHER_FIRST_MULTI(step, ec, enm); 947 for (u_int i = 0; enm != NULL; ) { 948 const char *addr = enm->enm_addrlo; 949 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 950 ifp->if_flags |= IFF_ALLMULTI; 951 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 952 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 953 break; 954 } 955 if ((sc->sc_rctrl & RCTRL_EMEN) 956 && i < __arraycount(sc->sc_macaddrs)) { 957 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 958 } else { 959 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 960 #if 0 961 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 962 ether_sprintf(addr), crc, 963 crc >> crc_shift, 964 crc >> (crc_shift + 5), 965 (crc >> crc_shift) & 31, 966 1 << (((crc >> crc_shift) & 31) ^ 31)); 967 #endif 968 /* 969 * The documentation doesn't completely follow PowerPC 970 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 971 * is 0x7fa32d9b. By empirical testing, the 972 * corresponding hash bit is word 3, bit 31 (ppc bit 973 * order). Since 3 << 31 | 31 is 0x7f, we deduce 974 * H[0:2] selects the register while H[3:7] selects 975 * the bit (ppc bit order). 976 */ 977 crc >>= crc_shift; 978 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 979 } 980 ETHER_NEXT_MULTI(step, enm); 981 } 982 for (u_int i = 0; i < 8; i++) { 983 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 984 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 985 #if 0 986 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 987 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 988 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 989 i, GADDR(i), etsec_read(sc, GADDR(i))); 990 #endif 991 } 992 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 993 uint64_t macaddr = sc->sc_macaddrs[i]; 994 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 995 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 996 #if 0 997 if (macaddr) 998 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 999 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1000 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1001 #endif 1002 } 1003 } 1004 1005 static int 1006 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1007 { 1008 struct pq3etsec_softc *sc = ifp->if_softc; 1009 struct ifreq * const ifr = data; 1010 const int s = splnet(); 1011 int error; 1012 1013 switch (cmd) { 1014 case SIOCSIFMEDIA: 1015 case SIOCGIFMEDIA: 1016 /* Flow control requires full-duplex mode. */ 1017 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1018 (ifr->ifr_media & IFM_FDX) == 0) 1019 ifr->ifr_media &= ~IFM_ETH_FMASK; 1020 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1021 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1022 /* We can do both TXPAUSE and RXPAUSE. */ 1023 ifr->ifr_media |= 1024 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1025 } 1026 } 1027 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1028 break; 1029 1030 default: 1031 error = ether_ioctl(ifp, cmd, data); 1032 if (error != ENETRESET) 1033 break; 1034 1035 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1036 error = 0; 1037 if (ifp->if_flags & IFF_RUNNING) 1038 pq3etsec_mc_setup(sc); 1039 break; 1040 } 1041 error = pq3etsec_ifinit(ifp); 1042 break; 1043 } 1044 1045 splx(s); 1046 return error; 1047 } 1048 1049 static void 1050 pq3etsec_rxq_desc_presync( 1051 struct pq3etsec_softc *sc, 1052 struct pq3etsec_rxqueue *rxq, 1053 volatile struct rxbd *rxbd, 1054 size_t count) 1055 { 1056 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1057 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1058 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1059 } 1060 1061 static void 1062 pq3etsec_rxq_desc_postsync( 1063 struct pq3etsec_softc *sc, 1064 struct pq3etsec_rxqueue *rxq, 1065 volatile struct rxbd *rxbd, 1066 size_t count) 1067 { 1068 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1069 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1070 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1071 } 1072 1073 static void 1074 pq3etsec_txq_desc_presync( 1075 struct pq3etsec_softc *sc, 1076 struct pq3etsec_txqueue *txq, 1077 volatile struct txbd *txbd, 1078 size_t count) 1079 { 1080 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1081 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1082 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1083 } 1084 1085 static void 1086 pq3etsec_txq_desc_postsync( 1087 struct pq3etsec_softc *sc, 1088 struct pq3etsec_txqueue *txq, 1089 volatile struct txbd *txbd, 1090 size_t count) 1091 { 1092 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1093 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1094 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1095 } 1096 1097 static bus_dmamap_t 1098 pq3etsec_mapcache_get( 1099 struct pq3etsec_softc *sc, 1100 struct pq3etsec_mapcache *dmc) 1101 { 1102 if (dmc->dmc_nmaps == 0) { 1103 bus_dmamap_t map; 1104 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1105 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1106 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &map); 1107 if (error) { 1108 aprint_error_dev(sc->sc_dev, 1109 "failed to allocate a %zuB map: %d\n", 1110 dmc->dmc_maxmapsize, error); 1111 return NULL; 1112 } 1113 return map; 1114 } 1115 1116 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1117 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1118 } 1119 1120 static void 1121 pq3etsec_mapcache_put( 1122 struct pq3etsec_softc *sc, 1123 struct pq3etsec_mapcache *dmc, 1124 bus_dmamap_t map) 1125 { 1126 KASSERT(map != NULL); 1127 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1128 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1129 } 1130 1131 static void 1132 pq3etsec_mapcache_destroy( 1133 struct pq3etsec_softc *sc, 1134 struct pq3etsec_mapcache *dmc) 1135 { 1136 const size_t dmc_size = 1137 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1138 1139 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1140 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1141 } 1142 kmem_free(dmc, dmc_size); 1143 } 1144 1145 static int 1146 pq3etsec_mapcache_create( 1147 struct pq3etsec_softc *sc, 1148 struct pq3etsec_mapcache **dmc_p, 1149 size_t maxmaps, 1150 size_t minmaps, 1151 size_t maxmapsize, 1152 size_t maxseg) 1153 { 1154 const size_t dmc_size = 1155 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1156 struct pq3etsec_mapcache * const dmc = kmem_zalloc(dmc_size, KM_SLEEP); 1157 1158 dmc->dmc_maxmaps = maxmaps; 1159 dmc->dmc_nmaps = minmaps; 1160 dmc->dmc_maxmapsize = maxmapsize; 1161 dmc->dmc_maxseg = maxseg; 1162 1163 for (u_int i = 0; i < minmaps; i++) { 1164 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1165 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1166 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1167 if (error) { 1168 aprint_error_dev(sc->sc_dev, 1169 "failed to creat dma map cache " 1170 "entry %u of %zu (max %zu): %d\n", 1171 i, minmaps, maxmaps, error); 1172 while (i-- > 0) { 1173 bus_dmamap_destroy(sc->sc_dmat, 1174 dmc->dmc_maps[i]); 1175 } 1176 kmem_free(dmc, dmc_size); 1177 return error; 1178 } 1179 KASSERT(dmc->dmc_maps[i] != NULL); 1180 } 1181 1182 *dmc_p = dmc; 1183 1184 return 0; 1185 } 1186 1187 #if 0 1188 static void 1189 pq3etsec_dmamem_free( 1190 bus_dma_tag_t dmat, 1191 size_t map_size, 1192 bus_dma_segment_t *seg, 1193 bus_dmamap_t map, 1194 void *kvap) 1195 { 1196 bus_dmamap_destroy(dmat, map); 1197 bus_dmamem_unmap(dmat, kvap, map_size); 1198 bus_dmamem_free(dmat, seg, 1); 1199 } 1200 #endif 1201 1202 static int 1203 pq3etsec_dmamem_alloc( 1204 bus_dma_tag_t dmat, 1205 size_t map_size, 1206 bus_dma_segment_t *seg, 1207 bus_dmamap_t *map, 1208 void **kvap) 1209 { 1210 int error; 1211 int nseg; 1212 1213 *kvap = NULL; 1214 *map = NULL; 1215 1216 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1217 seg, 1, &nseg, 0); 1218 if (error) 1219 return error; 1220 1221 KASSERT(nseg == 1); 1222 1223 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1224 BUS_DMA_COHERENT); 1225 if (error == 0) { 1226 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1227 map); 1228 if (error == 0) { 1229 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1230 NULL, 0); 1231 if (error == 0) 1232 return 0; 1233 bus_dmamap_destroy(dmat, *map); 1234 *map = NULL; 1235 } 1236 bus_dmamem_unmap(dmat, *kvap, map_size); 1237 *kvap = NULL; 1238 } 1239 bus_dmamem_free(dmat, seg, nseg); 1240 return 0; 1241 } 1242 1243 static struct mbuf * 1244 pq3etsec_rx_buf_alloc( 1245 struct pq3etsec_softc *sc) 1246 { 1247 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1248 if (m == NULL) { 1249 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1250 return NULL; 1251 } 1252 MCLGET(m, M_DONTWAIT); 1253 if ((m->m_flags & M_EXT) == 0) { 1254 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1255 m_freem(m); 1256 return NULL; 1257 } 1258 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1259 1260 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1261 if (map == NULL) { 1262 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1263 m_freem(m); 1264 return NULL; 1265 } 1266 M_SETCTX(m, map); 1267 m->m_len = m->m_pkthdr.len = MCLBYTES; 1268 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1269 BUS_DMA_READ|BUS_DMA_NOWAIT); 1270 if (error) { 1271 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1272 error); 1273 M_SETCTX(m, NULL); 1274 m_freem(m); 1275 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1276 return NULL; 1277 } 1278 KASSERT(map->dm_mapsize == MCLBYTES); 1279 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1280 BUS_DMASYNC_PREREAD); 1281 1282 return m; 1283 } 1284 1285 static void 1286 pq3etsec_rx_map_unload( 1287 struct pq3etsec_softc *sc, 1288 struct mbuf *m) 1289 { 1290 KASSERT(m); 1291 for (; m != NULL; m = m->m_next) { 1292 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1293 KASSERT(map); 1294 KASSERT(map->dm_mapsize == MCLBYTES); 1295 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1296 BUS_DMASYNC_POSTREAD); 1297 bus_dmamap_unload(sc->sc_dmat, map); 1298 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1299 M_SETCTX(m, NULL); 1300 } 1301 } 1302 1303 static bool 1304 pq3etsec_rxq_produce( 1305 struct pq3etsec_softc *sc, 1306 struct pq3etsec_rxqueue *rxq) 1307 { 1308 volatile struct rxbd *producer = rxq->rxq_producer; 1309 #if 0 1310 size_t inuse = rxq->rxq_inuse; 1311 #endif 1312 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1313 struct mbuf *m; 1314 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1315 if (m == NULL) { 1316 m = pq3etsec_rx_buf_alloc(sc); 1317 if (m == NULL) { 1318 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1319 break; 1320 } 1321 } 1322 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1323 KASSERT(map); 1324 1325 #ifdef ETSEC_DEBUG 1326 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1327 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1328 #endif 1329 1330 /* rxbd_len is write-only by the ETSEC */ 1331 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1332 membar_producer(); 1333 producer->rxbd_flags |= RXBD_E; 1334 if (__predict_false(rxq->rxq_mhead == NULL)) { 1335 KASSERT(producer == rxq->rxq_consumer); 1336 rxq->rxq_mconsumer = m; 1337 } 1338 *rxq->rxq_mtail = m; 1339 rxq->rxq_mtail = &m->m_next; 1340 m->m_len = MCLBYTES; 1341 m->m_next = NULL; 1342 rxq->rxq_inuse++; 1343 if (++producer == rxq->rxq_last) { 1344 membar_producer(); 1345 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1346 rxq->rxq_last - rxq->rxq_producer); 1347 producer = rxq->rxq_producer = rxq->rxq_first; 1348 } 1349 } 1350 if (producer != rxq->rxq_producer) { 1351 membar_producer(); 1352 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1353 producer - rxq->rxq_producer); 1354 rxq->rxq_producer = producer; 1355 } 1356 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1357 if (qhlt) { 1358 KASSERT(qhlt & rxq->rxq_qmask); 1359 sc->sc_ev_rx_stall.ev_count++; 1360 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1361 } 1362 #if 0 1363 aprint_normal_dev(sc->sc_dev, 1364 "%s: buffers inuse went from %zu to %zu\n", 1365 __func__, inuse, rxq->rxq_inuse); 1366 #endif 1367 return true; 1368 } 1369 1370 static bool 1371 pq3etsec_rx_offload( 1372 struct pq3etsec_softc *sc, 1373 struct mbuf *m, 1374 const struct rxfcb *fcb) 1375 { 1376 if (fcb->rxfcb_flags & RXFCB_VLN) { 1377 VLAN_INPUT_TAG(&sc->sc_if, m, fcb->rxfcb_vlctl, 1378 m_freem(m); return false); 1379 } 1380 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1381 || (fcb->rxfcb_flags & (RXFCB_CIP|RXFCB_CTU)) == 0) 1382 return true; 1383 int csum_flags = 0; 1384 if ((fcb->rxfcb_flags & (RXFCB_IP6|RXFCB_CIP)) == RXFCB_CIP) { 1385 csum_flags |= M_CSUM_IPv4; 1386 if (fcb->rxfcb_flags & RXFCB_EIP) 1387 csum_flags |= M_CSUM_IPv4_BAD; 1388 } 1389 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1390 int ipv_flags; 1391 if (fcb->rxfcb_flags & RXFCB_IP6) 1392 ipv_flags = M_CSUM_TCPv6|M_CSUM_UDPv6; 1393 else 1394 ipv_flags = M_CSUM_TCPv4|M_CSUM_UDPv4; 1395 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1396 csum_flags |= (M_CSUM_TCPv4|M_CSUM_TCPv6) & ipv_flags; 1397 } else { 1398 csum_flags |= (M_CSUM_UDPv4|M_CSUM_UDPv6) & ipv_flags; 1399 } 1400 if (fcb->rxfcb_flags & RXFCB_ETU) 1401 csum_flags |= M_CSUM_TCP_UDP_BAD; 1402 } 1403 1404 m->m_pkthdr.csum_flags = csum_flags; 1405 return true; 1406 } 1407 1408 static void 1409 pq3etsec_rx_input( 1410 struct pq3etsec_softc *sc, 1411 struct mbuf *m, 1412 uint16_t rxbd_flags) 1413 { 1414 struct ifnet * const ifp = &sc->sc_if; 1415 1416 pq3etsec_rx_map_unload(sc, m); 1417 1418 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1419 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1420 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1421 return; 1422 } 1423 m_adj(m, sc->sc_rx_adjlen); 1424 1425 if (rxbd_flags & RXBD_M) 1426 m->m_flags |= M_PROMISC; 1427 if (rxbd_flags & RXBD_BC) 1428 m->m_flags |= M_BCAST; 1429 if (rxbd_flags & RXBD_MC) 1430 m->m_flags |= M_MCAST; 1431 m->m_flags |= M_HASFCS; 1432 m->m_pkthdr.rcvif = &sc->sc_if; 1433 1434 ifp->if_ipackets++; 1435 ifp->if_ibytes += m->m_pkthdr.len; 1436 1437 /* 1438 * Let's give it to the network subsystm to deal with. 1439 */ 1440 int s = splnet(); 1441 bpf_mtap(ifp, m); 1442 (*ifp->if_input)(ifp, m); 1443 splx(s); 1444 } 1445 1446 static void 1447 pq3etsec_rxq_consume( 1448 struct pq3etsec_softc *sc, 1449 struct pq3etsec_rxqueue *rxq) 1450 { 1451 struct ifnet * const ifp = &sc->sc_if; 1452 volatile struct rxbd *consumer = rxq->rxq_consumer; 1453 size_t rxconsumed = 0; 1454 1455 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1456 1457 for (;;) { 1458 if (consumer == rxq->rxq_producer) { 1459 rxq->rxq_consumer = consumer; 1460 rxq->rxq_inuse -= rxconsumed; 1461 return; 1462 } 1463 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1464 const uint16_t rxbd_flags = consumer->rxbd_flags; 1465 if (rxbd_flags & RXBD_E) { 1466 rxq->rxq_consumer = consumer; 1467 rxq->rxq_inuse -= rxconsumed; 1468 return; 1469 } 1470 KASSERT(rxq->rxq_mconsumer != NULL); 1471 #ifdef ETSEC_DEBUG 1472 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1473 #endif 1474 #if 0 1475 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1476 __func__, 1477 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1478 mtod(rxq->rxq_mconsumer, int *)[0], 1479 mtod(rxq->rxq_mconsumer, int *)[1], 1480 mtod(rxq->rxq_mconsumer, int *)[2], 1481 mtod(rxq->rxq_mconsumer, int *)[3]); 1482 #endif 1483 /* 1484 * We own this packet again. Clear all flags except wrap. 1485 */ 1486 rxconsumed++; 1487 consumer->rxbd_flags = rxbd_flags & (RXBD_W|RXBD_I); 1488 1489 /* 1490 * If this descriptor has the LAST bit set and no errors, 1491 * it's a valid input packet. 1492 */ 1493 if ((rxbd_flags & (RXBD_L|RXBD_ERRORS)) == RXBD_L) { 1494 size_t rxbd_len = consumer->rxbd_len; 1495 struct mbuf *m = rxq->rxq_mhead; 1496 struct mbuf *m_last = rxq->rxq_mconsumer; 1497 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1498 rxq->rxq_mtail = &rxq->rxq_mhead; 1499 rxq->rxq_mconsumer = rxq->rxq_mhead; 1500 m_last->m_next = NULL; 1501 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1502 m->m_pkthdr.len = rxbd_len; 1503 pq3etsec_rx_input(sc, m, rxbd_flags); 1504 } else if (rxbd_flags & RXBD_L) { 1505 KASSERT(rxbd_flags & RXBD_ERRORS); 1506 struct mbuf *m; 1507 /* 1508 * We encountered an error, take the mbufs and add 1509 * then to the rx bufcache so we can reuse them. 1510 */ 1511 ifp->if_ierrors++; 1512 for (m = rxq->rxq_mhead; 1513 m != rxq->rxq_mconsumer; 1514 m = m->m_next) { 1515 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1516 } 1517 m = rxq->rxq_mconsumer; 1518 if ((rxq->rxq_mhead = m->m_next) == NULL) 1519 rxq->rxq_mtail = &rxq->rxq_mhead; 1520 rxq->rxq_mconsumer = m->m_next; 1521 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1522 } else { 1523 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1524 } 1525 #ifdef ETSEC_DEBUG 1526 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1527 #endif 1528 1529 /* 1530 * Wrap at the last entry! 1531 */ 1532 if (rxbd_flags & RXBD_W) { 1533 KASSERT(consumer + 1 == rxq->rxq_last); 1534 consumer = rxq->rxq_first; 1535 } else { 1536 consumer++; 1537 } 1538 #ifdef ETSEC_DEBUG 1539 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1540 #endif 1541 } 1542 } 1543 1544 static void 1545 pq3etsec_rxq_purge( 1546 struct pq3etsec_softc *sc, 1547 struct pq3etsec_rxqueue *rxq, 1548 bool discard) 1549 { 1550 struct mbuf *m; 1551 1552 if ((m = rxq->rxq_mhead) != NULL) { 1553 #ifdef ETSEC_DEBUG 1554 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1555 #endif 1556 1557 if (discard) { 1558 pq3etsec_rx_map_unload(sc, m); 1559 m_freem(m); 1560 } else { 1561 while (m != NULL) { 1562 struct mbuf *m0 = m->m_next; 1563 m->m_next = NULL; 1564 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1565 m = m0; 1566 } 1567 } 1568 1569 } 1570 1571 rxq->rxq_mconsumer = NULL; 1572 rxq->rxq_mhead = NULL; 1573 rxq->rxq_mtail = &rxq->rxq_mhead; 1574 rxq->rxq_inuse = 0; 1575 } 1576 1577 static void 1578 pq3etsec_rxq_reset( 1579 struct pq3etsec_softc *sc, 1580 struct pq3etsec_rxqueue *rxq) 1581 { 1582 /* 1583 * sync all the descriptors 1584 */ 1585 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1586 rxq->rxq_last - rxq->rxq_first); 1587 1588 /* 1589 * Make sure we own all descriptors in the ring. 1590 */ 1591 volatile struct rxbd *rxbd; 1592 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1593 rxbd->rxbd_flags = RXBD_I; 1594 } 1595 1596 /* 1597 * Last descriptor has the wrap flag. 1598 */ 1599 rxbd->rxbd_flags = RXBD_W|RXBD_I; 1600 1601 /* 1602 * Reset the producer consumer indexes. 1603 */ 1604 rxq->rxq_consumer = rxq->rxq_first; 1605 rxq->rxq_producer = rxq->rxq_first; 1606 rxq->rxq_inuse = 0; 1607 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1608 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1609 1610 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY; 1611 1612 /* 1613 * Restart the transmit at the first descriptor 1614 */ 1615 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1616 } 1617 1618 static int 1619 pq3etsec_rxq_attach( 1620 struct pq3etsec_softc *sc, 1621 struct pq3etsec_rxqueue *rxq, 1622 u_int qno) 1623 { 1624 size_t map_size = PAGE_SIZE; 1625 size_t desc_count = map_size / sizeof(struct rxbd); 1626 int error; 1627 void *descs; 1628 1629 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1630 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1631 if (error) 1632 return error; 1633 1634 memset(descs, 0, map_size); 1635 rxq->rxq_first = descs; 1636 rxq->rxq_last = rxq->rxq_first + desc_count; 1637 rxq->rxq_consumer = descs; 1638 rxq->rxq_producer = descs; 1639 1640 pq3etsec_rxq_purge(sc, rxq, true); 1641 pq3etsec_rxq_reset(sc, rxq); 1642 1643 rxq->rxq_reg_rbase = RBASEn(qno); 1644 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1645 1646 return 0; 1647 } 1648 1649 static bool 1650 pq3etsec_txq_active_p( 1651 struct pq3etsec_softc * const sc, 1652 struct pq3etsec_txqueue *txq) 1653 { 1654 return !IF_IS_EMPTY(&txq->txq_mbufs); 1655 } 1656 1657 static bool 1658 pq3etsec_txq_fillable_p( 1659 struct pq3etsec_softc * const sc, 1660 struct pq3etsec_txqueue *txq) 1661 { 1662 return txq->txq_free >= txq->txq_threshold; 1663 } 1664 1665 static int 1666 pq3etsec_txq_attach( 1667 struct pq3etsec_softc *sc, 1668 struct pq3etsec_txqueue *txq, 1669 u_int qno) 1670 { 1671 size_t map_size = PAGE_SIZE; 1672 size_t desc_count = map_size / sizeof(struct txbd); 1673 int error; 1674 void *descs; 1675 1676 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1677 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1678 if (error) 1679 return error; 1680 1681 memset(descs, 0, map_size); 1682 txq->txq_first = descs; 1683 txq->txq_last = txq->txq_first + desc_count; 1684 txq->txq_consumer = descs; 1685 txq->txq_producer = descs; 1686 1687 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1688 1689 txq->txq_reg_tbase = TBASEn(qno); 1690 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1691 1692 pq3etsec_txq_reset(sc, txq); 1693 1694 return 0; 1695 } 1696 1697 static int 1698 pq3etsec_txq_map_load( 1699 struct pq3etsec_softc *sc, 1700 struct pq3etsec_txqueue *txq, 1701 struct mbuf *m) 1702 { 1703 bus_dmamap_t map; 1704 int error; 1705 1706 map = M_GETCTX(m, bus_dmamap_t); 1707 if (map != NULL) 1708 return 0; 1709 1710 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1711 if (map == NULL) 1712 return ENOMEM; 1713 1714 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1715 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1716 if (error) 1717 return error; 1718 1719 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1720 BUS_DMASYNC_PREWRITE); 1721 M_SETCTX(m, map); 1722 return 0; 1723 } 1724 1725 static void 1726 pq3etsec_txq_map_unload( 1727 struct pq3etsec_softc *sc, 1728 struct pq3etsec_txqueue *txq, 1729 struct mbuf *m) 1730 { 1731 KASSERT(m); 1732 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1733 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1734 BUS_DMASYNC_POSTWRITE); 1735 bus_dmamap_unload(sc->sc_dmat, map); 1736 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1737 } 1738 1739 static bool 1740 pq3etsec_txq_produce( 1741 struct pq3etsec_softc *sc, 1742 struct pq3etsec_txqueue *txq, 1743 struct mbuf *m) 1744 { 1745 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1746 1747 if (map->dm_nsegs > txq->txq_free) 1748 return false; 1749 1750 /* 1751 * TCP Offload flag must be set in the first descriptor. 1752 */ 1753 volatile struct txbd *producer = txq->txq_producer; 1754 uint16_t last_flags = TXBD_L; 1755 uint16_t first_flags = TXBD_R 1756 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1757 1758 /* 1759 * If we've produced enough descriptors without consuming any 1760 * we need to ask for an interrupt to reclaim some. 1761 */ 1762 txq->txq_lastintr += map->dm_nsegs; 1763 if (txq->txq_lastintr >= txq->txq_threshold 1764 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1765 txq->txq_lastintr = 0; 1766 last_flags |= TXBD_I; 1767 } 1768 1769 #ifdef ETSEC_DEBUG 1770 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1771 #endif 1772 KASSERT(producer != txq->txq_last); 1773 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1774 producer->txbd_len = map->dm_segs[0].ds_len; 1775 1776 if (map->dm_nsegs > 1) { 1777 volatile struct txbd *start = producer + 1; 1778 size_t count = map->dm_nsegs - 1; 1779 for (u_int i = 1; i < map->dm_nsegs; i++) { 1780 if (__predict_false(++producer == txq->txq_last)) { 1781 producer = txq->txq_first; 1782 if (start < txq->txq_last) { 1783 pq3etsec_txq_desc_presync(sc, txq, 1784 start, txq->txq_last - start); 1785 count -= txq->txq_last - start; 1786 } 1787 start = txq->txq_first; 1788 } 1789 #ifdef ETSEC_DEBUG 1790 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1791 #endif 1792 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1793 producer->txbd_len = map->dm_segs[i].ds_len; 1794 producer->txbd_flags = TXBD_R 1795 | (producer->txbd_flags & TXBD_W) 1796 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1797 #if 0 1798 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1799 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1800 #endif 1801 } 1802 pq3etsec_txq_desc_presync(sc, txq, start, count); 1803 } else { 1804 first_flags |= last_flags; 1805 } 1806 1807 membar_producer(); 1808 txq->txq_producer->txbd_flags = 1809 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1810 #if 0 1811 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1812 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1813 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1814 #endif 1815 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1816 1817 /* 1818 * Reduce free count by the number of segments we consumed. 1819 */ 1820 txq->txq_free -= map->dm_nsegs; 1821 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 1822 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 1823 KASSERT(producer->txbd_flags & TXBD_L); 1824 #ifdef ETSEC_DEBUG 1825 txq->txq_lmbufs[producer - txq->txq_first] = m; 1826 #endif 1827 1828 #if 0 1829 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 1830 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 1831 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 1832 #endif 1833 1834 if (++producer == txq->txq_last) 1835 txq->txq_producer = txq->txq_first; 1836 else 1837 txq->txq_producer = producer; 1838 IF_ENQUEUE(&txq->txq_mbufs, m); 1839 1840 /* 1841 * Restart the transmitter. 1842 */ 1843 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 1844 1845 return true; 1846 } 1847 1848 static void 1849 pq3etsec_tx_offload( 1850 struct pq3etsec_softc *sc, 1851 struct pq3etsec_txqueue *txq, 1852 struct mbuf **mp) 1853 { 1854 struct mbuf *m = *mp; 1855 u_int csum_flags = m->m_pkthdr.csum_flags; 1856 struct m_tag *vtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m); 1857 1858 KASSERT(m->m_flags & M_PKTHDR); 1859 1860 /* 1861 * Let see if we are doing any offload first. 1862 */ 1863 if (csum_flags == 0 && vtag == 0) { 1864 m->m_flags &= ~M_HASFCB; 1865 return; 1866 } 1867 1868 uint16_t flags = 0; 1869 if (csum_flags & M_CSUM_IP) { 1870 flags |= TXFCB_IP 1871 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 1872 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 1873 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 1874 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 1875 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 1876 } 1877 if (vtag) { 1878 flags |= TXFCB_VLN; 1879 } 1880 if (flags == 0) { 1881 m->m_flags &= ~M_HASFCB; 1882 return; 1883 } 1884 1885 struct txfcb fcb; 1886 fcb.txfcb_flags = flags; 1887 if (csum_flags & M_CSUM_IPv4) 1888 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 1889 else 1890 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 1891 fcb.txfcb_l3os = ETHER_HDR_LEN; 1892 fcb.txfcb_phcs = 0; 1893 fcb.txfcb_vlctl = vtag ? VLAN_TAG_VALUE(vtag) & 0xffff : 0; 1894 1895 #if 0 1896 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 1897 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 1898 fcb.txfcb_phcs, fcb.txfcb_vlctl); 1899 #endif 1900 1901 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 1902 m->m_data -= sizeof(fcb); 1903 m->m_len += sizeof(fcb); 1904 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 1905 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 1906 m->m_data = m->m_pktdat; 1907 m->m_len += sizeof(fcb); 1908 } else { 1909 struct mbuf *mn; 1910 MGET(mn, M_DONTWAIT, m->m_type); 1911 if (mn == NULL) { 1912 if (csum_flags & M_CSUM_IP4) { 1913 #ifdef INET 1914 ip_undefer_csum(m, ETHER_HDR_LEN, 1915 csum_flags & M_CSUM_IP4); 1916 #else 1917 panic("%s: impossible M_CSUM flags %#x", 1918 device_xname(sc->sc_dev), csum_flags); 1919 #endif 1920 } else if (csum_flags & M_CSUM_IP6) { 1921 #ifdef INET6 1922 ip6_undefer_csum(m, ETHER_HDR_LEN, 1923 csum_flags & M_CSUM_IP6); 1924 #else 1925 panic("%s: impossible M_CSUM flags %#x", 1926 device_xname(sc->sc_dev), csum_flags); 1927 #endif 1928 } else if (vtag) { 1929 } 1930 1931 m->m_flags &= ~M_HASFCB; 1932 return; 1933 } 1934 1935 M_MOVE_PKTHDR(mn, m); 1936 mn->m_next = m; 1937 m = mn; 1938 MH_ALIGN(m, sizeof(fcb)); 1939 m->m_len = sizeof(fcb); 1940 *mp = m; 1941 } 1942 m->m_pkthdr.len += sizeof(fcb); 1943 m->m_flags |= M_HASFCB; 1944 *mtod(m, struct txfcb *) = fcb; 1945 return; 1946 } 1947 1948 static bool 1949 pq3etsec_txq_enqueue( 1950 struct pq3etsec_softc *sc, 1951 struct pq3etsec_txqueue *txq) 1952 { 1953 for (;;) { 1954 if (IF_QFULL(&txq->txq_mbufs)) 1955 return false; 1956 struct mbuf *m = txq->txq_next; 1957 if (m == NULL) { 1958 int s = splnet(); 1959 IF_DEQUEUE(&sc->sc_if.if_snd, m); 1960 splx(s); 1961 if (m == NULL) 1962 return true; 1963 M_SETCTX(m, NULL); 1964 pq3etsec_tx_offload(sc, txq, &m); 1965 } else { 1966 txq->txq_next = NULL; 1967 } 1968 int error = pq3etsec_txq_map_load(sc, txq, m); 1969 if (error) { 1970 aprint_error_dev(sc->sc_dev, 1971 "discarded packet due to " 1972 "dmamap load failure: %d\n", error); 1973 m_freem(m); 1974 continue; 1975 } 1976 KASSERT(txq->txq_next == NULL); 1977 if (!pq3etsec_txq_produce(sc, txq, m)) { 1978 txq->txq_next = m; 1979 return false; 1980 } 1981 KASSERT(txq->txq_next == NULL); 1982 } 1983 } 1984 1985 static bool 1986 pq3etsec_txq_consume( 1987 struct pq3etsec_softc *sc, 1988 struct pq3etsec_txqueue *txq) 1989 { 1990 struct ifnet * const ifp = &sc->sc_if; 1991 volatile struct txbd *consumer = txq->txq_consumer; 1992 size_t txfree = 0; 1993 1994 #if 0 1995 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 1996 #endif 1997 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 1998 1999 for (;;) { 2000 if (consumer == txq->txq_producer) { 2001 txq->txq_consumer = consumer; 2002 txq->txq_free += txfree; 2003 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2004 #if 0 2005 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2006 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2007 #endif 2008 KASSERT(txq->txq_lastintr == 0); 2009 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2010 return true; 2011 } 2012 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2013 const uint16_t txbd_flags = consumer->txbd_flags; 2014 if (txbd_flags & TXBD_R) { 2015 txq->txq_consumer = consumer; 2016 txq->txq_free += txfree; 2017 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2018 #if 0 2019 printf("%s: freed %zu descriptors\n", 2020 __func__, txfree); 2021 #endif 2022 return pq3etsec_txq_fillable_p(sc, txq); 2023 } 2024 2025 /* 2026 * If this is the last descriptor in the chain, get the 2027 * mbuf, free its dmamap, and free the mbuf chain itself. 2028 */ 2029 if (txbd_flags & TXBD_L) { 2030 struct mbuf *m; 2031 2032 IF_DEQUEUE(&txq->txq_mbufs, m); 2033 #ifdef ETSEC_DEBUG 2034 KASSERTMSG(m == txq->txq_lmbufs[consumer-txq->txq_first], 2035 ("%s: %p [%u]: flags %#x m (%p) != %p (%p)", __func__, 2036 consumer, consumer - txq->txq_first, txbd_flags, 2037 m, &txq->txq_lmbufs[consumer-txq->txq_first], 2038 txq->txq_lmbufs[consumer-txq->txq_first])); 2039 #endif 2040 KASSERT(m); 2041 pq3etsec_txq_map_unload(sc, txq, m); 2042 #if 0 2043 printf("%s: mbuf %p: consumed a %u byte packet\n", 2044 __func__, m, m->m_pkthdr.len); 2045 #endif 2046 if (m->m_flags & M_HASFCB) 2047 m_adj(m, sizeof(struct txfcb)); 2048 ifp->if_opackets++; 2049 ifp->if_obytes += m->m_pkthdr.len; 2050 if (m->m_flags & M_MCAST) 2051 ifp->if_omcasts++; 2052 if (txbd_flags & TXBD_ERRORS) 2053 ifp->if_oerrors++; 2054 m_freem(m); 2055 #ifdef ETSEC_DEBUG 2056 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2057 #endif 2058 } else { 2059 #ifdef ETSEC_DEBUG 2060 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2061 #endif 2062 } 2063 2064 /* 2065 * We own this packet again. Clear all flags except wrap. 2066 */ 2067 txfree++; 2068 //consumer->txbd_flags = txbd_flags & TXBD_W; 2069 2070 /* 2071 * Wrap at the last entry! 2072 */ 2073 if (txbd_flags & TXBD_W) { 2074 KASSERT(consumer + 1 == txq->txq_last); 2075 consumer = txq->txq_first; 2076 } else { 2077 consumer++; 2078 KASSERT(consumer < txq->txq_last); 2079 } 2080 } 2081 } 2082 2083 static void 2084 pq3etsec_txq_purge( 2085 struct pq3etsec_softc *sc, 2086 struct pq3etsec_txqueue *txq) 2087 { 2088 struct mbuf *m; 2089 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2090 2091 for (;;) { 2092 IF_DEQUEUE(&txq->txq_mbufs, m); 2093 if (m == NULL) 2094 break; 2095 pq3etsec_txq_map_unload(sc, txq, m); 2096 m_freem(m); 2097 } 2098 if ((m = txq->txq_next) != NULL) { 2099 txq->txq_next = NULL; 2100 pq3etsec_txq_map_unload(sc, txq, m); 2101 m_freem(m); 2102 } 2103 #ifdef ETSEC_DEBUG 2104 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2105 #endif 2106 } 2107 2108 static void 2109 pq3etsec_txq_reset( 2110 struct pq3etsec_softc *sc, 2111 struct pq3etsec_txqueue *txq) 2112 { 2113 /* 2114 * sync all the descriptors 2115 */ 2116 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2117 txq->txq_last - txq->txq_first); 2118 2119 /* 2120 * Make sure we own all descriptors in the ring. 2121 */ 2122 volatile struct txbd *txbd; 2123 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2124 txbd->txbd_flags = 0; 2125 } 2126 2127 /* 2128 * Last descriptor has the wrap flag. 2129 */ 2130 txbd->txbd_flags = TXBD_W; 2131 2132 /* 2133 * Reset the producer consumer indexes. 2134 */ 2135 txq->txq_consumer = txq->txq_first; 2136 txq->txq_producer = txq->txq_first; 2137 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2138 txq->txq_threshold = txq->txq_free / 2; 2139 txq->txq_lastintr = 0; 2140 2141 /* 2142 * What do we want to get interrupted on? 2143 */ 2144 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE; 2145 2146 /* 2147 * Restart the transmit at the first descriptor 2148 */ 2149 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2150 } 2151 2152 static void 2153 pq3etsec_ifstart(struct ifnet *ifp) 2154 { 2155 struct pq3etsec_softc * const sc = ifp->if_softc; 2156 2157 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2158 softint_schedule(sc->sc_soft_ih); 2159 } 2160 2161 static void 2162 pq3etsec_tx_error( 2163 struct pq3etsec_softc * const sc) 2164 { 2165 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2166 2167 pq3etsec_txq_consume(sc, txq); 2168 2169 if (pq3etsec_txq_fillable_p(sc, txq)) 2170 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2171 if (sc->sc_txerrors & (IEVENT_LC|IEVENT_CRL|IEVENT_XFUN|IEVENT_BABT)) { 2172 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2173 } 2174 2175 if (pq3etsec_txq_active_p(sc, txq)) 2176 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2177 if (!pq3etsec_txq_enqueue(sc, txq)) { 2178 sc->sc_ev_tx_stall.ev_count++; 2179 sc->sc_if.if_flags |= IFF_OACTIVE; 2180 } 2181 2182 sc->sc_txerrors = 0; 2183 } 2184 2185 int 2186 pq3etsec_tx_intr(void *arg) 2187 { 2188 struct pq3etsec_softc * const sc = arg; 2189 2190 sc->sc_ev_tx_intr.ev_count++; 2191 2192 uint32_t ievent = etsec_read(sc, IEVENT); 2193 ievent &= IEVENT_TXF|IEVENT_TXB; 2194 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2195 2196 #if 0 2197 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2198 __func__, ievent, etsec_read(sc, IMASK)); 2199 #endif 2200 2201 if (ievent == 0) 2202 return 0; 2203 2204 sc->sc_imask &= ~(IEVENT_TXF|IEVENT_TXB); 2205 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2206 etsec_write(sc, IMASK, sc->sc_imask); 2207 softint_schedule(sc->sc_soft_ih); 2208 return 1; 2209 } 2210 2211 int 2212 pq3etsec_rx_intr(void *arg) 2213 { 2214 struct pq3etsec_softc * const sc = arg; 2215 2216 sc->sc_ev_rx_intr.ev_count++; 2217 2218 uint32_t ievent = etsec_read(sc, IEVENT); 2219 ievent &= IEVENT_RXF|IEVENT_RXB; 2220 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2221 if (ievent == 0) 2222 return 0; 2223 2224 #if 0 2225 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2226 #endif 2227 2228 sc->sc_imask &= ~(IEVENT_RXF|IEVENT_RXB); 2229 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2230 etsec_write(sc, IMASK, sc->sc_imask); 2231 softint_schedule(sc->sc_soft_ih); 2232 return 1; 2233 } 2234 2235 int 2236 pq3etsec_error_intr(void *arg) 2237 { 2238 struct pq3etsec_softc * const sc = arg; 2239 2240 sc->sc_ev_error_intr.ev_count++; 2241 2242 for (int rv = 0, soft_flags = 0;; rv = 1) { 2243 uint32_t ievent = etsec_read(sc, IEVENT); 2244 ievent &= ~(IEVENT_RXF|IEVENT_RXB|IEVENT_TXF|IEVENT_TXB); 2245 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2246 if (ievent == 0) { 2247 if (soft_flags) { 2248 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2249 softint_schedule(sc->sc_soft_ih); 2250 } 2251 return rv; 2252 } 2253 #if 0 2254 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2255 __func__, ievent, etsec_read(sc, IMASK)); 2256 #endif 2257 2258 if (ievent & (IEVENT_GRSC|IEVENT_GTSC)) { 2259 sc->sc_imask &= ~(IEVENT_GRSC|IEVENT_GTSC); 2260 etsec_write(sc, IMASK, sc->sc_imask); 2261 wakeup(sc); 2262 } 2263 if (ievent & (IEVENT_MMRD|IEVENT_MMWR)) { 2264 sc->sc_imask &= ~(IEVENT_MMRD|IEVENT_MMWR); 2265 etsec_write(sc, IMASK, sc->sc_imask); 2266 wakeup(&sc->sc_mii); 2267 } 2268 if (ievent & IEVENT_BSY) { 2269 soft_flags |= SOFT_RXBSY; 2270 sc->sc_imask &= ~IEVENT_BSY; 2271 etsec_write(sc, IMASK, sc->sc_imask); 2272 } 2273 if (ievent & IEVENT_TXE) { 2274 soft_flags |= SOFT_TXERROR; 2275 sc->sc_imask &= ~IEVENT_TXE; 2276 sc->sc_txerrors |= ievent; 2277 } 2278 if (ievent & IEVENT_TXC) { 2279 sc->sc_ev_tx_pause.ev_count++; 2280 } 2281 if (ievent & IEVENT_RXC) { 2282 sc->sc_ev_rx_pause.ev_count++; 2283 } 2284 if (ievent & IEVENT_DPE) { 2285 soft_flags |= SOFT_RESET; 2286 sc->sc_imask &= ~IEVENT_DPE; 2287 etsec_write(sc, IMASK, sc->sc_imask); 2288 } 2289 } 2290 } 2291 2292 void 2293 pq3etsec_soft_intr(void *arg) 2294 { 2295 struct pq3etsec_softc * const sc = arg; 2296 struct ifnet * const ifp = &sc->sc_if; 2297 2298 mutex_enter(sc->sc_lock); 2299 2300 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2301 2302 sc->sc_ev_soft_intr.ev_count++; 2303 2304 if (soft_flags & SOFT_RESET) { 2305 int s = splnet(); 2306 pq3etsec_ifinit(ifp); 2307 splx(s); 2308 soft_flags = 0; 2309 } 2310 2311 if (soft_flags & SOFT_RXBSY) { 2312 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2313 size_t threshold = 5 * rxq->rxq_threshold / 4; 2314 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2315 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2316 } else { 2317 sc->sc_imask |= IEVENT_BSY; 2318 } 2319 aprint_normal_dev(sc->sc_dev, 2320 "increasing receive buffers from %zu to %zu\n", 2321 rxq->rxq_threshold, threshold); 2322 rxq->rxq_threshold = threshold; 2323 } 2324 2325 if ((soft_flags & SOFT_TXINTR) 2326 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2327 /* 2328 * Let's do what we came here for. Consume transmitted 2329 * packets off the the transmit ring. 2330 */ 2331 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2332 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2333 sc->sc_ev_tx_stall.ev_count++; 2334 ifp->if_flags |= IFF_OACTIVE; 2335 } else { 2336 ifp->if_flags &= ~IFF_OACTIVE; 2337 } 2338 sc->sc_imask |= IEVENT_TXF; 2339 } 2340 2341 if (soft_flags & (SOFT_RXINTR|SOFT_RXBSY)) { 2342 /* 2343 * Let's consume 2344 */ 2345 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2346 sc->sc_imask |= IEVENT_RXF; 2347 } 2348 2349 if (soft_flags & SOFT_TXERROR) { 2350 pq3etsec_tx_error(sc); 2351 sc->sc_imask |= IEVENT_TXE; 2352 } 2353 2354 if (ifp->if_flags & IFF_RUNNING) { 2355 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2356 etsec_write(sc, IMASK, sc->sc_imask); 2357 } else { 2358 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2359 } 2360 2361 mutex_exit(sc->sc_lock); 2362 } 2363 2364 static void 2365 pq3etsec_mii_tick(void *arg) 2366 { 2367 struct pq3etsec_softc * const sc = arg; 2368 mutex_enter(sc->sc_lock); 2369 callout_ack(&sc->sc_mii_callout); 2370 sc->sc_ev_mii_ticks.ev_count++; 2371 #ifdef DEBUG 2372 uint64_t now = mftb(); 2373 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2374 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2375 __func__, now - sc->sc_mii_last_tick); 2376 callout_stop(&sc->sc_mii_callout); 2377 } 2378 #endif 2379 mii_tick(&sc->sc_mii); 2380 int s = splnet(); 2381 if (sc->sc_soft_flags & SOFT_RESET) 2382 softint_schedule(sc->sc_soft_ih); 2383 splx(s); 2384 callout_schedule(&sc->sc_mii_callout, hz); 2385 sc->sc_mii_last_tick = now; 2386 mutex_exit(sc->sc_lock); 2387 } 2388
Indexes created Thu Oct 02 14:10:14 GMT 2025