pq3etsec.c revision 1.15
1 /* $NetBSD: pq3etsec.c,v 1.15 2012/07/17 01:36:13 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_inet.h" 38 #include "opt_mpc85xx.h" 39 40 #include <sys/cdefs.h> 41 42 __KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.15 2012/07/17 01:36:13 matt Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/cpu.h> 46 #include <sys/device.h> 47 #include <sys/mbuf.h> 48 #include <sys/ioctl.h> 49 #include <sys/intr.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/kmem.h> 53 #include <sys/proc.h> 54 #include <sys/atomic.h> 55 #include <sys/callout.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_ether.h> 60 #include <net/if_media.h> 61 62 #include <dev/mii/miivar.h> 63 64 #include "ioconf.h" 65 66 #include <net/bpf.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/ip.h> 72 #include <netinet/in_offload.h> 73 #endif /* INET */ 74 #ifdef INET6 75 #include <netinet6/in6.h> 76 #include <netinet/ip6.h> 77 #endif 78 #include <netinet6/in6_offload.h> 79 80 81 #include <powerpc/spr.h> 82 #include <powerpc/booke/spr.h> 83 84 #include <powerpc/booke/cpuvar.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/e500reg.h> 87 #include <powerpc/booke/etsecreg.h> 88 89 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 90 91 #define ETSEC_MAXTXMBUFS 30 92 #define ETSEC_NTXSEGS 30 93 #define ETSEC_MAXRXMBUFS 511 94 #define ETSEC_MINRXMBUFS 32 95 #define ETSEC_NRXSEGS 1 96 97 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 98 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx\ 99 |IFCAP_CSUM_UDPv4_Rx\ 100 |IFCAP_CSUM_TCPv6_Rx\ 101 |IFCAP_CSUM_UDPv6_Rx) 102 103 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 104 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx\ 105 |IFCAP_CSUM_UDPv4_Tx\ 106 |IFCAP_CSUM_TCPv6_Tx\ 107 |IFCAP_CSUM_UDPv6_Tx) 108 109 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN|IFCAP_RCTRL_TUCSEN\ 110 |IFCAP_TCTRL_IPCSEN|IFCAP_TCTRL_TUCSEN) 111 112 #define M_CSUM_IP (M_CSUM_CIP|M_CSUM_CTU) 113 #define M_CSUM_IP6 (M_CSUM_TCPv6|M_CSUM_UDPv6) 114 #define M_CSUM_TUP (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 115 #define M_CSUM_UDP (M_CSUM_UDPv4|M_CSUM_UDPv6) 116 #define M_CSUM_IP4 (M_CSUM_IPv4|M_CSUM_UDPv4|M_CSUM_TCPv4) 117 #define M_CSUM_CIP (M_CSUM_IPv4) 118 #define M_CSUM_CTU (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 119 120 struct pq3etsec_txqueue { 121 bus_dmamap_t txq_descmap; 122 volatile struct txbd *txq_consumer; 123 volatile struct txbd *txq_producer; 124 volatile struct txbd *txq_first; 125 volatile struct txbd *txq_last; 126 struct ifqueue txq_mbufs; 127 struct mbuf *txq_next; 128 #ifdef ETSEC_DEBUG 129 struct mbuf *txq_lmbufs[512]; 130 #endif 131 uint32_t txq_qmask; 132 uint32_t txq_free; 133 uint32_t txq_threshold; 134 uint32_t txq_lastintr; 135 bus_size_t txq_reg_tbase; 136 bus_dma_segment_t txq_descmap_seg; 137 }; 138 139 struct pq3etsec_rxqueue { 140 bus_dmamap_t rxq_descmap; 141 volatile struct rxbd *rxq_consumer; 142 volatile struct rxbd *rxq_producer; 143 volatile struct rxbd *rxq_first; 144 volatile struct rxbd *rxq_last; 145 struct mbuf *rxq_mhead; 146 struct mbuf **rxq_mtail; 147 struct mbuf *rxq_mconsumer; 148 #ifdef ETSEC_DEBUG 149 struct mbuf *rxq_mbufs[512]; 150 #endif 151 uint32_t rxq_qmask; 152 uint32_t rxq_inuse; 153 uint32_t rxq_threshold; 154 bus_size_t rxq_reg_rbase; 155 bus_size_t rxq_reg_rbptr; 156 bus_dma_segment_t rxq_descmap_seg; 157 }; 158 159 struct pq3etsec_mapcache { 160 u_int dmc_nmaps; 161 u_int dmc_maxseg; 162 u_int dmc_maxmaps; 163 u_int dmc_maxmapsize; 164 bus_dmamap_t dmc_maps[0]; 165 }; 166 167 struct pq3etsec_softc { 168 device_t sc_dev; 169 struct ethercom sc_ec; 170 #define sc_if sc_ec.ec_if 171 struct mii_data sc_mii; 172 bus_space_tag_t sc_bst; 173 bus_space_handle_t sc_bsh; 174 bus_space_handle_t sc_mdio_bsh; 175 bus_dma_tag_t sc_dmat; 176 int sc_phy_addr; 177 prop_dictionary_t sc_intrmap; 178 uint32_t sc_intrmask; 179 180 uint32_t sc_soft_flags; 181 #define SOFT_RESET 0x0001 182 #define SOFT_RXINTR 0x0010 183 #define SOFT_RXBSY 0x0020 184 #define SOFT_TXINTR 0x0100 185 #define SOFT_TXERROR 0x0200 186 187 struct pq3etsec_txqueue sc_txq; 188 struct pq3etsec_rxqueue sc_rxq; 189 uint32_t sc_txerrors; 190 uint32_t sc_rxerrors; 191 192 size_t sc_rx_adjlen; 193 194 /* 195 * Copies of various ETSEC registers. 196 */ 197 uint32_t sc_imask; 198 uint32_t sc_maccfg1; 199 uint32_t sc_maccfg2; 200 uint32_t sc_maxfrm; 201 uint32_t sc_ecntrl; 202 uint32_t sc_dmactrl; 203 uint32_t sc_macstnaddr1; 204 uint32_t sc_macstnaddr2; 205 uint32_t sc_tctrl; 206 uint32_t sc_rctrl; 207 uint32_t sc_gaddr[16]; 208 uint64_t sc_macaddrs[15]; 209 210 void *sc_tx_ih; 211 void *sc_rx_ih; 212 void *sc_error_ih; 213 void *sc_soft_ih; 214 215 kmutex_t *sc_lock; 216 217 struct evcnt sc_ev_tx_stall; 218 struct evcnt sc_ev_tx_intr; 219 struct evcnt sc_ev_rx_stall; 220 struct evcnt sc_ev_rx_intr; 221 struct evcnt sc_ev_error_intr; 222 struct evcnt sc_ev_soft_intr; 223 struct evcnt sc_ev_tx_pause; 224 struct evcnt sc_ev_rx_pause; 225 struct evcnt sc_ev_mii_ticks; 226 227 struct callout sc_mii_callout; 228 uint64_t sc_mii_last_tick; 229 230 struct ifqueue sc_rx_bufcache; 231 struct pq3etsec_mapcache *sc_rx_mapcache; 232 struct pq3etsec_mapcache *sc_tx_mapcache; 233 }; 234 235 static int pq3etsec_match(device_t, cfdata_t, void *); 236 static void pq3etsec_attach(device_t, device_t, void *); 237 238 static void pq3etsec_ifstart(struct ifnet *); 239 static void pq3etsec_ifwatchdog(struct ifnet *); 240 static int pq3etsec_ifinit(struct ifnet *); 241 static void pq3etsec_ifstop(struct ifnet *, int); 242 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 243 244 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 245 struct pq3etsec_mapcache **, size_t, size_t, size_t); 246 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 247 struct pq3etsec_mapcache *); 248 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 249 struct pq3etsec_mapcache *); 250 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 251 struct pq3etsec_mapcache *, bus_dmamap_t); 252 253 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 254 struct pq3etsec_txqueue *, u_int); 255 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 256 struct pq3etsec_txqueue *); 257 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 258 struct pq3etsec_txqueue *); 259 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 260 struct pq3etsec_txqueue *); 261 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 262 struct pq3etsec_txqueue *, struct mbuf *m); 263 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 264 struct pq3etsec_txqueue *); 265 266 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 267 struct pq3etsec_rxqueue *, u_int); 268 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 269 struct pq3etsec_rxqueue *); 270 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 271 struct pq3etsec_rxqueue *, bool); 272 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 273 struct pq3etsec_rxqueue *); 274 275 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 276 277 static void pq3etsec_mii_tick(void *); 278 static int pq3etsec_rx_intr(void *); 279 static int pq3etsec_tx_intr(void *); 280 static int pq3etsec_error_intr(void *); 281 static void pq3etsec_soft_intr(void *); 282 283 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 284 pq3etsec_match, pq3etsec_attach, NULL, NULL); 285 286 static int 287 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 288 { 289 290 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 291 return 0; 292 293 return 1; 294 } 295 296 static inline uint32_t 297 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 298 { 299 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 300 } 301 302 static inline void 303 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 304 { 305 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 306 } 307 308 static inline uint32_t 309 etsec_mdio_read(struct pq3etsec_softc *sc, bus_size_t off) 310 { 311 return bus_space_read_4(sc->sc_bst, sc->sc_mdio_bsh, off); 312 } 313 314 static inline void 315 etsec_mdio_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 316 { 317 bus_space_write_4(sc->sc_bst, sc->sc_mdio_bsh, off, data); 318 } 319 320 static int 321 pq3etsec_mii_readreg(device_t self, int phy, int reg) 322 { 323 struct pq3etsec_softc * const sc = device_private(self); 324 uint32_t miimcom = etsec_read(sc, MIIMCOM); 325 326 // int s = splnet(); 327 328 etsec_mdio_write(sc, MIIMADD, 329 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 330 331 etsec_write(sc, IEVENT, IEVENT_MMRD); 332 etsec_mdio_write(sc, MIIMCOM, 0); /* clear any past bits */ 333 etsec_mdio_write(sc, MIIMCOM, MIIMCOM_READ); 334 #if 0 335 sc->sc_imask |= IEVENT_MMRD; 336 etsec_write(sc, IMASK, sc->sc_imask); 337 #endif 338 339 while (etsec_mdio_read(sc, MIIMIND) != 0) { 340 delay(1); 341 } 342 int data = etsec_mdio_read(sc, MIIMSTAT); 343 344 if (miimcom == MIIMCOM_SCAN) 345 etsec_mdio_write(sc, MIIMCOM, miimcom); 346 347 #if 0 348 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 349 __func__, phy, reg, data); 350 #endif 351 etsec_write(sc, IEVENT, IEVENT_MMRD); 352 // splx(s); 353 return data; 354 } 355 356 static void 357 pq3etsec_mii_writereg(device_t self, int phy, int reg, int data) 358 { 359 struct pq3etsec_softc * const sc = device_private(self); 360 uint32_t miimcom = etsec_mdio_read(sc, MIIMCOM); 361 362 #if 0 363 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 364 __func__, phy, reg, data); 365 #endif 366 367 // int s = splnet(); 368 etsec_write(sc, IEVENT, IEVENT_MMWR); 369 etsec_mdio_write(sc, MIIMADD, 370 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 371 etsec_mdio_write(sc, MIIMCOM, 0); /* clear any past bits */ 372 etsec_mdio_write(sc, MIIMCON, data); 373 374 #if 0 375 sc->sc_imask |= IEVENT_MMWR; 376 etsec_write(sc, IMASK, sc->sc_imask); 377 #endif 378 379 int timo = 1000; /* 1ms */ 380 while ((etsec_mdio_read(sc, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 381 delay(1); 382 } 383 384 if (miimcom == MIIMCOM_SCAN) 385 etsec_mdio_write(sc, MIIMCOM, miimcom); 386 etsec_write(sc, IEVENT, IEVENT_MMWR); 387 // splx(s); 388 } 389 390 static void 391 pq3etsec_mii_statchg(device_t self) 392 { 393 struct pq3etsec_softc * const sc = device_private(self); 394 struct mii_data * const mii = &sc->sc_mii; 395 396 uint32_t maccfg1 = sc->sc_maccfg1; 397 uint32_t maccfg2 = sc->sc_maccfg2; 398 uint32_t ecntrl = sc->sc_ecntrl; 399 400 maccfg1 &= ~(MACCFG1_TX_FLOW|MACCFG1_RX_FLOW); 401 maccfg2 &= ~(MACCFG2_IFMODE|MACCFG2_FD); 402 403 if (sc->sc_mii.mii_media_active & IFM_FDX) { 404 maccfg2 |= MACCFG2_FD; 405 } 406 407 /* 408 * Now deal with the flow control bits. 409 */ 410 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 411 && (mii->mii_media_active & IFM_ETH_FMASK)) { 412 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 413 maccfg1 |= MACCFG1_RX_FLOW; 414 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 415 maccfg1 |= MACCFG1_TX_FLOW; 416 } 417 418 /* 419 * Now deal with the speed. 420 */ 421 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 422 maccfg2 |= MACCFG2_IFMODE_GMII; 423 } else { 424 maccfg2 |= MACCFG2_IFMODE_MII; 425 ecntrl &= ~ECNTRL_R100M; 426 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 427 ecntrl |= ECNTRL_R100M; 428 } 429 } 430 431 /* 432 * If things are different, re-init things. 433 */ 434 if (maccfg1 != sc->sc_maccfg1 435 || maccfg2 != sc->sc_maccfg2 436 || ecntrl != sc->sc_ecntrl) { 437 if (sc->sc_if.if_flags & IFF_RUNNING) 438 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 439 sc->sc_maccfg1 = maccfg1; 440 sc->sc_maccfg2 = maccfg2; 441 sc->sc_ecntrl = ecntrl; 442 } 443 } 444 445 #if 0 446 static void 447 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 448 { 449 struct pq3etsec_softc * const sc = ifp->if_softc; 450 451 mii_pollstat(&sc->sc_mii); 452 ether_mediastatus(ifp, ifmr); 453 ifmr->ifm_status = sc->sc_mii.mii_media_status; 454 ifmr->ifm_active = sc->sc_mii.mii_media_active; 455 } 456 457 static int 458 pq3etsec_mediachange(struct ifnet *ifp) 459 { 460 struct pq3etsec_softc * const sc = ifp->if_softc; 461 462 if ((ifp->if_flags & IFF_UP) == 0) 463 return 0; 464 465 int rv = mii_mediachg(&sc->sc_mii); 466 return (rv == ENXIO) ? 0 : rv; 467 } 468 #endif 469 470 471 static const struct { 472 bus_addr_t reg_base; 473 bus_addr_t mdio_base; 474 } etsec_mdio_map[] = { 475 { ETSEC1_BASE, ETSEC1_BASE }, 476 { ETSEC2_BASE, ETSEC2_BASE }, 477 { ETSEC3_BASE, ETSEC3_BASE }, 478 { ETSEC4_BASE, ETSEC4_BASE }, 479 #if defined(P1025) 480 { ETSEC1_G0_BASE, ETSEC1_BASE }, 481 { ETSEC1_G1_BASE, ETSEC1_BASE }, 482 { ETSEC2_G0_BASE, ETSEC2_BASE }, 483 { ETSEC2_G1_BASE, ETSEC2_BASE }, 484 { ETSEC3_G0_BASE, ETSEC3_BASE }, 485 { ETSEC3_G1_BASE, ETSEC3_BASE }, 486 #endif 487 }; 488 489 static bool 490 pq3etsec_mdio_map(struct pq3etsec_softc *sc, bus_addr_t reg_base, 491 bus_addr_t *mdio_basep) 492 { 493 *mdio_basep = 0; 494 for (size_t i = 0; i < __arraycount(etsec_mdio_map); i++) { 495 if (etsec_mdio_map[i].reg_base == reg_base) { 496 bus_addr_t mdio_base = etsec_mdio_map[i].mdio_base; 497 if (mdio_base == reg_base) { 498 sc->sc_mdio_bsh = sc->sc_bsh; 499 return true; 500 } 501 if (!bus_space_map(sc->sc_bst, 502 mdio_base, 503 ETSEC_SIZE, 0, &sc->sc_mdio_bsh)) { 504 return true; 505 } 506 *mdio_basep = mdio_base; 507 break; 508 } 509 } 510 511 return false; 512 } 513 514 static void 515 pq3etsec_attach(device_t parent, device_t self, void *aux) 516 { 517 struct cpunode_softc * const psc = device_private(parent); 518 struct pq3etsec_softc * const sc = device_private(self); 519 struct cpunode_attach_args * const cna = aux; 520 struct cpunode_locators * const cnl = &cna->cna_locs; 521 cfdata_t cf = device_cfdata(self); 522 int error; 523 bus_addr_t mdio_base; 524 525 psc->sc_children |= cna->cna_childmask; 526 sc->sc_dev = self; 527 sc->sc_bst = cna->cna_memt; 528 sc->sc_dmat = &booke_bus_dma_tag; 529 530 /* 531 * If we have a common MDIO bus, if all off instance 1. 532 */ 533 device_t miiself = (cf->cf_flags & 0x100) ? tsec_cd.cd_devs[0] : self; 534 535 /* 536 * See if the phy is in the config file... 537 */ 538 if (cf->cf_flags & 0x3f) { 539 sc->sc_phy_addr = (cf->cf_flags & 0x3f) - 1; 540 } else { 541 unsigned char prop_name[20]; 542 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 543 cnl->cnl_instance); 544 sc->sc_phy_addr = board_info_get_number(prop_name); 545 } 546 if (sc->sc_phy_addr != MII_PHY_ANY) 547 aprint_normal(" phy %d", sc->sc_phy_addr); 548 549 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 550 &sc->sc_bsh); 551 if (error) { 552 aprint_error(": error mapping registers: %d\n", error); 553 return; 554 } 555 556 if (!pq3etsec_mdio_map(sc, cnl->cnl_addr, &mdio_base)) { 557 aprint_error(": error mapping mdio registers @ %#x\n", 558 mdio_base); 559 return; 560 } 561 562 /* 563 * Assume firmware has aready set the mac address and fetch it 564 * before we reinit it. 565 */ 566 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 567 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 568 sc->sc_rctrl = RCTRL_DEFAULT; 569 sc->sc_ecntrl = etsec_read(sc, ECNTRL); 570 sc->sc_maccfg1 = etsec_read(sc, MACCFG1); 571 sc->sc_maccfg2 = etsec_read(sc, MACCFG2) | MACCFG2_DEFAULT; 572 573 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 574 size_t len; 575 const uint8_t *mac_addr = 576 board_info_get_data("tsec-mac-addr-base", &len); 577 KASSERT(len == ETHER_ADDR_LEN); 578 sc->sc_macstnaddr2 = 579 (mac_addr[1] << 24) 580 | (mac_addr[0] << 16); 581 sc->sc_macstnaddr1 = 582 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 583 | (mac_addr[4] << 16) 584 | (mac_addr[3] << 8) 585 | (mac_addr[2] << 0); 586 #if 0 587 aprint_error(": mac-address unknown\n"); 588 return; 589 #endif 590 } 591 592 char enaddr[ETHER_ADDR_LEN] = { 593 [0] = sc->sc_macstnaddr2 >> 16, 594 [1] = sc->sc_macstnaddr2 >> 24, 595 [2] = sc->sc_macstnaddr1 >> 0, 596 [3] = sc->sc_macstnaddr1 >> 8, 597 [4] = sc->sc_macstnaddr1 >> 16, 598 [5] = sc->sc_macstnaddr1 >> 24, 599 }; 600 601 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 602 if (error) { 603 aprint_error(": failed to init rxq: %d\n", error); 604 return; 605 } 606 607 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 608 if (error) { 609 aprint_error(": failed to init txq: %d\n", error); 610 return; 611 } 612 613 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 614 ETSEC_MAXRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 615 if (error) { 616 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 617 return; 618 } 619 620 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 621 ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 622 if (error) { 623 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 624 return; 625 } 626 627 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 628 pq3etsec_tx_intr, sc); 629 if (sc->sc_tx_ih == NULL) { 630 aprint_error(": failed to establish tx interrupt: %d\n", 631 cnl->cnl_intrs[0]); 632 return; 633 } 634 635 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 636 pq3etsec_rx_intr, sc); 637 if (sc->sc_rx_ih == NULL) { 638 aprint_error(": failed to establish rx interrupt: %d\n", 639 cnl->cnl_intrs[1]); 640 return; 641 } 642 643 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 644 pq3etsec_error_intr, sc); 645 if (sc->sc_error_ih == NULL) { 646 aprint_error(": failed to establish error interrupt: %d\n", 647 cnl->cnl_intrs[2]); 648 return; 649 } 650 651 sc->sc_soft_ih = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 652 pq3etsec_soft_intr, sc); 653 if (sc->sc_soft_ih == NULL) { 654 aprint_error(": failed to establish soft interrupt\n"); 655 return; 656 } 657 658 aprint_normal("\n"); 659 660 etsec_write(sc, ATTR, ATTR_DEFAULT); 661 etsec_write(sc, ATTRELI, ATTRELI_DEFAULT); 662 663 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 664 665 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 666 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 667 668 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 669 ether_sprintf(enaddr)); 670 671 const char * const xname = device_xname(sc->sc_dev); 672 struct ethercom * const ec = &sc->sc_ec; 673 struct ifnet * const ifp = &ec->ec_if; 674 675 ec->ec_mii = &sc->sc_mii; 676 677 sc->sc_mii.mii_ifp = ifp; 678 sc->sc_mii.mii_readreg = pq3etsec_mii_readreg; 679 sc->sc_mii.mii_writereg = pq3etsec_mii_writereg; 680 sc->sc_mii.mii_statchg = pq3etsec_mii_statchg; 681 682 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 683 ether_mediastatus); 684 685 if (sc->sc_phy_addr < 32) { 686 mii_attach(miiself, &sc->sc_mii, 0xffffffff, 687 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 688 689 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 690 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 691 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 692 } else { 693 callout_schedule(&sc->sc_mii_callout, hz); 694 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 695 } 696 } else { 697 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 698 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX); 699 } 700 701 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 702 | ETHERCAP_JUMBO_MTU; 703 704 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 705 ifp->if_softc = sc; 706 ifp->if_capabilities = IFCAP_ETSEC; 707 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 708 ifp->if_ioctl = pq3etsec_ifioctl; 709 ifp->if_start = pq3etsec_ifstart; 710 ifp->if_watchdog = pq3etsec_ifwatchdog; 711 ifp->if_init = pq3etsec_ifinit; 712 ifp->if_stop = pq3etsec_ifstop; 713 IFQ_SET_READY(&ifp->if_snd); 714 715 pq3etsec_ifstop(ifp, true); 716 717 /* 718 * Attach the interface. 719 */ 720 if_attach(ifp); 721 ether_ifattach(ifp, enaddr); 722 723 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 724 NULL, xname, "rx stall"); 725 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 726 NULL, xname, "tx stall"); 727 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 728 NULL, xname, "tx intr"); 729 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 730 NULL, xname, "rx intr"); 731 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 732 NULL, xname, "error intr"); 733 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 734 NULL, xname, "soft intr"); 735 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 736 NULL, xname, "tx pause"); 737 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 738 NULL, xname, "rx pause"); 739 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 740 NULL, xname, "mii ticks"); 741 } 742 743 static uint64_t 744 pq3etsec_macaddr_create(const uint8_t *lladdr) 745 { 746 uint64_t macaddr = 0; 747 748 lladdr += ETHER_ADDR_LEN; 749 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 750 macaddr = (macaddr << 8) | *--lladdr; 751 } 752 return macaddr << 16; 753 } 754 755 static int 756 pq3etsec_ifinit(struct ifnet *ifp) 757 { 758 struct pq3etsec_softc * const sc = ifp->if_softc; 759 int error = 0; 760 761 sc->sc_maxfrm = max(ifp->if_mtu + 32, MCLBYTES); 762 if (ifp->if_mtu > ETHERMTU_JUMBO) 763 return error; 764 765 KASSERT(ifp->if_flags & IFF_UP); 766 767 /* 768 * Stop the interface (steps 1 to 4 in the Soft Reset and 769 * Reconfigurating Procedure. 770 */ 771 pq3etsec_ifstop(ifp, 0); 772 773 /* 774 * If our frame size has changed (or it's our first time through) 775 * destroy the existing transmit mapcache. 776 */ 777 if (sc->sc_tx_mapcache != NULL 778 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 779 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 780 sc->sc_tx_mapcache = NULL; 781 } 782 783 if (sc->sc_tx_mapcache == NULL) { 784 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 785 ETSEC_MAXTXMBUFS, sc->sc_maxfrm, ETSEC_NTXSEGS); 786 if (error) 787 return error; 788 } 789 790 sc->sc_ev_mii_ticks.ev_count++; 791 mii_tick(&sc->sc_mii); 792 793 if (ifp->if_flags & IFF_PROMISC) { 794 sc->sc_rctrl |= RCTRL_PROM; 795 } else { 796 sc->sc_rctrl &= ~RCTRL_PROM; 797 } 798 799 uint32_t rctrl_prsdep = 0; 800 sc->sc_rctrl &= ~(RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP); 801 if (VLAN_ATTACHED(&sc->sc_ec)) { 802 sc->sc_rctrl |= RCTRL_VLEX; 803 rctrl_prsdep = RCTRL_PRSDEP_L2; 804 } 805 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 806 sc->sc_rctrl |= RCTRL_IPCSEN; 807 rctrl_prsdep = RCTRL_PRSDEP_L3; 808 } 809 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 810 sc->sc_rctrl |= RCTRL_TUCSEN; 811 rctrl_prsdep = RCTRL_PRSDEP_L4; 812 } 813 sc->sc_rctrl |= rctrl_prsdep; 814 #if 0 815 if (sc->sc_rctrl & (RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP)) 816 aprint_normal_dev(sc->sc_dev, 817 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 818 sc->sc_rctrl, 819 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 820 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 821 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 822 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 823 #endif 824 825 sc->sc_tctrl &= ~(TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS); 826 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 827 sc->sc_tctrl |= TCTRL_VLINS; 828 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 829 sc->sc_tctrl |= TCTRL_IPCSEN; 830 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 831 sc->sc_tctrl |= TCTRL_TUCSEN; 832 #if 0 833 if (sc->sc_tctrl & (TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS)) 834 aprint_normal_dev(sc->sc_dev, 835 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 836 sc->sc_tctrl, 837 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 838 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 839 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 840 #endif 841 842 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN|MACCFG1_RX_EN); 843 844 const uint64_t macstnaddr = 845 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 846 847 sc->sc_imask = IEVENT_DPE; 848 849 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 850 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 851 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 852 853 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 854 pq3etsec_txq_reset(sc, &sc->sc_txq); 855 856 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 857 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 858 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 859 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 860 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 861 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 862 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 863 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 864 865 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 866 pq3etsec_mc_setup(sc); 867 868 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 869 etsec_write(sc, MRBLR, MCLBYTES); 870 871 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 872 sc->sc_dmactrl |= DMACTRL_DEFAULT; 873 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 874 875 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 876 etsec_write(sc, TQUEUE, TQUEUE_EN0); 877 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE|IEVENT_TXC; 878 879 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 880 881 /* 12. Enable receive queues in RQUEUE, */ 882 etsec_write(sc, RQUEUE, RQUEUE_EN0|RQUEUE_EX0); 883 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY|IEVENT_RXC; 884 885 /* and optionally set TOE functionality in RCTRL. */ 886 etsec_write(sc, RCTRL, sc->sc_rctrl); 887 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 888 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 889 sc->sc_rx_adjlen += sizeof(struct rxfcb); 890 891 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 892 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 893 894 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 895 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 896 897 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 898 sc->sc_dmactrl &= ~(DMACTRL_GRS|DMACTRL_GTS); 899 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 900 901 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 902 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 903 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 904 905 sc->sc_soft_flags = 0; 906 907 etsec_write(sc, IMASK, sc->sc_imask); 908 909 ifp->if_flags |= IFF_RUNNING; 910 911 return error; 912 } 913 914 static void 915 pq3etsec_ifstop(struct ifnet *ifp, int disable) 916 { 917 struct pq3etsec_softc * const sc = ifp->if_softc; 918 919 KASSERT(!cpu_intr_p()); 920 const uint32_t imask_gsc_mask = IEVENT_GTSC|IEVENT_GRSC; 921 /* 922 * Clear the GTSC and GRSC from the interrupt mask until 923 * we are ready for them. Then clear them from IEVENT, 924 * request the graceful shutdown, and then enable the 925 * GTSC and GRSC bits in the mask. This should cause the 926 * error interrupt to fire which will issue a wakeup to 927 * allow us to resume. 928 */ 929 930 /* 931 * 1. Set GRS/GTS bits in DMACTRL register 932 */ 933 sc->sc_dmactrl |= DMACTRL_GRS|DMACTRL_GTS; 934 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 935 etsec_write(sc, IEVENT, imask_gsc_mask); 936 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 937 938 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN|MACCFG1_RX_EN)) { 939 /* 940 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 941 */ 942 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 943 944 u_int timo = 1000; 945 uint32_t ievent = etsec_read(sc, IEVENT); 946 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 947 if (--timo == 0) { 948 aprint_error_dev(sc->sc_dev, 949 "WARNING: " 950 "request to stop failed (IEVENT=%#x)\n", 951 ievent); 952 break; 953 } 954 delay(10); 955 ievent = etsec_read(sc, IEVENT); 956 } 957 } 958 959 /* 960 * Now reset the controller. 961 * 962 * 3. Set SOFT_RESET bit in MACCFG1 register 963 * 4. Clear SOFT_RESET bit in MACCFG1 register 964 */ 965 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 966 etsec_write(sc, MACCFG1, 0); 967 etsec_write(sc, IMASK, 0); 968 etsec_write(sc, IEVENT, ~0); 969 sc->sc_imask = 0; 970 ifp->if_flags &= ~IFF_RUNNING; 971 972 uint32_t tbipa = etsec_read(sc, TBIPA); 973 if (tbipa == sc->sc_phy_addr) { 974 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 975 etsec_write(sc, TBIPA, 0x1f); 976 } 977 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 978 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 979 etsec_write(sc, MIIMCFG, miimcfg); 980 981 /* 982 * Let's consume any remaing transmitted packets. And if we are 983 * disabling the interface, purge ourselves of any untransmitted 984 * packets. But don't consume any received packets, just drop them. 985 * If we aren't disabling the interface, save the mbufs in the 986 * receive queue for reuse. 987 */ 988 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 989 pq3etsec_txq_consume(sc, &sc->sc_txq); 990 if (disable) { 991 pq3etsec_txq_purge(sc, &sc->sc_txq); 992 IF_PURGE(&ifp->if_snd); 993 } 994 } 995 996 static void 997 pq3etsec_ifwatchdog(struct ifnet *ifp) 998 { 999 } 1000 1001 static void 1002 pq3etsec_mc_setup( 1003 struct pq3etsec_softc *sc) 1004 { 1005 struct ethercom * const ec = &sc->sc_ec; 1006 struct ifnet * const ifp = &sc->sc_if; 1007 struct ether_multi *enm; 1008 struct ether_multistep step; 1009 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 1010 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 1011 1012 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 1013 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1014 1015 ifp->if_flags &= ~IFF_ALLMULTI; 1016 1017 ETHER_FIRST_MULTI(step, ec, enm); 1018 for (u_int i = 0; enm != NULL; ) { 1019 const char *addr = enm->enm_addrlo; 1020 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1021 ifp->if_flags |= IFF_ALLMULTI; 1022 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 1023 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1024 break; 1025 } 1026 if ((sc->sc_rctrl & RCTRL_EMEN) 1027 && i < __arraycount(sc->sc_macaddrs)) { 1028 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 1029 } else { 1030 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1031 #if 0 1032 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 1033 ether_sprintf(addr), crc, 1034 crc >> crc_shift, 1035 crc >> (crc_shift + 5), 1036 (crc >> crc_shift) & 31, 1037 1 << (((crc >> crc_shift) & 31) ^ 31)); 1038 #endif 1039 /* 1040 * The documentation doesn't completely follow PowerPC 1041 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 1042 * is 0x7fa32d9b. By empirical testing, the 1043 * corresponding hash bit is word 3, bit 31 (ppc bit 1044 * order). Since 3 << 31 | 31 is 0x7f, we deduce 1045 * H[0:2] selects the register while H[3:7] selects 1046 * the bit (ppc bit order). 1047 */ 1048 crc >>= crc_shift; 1049 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 1050 } 1051 ETHER_NEXT_MULTI(step, enm); 1052 } 1053 for (u_int i = 0; i < 8; i++) { 1054 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 1055 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 1056 #if 0 1057 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 1058 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 1059 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 1060 i, GADDR(i), etsec_read(sc, GADDR(i))); 1061 #endif 1062 } 1063 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 1064 uint64_t macaddr = sc->sc_macaddrs[i]; 1065 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 1066 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 1067 #if 0 1068 if (macaddr) 1069 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 1070 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1071 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1072 #endif 1073 } 1074 } 1075 1076 static int 1077 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1078 { 1079 struct pq3etsec_softc *sc = ifp->if_softc; 1080 struct ifreq * const ifr = data; 1081 const int s = splnet(); 1082 int error; 1083 1084 switch (cmd) { 1085 case SIOCSIFMEDIA: 1086 case SIOCGIFMEDIA: 1087 /* Flow control requires full-duplex mode. */ 1088 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1089 (ifr->ifr_media & IFM_FDX) == 0) 1090 ifr->ifr_media &= ~IFM_ETH_FMASK; 1091 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1092 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1093 /* We can do both TXPAUSE and RXPAUSE. */ 1094 ifr->ifr_media |= 1095 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1096 } 1097 } 1098 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1099 break; 1100 1101 default: 1102 error = ether_ioctl(ifp, cmd, data); 1103 if (error != ENETRESET) 1104 break; 1105 1106 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1107 error = 0; 1108 if (ifp->if_flags & IFF_RUNNING) 1109 pq3etsec_mc_setup(sc); 1110 break; 1111 } 1112 error = pq3etsec_ifinit(ifp); 1113 break; 1114 } 1115 1116 splx(s); 1117 return error; 1118 } 1119 1120 static void 1121 pq3etsec_rxq_desc_presync( 1122 struct pq3etsec_softc *sc, 1123 struct pq3etsec_rxqueue *rxq, 1124 volatile struct rxbd *rxbd, 1125 size_t count) 1126 { 1127 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1128 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1129 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1130 } 1131 1132 static void 1133 pq3etsec_rxq_desc_postsync( 1134 struct pq3etsec_softc *sc, 1135 struct pq3etsec_rxqueue *rxq, 1136 volatile struct rxbd *rxbd, 1137 size_t count) 1138 { 1139 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1140 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1141 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1142 } 1143 1144 static void 1145 pq3etsec_txq_desc_presync( 1146 struct pq3etsec_softc *sc, 1147 struct pq3etsec_txqueue *txq, 1148 volatile struct txbd *txbd, 1149 size_t count) 1150 { 1151 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1152 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1153 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1154 } 1155 1156 static void 1157 pq3etsec_txq_desc_postsync( 1158 struct pq3etsec_softc *sc, 1159 struct pq3etsec_txqueue *txq, 1160 volatile struct txbd *txbd, 1161 size_t count) 1162 { 1163 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1164 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1165 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1166 } 1167 1168 static bus_dmamap_t 1169 pq3etsec_mapcache_get( 1170 struct pq3etsec_softc *sc, 1171 struct pq3etsec_mapcache *dmc) 1172 { 1173 KASSERT(dmc->dmc_nmaps > 0); 1174 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1175 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1176 } 1177 1178 static void 1179 pq3etsec_mapcache_put( 1180 struct pq3etsec_softc *sc, 1181 struct pq3etsec_mapcache *dmc, 1182 bus_dmamap_t map) 1183 { 1184 KASSERT(map != NULL); 1185 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1186 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1187 } 1188 1189 static void 1190 pq3etsec_mapcache_destroy( 1191 struct pq3etsec_softc *sc, 1192 struct pq3etsec_mapcache *dmc) 1193 { 1194 const size_t dmc_size = 1195 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1196 1197 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1198 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1199 } 1200 kmem_intr_free(dmc, dmc_size); 1201 } 1202 1203 static int 1204 pq3etsec_mapcache_create( 1205 struct pq3etsec_softc *sc, 1206 struct pq3etsec_mapcache **dmc_p, 1207 size_t maxmaps, 1208 size_t maxmapsize, 1209 size_t maxseg) 1210 { 1211 const size_t dmc_size = 1212 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1213 struct pq3etsec_mapcache * const dmc = 1214 kmem_intr_zalloc(dmc_size, KM_NOSLEEP); 1215 1216 dmc->dmc_maxmaps = maxmaps; 1217 dmc->dmc_nmaps = maxmaps; 1218 dmc->dmc_maxmapsize = maxmapsize; 1219 dmc->dmc_maxseg = maxseg; 1220 1221 for (u_int i = 0; i < maxmaps; i++) { 1222 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1223 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1224 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1225 if (error) { 1226 aprint_error_dev(sc->sc_dev, 1227 "failed to creat dma map cache " 1228 "entry %u of %zu: %d\n", 1229 i, maxmaps, error); 1230 while (i-- > 0) { 1231 bus_dmamap_destroy(sc->sc_dmat, 1232 dmc->dmc_maps[i]); 1233 } 1234 kmem_intr_free(dmc, dmc_size); 1235 return error; 1236 } 1237 KASSERT(dmc->dmc_maps[i] != NULL); 1238 } 1239 1240 *dmc_p = dmc; 1241 1242 return 0; 1243 } 1244 1245 #if 0 1246 static void 1247 pq3etsec_dmamem_free( 1248 bus_dma_tag_t dmat, 1249 size_t map_size, 1250 bus_dma_segment_t *seg, 1251 bus_dmamap_t map, 1252 void *kvap) 1253 { 1254 bus_dmamap_destroy(dmat, map); 1255 bus_dmamem_unmap(dmat, kvap, map_size); 1256 bus_dmamem_free(dmat, seg, 1); 1257 } 1258 #endif 1259 1260 static int 1261 pq3etsec_dmamem_alloc( 1262 bus_dma_tag_t dmat, 1263 size_t map_size, 1264 bus_dma_segment_t *seg, 1265 bus_dmamap_t *map, 1266 void **kvap) 1267 { 1268 int error; 1269 int nseg; 1270 1271 *kvap = NULL; 1272 *map = NULL; 1273 1274 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1275 seg, 1, &nseg, 0); 1276 if (error) 1277 return error; 1278 1279 KASSERT(nseg == 1); 1280 1281 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1282 BUS_DMA_COHERENT); 1283 if (error == 0) { 1284 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1285 map); 1286 if (error == 0) { 1287 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1288 NULL, 0); 1289 if (error == 0) 1290 return 0; 1291 bus_dmamap_destroy(dmat, *map); 1292 *map = NULL; 1293 } 1294 bus_dmamem_unmap(dmat, *kvap, map_size); 1295 *kvap = NULL; 1296 } 1297 bus_dmamem_free(dmat, seg, nseg); 1298 return 0; 1299 } 1300 1301 static struct mbuf * 1302 pq3etsec_rx_buf_alloc( 1303 struct pq3etsec_softc *sc) 1304 { 1305 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1306 if (m == NULL) { 1307 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1308 return NULL; 1309 } 1310 MCLGET(m, M_DONTWAIT); 1311 if ((m->m_flags & M_EXT) == 0) { 1312 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1313 m_freem(m); 1314 return NULL; 1315 } 1316 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1317 1318 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1319 if (map == NULL) { 1320 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1321 m_freem(m); 1322 return NULL; 1323 } 1324 M_SETCTX(m, map); 1325 m->m_len = m->m_pkthdr.len = MCLBYTES; 1326 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1327 BUS_DMA_READ|BUS_DMA_NOWAIT); 1328 if (error) { 1329 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1330 error); 1331 M_SETCTX(m, NULL); 1332 m_freem(m); 1333 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1334 return NULL; 1335 } 1336 KASSERT(map->dm_mapsize == MCLBYTES); 1337 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1338 BUS_DMASYNC_PREREAD); 1339 1340 return m; 1341 } 1342 1343 static void 1344 pq3etsec_rx_map_unload( 1345 struct pq3etsec_softc *sc, 1346 struct mbuf *m) 1347 { 1348 KASSERT(m); 1349 for (; m != NULL; m = m->m_next) { 1350 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1351 KASSERT(map); 1352 KASSERT(map->dm_mapsize == MCLBYTES); 1353 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1354 BUS_DMASYNC_POSTREAD); 1355 bus_dmamap_unload(sc->sc_dmat, map); 1356 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1357 M_SETCTX(m, NULL); 1358 } 1359 } 1360 1361 static bool 1362 pq3etsec_rxq_produce( 1363 struct pq3etsec_softc *sc, 1364 struct pq3etsec_rxqueue *rxq) 1365 { 1366 volatile struct rxbd *producer = rxq->rxq_producer; 1367 #if 0 1368 size_t inuse = rxq->rxq_inuse; 1369 #endif 1370 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1371 struct mbuf *m; 1372 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1373 if (m == NULL) { 1374 m = pq3etsec_rx_buf_alloc(sc); 1375 if (m == NULL) { 1376 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1377 break; 1378 } 1379 } 1380 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1381 KASSERT(map); 1382 1383 #ifdef ETSEC_DEBUG 1384 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1385 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1386 #endif 1387 1388 /* rxbd_len is write-only by the ETSEC */ 1389 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1390 membar_producer(); 1391 producer->rxbd_flags |= RXBD_E; 1392 if (__predict_false(rxq->rxq_mhead == NULL)) { 1393 KASSERT(producer == rxq->rxq_consumer); 1394 rxq->rxq_mconsumer = m; 1395 } 1396 *rxq->rxq_mtail = m; 1397 rxq->rxq_mtail = &m->m_next; 1398 m->m_len = MCLBYTES; 1399 m->m_next = NULL; 1400 rxq->rxq_inuse++; 1401 if (++producer == rxq->rxq_last) { 1402 membar_producer(); 1403 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1404 rxq->rxq_last - rxq->rxq_producer); 1405 producer = rxq->rxq_producer = rxq->rxq_first; 1406 } 1407 } 1408 if (producer != rxq->rxq_producer) { 1409 membar_producer(); 1410 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1411 producer - rxq->rxq_producer); 1412 rxq->rxq_producer = producer; 1413 } 1414 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1415 if (qhlt) { 1416 KASSERT(qhlt & rxq->rxq_qmask); 1417 sc->sc_ev_rx_stall.ev_count++; 1418 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1419 } 1420 #if 0 1421 aprint_normal_dev(sc->sc_dev, 1422 "%s: buffers inuse went from %zu to %zu\n", 1423 __func__, inuse, rxq->rxq_inuse); 1424 #endif 1425 return true; 1426 } 1427 1428 static bool 1429 pq3etsec_rx_offload( 1430 struct pq3etsec_softc *sc, 1431 struct mbuf *m, 1432 const struct rxfcb *fcb) 1433 { 1434 if (fcb->rxfcb_flags & RXFCB_VLN) { 1435 VLAN_INPUT_TAG(&sc->sc_if, m, fcb->rxfcb_vlctl, 1436 m_freem(m); return false); 1437 } 1438 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1439 || (fcb->rxfcb_flags & (RXFCB_CIP|RXFCB_CTU)) == 0) 1440 return true; 1441 int csum_flags = 0; 1442 if ((fcb->rxfcb_flags & (RXFCB_IP6|RXFCB_CIP)) == RXFCB_CIP) { 1443 csum_flags |= M_CSUM_IPv4; 1444 if (fcb->rxfcb_flags & RXFCB_EIP) 1445 csum_flags |= M_CSUM_IPv4_BAD; 1446 } 1447 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1448 int ipv_flags; 1449 if (fcb->rxfcb_flags & RXFCB_IP6) 1450 ipv_flags = M_CSUM_TCPv6|M_CSUM_UDPv6; 1451 else 1452 ipv_flags = M_CSUM_TCPv4|M_CSUM_UDPv4; 1453 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1454 csum_flags |= (M_CSUM_TCPv4|M_CSUM_TCPv6) & ipv_flags; 1455 } else { 1456 csum_flags |= (M_CSUM_UDPv4|M_CSUM_UDPv6) & ipv_flags; 1457 } 1458 if (fcb->rxfcb_flags & RXFCB_ETU) 1459 csum_flags |= M_CSUM_TCP_UDP_BAD; 1460 } 1461 1462 m->m_pkthdr.csum_flags = csum_flags; 1463 return true; 1464 } 1465 1466 static void 1467 pq3etsec_rx_input( 1468 struct pq3etsec_softc *sc, 1469 struct mbuf *m, 1470 uint16_t rxbd_flags) 1471 { 1472 struct ifnet * const ifp = &sc->sc_if; 1473 1474 pq3etsec_rx_map_unload(sc, m); 1475 1476 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1477 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1478 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1479 return; 1480 } 1481 m_adj(m, sc->sc_rx_adjlen); 1482 1483 if (rxbd_flags & RXBD_M) 1484 m->m_flags |= M_PROMISC; 1485 if (rxbd_flags & RXBD_BC) 1486 m->m_flags |= M_BCAST; 1487 if (rxbd_flags & RXBD_MC) 1488 m->m_flags |= M_MCAST; 1489 m->m_flags |= M_HASFCS; 1490 m->m_pkthdr.rcvif = &sc->sc_if; 1491 1492 ifp->if_ipackets++; 1493 ifp->if_ibytes += m->m_pkthdr.len; 1494 1495 /* 1496 * Let's give it to the network subsystm to deal with. 1497 */ 1498 int s = splnet(); 1499 bpf_mtap(ifp, m); 1500 (*ifp->if_input)(ifp, m); 1501 splx(s); 1502 } 1503 1504 static void 1505 pq3etsec_rxq_consume( 1506 struct pq3etsec_softc *sc, 1507 struct pq3etsec_rxqueue *rxq) 1508 { 1509 struct ifnet * const ifp = &sc->sc_if; 1510 volatile struct rxbd *consumer = rxq->rxq_consumer; 1511 size_t rxconsumed = 0; 1512 1513 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1514 1515 for (;;) { 1516 if (consumer == rxq->rxq_producer) { 1517 rxq->rxq_consumer = consumer; 1518 rxq->rxq_inuse -= rxconsumed; 1519 KASSERT(rxq->rxq_inuse == 0); 1520 return; 1521 } 1522 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1523 const uint16_t rxbd_flags = consumer->rxbd_flags; 1524 if (rxbd_flags & RXBD_E) { 1525 rxq->rxq_consumer = consumer; 1526 rxq->rxq_inuse -= rxconsumed; 1527 return; 1528 } 1529 KASSERT(rxq->rxq_mconsumer != NULL); 1530 #ifdef ETSEC_DEBUG 1531 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1532 #endif 1533 #if 0 1534 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1535 __func__, 1536 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1537 mtod(rxq->rxq_mconsumer, int *)[0], 1538 mtod(rxq->rxq_mconsumer, int *)[1], 1539 mtod(rxq->rxq_mconsumer, int *)[2], 1540 mtod(rxq->rxq_mconsumer, int *)[3]); 1541 #endif 1542 /* 1543 * We own this packet again. Clear all flags except wrap. 1544 */ 1545 rxconsumed++; 1546 consumer->rxbd_flags = rxbd_flags & (RXBD_W|RXBD_I); 1547 1548 /* 1549 * If this descriptor has the LAST bit set and no errors, 1550 * it's a valid input packet. 1551 */ 1552 if ((rxbd_flags & (RXBD_L|RXBD_ERRORS)) == RXBD_L) { 1553 size_t rxbd_len = consumer->rxbd_len; 1554 struct mbuf *m = rxq->rxq_mhead; 1555 struct mbuf *m_last = rxq->rxq_mconsumer; 1556 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1557 rxq->rxq_mtail = &rxq->rxq_mhead; 1558 rxq->rxq_mconsumer = rxq->rxq_mhead; 1559 m_last->m_next = NULL; 1560 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1561 m->m_pkthdr.len = rxbd_len; 1562 pq3etsec_rx_input(sc, m, rxbd_flags); 1563 } else if (rxbd_flags & RXBD_L) { 1564 KASSERT(rxbd_flags & RXBD_ERRORS); 1565 struct mbuf *m; 1566 /* 1567 * We encountered an error, take the mbufs and add 1568 * then to the rx bufcache so we can reuse them. 1569 */ 1570 ifp->if_ierrors++; 1571 for (m = rxq->rxq_mhead; 1572 m != rxq->rxq_mconsumer; 1573 m = m->m_next) { 1574 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1575 } 1576 m = rxq->rxq_mconsumer; 1577 if ((rxq->rxq_mhead = m->m_next) == NULL) 1578 rxq->rxq_mtail = &rxq->rxq_mhead; 1579 rxq->rxq_mconsumer = m->m_next; 1580 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1581 } else { 1582 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1583 } 1584 #ifdef ETSEC_DEBUG 1585 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1586 #endif 1587 1588 /* 1589 * Wrap at the last entry! 1590 */ 1591 if (rxbd_flags & RXBD_W) { 1592 KASSERT(consumer + 1 == rxq->rxq_last); 1593 consumer = rxq->rxq_first; 1594 } else { 1595 consumer++; 1596 } 1597 #ifdef ETSEC_DEBUG 1598 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1599 #endif 1600 } 1601 } 1602 1603 static void 1604 pq3etsec_rxq_purge( 1605 struct pq3etsec_softc *sc, 1606 struct pq3etsec_rxqueue *rxq, 1607 bool discard) 1608 { 1609 struct mbuf *m; 1610 1611 if ((m = rxq->rxq_mhead) != NULL) { 1612 #ifdef ETSEC_DEBUG 1613 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1614 #endif 1615 1616 if (discard) { 1617 pq3etsec_rx_map_unload(sc, m); 1618 m_freem(m); 1619 } else { 1620 while (m != NULL) { 1621 struct mbuf *m0 = m->m_next; 1622 m->m_next = NULL; 1623 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1624 m = m0; 1625 } 1626 } 1627 1628 } 1629 1630 rxq->rxq_mconsumer = NULL; 1631 rxq->rxq_mhead = NULL; 1632 rxq->rxq_mtail = &rxq->rxq_mhead; 1633 rxq->rxq_inuse = 0; 1634 } 1635 1636 static void 1637 pq3etsec_rxq_reset( 1638 struct pq3etsec_softc *sc, 1639 struct pq3etsec_rxqueue *rxq) 1640 { 1641 /* 1642 * sync all the descriptors 1643 */ 1644 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1645 rxq->rxq_last - rxq->rxq_first); 1646 1647 /* 1648 * Make sure we own all descriptors in the ring. 1649 */ 1650 volatile struct rxbd *rxbd; 1651 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1652 rxbd->rxbd_flags = RXBD_I; 1653 } 1654 1655 /* 1656 * Last descriptor has the wrap flag. 1657 */ 1658 rxbd->rxbd_flags = RXBD_W|RXBD_I; 1659 1660 /* 1661 * Reset the producer consumer indexes. 1662 */ 1663 rxq->rxq_consumer = rxq->rxq_first; 1664 rxq->rxq_producer = rxq->rxq_first; 1665 rxq->rxq_inuse = 0; 1666 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1667 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1668 1669 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY; 1670 1671 /* 1672 * Restart the transmit at the first descriptor 1673 */ 1674 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1675 } 1676 1677 static int 1678 pq3etsec_rxq_attach( 1679 struct pq3etsec_softc *sc, 1680 struct pq3etsec_rxqueue *rxq, 1681 u_int qno) 1682 { 1683 size_t map_size = PAGE_SIZE; 1684 size_t desc_count = map_size / sizeof(struct rxbd); 1685 int error; 1686 void *descs; 1687 1688 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1689 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1690 if (error) 1691 return error; 1692 1693 memset(descs, 0, map_size); 1694 rxq->rxq_first = descs; 1695 rxq->rxq_last = rxq->rxq_first + desc_count; 1696 rxq->rxq_consumer = descs; 1697 rxq->rxq_producer = descs; 1698 1699 pq3etsec_rxq_purge(sc, rxq, true); 1700 pq3etsec_rxq_reset(sc, rxq); 1701 1702 rxq->rxq_reg_rbase = RBASEn(qno); 1703 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1704 1705 return 0; 1706 } 1707 1708 static bool 1709 pq3etsec_txq_active_p( 1710 struct pq3etsec_softc * const sc, 1711 struct pq3etsec_txqueue *txq) 1712 { 1713 return !IF_IS_EMPTY(&txq->txq_mbufs); 1714 } 1715 1716 static bool 1717 pq3etsec_txq_fillable_p( 1718 struct pq3etsec_softc * const sc, 1719 struct pq3etsec_txqueue *txq) 1720 { 1721 return txq->txq_free >= txq->txq_threshold; 1722 } 1723 1724 static int 1725 pq3etsec_txq_attach( 1726 struct pq3etsec_softc *sc, 1727 struct pq3etsec_txqueue *txq, 1728 u_int qno) 1729 { 1730 size_t map_size = PAGE_SIZE; 1731 size_t desc_count = map_size / sizeof(struct txbd); 1732 int error; 1733 void *descs; 1734 1735 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1736 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1737 if (error) 1738 return error; 1739 1740 memset(descs, 0, map_size); 1741 txq->txq_first = descs; 1742 txq->txq_last = txq->txq_first + desc_count; 1743 txq->txq_consumer = descs; 1744 txq->txq_producer = descs; 1745 1746 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1747 1748 txq->txq_reg_tbase = TBASEn(qno); 1749 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1750 1751 pq3etsec_txq_reset(sc, txq); 1752 1753 return 0; 1754 } 1755 1756 static int 1757 pq3etsec_txq_map_load( 1758 struct pq3etsec_softc *sc, 1759 struct pq3etsec_txqueue *txq, 1760 struct mbuf *m) 1761 { 1762 bus_dmamap_t map; 1763 int error; 1764 1765 map = M_GETCTX(m, bus_dmamap_t); 1766 if (map != NULL) 1767 return 0; 1768 1769 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1770 if (map == NULL) 1771 return ENOMEM; 1772 1773 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1774 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1775 if (error) 1776 return error; 1777 1778 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1779 BUS_DMASYNC_PREWRITE); 1780 M_SETCTX(m, map); 1781 return 0; 1782 } 1783 1784 static void 1785 pq3etsec_txq_map_unload( 1786 struct pq3etsec_softc *sc, 1787 struct pq3etsec_txqueue *txq, 1788 struct mbuf *m) 1789 { 1790 KASSERT(m); 1791 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1792 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1793 BUS_DMASYNC_POSTWRITE); 1794 bus_dmamap_unload(sc->sc_dmat, map); 1795 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1796 } 1797 1798 static bool 1799 pq3etsec_txq_produce( 1800 struct pq3etsec_softc *sc, 1801 struct pq3etsec_txqueue *txq, 1802 struct mbuf *m) 1803 { 1804 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1805 1806 if (map->dm_nsegs > txq->txq_free) 1807 return false; 1808 1809 /* 1810 * TCP Offload flag must be set in the first descriptor. 1811 */ 1812 volatile struct txbd *producer = txq->txq_producer; 1813 uint16_t last_flags = TXBD_L; 1814 uint16_t first_flags = TXBD_R 1815 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1816 1817 /* 1818 * If we've produced enough descriptors without consuming any 1819 * we need to ask for an interrupt to reclaim some. 1820 */ 1821 txq->txq_lastintr += map->dm_nsegs; 1822 if (txq->txq_lastintr >= txq->txq_threshold 1823 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1824 txq->txq_lastintr = 0; 1825 last_flags |= TXBD_I; 1826 } 1827 1828 #ifdef ETSEC_DEBUG 1829 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1830 #endif 1831 KASSERT(producer != txq->txq_last); 1832 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1833 producer->txbd_len = map->dm_segs[0].ds_len; 1834 1835 if (map->dm_nsegs > 1) { 1836 volatile struct txbd *start = producer + 1; 1837 size_t count = map->dm_nsegs - 1; 1838 for (u_int i = 1; i < map->dm_nsegs; i++) { 1839 if (__predict_false(++producer == txq->txq_last)) { 1840 producer = txq->txq_first; 1841 if (start < txq->txq_last) { 1842 pq3etsec_txq_desc_presync(sc, txq, 1843 start, txq->txq_last - start); 1844 count -= txq->txq_last - start; 1845 } 1846 start = txq->txq_first; 1847 } 1848 #ifdef ETSEC_DEBUG 1849 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1850 #endif 1851 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1852 producer->txbd_len = map->dm_segs[i].ds_len; 1853 producer->txbd_flags = TXBD_R 1854 | (producer->txbd_flags & TXBD_W) 1855 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1856 #if 0 1857 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1858 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1859 #endif 1860 } 1861 pq3etsec_txq_desc_presync(sc, txq, start, count); 1862 } else { 1863 first_flags |= last_flags; 1864 } 1865 1866 membar_producer(); 1867 txq->txq_producer->txbd_flags = 1868 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1869 #if 0 1870 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1871 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1872 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1873 #endif 1874 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1875 1876 /* 1877 * Reduce free count by the number of segments we consumed. 1878 */ 1879 txq->txq_free -= map->dm_nsegs; 1880 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 1881 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 1882 KASSERT(producer->txbd_flags & TXBD_L); 1883 #ifdef ETSEC_DEBUG 1884 txq->txq_lmbufs[producer - txq->txq_first] = m; 1885 #endif 1886 1887 #if 0 1888 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 1889 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 1890 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 1891 #endif 1892 1893 if (++producer == txq->txq_last) 1894 txq->txq_producer = txq->txq_first; 1895 else 1896 txq->txq_producer = producer; 1897 IF_ENQUEUE(&txq->txq_mbufs, m); 1898 1899 /* 1900 * Restart the transmitter. 1901 */ 1902 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 1903 1904 return true; 1905 } 1906 1907 static void 1908 pq3etsec_tx_offload( 1909 struct pq3etsec_softc *sc, 1910 struct pq3etsec_txqueue *txq, 1911 struct mbuf **mp) 1912 { 1913 struct mbuf *m = *mp; 1914 u_int csum_flags = m->m_pkthdr.csum_flags; 1915 struct m_tag *vtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m); 1916 1917 KASSERT(m->m_flags & M_PKTHDR); 1918 1919 /* 1920 * Let see if we are doing any offload first. 1921 */ 1922 if (csum_flags == 0 && vtag == 0) { 1923 m->m_flags &= ~M_HASFCB; 1924 return; 1925 } 1926 1927 uint16_t flags = 0; 1928 if (csum_flags & M_CSUM_IP) { 1929 flags |= TXFCB_IP 1930 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 1931 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 1932 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 1933 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 1934 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 1935 } 1936 if (vtag) { 1937 flags |= TXFCB_VLN; 1938 } 1939 if (flags == 0) { 1940 m->m_flags &= ~M_HASFCB; 1941 return; 1942 } 1943 1944 struct txfcb fcb; 1945 fcb.txfcb_flags = flags; 1946 if (csum_flags & M_CSUM_IPv4) 1947 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 1948 else 1949 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 1950 fcb.txfcb_l3os = ETHER_HDR_LEN; 1951 fcb.txfcb_phcs = 0; 1952 fcb.txfcb_vlctl = vtag ? VLAN_TAG_VALUE(vtag) & 0xffff : 0; 1953 1954 #if 0 1955 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 1956 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 1957 fcb.txfcb_phcs, fcb.txfcb_vlctl); 1958 #endif 1959 1960 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 1961 m->m_data -= sizeof(fcb); 1962 m->m_len += sizeof(fcb); 1963 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 1964 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 1965 m->m_data = m->m_pktdat; 1966 m->m_len += sizeof(fcb); 1967 } else { 1968 struct mbuf *mn; 1969 MGET(mn, M_DONTWAIT, m->m_type); 1970 if (mn == NULL) { 1971 if (csum_flags & M_CSUM_IP4) { 1972 #ifdef INET 1973 ip_undefer_csum(m, ETHER_HDR_LEN, 1974 csum_flags & M_CSUM_IP4); 1975 #else 1976 panic("%s: impossible M_CSUM flags %#x", 1977 device_xname(sc->sc_dev), csum_flags); 1978 #endif 1979 } else if (csum_flags & M_CSUM_IP6) { 1980 #ifdef INET6 1981 ip6_undefer_csum(m, ETHER_HDR_LEN, 1982 csum_flags & M_CSUM_IP6); 1983 #else 1984 panic("%s: impossible M_CSUM flags %#x", 1985 device_xname(sc->sc_dev), csum_flags); 1986 #endif 1987 } else if (vtag) { 1988 } 1989 1990 m->m_flags &= ~M_HASFCB; 1991 return; 1992 } 1993 1994 M_MOVE_PKTHDR(mn, m); 1995 mn->m_next = m; 1996 m = mn; 1997 MH_ALIGN(m, sizeof(fcb)); 1998 m->m_len = sizeof(fcb); 1999 *mp = m; 2000 } 2001 m->m_pkthdr.len += sizeof(fcb); 2002 m->m_flags |= M_HASFCB; 2003 *mtod(m, struct txfcb *) = fcb; 2004 return; 2005 } 2006 2007 static bool 2008 pq3etsec_txq_enqueue( 2009 struct pq3etsec_softc *sc, 2010 struct pq3etsec_txqueue *txq) 2011 { 2012 for (;;) { 2013 if (IF_QFULL(&txq->txq_mbufs)) 2014 return false; 2015 struct mbuf *m = txq->txq_next; 2016 if (m == NULL) { 2017 int s = splnet(); 2018 IF_DEQUEUE(&sc->sc_if.if_snd, m); 2019 splx(s); 2020 if (m == NULL) 2021 return true; 2022 M_SETCTX(m, NULL); 2023 pq3etsec_tx_offload(sc, txq, &m); 2024 } else { 2025 txq->txq_next = NULL; 2026 } 2027 int error = pq3etsec_txq_map_load(sc, txq, m); 2028 if (error) { 2029 aprint_error_dev(sc->sc_dev, 2030 "discarded packet due to " 2031 "dmamap load failure: %d\n", error); 2032 m_freem(m); 2033 continue; 2034 } 2035 KASSERT(txq->txq_next == NULL); 2036 if (!pq3etsec_txq_produce(sc, txq, m)) { 2037 txq->txq_next = m; 2038 return false; 2039 } 2040 KASSERT(txq->txq_next == NULL); 2041 } 2042 } 2043 2044 static bool 2045 pq3etsec_txq_consume( 2046 struct pq3etsec_softc *sc, 2047 struct pq3etsec_txqueue *txq) 2048 { 2049 struct ifnet * const ifp = &sc->sc_if; 2050 volatile struct txbd *consumer = txq->txq_consumer; 2051 size_t txfree = 0; 2052 2053 #if 0 2054 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 2055 #endif 2056 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 2057 2058 for (;;) { 2059 if (consumer == txq->txq_producer) { 2060 txq->txq_consumer = consumer; 2061 txq->txq_free += txfree; 2062 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2063 #if 0 2064 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2065 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2066 #endif 2067 KASSERT(txq->txq_lastintr == 0); 2068 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2069 return true; 2070 } 2071 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2072 const uint16_t txbd_flags = consumer->txbd_flags; 2073 if (txbd_flags & TXBD_R) { 2074 txq->txq_consumer = consumer; 2075 txq->txq_free += txfree; 2076 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2077 #if 0 2078 printf("%s: freed %zu descriptors\n", 2079 __func__, txfree); 2080 #endif 2081 return pq3etsec_txq_fillable_p(sc, txq); 2082 } 2083 2084 /* 2085 * If this is the last descriptor in the chain, get the 2086 * mbuf, free its dmamap, and free the mbuf chain itself. 2087 */ 2088 if (txbd_flags & TXBD_L) { 2089 struct mbuf *m; 2090 2091 IF_DEQUEUE(&txq->txq_mbufs, m); 2092 #ifdef ETSEC_DEBUG 2093 KASSERTMSG( 2094 m == txq->txq_lmbufs[consumer-txq->txq_first], 2095 "%s: %p [%u]: flags %#x m (%p) != %p (%p)", 2096 __func__, consumer, consumer - txq->txq_first, 2097 txbd_flags, m, 2098 &txq->txq_lmbufs[consumer-txq->txq_first], 2099 txq->txq_lmbufs[consumer-txq->txq_first]); 2100 #endif 2101 KASSERT(m); 2102 pq3etsec_txq_map_unload(sc, txq, m); 2103 #if 0 2104 printf("%s: mbuf %p: consumed a %u byte packet\n", 2105 __func__, m, m->m_pkthdr.len); 2106 #endif 2107 if (m->m_flags & M_HASFCB) 2108 m_adj(m, sizeof(struct txfcb)); 2109 ifp->if_opackets++; 2110 ifp->if_obytes += m->m_pkthdr.len; 2111 if (m->m_flags & M_MCAST) 2112 ifp->if_omcasts++; 2113 if (txbd_flags & TXBD_ERRORS) 2114 ifp->if_oerrors++; 2115 m_freem(m); 2116 #ifdef ETSEC_DEBUG 2117 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2118 #endif 2119 } else { 2120 #ifdef ETSEC_DEBUG 2121 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2122 #endif 2123 } 2124 2125 /* 2126 * We own this packet again. Clear all flags except wrap. 2127 */ 2128 txfree++; 2129 //consumer->txbd_flags = txbd_flags & TXBD_W; 2130 2131 /* 2132 * Wrap at the last entry! 2133 */ 2134 if (txbd_flags & TXBD_W) { 2135 KASSERT(consumer + 1 == txq->txq_last); 2136 consumer = txq->txq_first; 2137 } else { 2138 consumer++; 2139 KASSERT(consumer < txq->txq_last); 2140 } 2141 } 2142 } 2143 2144 static void 2145 pq3etsec_txq_purge( 2146 struct pq3etsec_softc *sc, 2147 struct pq3etsec_txqueue *txq) 2148 { 2149 struct mbuf *m; 2150 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2151 2152 for (;;) { 2153 IF_DEQUEUE(&txq->txq_mbufs, m); 2154 if (m == NULL) 2155 break; 2156 pq3etsec_txq_map_unload(sc, txq, m); 2157 m_freem(m); 2158 } 2159 if ((m = txq->txq_next) != NULL) { 2160 txq->txq_next = NULL; 2161 pq3etsec_txq_map_unload(sc, txq, m); 2162 m_freem(m); 2163 } 2164 #ifdef ETSEC_DEBUG 2165 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2166 #endif 2167 } 2168 2169 static void 2170 pq3etsec_txq_reset( 2171 struct pq3etsec_softc *sc, 2172 struct pq3etsec_txqueue *txq) 2173 { 2174 /* 2175 * sync all the descriptors 2176 */ 2177 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2178 txq->txq_last - txq->txq_first); 2179 2180 /* 2181 * Make sure we own all descriptors in the ring. 2182 */ 2183 volatile struct txbd *txbd; 2184 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2185 txbd->txbd_flags = 0; 2186 } 2187 2188 /* 2189 * Last descriptor has the wrap flag. 2190 */ 2191 txbd->txbd_flags = TXBD_W; 2192 2193 /* 2194 * Reset the producer consumer indexes. 2195 */ 2196 txq->txq_consumer = txq->txq_first; 2197 txq->txq_producer = txq->txq_first; 2198 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2199 txq->txq_threshold = txq->txq_free / 2; 2200 txq->txq_lastintr = 0; 2201 2202 /* 2203 * What do we want to get interrupted on? 2204 */ 2205 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE; 2206 2207 /* 2208 * Restart the transmit at the first descriptor 2209 */ 2210 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2211 } 2212 2213 static void 2214 pq3etsec_ifstart(struct ifnet *ifp) 2215 { 2216 struct pq3etsec_softc * const sc = ifp->if_softc; 2217 2218 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2219 softint_schedule(sc->sc_soft_ih); 2220 } 2221 2222 static void 2223 pq3etsec_tx_error( 2224 struct pq3etsec_softc * const sc) 2225 { 2226 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2227 2228 pq3etsec_txq_consume(sc, txq); 2229 2230 if (pq3etsec_txq_fillable_p(sc, txq)) 2231 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2232 if (sc->sc_txerrors & (IEVENT_LC|IEVENT_CRL|IEVENT_XFUN|IEVENT_BABT)) { 2233 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2234 } 2235 2236 if (pq3etsec_txq_active_p(sc, txq)) 2237 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2238 if (!pq3etsec_txq_enqueue(sc, txq)) { 2239 sc->sc_ev_tx_stall.ev_count++; 2240 sc->sc_if.if_flags |= IFF_OACTIVE; 2241 } 2242 2243 sc->sc_txerrors = 0; 2244 } 2245 2246 int 2247 pq3etsec_tx_intr(void *arg) 2248 { 2249 struct pq3etsec_softc * const sc = arg; 2250 2251 sc->sc_ev_tx_intr.ev_count++; 2252 2253 uint32_t ievent = etsec_read(sc, IEVENT); 2254 ievent &= IEVENT_TXF|IEVENT_TXB; 2255 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2256 2257 #if 0 2258 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2259 __func__, ievent, etsec_read(sc, IMASK)); 2260 #endif 2261 2262 if (ievent == 0) 2263 return 0; 2264 2265 sc->sc_imask &= ~(IEVENT_TXF|IEVENT_TXB); 2266 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2267 etsec_write(sc, IMASK, sc->sc_imask); 2268 softint_schedule(sc->sc_soft_ih); 2269 return 1; 2270 } 2271 2272 int 2273 pq3etsec_rx_intr(void *arg) 2274 { 2275 struct pq3etsec_softc * const sc = arg; 2276 2277 sc->sc_ev_rx_intr.ev_count++; 2278 2279 uint32_t ievent = etsec_read(sc, IEVENT); 2280 ievent &= IEVENT_RXF|IEVENT_RXB; 2281 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2282 if (ievent == 0) 2283 return 0; 2284 2285 #if 0 2286 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2287 #endif 2288 2289 sc->sc_imask &= ~(IEVENT_RXF|IEVENT_RXB); 2290 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2291 etsec_write(sc, IMASK, sc->sc_imask); 2292 softint_schedule(sc->sc_soft_ih); 2293 return 1; 2294 } 2295 2296 int 2297 pq3etsec_error_intr(void *arg) 2298 { 2299 struct pq3etsec_softc * const sc = arg; 2300 2301 sc->sc_ev_error_intr.ev_count++; 2302 2303 for (int rv = 0, soft_flags = 0;; rv = 1) { 2304 uint32_t ievent = etsec_read(sc, IEVENT); 2305 ievent &= ~(IEVENT_RXF|IEVENT_RXB|IEVENT_TXF|IEVENT_TXB); 2306 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2307 if (ievent == 0) { 2308 if (soft_flags) { 2309 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2310 softint_schedule(sc->sc_soft_ih); 2311 } 2312 return rv; 2313 } 2314 #if 0 2315 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2316 __func__, ievent, etsec_read(sc, IMASK)); 2317 #endif 2318 2319 if (ievent & (IEVENT_GRSC|IEVENT_GTSC)) { 2320 sc->sc_imask &= ~(IEVENT_GRSC|IEVENT_GTSC); 2321 etsec_write(sc, IMASK, sc->sc_imask); 2322 wakeup(sc); 2323 } 2324 if (ievent & (IEVENT_MMRD|IEVENT_MMWR)) { 2325 sc->sc_imask &= ~(IEVENT_MMRD|IEVENT_MMWR); 2326 etsec_write(sc, IMASK, sc->sc_imask); 2327 wakeup(&sc->sc_mii); 2328 } 2329 if (ievent & IEVENT_BSY) { 2330 soft_flags |= SOFT_RXBSY; 2331 sc->sc_imask &= ~IEVENT_BSY; 2332 etsec_write(sc, IMASK, sc->sc_imask); 2333 } 2334 if (ievent & IEVENT_TXE) { 2335 soft_flags |= SOFT_TXERROR; 2336 sc->sc_imask &= ~IEVENT_TXE; 2337 sc->sc_txerrors |= ievent; 2338 } 2339 if (ievent & IEVENT_TXC) { 2340 sc->sc_ev_tx_pause.ev_count++; 2341 } 2342 if (ievent & IEVENT_RXC) { 2343 sc->sc_ev_rx_pause.ev_count++; 2344 } 2345 if (ievent & IEVENT_DPE) { 2346 soft_flags |= SOFT_RESET; 2347 sc->sc_imask &= ~IEVENT_DPE; 2348 etsec_write(sc, IMASK, sc->sc_imask); 2349 } 2350 } 2351 } 2352 2353 void 2354 pq3etsec_soft_intr(void *arg) 2355 { 2356 struct pq3etsec_softc * const sc = arg; 2357 struct ifnet * const ifp = &sc->sc_if; 2358 2359 mutex_enter(sc->sc_lock); 2360 2361 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2362 2363 sc->sc_ev_soft_intr.ev_count++; 2364 2365 if (soft_flags & SOFT_RESET) { 2366 int s = splnet(); 2367 pq3etsec_ifinit(ifp); 2368 splx(s); 2369 soft_flags = 0; 2370 } 2371 2372 if (soft_flags & SOFT_RXBSY) { 2373 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2374 size_t threshold = 5 * rxq->rxq_threshold / 4; 2375 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2376 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2377 } else { 2378 sc->sc_imask |= IEVENT_BSY; 2379 } 2380 aprint_normal_dev(sc->sc_dev, 2381 "increasing receive buffers from %zu to %zu\n", 2382 rxq->rxq_threshold, threshold); 2383 rxq->rxq_threshold = threshold; 2384 } 2385 2386 if ((soft_flags & SOFT_TXINTR) 2387 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2388 /* 2389 * Let's do what we came here for. Consume transmitted 2390 * packets off the the transmit ring. 2391 */ 2392 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2393 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2394 sc->sc_ev_tx_stall.ev_count++; 2395 ifp->if_flags |= IFF_OACTIVE; 2396 } else { 2397 ifp->if_flags &= ~IFF_OACTIVE; 2398 } 2399 sc->sc_imask |= IEVENT_TXF; 2400 } 2401 2402 if (soft_flags & (SOFT_RXINTR|SOFT_RXBSY)) { 2403 /* 2404 * Let's consume 2405 */ 2406 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2407 sc->sc_imask |= IEVENT_RXF; 2408 } 2409 2410 if (soft_flags & SOFT_TXERROR) { 2411 pq3etsec_tx_error(sc); 2412 sc->sc_imask |= IEVENT_TXE; 2413 } 2414 2415 if (ifp->if_flags & IFF_RUNNING) { 2416 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2417 etsec_write(sc, IMASK, sc->sc_imask); 2418 } else { 2419 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2420 } 2421 2422 mutex_exit(sc->sc_lock); 2423 } 2424 2425 static void 2426 pq3etsec_mii_tick(void *arg) 2427 { 2428 struct pq3etsec_softc * const sc = arg; 2429 mutex_enter(sc->sc_lock); 2430 callout_ack(&sc->sc_mii_callout); 2431 sc->sc_ev_mii_ticks.ev_count++; 2432 #ifdef DEBUG 2433 uint64_t now = mftb(); 2434 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2435 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2436 __func__, now - sc->sc_mii_last_tick); 2437 callout_stop(&sc->sc_mii_callout); 2438 } 2439 #endif 2440 mii_tick(&sc->sc_mii); 2441 int s = splnet(); 2442 if (sc->sc_soft_flags & SOFT_RESET) 2443 softint_schedule(sc->sc_soft_ih); 2444 splx(s); 2445 callout_schedule(&sc->sc_mii_callout, hz); 2446 #ifdef DEBUG 2447 sc->sc_mii_last_tick = now; 2448 #endif 2449 mutex_exit(sc->sc_lock); 2450 } 2451
Indexes created Tue Sep 30 07:10:03 GMT 2025