pq3etsec.c revision 1.17
1 /* $NetBSD: pq3etsec.c,v 1.17 2014/12/20 17:55:08 nonaka Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_inet.h" 38 #include "opt_mpc85xx.h" 39 40 #include <sys/cdefs.h> 41 42 __KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.17 2014/12/20 17:55:08 nonaka Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/cpu.h> 46 #include <sys/device.h> 47 #include <sys/mbuf.h> 48 #include <sys/ioctl.h> 49 #include <sys/intr.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/kmem.h> 53 #include <sys/proc.h> 54 #include <sys/atomic.h> 55 #include <sys/callout.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_ether.h> 60 #include <net/if_media.h> 61 62 #include <dev/mii/miivar.h> 63 64 #include <net/bpf.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/ip.h> 70 #include <netinet/in_offload.h> 71 #endif /* INET */ 72 #ifdef INET6 73 #include <netinet6/in6.h> 74 #include <netinet/ip6.h> 75 #endif 76 #include <netinet6/in6_offload.h> 77 78 79 #include <powerpc/spr.h> 80 #include <powerpc/booke/spr.h> 81 82 #include <powerpc/booke/cpuvar.h> 83 #include <powerpc/booke/e500var.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/etsecreg.h> 86 87 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 88 89 #define ETSEC_MAXTXMBUFS 30 90 #define ETSEC_NTXSEGS 30 91 #define ETSEC_MAXRXMBUFS 511 92 #define ETSEC_MINRXMBUFS 32 93 #define ETSEC_NRXSEGS 1 94 95 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 96 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx\ 97 |IFCAP_CSUM_UDPv4_Rx\ 98 |IFCAP_CSUM_TCPv6_Rx\ 99 |IFCAP_CSUM_UDPv6_Rx) 100 101 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 102 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx\ 103 |IFCAP_CSUM_UDPv4_Tx\ 104 |IFCAP_CSUM_TCPv6_Tx\ 105 |IFCAP_CSUM_UDPv6_Tx) 106 107 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN|IFCAP_RCTRL_TUCSEN\ 108 |IFCAP_TCTRL_IPCSEN|IFCAP_TCTRL_TUCSEN) 109 110 #define M_CSUM_IP (M_CSUM_CIP|M_CSUM_CTU) 111 #define M_CSUM_IP6 (M_CSUM_TCPv6|M_CSUM_UDPv6) 112 #define M_CSUM_TUP (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 113 #define M_CSUM_UDP (M_CSUM_UDPv4|M_CSUM_UDPv6) 114 #define M_CSUM_IP4 (M_CSUM_IPv4|M_CSUM_UDPv4|M_CSUM_TCPv4) 115 #define M_CSUM_CIP (M_CSUM_IPv4) 116 #define M_CSUM_CTU (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 117 118 struct pq3etsec_txqueue { 119 bus_dmamap_t txq_descmap; 120 volatile struct txbd *txq_consumer; 121 volatile struct txbd *txq_producer; 122 volatile struct txbd *txq_first; 123 volatile struct txbd *txq_last; 124 struct ifqueue txq_mbufs; 125 struct mbuf *txq_next; 126 #ifdef ETSEC_DEBUG 127 struct mbuf *txq_lmbufs[512]; 128 #endif 129 uint32_t txq_qmask; 130 uint32_t txq_free; 131 uint32_t txq_threshold; 132 uint32_t txq_lastintr; 133 bus_size_t txq_reg_tbase; 134 bus_dma_segment_t txq_descmap_seg; 135 }; 136 137 struct pq3etsec_rxqueue { 138 bus_dmamap_t rxq_descmap; 139 volatile struct rxbd *rxq_consumer; 140 volatile struct rxbd *rxq_producer; 141 volatile struct rxbd *rxq_first; 142 volatile struct rxbd *rxq_last; 143 struct mbuf *rxq_mhead; 144 struct mbuf **rxq_mtail; 145 struct mbuf *rxq_mconsumer; 146 #ifdef ETSEC_DEBUG 147 struct mbuf *rxq_mbufs[512]; 148 #endif 149 uint32_t rxq_qmask; 150 uint32_t rxq_inuse; 151 uint32_t rxq_threshold; 152 bus_size_t rxq_reg_rbase; 153 bus_size_t rxq_reg_rbptr; 154 bus_dma_segment_t rxq_descmap_seg; 155 }; 156 157 struct pq3etsec_mapcache { 158 u_int dmc_nmaps; 159 u_int dmc_maxseg; 160 u_int dmc_maxmaps; 161 u_int dmc_maxmapsize; 162 bus_dmamap_t dmc_maps[0]; 163 }; 164 165 struct pq3etsec_softc { 166 device_t sc_dev; 167 device_t sc_mdio_dev; 168 struct ethercom sc_ec; 169 #define sc_if sc_ec.ec_if 170 struct mii_data sc_mii; 171 bus_space_tag_t sc_bst; 172 bus_space_handle_t sc_bsh; 173 bus_space_handle_t sc_mdio_bsh; 174 bus_dma_tag_t sc_dmat; 175 int sc_phy_addr; 176 prop_dictionary_t sc_intrmap; 177 uint32_t sc_intrmask; 178 179 uint32_t sc_soft_flags; 180 #define SOFT_RESET 0x0001 181 #define SOFT_RXINTR 0x0010 182 #define SOFT_RXBSY 0x0020 183 #define SOFT_TXINTR 0x0100 184 #define SOFT_TXERROR 0x0200 185 186 struct pq3etsec_txqueue sc_txq; 187 struct pq3etsec_rxqueue sc_rxq; 188 uint32_t sc_txerrors; 189 uint32_t sc_rxerrors; 190 191 size_t sc_rx_adjlen; 192 193 /* 194 * Copies of various ETSEC registers. 195 */ 196 uint32_t sc_imask; 197 uint32_t sc_maccfg1; 198 uint32_t sc_maccfg2; 199 uint32_t sc_maxfrm; 200 uint32_t sc_ecntrl; 201 uint32_t sc_dmactrl; 202 uint32_t sc_macstnaddr1; 203 uint32_t sc_macstnaddr2; 204 uint32_t sc_tctrl; 205 uint32_t sc_rctrl; 206 uint32_t sc_gaddr[16]; 207 uint64_t sc_macaddrs[15]; 208 209 void *sc_tx_ih; 210 void *sc_rx_ih; 211 void *sc_error_ih; 212 void *sc_soft_ih; 213 214 kmutex_t *sc_lock; 215 216 struct evcnt sc_ev_tx_stall; 217 struct evcnt sc_ev_tx_intr; 218 struct evcnt sc_ev_rx_stall; 219 struct evcnt sc_ev_rx_intr; 220 struct evcnt sc_ev_error_intr; 221 struct evcnt sc_ev_soft_intr; 222 struct evcnt sc_ev_tx_pause; 223 struct evcnt sc_ev_rx_pause; 224 struct evcnt sc_ev_mii_ticks; 225 226 struct callout sc_mii_callout; 227 uint64_t sc_mii_last_tick; 228 229 struct ifqueue sc_rx_bufcache; 230 struct pq3etsec_mapcache *sc_rx_mapcache; 231 struct pq3etsec_mapcache *sc_tx_mapcache; 232 }; 233 234 struct pq3mdio_softc { 235 device_t mdio_dev; 236 237 kmutex_t *mdio_lock; 238 239 bus_space_tag_t mdio_bst; 240 bus_space_handle_t mdio_bsh; 241 }; 242 243 static int pq3etsec_match(device_t, cfdata_t, void *); 244 static void pq3etsec_attach(device_t, device_t, void *); 245 246 static int pq3mdio_match(device_t, cfdata_t, void *); 247 static void pq3mdio_attach(device_t, device_t, void *); 248 249 static void pq3etsec_ifstart(struct ifnet *); 250 static void pq3etsec_ifwatchdog(struct ifnet *); 251 static int pq3etsec_ifinit(struct ifnet *); 252 static void pq3etsec_ifstop(struct ifnet *, int); 253 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 254 255 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 256 struct pq3etsec_mapcache **, size_t, size_t, size_t); 257 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 258 struct pq3etsec_mapcache *); 259 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 260 struct pq3etsec_mapcache *); 261 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 262 struct pq3etsec_mapcache *, bus_dmamap_t); 263 264 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 265 struct pq3etsec_txqueue *, u_int); 266 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 267 struct pq3etsec_txqueue *); 268 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 269 struct pq3etsec_txqueue *); 270 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 271 struct pq3etsec_txqueue *); 272 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 273 struct pq3etsec_txqueue *, struct mbuf *m); 274 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 275 struct pq3etsec_txqueue *); 276 277 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 278 struct pq3etsec_rxqueue *, u_int); 279 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 280 struct pq3etsec_rxqueue *); 281 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 282 struct pq3etsec_rxqueue *, bool); 283 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 284 struct pq3etsec_rxqueue *); 285 286 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 287 288 static void pq3etsec_mii_tick(void *); 289 static int pq3etsec_rx_intr(void *); 290 static int pq3etsec_tx_intr(void *); 291 static int pq3etsec_error_intr(void *); 292 static void pq3etsec_soft_intr(void *); 293 294 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 295 pq3etsec_match, pq3etsec_attach, NULL, NULL); 296 297 CFATTACH_DECL_NEW(pq3mdio_tsec, sizeof(struct pq3mdio_softc), 298 pq3mdio_match, pq3mdio_attach, NULL, NULL); 299 300 CFATTACH_DECL_NEW(pq3mdio_cpunode, sizeof(struct pq3mdio_softc), 301 pq3mdio_match, pq3mdio_attach, NULL, NULL); 302 303 static inline uint32_t 304 etsec_mdio_read(struct pq3mdio_softc *mdio, bus_size_t off) 305 { 306 return bus_space_read_4(mdio->mdio_bst, mdio->mdio_bsh, off); 307 } 308 309 static inline void 310 etsec_mdio_write(struct pq3mdio_softc *mdio, bus_size_t off, uint32_t data) 311 { 312 bus_space_write_4(mdio->mdio_bst, mdio->mdio_bsh, off, data); 313 } 314 315 static inline uint32_t 316 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 317 { 318 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 319 } 320 321 static int 322 pq3mdio_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 323 { 324 return strcmp(cf->cf_name, "mdio") == 0; 325 } 326 327 static int 328 pq3mdio_match(device_t parent, cfdata_t cf, void *aux) 329 { 330 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 331 const bool p1025_p = (svr == (SVR_P1025v1 >> 16) 332 || svr == (SVR_P1016v1 >> 16)); 333 const bool p1023_p = (svr == (SVR_P1023v1 >> 16) 334 || svr == (SVR_P1017v1 >> 16)); 335 336 if (device_is_a(parent, "cpunode")) { 337 if ((!p1025_p && !p1023_p) 338 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 339 return 0; 340 341 return 1; 342 } 343 344 if (device_is_a(parent, "tsec")) { 345 if ((p1025_p || p1023_p) 346 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 347 return 0; 348 349 return 1; 350 } 351 352 return 0; 353 } 354 355 static void 356 pq3mdio_attach(device_t parent, device_t self, void *aux) 357 { 358 struct pq3mdio_softc * const mdio = device_private(self); 359 struct cpunode_attach_args * const cna = aux; 360 struct cpunode_locators * const cnl = &cna->cna_locs; 361 362 mdio->mdio_dev = self; 363 mdio->mdio_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 364 365 if (device_is_a(parent, "cpunode")) { 366 struct cpunode_softc * const psc = device_private(parent); 367 psc->sc_children |= cna->cna_childmask; 368 369 mdio->mdio_bst = cna->cna_memt; 370 if (bus_space_map(mdio->mdio_bst, cnl->cnl_addr, 371 cnl->cnl_size, 0, &mdio->mdio_bsh) != 0) { 372 aprint_error(": error mapping registers @ %#x\n", 373 cnl->cnl_addr); 374 return; 375 } 376 } else { 377 struct pq3etsec_softc * const sc = device_private(parent); 378 379 KASSERT(device_is_a(parent, "tsec")); 380 KASSERTMSG(cnl->cnl_addr == ETSEC1_BASE 381 || cnl->cnl_addr == ETSEC2_BASE 382 || cnl->cnl_addr == ETSEC3_BASE 383 || cnl->cnl_addr == ETSEC4_BASE, 384 "unknown tsec addr %x", cnl->cnl_addr); 385 386 mdio->mdio_bst = sc->sc_bst; 387 mdio->mdio_bsh = sc->sc_bsh; 388 } 389 390 aprint_normal("\n"); 391 } 392 393 static int 394 pq3mdio_mii_readreg(device_t self, int phy, int reg) 395 { 396 struct pq3mdio_softc * const mdio = device_private(self); 397 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 398 399 mutex_enter(mdio->mdio_lock); 400 401 etsec_mdio_write(mdio, MIIMADD, 402 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 403 404 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 405 etsec_mdio_write(mdio, MIIMCOM, MIIMCOM_READ); 406 407 while (etsec_mdio_read(mdio, MIIMIND) != 0) { 408 delay(1); 409 } 410 int data = etsec_mdio_read(mdio, MIIMSTAT); 411 412 if (miimcom == MIIMCOM_SCAN) 413 etsec_mdio_write(mdio, MIIMCOM, miimcom); 414 415 #if 0 416 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 417 __func__, phy, reg, data); 418 #endif 419 mutex_exit(mdio->mdio_lock); 420 return data; 421 } 422 423 static void 424 pq3mdio_mii_writereg(device_t self, int phy, int reg, int data) 425 { 426 struct pq3mdio_softc * const mdio = device_private(self); 427 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 428 429 #if 0 430 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 431 __func__, phy, reg, data); 432 #endif 433 434 mutex_enter(mdio->mdio_lock); 435 436 etsec_mdio_write(mdio, MIIMADD, 437 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 438 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 439 etsec_mdio_write(mdio, MIIMCON, data); 440 441 int timo = 1000; /* 1ms */ 442 while ((etsec_mdio_read(mdio, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 443 delay(1); 444 } 445 446 if (miimcom == MIIMCOM_SCAN) 447 etsec_mdio_write(mdio, MIIMCOM, miimcom); 448 449 mutex_exit(mdio->mdio_lock); 450 } 451 452 static inline void 453 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 454 { 455 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 456 } 457 458 static void 459 pq3etsec_mii_statchg(struct ifnet *ifp) 460 { 461 struct pq3etsec_softc * const sc = ifp->if_softc; 462 struct mii_data * const mii = &sc->sc_mii; 463 464 uint32_t maccfg1 = sc->sc_maccfg1; 465 uint32_t maccfg2 = sc->sc_maccfg2; 466 uint32_t ecntrl = sc->sc_ecntrl; 467 468 maccfg1 &= ~(MACCFG1_TX_FLOW|MACCFG1_RX_FLOW); 469 maccfg2 &= ~(MACCFG2_IFMODE|MACCFG2_FD); 470 471 if (sc->sc_mii.mii_media_active & IFM_FDX) { 472 maccfg2 |= MACCFG2_FD; 473 } 474 475 /* 476 * Now deal with the flow control bits. 477 */ 478 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 479 && (mii->mii_media_active & IFM_ETH_FMASK)) { 480 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 481 maccfg1 |= MACCFG1_RX_FLOW; 482 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 483 maccfg1 |= MACCFG1_TX_FLOW; 484 } 485 486 /* 487 * Now deal with the speed. 488 */ 489 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 490 maccfg2 |= MACCFG2_IFMODE_GMII; 491 } else { 492 maccfg2 |= MACCFG2_IFMODE_MII; 493 ecntrl &= ~ECNTRL_R100M; 494 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 495 ecntrl |= ECNTRL_R100M; 496 } 497 } 498 499 /* 500 * If things are different, re-init things. 501 */ 502 if (maccfg1 != sc->sc_maccfg1 503 || maccfg2 != sc->sc_maccfg2 504 || ecntrl != sc->sc_ecntrl) { 505 if (sc->sc_if.if_flags & IFF_RUNNING) 506 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 507 sc->sc_maccfg1 = maccfg1; 508 sc->sc_maccfg2 = maccfg2; 509 sc->sc_ecntrl = ecntrl; 510 } 511 } 512 513 #if 0 514 static void 515 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 516 { 517 struct pq3etsec_softc * const sc = ifp->if_softc; 518 519 mii_pollstat(&sc->sc_mii); 520 ether_mediastatus(ifp, ifmr); 521 ifmr->ifm_status = sc->sc_mii.mii_media_status; 522 ifmr->ifm_active = sc->sc_mii.mii_media_active; 523 } 524 525 static int 526 pq3etsec_mediachange(struct ifnet *ifp) 527 { 528 struct pq3etsec_softc * const sc = ifp->if_softc; 529 530 if ((ifp->if_flags & IFF_UP) == 0) 531 return 0; 532 533 int rv = mii_mediachg(&sc->sc_mii); 534 return (rv == ENXIO) ? 0 : rv; 535 } 536 #endif 537 538 static int 539 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 540 { 541 542 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 543 return 0; 544 545 return 1; 546 } 547 548 static void 549 pq3etsec_attach(device_t parent, device_t self, void *aux) 550 { 551 struct cpunode_softc * const psc = device_private(parent); 552 struct pq3etsec_softc * const sc = device_private(self); 553 struct cpunode_attach_args * const cna = aux; 554 struct cpunode_locators * const cnl = &cna->cna_locs; 555 cfdata_t cf = device_cfdata(self); 556 int error; 557 558 psc->sc_children |= cna->cna_childmask; 559 sc->sc_dev = self; 560 sc->sc_bst = cna->cna_memt; 561 sc->sc_dmat = &booke_bus_dma_tag; 562 563 /* 564 * Pull out the mdio bus and phy we are supposed to use. 565 */ 566 const int mdio = cf->cf_loc[CPUNODECF_MDIO]; 567 const int phy = cf->cf_loc[CPUNODECF_PHY]; 568 if (mdio != CPUNODECF_MDIO_DEFAULT) 569 aprint_normal(" mdio %d", mdio); 570 571 /* 572 * See if the phy is in the config file... 573 */ 574 if (phy != CPUNODECF_PHY_DEFAULT) { 575 sc->sc_phy_addr = phy; 576 } else { 577 unsigned char prop_name[20]; 578 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 579 cnl->cnl_instance); 580 sc->sc_phy_addr = board_info_get_number(prop_name); 581 } 582 if (sc->sc_phy_addr != MII_PHY_ANY) 583 aprint_normal(" phy %d", sc->sc_phy_addr); 584 585 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 586 &sc->sc_bsh); 587 if (error) { 588 aprint_error(": error mapping registers: %d\n", error); 589 return; 590 } 591 592 /* 593 * Assume firmware has aready set the mac address and fetch it 594 * before we reinit it. 595 */ 596 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 597 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 598 sc->sc_rctrl = RCTRL_DEFAULT; 599 sc->sc_ecntrl = etsec_read(sc, ECNTRL); 600 sc->sc_maccfg1 = etsec_read(sc, MACCFG1); 601 sc->sc_maccfg2 = etsec_read(sc, MACCFG2) | MACCFG2_DEFAULT; 602 603 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 604 size_t len; 605 const uint8_t *mac_addr = 606 board_info_get_data("tsec-mac-addr-base", &len); 607 KASSERT(len == ETHER_ADDR_LEN); 608 sc->sc_macstnaddr2 = 609 (mac_addr[1] << 24) 610 | (mac_addr[0] << 16); 611 sc->sc_macstnaddr1 = 612 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 613 | (mac_addr[4] << 16) 614 | (mac_addr[3] << 8) 615 | (mac_addr[2] << 0); 616 #if 0 617 aprint_error(": mac-address unknown\n"); 618 return; 619 #endif 620 } 621 622 char enaddr[ETHER_ADDR_LEN] = { 623 [0] = sc->sc_macstnaddr2 >> 16, 624 [1] = sc->sc_macstnaddr2 >> 24, 625 [2] = sc->sc_macstnaddr1 >> 0, 626 [3] = sc->sc_macstnaddr1 >> 8, 627 [4] = sc->sc_macstnaddr1 >> 16, 628 [5] = sc->sc_macstnaddr1 >> 24, 629 }; 630 631 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 632 if (error) { 633 aprint_error(": failed to init rxq: %d\n", error); 634 return; 635 } 636 637 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 638 if (error) { 639 aprint_error(": failed to init txq: %d\n", error); 640 return; 641 } 642 643 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 644 ETSEC_MAXRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 645 if (error) { 646 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 647 return; 648 } 649 650 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 651 ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 652 if (error) { 653 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 654 return; 655 } 656 657 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 658 pq3etsec_tx_intr, sc); 659 if (sc->sc_tx_ih == NULL) { 660 aprint_error(": failed to establish tx interrupt: %d\n", 661 cnl->cnl_intrs[0]); 662 return; 663 } 664 665 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 666 pq3etsec_rx_intr, sc); 667 if (sc->sc_rx_ih == NULL) { 668 aprint_error(": failed to establish rx interrupt: %d\n", 669 cnl->cnl_intrs[1]); 670 return; 671 } 672 673 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 674 pq3etsec_error_intr, sc); 675 if (sc->sc_error_ih == NULL) { 676 aprint_error(": failed to establish error interrupt: %d\n", 677 cnl->cnl_intrs[2]); 678 return; 679 } 680 681 sc->sc_soft_ih = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 682 pq3etsec_soft_intr, sc); 683 if (sc->sc_soft_ih == NULL) { 684 aprint_error(": failed to establish soft interrupt\n"); 685 return; 686 } 687 688 /* 689 * If there was no MDIO 690 */ 691 if (mdio == CPUNODECF_MDIO_DEFAULT) { 692 aprint_normal("\n"); 693 cfdata_t mdio_cf = config_search_ia(pq3mdio_find, self, NULL, cna); 694 if (mdio_cf != NULL) { 695 sc->sc_mdio_dev = config_attach(self, mdio_cf, cna, NULL); 696 } 697 } else { 698 sc->sc_mdio_dev = device_find_by_driver_unit("mdio", mdio); 699 if (sc->sc_mdio_dev == NULL) { 700 aprint_error(": failed to locate mdio device\n"); 701 return; 702 } 703 aprint_normal("\n"); 704 } 705 706 etsec_write(sc, ATTR, ATTR_DEFAULT); 707 etsec_write(sc, ATTRELI, ATTRELI_DEFAULT); 708 709 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 710 711 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 712 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 713 714 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 715 ether_sprintf(enaddr)); 716 717 const char * const xname = device_xname(sc->sc_dev); 718 struct ethercom * const ec = &sc->sc_ec; 719 struct ifnet * const ifp = &ec->ec_if; 720 721 ec->ec_mii = &sc->sc_mii; 722 723 sc->sc_mii.mii_ifp = ifp; 724 sc->sc_mii.mii_readreg = pq3mdio_mii_readreg; 725 sc->sc_mii.mii_writereg = pq3mdio_mii_writereg; 726 sc->sc_mii.mii_statchg = pq3etsec_mii_statchg; 727 728 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 729 ether_mediastatus); 730 731 if (sc->sc_mdio_dev != NULL && sc->sc_phy_addr < 32) { 732 mii_attach(sc->sc_mdio_dev, &sc->sc_mii, 0xffffffff, 733 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 734 735 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 736 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 737 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 738 } else { 739 callout_schedule(&sc->sc_mii_callout, hz); 740 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 741 } 742 } else { 743 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 744 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX); 745 } 746 747 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 748 | ETHERCAP_JUMBO_MTU; 749 750 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 751 ifp->if_softc = sc; 752 ifp->if_capabilities = IFCAP_ETSEC; 753 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 754 ifp->if_ioctl = pq3etsec_ifioctl; 755 ifp->if_start = pq3etsec_ifstart; 756 ifp->if_watchdog = pq3etsec_ifwatchdog; 757 ifp->if_init = pq3etsec_ifinit; 758 ifp->if_stop = pq3etsec_ifstop; 759 IFQ_SET_READY(&ifp->if_snd); 760 761 pq3etsec_ifstop(ifp, true); 762 763 /* 764 * Attach the interface. 765 */ 766 if_attach(ifp); 767 ether_ifattach(ifp, enaddr); 768 769 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 770 NULL, xname, "rx stall"); 771 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 772 NULL, xname, "tx stall"); 773 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 774 NULL, xname, "tx intr"); 775 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 776 NULL, xname, "rx intr"); 777 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 778 NULL, xname, "error intr"); 779 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 780 NULL, xname, "soft intr"); 781 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 782 NULL, xname, "tx pause"); 783 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 784 NULL, xname, "rx pause"); 785 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 786 NULL, xname, "mii ticks"); 787 } 788 789 static uint64_t 790 pq3etsec_macaddr_create(const uint8_t *lladdr) 791 { 792 uint64_t macaddr = 0; 793 794 lladdr += ETHER_ADDR_LEN; 795 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 796 macaddr = (macaddr << 8) | *--lladdr; 797 } 798 return macaddr << 16; 799 } 800 801 static int 802 pq3etsec_ifinit(struct ifnet *ifp) 803 { 804 struct pq3etsec_softc * const sc = ifp->if_softc; 805 int error = 0; 806 807 sc->sc_maxfrm = max(ifp->if_mtu + 32, MCLBYTES); 808 if (ifp->if_mtu > ETHERMTU_JUMBO) 809 return error; 810 811 KASSERT(ifp->if_flags & IFF_UP); 812 813 /* 814 * Stop the interface (steps 1 to 4 in the Soft Reset and 815 * Reconfigurating Procedure. 816 */ 817 pq3etsec_ifstop(ifp, 0); 818 819 /* 820 * If our frame size has changed (or it's our first time through) 821 * destroy the existing transmit mapcache. 822 */ 823 if (sc->sc_tx_mapcache != NULL 824 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 825 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 826 sc->sc_tx_mapcache = NULL; 827 } 828 829 if (sc->sc_tx_mapcache == NULL) { 830 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 831 ETSEC_MAXTXMBUFS, sc->sc_maxfrm, ETSEC_NTXSEGS); 832 if (error) 833 return error; 834 } 835 836 sc->sc_ev_mii_ticks.ev_count++; 837 mii_tick(&sc->sc_mii); 838 839 if (ifp->if_flags & IFF_PROMISC) { 840 sc->sc_rctrl |= RCTRL_PROM; 841 } else { 842 sc->sc_rctrl &= ~RCTRL_PROM; 843 } 844 845 uint32_t rctrl_prsdep = 0; 846 sc->sc_rctrl &= ~(RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP); 847 if (VLAN_ATTACHED(&sc->sc_ec)) { 848 sc->sc_rctrl |= RCTRL_VLEX; 849 rctrl_prsdep = RCTRL_PRSDEP_L2; 850 } 851 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 852 sc->sc_rctrl |= RCTRL_IPCSEN; 853 rctrl_prsdep = RCTRL_PRSDEP_L3; 854 } 855 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 856 sc->sc_rctrl |= RCTRL_TUCSEN; 857 rctrl_prsdep = RCTRL_PRSDEP_L4; 858 } 859 sc->sc_rctrl |= rctrl_prsdep; 860 #if 0 861 if (sc->sc_rctrl & (RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP)) 862 aprint_normal_dev(sc->sc_dev, 863 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 864 sc->sc_rctrl, 865 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 866 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 867 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 868 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 869 #endif 870 871 sc->sc_tctrl &= ~(TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS); 872 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 873 sc->sc_tctrl |= TCTRL_VLINS; 874 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 875 sc->sc_tctrl |= TCTRL_IPCSEN; 876 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 877 sc->sc_tctrl |= TCTRL_TUCSEN; 878 #if 0 879 if (sc->sc_tctrl & (TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS)) 880 aprint_normal_dev(sc->sc_dev, 881 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 882 sc->sc_tctrl, 883 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 884 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 885 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 886 #endif 887 888 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN|MACCFG1_RX_EN); 889 890 const uint64_t macstnaddr = 891 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 892 893 sc->sc_imask = IEVENT_DPE; 894 895 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 896 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 897 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 898 899 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 900 pq3etsec_txq_reset(sc, &sc->sc_txq); 901 902 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 903 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 904 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 905 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 906 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 907 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 908 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 909 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 910 911 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 912 pq3etsec_mc_setup(sc); 913 914 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 915 etsec_write(sc, MRBLR, MCLBYTES); 916 917 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 918 sc->sc_dmactrl |= DMACTRL_DEFAULT; 919 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 920 921 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 922 etsec_write(sc, TQUEUE, TQUEUE_EN0); 923 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE|IEVENT_TXC; 924 925 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 926 927 /* 12. Enable receive queues in RQUEUE, */ 928 etsec_write(sc, RQUEUE, RQUEUE_EN0|RQUEUE_EX0); 929 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY|IEVENT_RXC; 930 931 /* and optionally set TOE functionality in RCTRL. */ 932 etsec_write(sc, RCTRL, sc->sc_rctrl); 933 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 934 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 935 sc->sc_rx_adjlen += sizeof(struct rxfcb); 936 937 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 938 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 939 940 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 941 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 942 943 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 944 sc->sc_dmactrl &= ~(DMACTRL_GRS|DMACTRL_GTS); 945 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 946 947 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 948 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 949 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 950 951 sc->sc_soft_flags = 0; 952 953 etsec_write(sc, IMASK, sc->sc_imask); 954 955 ifp->if_flags |= IFF_RUNNING; 956 957 return error; 958 } 959 960 static void 961 pq3etsec_ifstop(struct ifnet *ifp, int disable) 962 { 963 struct pq3etsec_softc * const sc = ifp->if_softc; 964 965 KASSERT(!cpu_intr_p()); 966 const uint32_t imask_gsc_mask = IEVENT_GTSC|IEVENT_GRSC; 967 /* 968 * Clear the GTSC and GRSC from the interrupt mask until 969 * we are ready for them. Then clear them from IEVENT, 970 * request the graceful shutdown, and then enable the 971 * GTSC and GRSC bits in the mask. This should cause the 972 * error interrupt to fire which will issue a wakeup to 973 * allow us to resume. 974 */ 975 976 /* 977 * 1. Set GRS/GTS bits in DMACTRL register 978 */ 979 sc->sc_dmactrl |= DMACTRL_GRS|DMACTRL_GTS; 980 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 981 etsec_write(sc, IEVENT, imask_gsc_mask); 982 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 983 984 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN|MACCFG1_RX_EN)) { 985 /* 986 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 987 */ 988 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 989 990 u_int timo = 1000; 991 uint32_t ievent = etsec_read(sc, IEVENT); 992 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 993 if (--timo == 0) { 994 aprint_error_dev(sc->sc_dev, 995 "WARNING: " 996 "request to stop failed (IEVENT=%#x)\n", 997 ievent); 998 break; 999 } 1000 delay(10); 1001 ievent = etsec_read(sc, IEVENT); 1002 } 1003 } 1004 1005 /* 1006 * Now reset the controller. 1007 * 1008 * 3. Set SOFT_RESET bit in MACCFG1 register 1009 * 4. Clear SOFT_RESET bit in MACCFG1 register 1010 */ 1011 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 1012 etsec_write(sc, MACCFG1, 0); 1013 etsec_write(sc, IMASK, 0); 1014 etsec_write(sc, IEVENT, ~0); 1015 sc->sc_imask = 0; 1016 ifp->if_flags &= ~IFF_RUNNING; 1017 1018 uint32_t tbipa = etsec_read(sc, TBIPA); 1019 if (tbipa == sc->sc_phy_addr) { 1020 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 1021 etsec_write(sc, TBIPA, 0x1f); 1022 } 1023 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 1024 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 1025 etsec_write(sc, MIIMCFG, miimcfg); 1026 1027 /* 1028 * Let's consume any remaing transmitted packets. And if we are 1029 * disabling the interface, purge ourselves of any untransmitted 1030 * packets. But don't consume any received packets, just drop them. 1031 * If we aren't disabling the interface, save the mbufs in the 1032 * receive queue for reuse. 1033 */ 1034 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 1035 pq3etsec_txq_consume(sc, &sc->sc_txq); 1036 if (disable) { 1037 pq3etsec_txq_purge(sc, &sc->sc_txq); 1038 IF_PURGE(&ifp->if_snd); 1039 } 1040 } 1041 1042 static void 1043 pq3etsec_ifwatchdog(struct ifnet *ifp) 1044 { 1045 } 1046 1047 static void 1048 pq3etsec_mc_setup( 1049 struct pq3etsec_softc *sc) 1050 { 1051 struct ethercom * const ec = &sc->sc_ec; 1052 struct ifnet * const ifp = &sc->sc_if; 1053 struct ether_multi *enm; 1054 struct ether_multistep step; 1055 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 1056 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 1057 1058 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 1059 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1060 1061 ifp->if_flags &= ~IFF_ALLMULTI; 1062 1063 ETHER_FIRST_MULTI(step, ec, enm); 1064 for (u_int i = 0; enm != NULL; ) { 1065 const char *addr = enm->enm_addrlo; 1066 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1067 ifp->if_flags |= IFF_ALLMULTI; 1068 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 1069 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1070 break; 1071 } 1072 if ((sc->sc_rctrl & RCTRL_EMEN) 1073 && i < __arraycount(sc->sc_macaddrs)) { 1074 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 1075 } else { 1076 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1077 #if 0 1078 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 1079 ether_sprintf(addr), crc, 1080 crc >> crc_shift, 1081 crc >> (crc_shift + 5), 1082 (crc >> crc_shift) & 31, 1083 1 << (((crc >> crc_shift) & 31) ^ 31)); 1084 #endif 1085 /* 1086 * The documentation doesn't completely follow PowerPC 1087 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 1088 * is 0x7fa32d9b. By empirical testing, the 1089 * corresponding hash bit is word 3, bit 31 (ppc bit 1090 * order). Since 3 << 31 | 31 is 0x7f, we deduce 1091 * H[0:2] selects the register while H[3:7] selects 1092 * the bit (ppc bit order). 1093 */ 1094 crc >>= crc_shift; 1095 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 1096 } 1097 ETHER_NEXT_MULTI(step, enm); 1098 } 1099 for (u_int i = 0; i < 8; i++) { 1100 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 1101 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 1102 #if 0 1103 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 1104 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 1105 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 1106 i, GADDR(i), etsec_read(sc, GADDR(i))); 1107 #endif 1108 } 1109 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 1110 uint64_t macaddr = sc->sc_macaddrs[i]; 1111 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 1112 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 1113 #if 0 1114 if (macaddr) 1115 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 1116 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1117 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1118 #endif 1119 } 1120 } 1121 1122 static int 1123 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1124 { 1125 struct pq3etsec_softc *sc = ifp->if_softc; 1126 struct ifreq * const ifr = data; 1127 const int s = splnet(); 1128 int error; 1129 1130 switch (cmd) { 1131 case SIOCSIFMEDIA: 1132 case SIOCGIFMEDIA: 1133 /* Flow control requires full-duplex mode. */ 1134 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1135 (ifr->ifr_media & IFM_FDX) == 0) 1136 ifr->ifr_media &= ~IFM_ETH_FMASK; 1137 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1138 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1139 /* We can do both TXPAUSE and RXPAUSE. */ 1140 ifr->ifr_media |= 1141 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1142 } 1143 } 1144 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1145 break; 1146 1147 default: 1148 error = ether_ioctl(ifp, cmd, data); 1149 if (error != ENETRESET) 1150 break; 1151 1152 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1153 error = 0; 1154 if (ifp->if_flags & IFF_RUNNING) 1155 pq3etsec_mc_setup(sc); 1156 break; 1157 } 1158 error = pq3etsec_ifinit(ifp); 1159 break; 1160 } 1161 1162 splx(s); 1163 return error; 1164 } 1165 1166 static void 1167 pq3etsec_rxq_desc_presync( 1168 struct pq3etsec_softc *sc, 1169 struct pq3etsec_rxqueue *rxq, 1170 volatile struct rxbd *rxbd, 1171 size_t count) 1172 { 1173 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1174 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1175 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1176 } 1177 1178 static void 1179 pq3etsec_rxq_desc_postsync( 1180 struct pq3etsec_softc *sc, 1181 struct pq3etsec_rxqueue *rxq, 1182 volatile struct rxbd *rxbd, 1183 size_t count) 1184 { 1185 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1186 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1187 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1188 } 1189 1190 static void 1191 pq3etsec_txq_desc_presync( 1192 struct pq3etsec_softc *sc, 1193 struct pq3etsec_txqueue *txq, 1194 volatile struct txbd *txbd, 1195 size_t count) 1196 { 1197 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1198 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1199 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1200 } 1201 1202 static void 1203 pq3etsec_txq_desc_postsync( 1204 struct pq3etsec_softc *sc, 1205 struct pq3etsec_txqueue *txq, 1206 volatile struct txbd *txbd, 1207 size_t count) 1208 { 1209 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1210 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1211 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1212 } 1213 1214 static bus_dmamap_t 1215 pq3etsec_mapcache_get( 1216 struct pq3etsec_softc *sc, 1217 struct pq3etsec_mapcache *dmc) 1218 { 1219 KASSERT(dmc->dmc_nmaps > 0); 1220 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1221 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1222 } 1223 1224 static void 1225 pq3etsec_mapcache_put( 1226 struct pq3etsec_softc *sc, 1227 struct pq3etsec_mapcache *dmc, 1228 bus_dmamap_t map) 1229 { 1230 KASSERT(map != NULL); 1231 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1232 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1233 } 1234 1235 static void 1236 pq3etsec_mapcache_destroy( 1237 struct pq3etsec_softc *sc, 1238 struct pq3etsec_mapcache *dmc) 1239 { 1240 const size_t dmc_size = 1241 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1242 1243 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1244 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1245 } 1246 kmem_intr_free(dmc, dmc_size); 1247 } 1248 1249 static int 1250 pq3etsec_mapcache_create( 1251 struct pq3etsec_softc *sc, 1252 struct pq3etsec_mapcache **dmc_p, 1253 size_t maxmaps, 1254 size_t maxmapsize, 1255 size_t maxseg) 1256 { 1257 const size_t dmc_size = 1258 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1259 struct pq3etsec_mapcache * const dmc = 1260 kmem_intr_zalloc(dmc_size, KM_NOSLEEP); 1261 1262 dmc->dmc_maxmaps = maxmaps; 1263 dmc->dmc_nmaps = maxmaps; 1264 dmc->dmc_maxmapsize = maxmapsize; 1265 dmc->dmc_maxseg = maxseg; 1266 1267 for (u_int i = 0; i < maxmaps; i++) { 1268 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1269 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1270 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1271 if (error) { 1272 aprint_error_dev(sc->sc_dev, 1273 "failed to creat dma map cache " 1274 "entry %u of %zu: %d\n", 1275 i, maxmaps, error); 1276 while (i-- > 0) { 1277 bus_dmamap_destroy(sc->sc_dmat, 1278 dmc->dmc_maps[i]); 1279 } 1280 kmem_intr_free(dmc, dmc_size); 1281 return error; 1282 } 1283 KASSERT(dmc->dmc_maps[i] != NULL); 1284 } 1285 1286 *dmc_p = dmc; 1287 1288 return 0; 1289 } 1290 1291 #if 0 1292 static void 1293 pq3etsec_dmamem_free( 1294 bus_dma_tag_t dmat, 1295 size_t map_size, 1296 bus_dma_segment_t *seg, 1297 bus_dmamap_t map, 1298 void *kvap) 1299 { 1300 bus_dmamap_destroy(dmat, map); 1301 bus_dmamem_unmap(dmat, kvap, map_size); 1302 bus_dmamem_free(dmat, seg, 1); 1303 } 1304 #endif 1305 1306 static int 1307 pq3etsec_dmamem_alloc( 1308 bus_dma_tag_t dmat, 1309 size_t map_size, 1310 bus_dma_segment_t *seg, 1311 bus_dmamap_t *map, 1312 void **kvap) 1313 { 1314 int error; 1315 int nseg; 1316 1317 *kvap = NULL; 1318 *map = NULL; 1319 1320 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1321 seg, 1, &nseg, 0); 1322 if (error) 1323 return error; 1324 1325 KASSERT(nseg == 1); 1326 1327 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1328 BUS_DMA_COHERENT); 1329 if (error == 0) { 1330 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1331 map); 1332 if (error == 0) { 1333 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1334 NULL, 0); 1335 if (error == 0) 1336 return 0; 1337 bus_dmamap_destroy(dmat, *map); 1338 *map = NULL; 1339 } 1340 bus_dmamem_unmap(dmat, *kvap, map_size); 1341 *kvap = NULL; 1342 } 1343 bus_dmamem_free(dmat, seg, nseg); 1344 return 0; 1345 } 1346 1347 static struct mbuf * 1348 pq3etsec_rx_buf_alloc( 1349 struct pq3etsec_softc *sc) 1350 { 1351 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1352 if (m == NULL) { 1353 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1354 return NULL; 1355 } 1356 MCLGET(m, M_DONTWAIT); 1357 if ((m->m_flags & M_EXT) == 0) { 1358 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1359 m_freem(m); 1360 return NULL; 1361 } 1362 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1363 1364 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1365 if (map == NULL) { 1366 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1367 m_freem(m); 1368 return NULL; 1369 } 1370 M_SETCTX(m, map); 1371 m->m_len = m->m_pkthdr.len = MCLBYTES; 1372 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1373 BUS_DMA_READ|BUS_DMA_NOWAIT); 1374 if (error) { 1375 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1376 error); 1377 M_SETCTX(m, NULL); 1378 m_freem(m); 1379 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1380 return NULL; 1381 } 1382 KASSERT(map->dm_mapsize == MCLBYTES); 1383 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1384 BUS_DMASYNC_PREREAD); 1385 1386 return m; 1387 } 1388 1389 static void 1390 pq3etsec_rx_map_unload( 1391 struct pq3etsec_softc *sc, 1392 struct mbuf *m) 1393 { 1394 KASSERT(m); 1395 for (; m != NULL; m = m->m_next) { 1396 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1397 KASSERT(map); 1398 KASSERT(map->dm_mapsize == MCLBYTES); 1399 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1400 BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_unload(sc->sc_dmat, map); 1402 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1403 M_SETCTX(m, NULL); 1404 } 1405 } 1406 1407 static bool 1408 pq3etsec_rxq_produce( 1409 struct pq3etsec_softc *sc, 1410 struct pq3etsec_rxqueue *rxq) 1411 { 1412 volatile struct rxbd *producer = rxq->rxq_producer; 1413 #if 0 1414 size_t inuse = rxq->rxq_inuse; 1415 #endif 1416 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1417 struct mbuf *m; 1418 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1419 if (m == NULL) { 1420 m = pq3etsec_rx_buf_alloc(sc); 1421 if (m == NULL) { 1422 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1423 break; 1424 } 1425 } 1426 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1427 KASSERT(map); 1428 1429 #ifdef ETSEC_DEBUG 1430 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1431 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1432 #endif 1433 1434 /* rxbd_len is write-only by the ETSEC */ 1435 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1436 membar_producer(); 1437 producer->rxbd_flags |= RXBD_E; 1438 if (__predict_false(rxq->rxq_mhead == NULL)) { 1439 KASSERT(producer == rxq->rxq_consumer); 1440 rxq->rxq_mconsumer = m; 1441 } 1442 *rxq->rxq_mtail = m; 1443 rxq->rxq_mtail = &m->m_next; 1444 m->m_len = MCLBYTES; 1445 m->m_next = NULL; 1446 rxq->rxq_inuse++; 1447 if (++producer == rxq->rxq_last) { 1448 membar_producer(); 1449 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1450 rxq->rxq_last - rxq->rxq_producer); 1451 producer = rxq->rxq_producer = rxq->rxq_first; 1452 } 1453 } 1454 if (producer != rxq->rxq_producer) { 1455 membar_producer(); 1456 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1457 producer - rxq->rxq_producer); 1458 rxq->rxq_producer = producer; 1459 } 1460 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1461 if (qhlt) { 1462 KASSERT(qhlt & rxq->rxq_qmask); 1463 sc->sc_ev_rx_stall.ev_count++; 1464 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1465 } 1466 #if 0 1467 aprint_normal_dev(sc->sc_dev, 1468 "%s: buffers inuse went from %zu to %zu\n", 1469 __func__, inuse, rxq->rxq_inuse); 1470 #endif 1471 return true; 1472 } 1473 1474 static bool 1475 pq3etsec_rx_offload( 1476 struct pq3etsec_softc *sc, 1477 struct mbuf *m, 1478 const struct rxfcb *fcb) 1479 { 1480 if (fcb->rxfcb_flags & RXFCB_VLN) { 1481 VLAN_INPUT_TAG(&sc->sc_if, m, fcb->rxfcb_vlctl, 1482 m_freem(m); return false); 1483 } 1484 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1485 || (fcb->rxfcb_flags & (RXFCB_CIP|RXFCB_CTU)) == 0) 1486 return true; 1487 int csum_flags = 0; 1488 if ((fcb->rxfcb_flags & (RXFCB_IP6|RXFCB_CIP)) == RXFCB_CIP) { 1489 csum_flags |= M_CSUM_IPv4; 1490 if (fcb->rxfcb_flags & RXFCB_EIP) 1491 csum_flags |= M_CSUM_IPv4_BAD; 1492 } 1493 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1494 int ipv_flags; 1495 if (fcb->rxfcb_flags & RXFCB_IP6) 1496 ipv_flags = M_CSUM_TCPv6|M_CSUM_UDPv6; 1497 else 1498 ipv_flags = M_CSUM_TCPv4|M_CSUM_UDPv4; 1499 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1500 csum_flags |= (M_CSUM_TCPv4|M_CSUM_TCPv6) & ipv_flags; 1501 } else { 1502 csum_flags |= (M_CSUM_UDPv4|M_CSUM_UDPv6) & ipv_flags; 1503 } 1504 if (fcb->rxfcb_flags & RXFCB_ETU) 1505 csum_flags |= M_CSUM_TCP_UDP_BAD; 1506 } 1507 1508 m->m_pkthdr.csum_flags = csum_flags; 1509 return true; 1510 } 1511 1512 static void 1513 pq3etsec_rx_input( 1514 struct pq3etsec_softc *sc, 1515 struct mbuf *m, 1516 uint16_t rxbd_flags) 1517 { 1518 struct ifnet * const ifp = &sc->sc_if; 1519 1520 pq3etsec_rx_map_unload(sc, m); 1521 1522 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1523 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1524 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1525 return; 1526 } 1527 m_adj(m, sc->sc_rx_adjlen); 1528 1529 if (rxbd_flags & RXBD_M) 1530 m->m_flags |= M_PROMISC; 1531 if (rxbd_flags & RXBD_BC) 1532 m->m_flags |= M_BCAST; 1533 if (rxbd_flags & RXBD_MC) 1534 m->m_flags |= M_MCAST; 1535 m->m_flags |= M_HASFCS; 1536 m->m_pkthdr.rcvif = &sc->sc_if; 1537 1538 ifp->if_ipackets++; 1539 ifp->if_ibytes += m->m_pkthdr.len; 1540 1541 /* 1542 * Let's give it to the network subsystm to deal with. 1543 */ 1544 int s = splnet(); 1545 bpf_mtap(ifp, m); 1546 (*ifp->if_input)(ifp, m); 1547 splx(s); 1548 } 1549 1550 static void 1551 pq3etsec_rxq_consume( 1552 struct pq3etsec_softc *sc, 1553 struct pq3etsec_rxqueue *rxq) 1554 { 1555 struct ifnet * const ifp = &sc->sc_if; 1556 volatile struct rxbd *consumer = rxq->rxq_consumer; 1557 size_t rxconsumed = 0; 1558 1559 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1560 1561 for (;;) { 1562 if (consumer == rxq->rxq_producer) { 1563 rxq->rxq_consumer = consumer; 1564 rxq->rxq_inuse -= rxconsumed; 1565 KASSERT(rxq->rxq_inuse == 0); 1566 return; 1567 } 1568 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1569 const uint16_t rxbd_flags = consumer->rxbd_flags; 1570 if (rxbd_flags & RXBD_E) { 1571 rxq->rxq_consumer = consumer; 1572 rxq->rxq_inuse -= rxconsumed; 1573 return; 1574 } 1575 KASSERT(rxq->rxq_mconsumer != NULL); 1576 #ifdef ETSEC_DEBUG 1577 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1578 #endif 1579 #if 0 1580 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1581 __func__, 1582 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1583 mtod(rxq->rxq_mconsumer, int *)[0], 1584 mtod(rxq->rxq_mconsumer, int *)[1], 1585 mtod(rxq->rxq_mconsumer, int *)[2], 1586 mtod(rxq->rxq_mconsumer, int *)[3]); 1587 #endif 1588 /* 1589 * We own this packet again. Clear all flags except wrap. 1590 */ 1591 rxconsumed++; 1592 consumer->rxbd_flags = rxbd_flags & (RXBD_W|RXBD_I); 1593 1594 /* 1595 * If this descriptor has the LAST bit set and no errors, 1596 * it's a valid input packet. 1597 */ 1598 if ((rxbd_flags & (RXBD_L|RXBD_ERRORS)) == RXBD_L) { 1599 size_t rxbd_len = consumer->rxbd_len; 1600 struct mbuf *m = rxq->rxq_mhead; 1601 struct mbuf *m_last = rxq->rxq_mconsumer; 1602 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1603 rxq->rxq_mtail = &rxq->rxq_mhead; 1604 rxq->rxq_mconsumer = rxq->rxq_mhead; 1605 m_last->m_next = NULL; 1606 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1607 m->m_pkthdr.len = rxbd_len; 1608 pq3etsec_rx_input(sc, m, rxbd_flags); 1609 } else if (rxbd_flags & RXBD_L) { 1610 KASSERT(rxbd_flags & RXBD_ERRORS); 1611 struct mbuf *m; 1612 /* 1613 * We encountered an error, take the mbufs and add 1614 * then to the rx bufcache so we can reuse them. 1615 */ 1616 ifp->if_ierrors++; 1617 for (m = rxq->rxq_mhead; 1618 m != rxq->rxq_mconsumer; 1619 m = m->m_next) { 1620 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1621 } 1622 m = rxq->rxq_mconsumer; 1623 if ((rxq->rxq_mhead = m->m_next) == NULL) 1624 rxq->rxq_mtail = &rxq->rxq_mhead; 1625 rxq->rxq_mconsumer = m->m_next; 1626 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1627 } else { 1628 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1629 } 1630 #ifdef ETSEC_DEBUG 1631 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1632 #endif 1633 1634 /* 1635 * Wrap at the last entry! 1636 */ 1637 if (rxbd_flags & RXBD_W) { 1638 KASSERT(consumer + 1 == rxq->rxq_last); 1639 consumer = rxq->rxq_first; 1640 } else { 1641 consumer++; 1642 } 1643 #ifdef ETSEC_DEBUG 1644 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1645 #endif 1646 } 1647 } 1648 1649 static void 1650 pq3etsec_rxq_purge( 1651 struct pq3etsec_softc *sc, 1652 struct pq3etsec_rxqueue *rxq, 1653 bool discard) 1654 { 1655 struct mbuf *m; 1656 1657 if ((m = rxq->rxq_mhead) != NULL) { 1658 #ifdef ETSEC_DEBUG 1659 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1660 #endif 1661 1662 if (discard) { 1663 pq3etsec_rx_map_unload(sc, m); 1664 m_freem(m); 1665 } else { 1666 while (m != NULL) { 1667 struct mbuf *m0 = m->m_next; 1668 m->m_next = NULL; 1669 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1670 m = m0; 1671 } 1672 } 1673 1674 } 1675 1676 rxq->rxq_mconsumer = NULL; 1677 rxq->rxq_mhead = NULL; 1678 rxq->rxq_mtail = &rxq->rxq_mhead; 1679 rxq->rxq_inuse = 0; 1680 } 1681 1682 static void 1683 pq3etsec_rxq_reset( 1684 struct pq3etsec_softc *sc, 1685 struct pq3etsec_rxqueue *rxq) 1686 { 1687 /* 1688 * sync all the descriptors 1689 */ 1690 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1691 rxq->rxq_last - rxq->rxq_first); 1692 1693 /* 1694 * Make sure we own all descriptors in the ring. 1695 */ 1696 volatile struct rxbd *rxbd; 1697 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1698 rxbd->rxbd_flags = RXBD_I; 1699 } 1700 1701 /* 1702 * Last descriptor has the wrap flag. 1703 */ 1704 rxbd->rxbd_flags = RXBD_W|RXBD_I; 1705 1706 /* 1707 * Reset the producer consumer indexes. 1708 */ 1709 rxq->rxq_consumer = rxq->rxq_first; 1710 rxq->rxq_producer = rxq->rxq_first; 1711 rxq->rxq_inuse = 0; 1712 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1713 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1714 1715 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY; 1716 1717 /* 1718 * Restart the transmit at the first descriptor 1719 */ 1720 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1721 } 1722 1723 static int 1724 pq3etsec_rxq_attach( 1725 struct pq3etsec_softc *sc, 1726 struct pq3etsec_rxqueue *rxq, 1727 u_int qno) 1728 { 1729 size_t map_size = PAGE_SIZE; 1730 size_t desc_count = map_size / sizeof(struct rxbd); 1731 int error; 1732 void *descs; 1733 1734 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1735 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1736 if (error) 1737 return error; 1738 1739 memset(descs, 0, map_size); 1740 rxq->rxq_first = descs; 1741 rxq->rxq_last = rxq->rxq_first + desc_count; 1742 rxq->rxq_consumer = descs; 1743 rxq->rxq_producer = descs; 1744 1745 pq3etsec_rxq_purge(sc, rxq, true); 1746 pq3etsec_rxq_reset(sc, rxq); 1747 1748 rxq->rxq_reg_rbase = RBASEn(qno); 1749 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1750 1751 return 0; 1752 } 1753 1754 static bool 1755 pq3etsec_txq_active_p( 1756 struct pq3etsec_softc * const sc, 1757 struct pq3etsec_txqueue *txq) 1758 { 1759 return !IF_IS_EMPTY(&txq->txq_mbufs); 1760 } 1761 1762 static bool 1763 pq3etsec_txq_fillable_p( 1764 struct pq3etsec_softc * const sc, 1765 struct pq3etsec_txqueue *txq) 1766 { 1767 return txq->txq_free >= txq->txq_threshold; 1768 } 1769 1770 static int 1771 pq3etsec_txq_attach( 1772 struct pq3etsec_softc *sc, 1773 struct pq3etsec_txqueue *txq, 1774 u_int qno) 1775 { 1776 size_t map_size = PAGE_SIZE; 1777 size_t desc_count = map_size / sizeof(struct txbd); 1778 int error; 1779 void *descs; 1780 1781 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1782 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1783 if (error) 1784 return error; 1785 1786 memset(descs, 0, map_size); 1787 txq->txq_first = descs; 1788 txq->txq_last = txq->txq_first + desc_count; 1789 txq->txq_consumer = descs; 1790 txq->txq_producer = descs; 1791 1792 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1793 1794 txq->txq_reg_tbase = TBASEn(qno); 1795 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1796 1797 pq3etsec_txq_reset(sc, txq); 1798 1799 return 0; 1800 } 1801 1802 static int 1803 pq3etsec_txq_map_load( 1804 struct pq3etsec_softc *sc, 1805 struct pq3etsec_txqueue *txq, 1806 struct mbuf *m) 1807 { 1808 bus_dmamap_t map; 1809 int error; 1810 1811 map = M_GETCTX(m, bus_dmamap_t); 1812 if (map != NULL) 1813 return 0; 1814 1815 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1816 if (map == NULL) 1817 return ENOMEM; 1818 1819 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1820 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1821 if (error) 1822 return error; 1823 1824 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1825 BUS_DMASYNC_PREWRITE); 1826 M_SETCTX(m, map); 1827 return 0; 1828 } 1829 1830 static void 1831 pq3etsec_txq_map_unload( 1832 struct pq3etsec_softc *sc, 1833 struct pq3etsec_txqueue *txq, 1834 struct mbuf *m) 1835 { 1836 KASSERT(m); 1837 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1838 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1839 BUS_DMASYNC_POSTWRITE); 1840 bus_dmamap_unload(sc->sc_dmat, map); 1841 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1842 } 1843 1844 static bool 1845 pq3etsec_txq_produce( 1846 struct pq3etsec_softc *sc, 1847 struct pq3etsec_txqueue *txq, 1848 struct mbuf *m) 1849 { 1850 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1851 1852 if (map->dm_nsegs > txq->txq_free) 1853 return false; 1854 1855 /* 1856 * TCP Offload flag must be set in the first descriptor. 1857 */ 1858 volatile struct txbd *producer = txq->txq_producer; 1859 uint16_t last_flags = TXBD_L; 1860 uint16_t first_flags = TXBD_R 1861 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1862 1863 /* 1864 * If we've produced enough descriptors without consuming any 1865 * we need to ask for an interrupt to reclaim some. 1866 */ 1867 txq->txq_lastintr += map->dm_nsegs; 1868 if (txq->txq_lastintr >= txq->txq_threshold 1869 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1870 txq->txq_lastintr = 0; 1871 last_flags |= TXBD_I; 1872 } 1873 1874 #ifdef ETSEC_DEBUG 1875 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1876 #endif 1877 KASSERT(producer != txq->txq_last); 1878 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1879 producer->txbd_len = map->dm_segs[0].ds_len; 1880 1881 if (map->dm_nsegs > 1) { 1882 volatile struct txbd *start = producer + 1; 1883 size_t count = map->dm_nsegs - 1; 1884 for (u_int i = 1; i < map->dm_nsegs; i++) { 1885 if (__predict_false(++producer == txq->txq_last)) { 1886 producer = txq->txq_first; 1887 if (start < txq->txq_last) { 1888 pq3etsec_txq_desc_presync(sc, txq, 1889 start, txq->txq_last - start); 1890 count -= txq->txq_last - start; 1891 } 1892 start = txq->txq_first; 1893 } 1894 #ifdef ETSEC_DEBUG 1895 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1896 #endif 1897 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1898 producer->txbd_len = map->dm_segs[i].ds_len; 1899 producer->txbd_flags = TXBD_R 1900 | (producer->txbd_flags & TXBD_W) 1901 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1902 #if 0 1903 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1904 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1905 #endif 1906 } 1907 pq3etsec_txq_desc_presync(sc, txq, start, count); 1908 } else { 1909 first_flags |= last_flags; 1910 } 1911 1912 membar_producer(); 1913 txq->txq_producer->txbd_flags = 1914 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1915 #if 0 1916 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1917 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1918 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1919 #endif 1920 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1921 1922 /* 1923 * Reduce free count by the number of segments we consumed. 1924 */ 1925 txq->txq_free -= map->dm_nsegs; 1926 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 1927 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 1928 KASSERT(producer->txbd_flags & TXBD_L); 1929 #ifdef ETSEC_DEBUG 1930 txq->txq_lmbufs[producer - txq->txq_first] = m; 1931 #endif 1932 1933 #if 0 1934 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 1935 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 1936 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 1937 #endif 1938 1939 if (++producer == txq->txq_last) 1940 txq->txq_producer = txq->txq_first; 1941 else 1942 txq->txq_producer = producer; 1943 IF_ENQUEUE(&txq->txq_mbufs, m); 1944 1945 /* 1946 * Restart the transmitter. 1947 */ 1948 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 1949 1950 return true; 1951 } 1952 1953 static void 1954 pq3etsec_tx_offload( 1955 struct pq3etsec_softc *sc, 1956 struct pq3etsec_txqueue *txq, 1957 struct mbuf **mp) 1958 { 1959 struct mbuf *m = *mp; 1960 u_int csum_flags = m->m_pkthdr.csum_flags; 1961 struct m_tag *vtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m); 1962 1963 KASSERT(m->m_flags & M_PKTHDR); 1964 1965 /* 1966 * Let see if we are doing any offload first. 1967 */ 1968 if (csum_flags == 0 && vtag == 0) { 1969 m->m_flags &= ~M_HASFCB; 1970 return; 1971 } 1972 1973 uint16_t flags = 0; 1974 if (csum_flags & M_CSUM_IP) { 1975 flags |= TXFCB_IP 1976 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 1977 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 1978 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 1979 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 1980 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 1981 } 1982 if (vtag) { 1983 flags |= TXFCB_VLN; 1984 } 1985 if (flags == 0) { 1986 m->m_flags &= ~M_HASFCB; 1987 return; 1988 } 1989 1990 struct txfcb fcb; 1991 fcb.txfcb_flags = flags; 1992 if (csum_flags & M_CSUM_IPv4) 1993 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 1994 else 1995 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 1996 fcb.txfcb_l3os = ETHER_HDR_LEN; 1997 fcb.txfcb_phcs = 0; 1998 fcb.txfcb_vlctl = vtag ? VLAN_TAG_VALUE(vtag) & 0xffff : 0; 1999 2000 #if 0 2001 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 2002 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 2003 fcb.txfcb_phcs, fcb.txfcb_vlctl); 2004 #endif 2005 2006 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 2007 m->m_data -= sizeof(fcb); 2008 m->m_len += sizeof(fcb); 2009 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 2010 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 2011 m->m_data = m->m_pktdat; 2012 m->m_len += sizeof(fcb); 2013 } else { 2014 struct mbuf *mn; 2015 MGET(mn, M_DONTWAIT, m->m_type); 2016 if (mn == NULL) { 2017 if (csum_flags & M_CSUM_IP4) { 2018 #ifdef INET 2019 ip_undefer_csum(m, ETHER_HDR_LEN, 2020 csum_flags & M_CSUM_IP4); 2021 #else 2022 panic("%s: impossible M_CSUM flags %#x", 2023 device_xname(sc->sc_dev), csum_flags); 2024 #endif 2025 } else if (csum_flags & M_CSUM_IP6) { 2026 #ifdef INET6 2027 ip6_undefer_csum(m, ETHER_HDR_LEN, 2028 csum_flags & M_CSUM_IP6); 2029 #else 2030 panic("%s: impossible M_CSUM flags %#x", 2031 device_xname(sc->sc_dev), csum_flags); 2032 #endif 2033 } else if (vtag) { 2034 } 2035 2036 m->m_flags &= ~M_HASFCB; 2037 return; 2038 } 2039 2040 M_MOVE_PKTHDR(mn, m); 2041 mn->m_next = m; 2042 m = mn; 2043 MH_ALIGN(m, sizeof(fcb)); 2044 m->m_len = sizeof(fcb); 2045 *mp = m; 2046 } 2047 m->m_pkthdr.len += sizeof(fcb); 2048 m->m_flags |= M_HASFCB; 2049 *mtod(m, struct txfcb *) = fcb; 2050 return; 2051 } 2052 2053 static bool 2054 pq3etsec_txq_enqueue( 2055 struct pq3etsec_softc *sc, 2056 struct pq3etsec_txqueue *txq) 2057 { 2058 for (;;) { 2059 if (IF_QFULL(&txq->txq_mbufs)) 2060 return false; 2061 struct mbuf *m = txq->txq_next; 2062 if (m == NULL) { 2063 int s = splnet(); 2064 IF_DEQUEUE(&sc->sc_if.if_snd, m); 2065 splx(s); 2066 if (m == NULL) 2067 return true; 2068 M_SETCTX(m, NULL); 2069 pq3etsec_tx_offload(sc, txq, &m); 2070 } else { 2071 txq->txq_next = NULL; 2072 } 2073 int error = pq3etsec_txq_map_load(sc, txq, m); 2074 if (error) { 2075 aprint_error_dev(sc->sc_dev, 2076 "discarded packet due to " 2077 "dmamap load failure: %d\n", error); 2078 m_freem(m); 2079 continue; 2080 } 2081 KASSERT(txq->txq_next == NULL); 2082 if (!pq3etsec_txq_produce(sc, txq, m)) { 2083 txq->txq_next = m; 2084 return false; 2085 } 2086 KASSERT(txq->txq_next == NULL); 2087 } 2088 } 2089 2090 static bool 2091 pq3etsec_txq_consume( 2092 struct pq3etsec_softc *sc, 2093 struct pq3etsec_txqueue *txq) 2094 { 2095 struct ifnet * const ifp = &sc->sc_if; 2096 volatile struct txbd *consumer = txq->txq_consumer; 2097 size_t txfree = 0; 2098 2099 #if 0 2100 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 2101 #endif 2102 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 2103 2104 for (;;) { 2105 if (consumer == txq->txq_producer) { 2106 txq->txq_consumer = consumer; 2107 txq->txq_free += txfree; 2108 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2109 #if 0 2110 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2111 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2112 #endif 2113 KASSERT(txq->txq_lastintr == 0); 2114 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2115 return true; 2116 } 2117 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2118 const uint16_t txbd_flags = consumer->txbd_flags; 2119 if (txbd_flags & TXBD_R) { 2120 txq->txq_consumer = consumer; 2121 txq->txq_free += txfree; 2122 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2123 #if 0 2124 printf("%s: freed %zu descriptors\n", 2125 __func__, txfree); 2126 #endif 2127 return pq3etsec_txq_fillable_p(sc, txq); 2128 } 2129 2130 /* 2131 * If this is the last descriptor in the chain, get the 2132 * mbuf, free its dmamap, and free the mbuf chain itself. 2133 */ 2134 if (txbd_flags & TXBD_L) { 2135 struct mbuf *m; 2136 2137 IF_DEQUEUE(&txq->txq_mbufs, m); 2138 #ifdef ETSEC_DEBUG 2139 KASSERTMSG( 2140 m == txq->txq_lmbufs[consumer-txq->txq_first], 2141 "%s: %p [%u]: flags %#x m (%p) != %p (%p)", 2142 __func__, consumer, consumer - txq->txq_first, 2143 txbd_flags, m, 2144 &txq->txq_lmbufs[consumer-txq->txq_first], 2145 txq->txq_lmbufs[consumer-txq->txq_first]); 2146 #endif 2147 KASSERT(m); 2148 pq3etsec_txq_map_unload(sc, txq, m); 2149 #if 0 2150 printf("%s: mbuf %p: consumed a %u byte packet\n", 2151 __func__, m, m->m_pkthdr.len); 2152 #endif 2153 if (m->m_flags & M_HASFCB) 2154 m_adj(m, sizeof(struct txfcb)); 2155 ifp->if_opackets++; 2156 ifp->if_obytes += m->m_pkthdr.len; 2157 if (m->m_flags & M_MCAST) 2158 ifp->if_omcasts++; 2159 if (txbd_flags & TXBD_ERRORS) 2160 ifp->if_oerrors++; 2161 m_freem(m); 2162 #ifdef ETSEC_DEBUG 2163 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2164 #endif 2165 } else { 2166 #ifdef ETSEC_DEBUG 2167 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2168 #endif 2169 } 2170 2171 /* 2172 * We own this packet again. Clear all flags except wrap. 2173 */ 2174 txfree++; 2175 //consumer->txbd_flags = txbd_flags & TXBD_W; 2176 2177 /* 2178 * Wrap at the last entry! 2179 */ 2180 if (txbd_flags & TXBD_W) { 2181 KASSERT(consumer + 1 == txq->txq_last); 2182 consumer = txq->txq_first; 2183 } else { 2184 consumer++; 2185 KASSERT(consumer < txq->txq_last); 2186 } 2187 } 2188 } 2189 2190 static void 2191 pq3etsec_txq_purge( 2192 struct pq3etsec_softc *sc, 2193 struct pq3etsec_txqueue *txq) 2194 { 2195 struct mbuf *m; 2196 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2197 2198 for (;;) { 2199 IF_DEQUEUE(&txq->txq_mbufs, m); 2200 if (m == NULL) 2201 break; 2202 pq3etsec_txq_map_unload(sc, txq, m); 2203 m_freem(m); 2204 } 2205 if ((m = txq->txq_next) != NULL) { 2206 txq->txq_next = NULL; 2207 pq3etsec_txq_map_unload(sc, txq, m); 2208 m_freem(m); 2209 } 2210 #ifdef ETSEC_DEBUG 2211 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2212 #endif 2213 } 2214 2215 static void 2216 pq3etsec_txq_reset( 2217 struct pq3etsec_softc *sc, 2218 struct pq3etsec_txqueue *txq) 2219 { 2220 /* 2221 * sync all the descriptors 2222 */ 2223 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2224 txq->txq_last - txq->txq_first); 2225 2226 /* 2227 * Make sure we own all descriptors in the ring. 2228 */ 2229 volatile struct txbd *txbd; 2230 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2231 txbd->txbd_flags = 0; 2232 } 2233 2234 /* 2235 * Last descriptor has the wrap flag. 2236 */ 2237 txbd->txbd_flags = TXBD_W; 2238 2239 /* 2240 * Reset the producer consumer indexes. 2241 */ 2242 txq->txq_consumer = txq->txq_first; 2243 txq->txq_producer = txq->txq_first; 2244 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2245 txq->txq_threshold = txq->txq_free / 2; 2246 txq->txq_lastintr = 0; 2247 2248 /* 2249 * What do we want to get interrupted on? 2250 */ 2251 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE; 2252 2253 /* 2254 * Restart the transmit at the first descriptor 2255 */ 2256 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2257 } 2258 2259 static void 2260 pq3etsec_ifstart(struct ifnet *ifp) 2261 { 2262 struct pq3etsec_softc * const sc = ifp->if_softc; 2263 2264 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2265 softint_schedule(sc->sc_soft_ih); 2266 } 2267 2268 static void 2269 pq3etsec_tx_error( 2270 struct pq3etsec_softc * const sc) 2271 { 2272 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2273 2274 pq3etsec_txq_consume(sc, txq); 2275 2276 if (pq3etsec_txq_fillable_p(sc, txq)) 2277 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2278 if (sc->sc_txerrors & (IEVENT_LC|IEVENT_CRL|IEVENT_XFUN|IEVENT_BABT)) { 2279 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2280 } 2281 2282 if (pq3etsec_txq_active_p(sc, txq)) 2283 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2284 if (!pq3etsec_txq_enqueue(sc, txq)) { 2285 sc->sc_ev_tx_stall.ev_count++; 2286 sc->sc_if.if_flags |= IFF_OACTIVE; 2287 } 2288 2289 sc->sc_txerrors = 0; 2290 } 2291 2292 int 2293 pq3etsec_tx_intr(void *arg) 2294 { 2295 struct pq3etsec_softc * const sc = arg; 2296 2297 sc->sc_ev_tx_intr.ev_count++; 2298 2299 uint32_t ievent = etsec_read(sc, IEVENT); 2300 ievent &= IEVENT_TXF|IEVENT_TXB; 2301 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2302 2303 #if 0 2304 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2305 __func__, ievent, etsec_read(sc, IMASK)); 2306 #endif 2307 2308 if (ievent == 0) 2309 return 0; 2310 2311 sc->sc_imask &= ~(IEVENT_TXF|IEVENT_TXB); 2312 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2313 etsec_write(sc, IMASK, sc->sc_imask); 2314 softint_schedule(sc->sc_soft_ih); 2315 return 1; 2316 } 2317 2318 int 2319 pq3etsec_rx_intr(void *arg) 2320 { 2321 struct pq3etsec_softc * const sc = arg; 2322 2323 sc->sc_ev_rx_intr.ev_count++; 2324 2325 uint32_t ievent = etsec_read(sc, IEVENT); 2326 ievent &= IEVENT_RXF|IEVENT_RXB; 2327 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2328 if (ievent == 0) 2329 return 0; 2330 2331 #if 0 2332 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2333 #endif 2334 2335 sc->sc_imask &= ~(IEVENT_RXF|IEVENT_RXB); 2336 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2337 etsec_write(sc, IMASK, sc->sc_imask); 2338 softint_schedule(sc->sc_soft_ih); 2339 return 1; 2340 } 2341 2342 int 2343 pq3etsec_error_intr(void *arg) 2344 { 2345 struct pq3etsec_softc * const sc = arg; 2346 2347 sc->sc_ev_error_intr.ev_count++; 2348 2349 for (int rv = 0, soft_flags = 0;; rv = 1) { 2350 uint32_t ievent = etsec_read(sc, IEVENT); 2351 ievent &= ~(IEVENT_RXF|IEVENT_RXB|IEVENT_TXF|IEVENT_TXB); 2352 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2353 if (ievent == 0) { 2354 if (soft_flags) { 2355 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2356 softint_schedule(sc->sc_soft_ih); 2357 } 2358 return rv; 2359 } 2360 #if 0 2361 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2362 __func__, ievent, etsec_read(sc, IMASK)); 2363 #endif 2364 2365 if (ievent & (IEVENT_GRSC|IEVENT_GTSC)) { 2366 sc->sc_imask &= ~(IEVENT_GRSC|IEVENT_GTSC); 2367 etsec_write(sc, IMASK, sc->sc_imask); 2368 wakeup(sc); 2369 } 2370 if (ievent & (IEVENT_MMRD|IEVENT_MMWR)) { 2371 sc->sc_imask &= ~(IEVENT_MMRD|IEVENT_MMWR); 2372 etsec_write(sc, IMASK, sc->sc_imask); 2373 wakeup(&sc->sc_mii); 2374 } 2375 if (ievent & IEVENT_BSY) { 2376 soft_flags |= SOFT_RXBSY; 2377 sc->sc_imask &= ~IEVENT_BSY; 2378 etsec_write(sc, IMASK, sc->sc_imask); 2379 } 2380 if (ievent & IEVENT_TXE) { 2381 soft_flags |= SOFT_TXERROR; 2382 sc->sc_imask &= ~IEVENT_TXE; 2383 sc->sc_txerrors |= ievent; 2384 } 2385 if (ievent & IEVENT_TXC) { 2386 sc->sc_ev_tx_pause.ev_count++; 2387 } 2388 if (ievent & IEVENT_RXC) { 2389 sc->sc_ev_rx_pause.ev_count++; 2390 } 2391 if (ievent & IEVENT_DPE) { 2392 soft_flags |= SOFT_RESET; 2393 sc->sc_imask &= ~IEVENT_DPE; 2394 etsec_write(sc, IMASK, sc->sc_imask); 2395 } 2396 } 2397 } 2398 2399 void 2400 pq3etsec_soft_intr(void *arg) 2401 { 2402 struct pq3etsec_softc * const sc = arg; 2403 struct ifnet * const ifp = &sc->sc_if; 2404 2405 mutex_enter(sc->sc_lock); 2406 2407 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2408 2409 sc->sc_ev_soft_intr.ev_count++; 2410 2411 if (soft_flags & SOFT_RESET) { 2412 int s = splnet(); 2413 pq3etsec_ifinit(ifp); 2414 splx(s); 2415 soft_flags = 0; 2416 } 2417 2418 if (soft_flags & SOFT_RXBSY) { 2419 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2420 size_t threshold = 5 * rxq->rxq_threshold / 4; 2421 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2422 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2423 } else { 2424 sc->sc_imask |= IEVENT_BSY; 2425 } 2426 aprint_normal_dev(sc->sc_dev, 2427 "increasing receive buffers from %zu to %zu\n", 2428 rxq->rxq_threshold, threshold); 2429 rxq->rxq_threshold = threshold; 2430 } 2431 2432 if ((soft_flags & SOFT_TXINTR) 2433 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2434 /* 2435 * Let's do what we came here for. Consume transmitted 2436 * packets off the the transmit ring. 2437 */ 2438 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2439 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2440 sc->sc_ev_tx_stall.ev_count++; 2441 ifp->if_flags |= IFF_OACTIVE; 2442 } else { 2443 ifp->if_flags &= ~IFF_OACTIVE; 2444 } 2445 sc->sc_imask |= IEVENT_TXF; 2446 } 2447 2448 if (soft_flags & (SOFT_RXINTR|SOFT_RXBSY)) { 2449 /* 2450 * Let's consume 2451 */ 2452 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2453 sc->sc_imask |= IEVENT_RXF; 2454 } 2455 2456 if (soft_flags & SOFT_TXERROR) { 2457 pq3etsec_tx_error(sc); 2458 sc->sc_imask |= IEVENT_TXE; 2459 } 2460 2461 if (ifp->if_flags & IFF_RUNNING) { 2462 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2463 etsec_write(sc, IMASK, sc->sc_imask); 2464 } else { 2465 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2466 } 2467 2468 mutex_exit(sc->sc_lock); 2469 } 2470 2471 static void 2472 pq3etsec_mii_tick(void *arg) 2473 { 2474 struct pq3etsec_softc * const sc = arg; 2475 mutex_enter(sc->sc_lock); 2476 callout_ack(&sc->sc_mii_callout); 2477 sc->sc_ev_mii_ticks.ev_count++; 2478 #ifdef DEBUG 2479 uint64_t now = mftb(); 2480 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2481 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2482 __func__, now - sc->sc_mii_last_tick); 2483 callout_stop(&sc->sc_mii_callout); 2484 } 2485 #endif 2486 mii_tick(&sc->sc_mii); 2487 int s = splnet(); 2488 if (sc->sc_soft_flags & SOFT_RESET) 2489 softint_schedule(sc->sc_soft_ih); 2490 splx(s); 2491 callout_schedule(&sc->sc_mii_callout, hz); 2492 #ifdef DEBUG 2493 sc->sc_mii_last_tick = now; 2494 #endif 2495 mutex_exit(sc->sc_lock); 2496 } 2497
Indexes created Tue Sep 30 07:10:03 GMT 2025