pq3etsec.c revision 1.2.4.2
1 /* $NetBSD: pq3etsec.c,v 1.2.4.2 2011/03/05 20:51:34 rmind Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_inet.h" 38 39 #include <sys/cdefs.h> 40 41 #include <sys/param.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 #include <sys/mbuf.h> 45 #include <sys/ioctl.h> 46 #include <sys/intr.h> 47 #include <sys/bus.h> 48 #include <sys/kernel.h> 49 #include <sys/kmem.h> 50 #include <sys/proc.h> 51 #include <sys/atomic.h> 52 #include <sys/callout.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_ether.h> 57 #include <net/if_media.h> 58 59 #include <dev/mii/miivar.h> 60 61 #include "ioconf.h" 62 63 #include <net/bpf.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/ip.h> 69 #include <netinet/in_offload.h> 70 #endif /* INET */ 71 #ifdef INET6 72 #include <netinet6/in6.h> 73 #include <netinet/ip6.h> 74 #endif 75 #include <netinet6/in6_offload.h> 76 77 78 #include <powerpc/spr.h> 79 #include <powerpc/booke/spr.h> 80 81 #include <powerpc/booke/cpuvar.h> 82 #include <powerpc/booke/e500var.h> 83 #include <powerpc/booke/e500reg.h> 84 #include <powerpc/booke/etsecreg.h> 85 86 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 87 88 #define ETSEC_MAXTXMBUFS 30 89 #define ETSEC_NTXSEGS 30 90 #define ETSEC_MAXRXMBUFS 511 91 #define ETSEC_MINRXMBUFS 32 92 #define ETSEC_NRXSEGS 1 93 94 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 95 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx\ 96 |IFCAP_CSUM_UDPv4_Rx\ 97 |IFCAP_CSUM_TCPv6_Rx\ 98 |IFCAP_CSUM_UDPv6_Rx) 99 100 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 101 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx\ 102 |IFCAP_CSUM_UDPv4_Tx\ 103 |IFCAP_CSUM_TCPv6_Tx\ 104 |IFCAP_CSUM_UDPv6_Tx) 105 106 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN|IFCAP_RCTRL_TUCSEN\ 107 |IFCAP_TCTRL_IPCSEN|IFCAP_TCTRL_TUCSEN) 108 109 #define M_CSUM_IP (M_CSUM_CIP|M_CSUM_CTU) 110 #define M_CSUM_IP6 (M_CSUM_TCPv6|M_CSUM_UDPv6) 111 #define M_CSUM_TUP (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 112 #define M_CSUM_UDP (M_CSUM_UDPv4|M_CSUM_UDPv6) 113 #define M_CSUM_IP4 (M_CSUM_IPv4|M_CSUM_UDPv4|M_CSUM_TCPv4) 114 #define M_CSUM_CIP (M_CSUM_IPv4) 115 #define M_CSUM_CTU (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 116 117 struct pq3etsec_txqueue { 118 bus_dmamap_t txq_descmap; 119 volatile struct txbd *txq_consumer; 120 volatile struct txbd *txq_producer; 121 volatile struct txbd *txq_first; 122 volatile struct txbd *txq_last; 123 struct ifqueue txq_mbufs; 124 struct mbuf *txq_next; 125 #ifdef ETSEC_DEBUG 126 struct mbuf *txq_lmbufs[512]; 127 #endif 128 uint32_t txq_qmask; 129 uint32_t txq_free; 130 uint32_t txq_threshold; 131 uint32_t txq_lastintr; 132 bus_size_t txq_reg_tbase; 133 bus_dma_segment_t txq_descmap_seg; 134 }; 135 136 struct pq3etsec_rxqueue { 137 bus_dmamap_t rxq_descmap; 138 volatile struct rxbd *rxq_consumer; 139 volatile struct rxbd *rxq_producer; 140 volatile struct rxbd *rxq_first; 141 volatile struct rxbd *rxq_last; 142 struct mbuf *rxq_mhead; 143 struct mbuf **rxq_mtail; 144 struct mbuf *rxq_mconsumer; 145 #ifdef ETSEC_DEBUG 146 struct mbuf *rxq_mbufs[512]; 147 #endif 148 uint32_t rxq_qmask; 149 uint32_t rxq_inuse; 150 uint32_t rxq_threshold; 151 bus_size_t rxq_reg_rbase; 152 bus_size_t rxq_reg_rbptr; 153 bus_dma_segment_t rxq_descmap_seg; 154 }; 155 156 struct pq3etsec_mapcache { 157 u_int dmc_nmaps; 158 u_int dmc_maxseg; 159 u_int dmc_maxmaps; 160 u_int dmc_maxmapsize; 161 bus_dmamap_t dmc_maps[0]; 162 }; 163 164 struct pq3etsec_softc { 165 device_t sc_dev; 166 struct ethercom sc_ec; 167 #define sc_if sc_ec.ec_if 168 struct mii_data sc_mii; 169 bus_space_tag_t sc_bst; 170 bus_space_handle_t sc_bsh; 171 bus_dma_tag_t sc_dmat; 172 int sc_phy_addr; 173 prop_dictionary_t sc_intrmap; 174 uint32_t sc_intrmask; 175 176 uint32_t sc_soft_flags; 177 #define SOFT_RESET 0x0001 178 #define SOFT_RXINTR 0x0010 179 #define SOFT_RXBSY 0x0020 180 #define SOFT_TXINTR 0x0100 181 #define SOFT_TXERROR 0x0200 182 183 struct pq3etsec_txqueue sc_txq; 184 struct pq3etsec_rxqueue sc_rxq; 185 uint32_t sc_txerrors; 186 uint32_t sc_rxerrors; 187 188 size_t sc_rx_adjlen; 189 190 /* 191 * Copies of various ETSEC registers. 192 */ 193 uint32_t sc_imask; 194 uint32_t sc_maccfg1; 195 uint32_t sc_maccfg2; 196 uint32_t sc_maxfrm; 197 uint32_t sc_ecntrl; 198 uint32_t sc_dmactrl; 199 uint32_t sc_macstnaddr1; 200 uint32_t sc_macstnaddr2; 201 uint32_t sc_tctrl; 202 uint32_t sc_rctrl; 203 uint32_t sc_gaddr[16]; 204 uint64_t sc_macaddrs[15]; 205 206 void *sc_tx_ih; 207 void *sc_rx_ih; 208 void *sc_error_ih; 209 void *sc_soft_ih; 210 211 kmutex_t *sc_lock; 212 213 struct evcnt sc_ev_tx_stall; 214 struct evcnt sc_ev_tx_intr; 215 struct evcnt sc_ev_rx_stall; 216 struct evcnt sc_ev_rx_intr; 217 struct evcnt sc_ev_error_intr; 218 struct evcnt sc_ev_soft_intr; 219 struct evcnt sc_ev_tx_pause; 220 struct evcnt sc_ev_rx_pause; 221 struct evcnt sc_ev_mii_ticks; 222 223 struct callout sc_mii_callout; 224 uint64_t sc_mii_last_tick; 225 226 struct ifqueue sc_rx_bufcache; 227 struct pq3etsec_mapcache *sc_rx_mapcache; 228 struct pq3etsec_mapcache *sc_tx_mapcache; 229 }; 230 231 static int pq3etsec_match(device_t, cfdata_t, void *); 232 static void pq3etsec_attach(device_t, device_t, void *); 233 234 static void pq3etsec_ifstart(struct ifnet *); 235 static void pq3etsec_ifwatchdog(struct ifnet *); 236 static int pq3etsec_ifinit(struct ifnet *); 237 static void pq3etsec_ifstop(struct ifnet *, int); 238 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 239 240 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 241 struct pq3etsec_mapcache **, size_t, size_t, size_t, size_t); 242 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 243 struct pq3etsec_mapcache *); 244 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 245 struct pq3etsec_mapcache *); 246 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 247 struct pq3etsec_mapcache *, bus_dmamap_t); 248 249 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 250 struct pq3etsec_txqueue *, u_int); 251 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 252 struct pq3etsec_txqueue *); 253 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 254 struct pq3etsec_txqueue *); 255 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 256 struct pq3etsec_txqueue *); 257 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 258 struct pq3etsec_txqueue *, struct mbuf *m); 259 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 260 struct pq3etsec_txqueue *); 261 262 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 263 struct pq3etsec_rxqueue *, u_int); 264 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 265 struct pq3etsec_rxqueue *); 266 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 267 struct pq3etsec_rxqueue *, bool); 268 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 269 struct pq3etsec_rxqueue *); 270 271 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 272 273 static void pq3etsec_mii_tick(void *); 274 static int pq3etsec_rx_intr(void *); 275 static int pq3etsec_tx_intr(void *); 276 static int pq3etsec_error_intr(void *); 277 static void pq3etsec_soft_intr(void *); 278 279 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 280 pq3etsec_match, pq3etsec_attach, NULL, NULL); 281 282 static int 283 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 284 { 285 286 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 287 return 0; 288 289 return 1; 290 } 291 292 static inline uint32_t 293 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 294 { 295 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 296 } 297 298 static inline void 299 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 300 { 301 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 302 } 303 304 static int 305 pq3etsec_mii_readreg(device_t self, int phy, int reg) 306 { 307 struct pq3etsec_softc * const sc = device_private(self); 308 uint32_t miimcom = etsec_read(sc, MIIMCOM); 309 310 // int s = splnet(); 311 312 etsec_write(sc, MIIMADD, 313 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 314 315 etsec_write(sc, IEVENT, IEVENT_MMRD); 316 etsec_write(sc, MIIMCOM, 0); /* clear any past bits */ 317 etsec_write(sc, MIIMCOM, MIIMCOM_READ); 318 #if 0 319 sc->sc_imask |= IEVENT_MMRD; 320 etsec_write(sc, IMASK, sc->sc_imask); 321 #endif 322 323 while (etsec_read(sc, MIIMIND) != 0) { 324 delay(1); 325 } 326 int data = etsec_read(sc, MIIMSTAT); 327 328 if (miimcom == MIIMCOM_SCAN) 329 etsec_write(sc, MIIMCOM, miimcom); 330 331 #if 0 332 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 333 __func__, phy, reg, data); 334 #endif 335 etsec_write(sc, IEVENT, IEVENT_MMRD); 336 // splx(s); 337 return data; 338 } 339 340 static void 341 pq3etsec_mii_writereg(device_t self, int phy, int reg, int data) 342 { 343 struct pq3etsec_softc * const sc = device_private(self); 344 uint32_t miimcom = etsec_read(sc, MIIMCOM); 345 346 #if 0 347 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 348 __func__, phy, reg, data); 349 #endif 350 351 // int s = splnet(); 352 etsec_write(sc, IEVENT, IEVENT_MMWR); 353 etsec_write(sc, MIIMADD, 354 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 355 etsec_write(sc, MIIMCOM, 0); /* clear any past bits */ 356 etsec_write(sc, MIIMCON, data); 357 358 #if 0 359 sc->sc_imask |= IEVENT_MMWR; 360 etsec_write(sc, IMASK, sc->sc_imask); 361 #endif 362 363 int timo = 1000; /* 1ms */ 364 while ((etsec_read(sc, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 365 delay(1); 366 } 367 368 if (miimcom == MIIMCOM_SCAN) 369 etsec_write(sc, MIIMCOM, miimcom); 370 etsec_write(sc, IEVENT, IEVENT_MMWR); 371 // splx(s); 372 } 373 374 static void 375 pq3etsec_mii_statchg(device_t self) 376 { 377 struct pq3etsec_softc * const sc = device_private(self); 378 struct mii_data * const mii = &sc->sc_mii; 379 380 uint32_t maccfg1 = sc->sc_maccfg1; 381 uint32_t maccfg2 = sc->sc_maccfg2; 382 uint32_t ecntrl = sc->sc_ecntrl; 383 384 maccfg1 &= ~(MACCFG1_TX_FLOW|MACCFG1_RX_FLOW); 385 maccfg2 &= ~(MACCFG2_IFMODE|MACCFG2_FD); 386 387 if (sc->sc_mii.mii_media_active & IFM_FDX) { 388 maccfg2 |= MACCFG2_FD; 389 } 390 391 /* 392 * Now deal with the flow control bits. 393 */ 394 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 395 && (mii->mii_media_active & IFM_ETH_FMASK)) { 396 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 397 maccfg1 |= MACCFG1_RX_FLOW; 398 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 399 maccfg1 |= MACCFG1_TX_FLOW; 400 } 401 402 /* 403 * Now deal with the speed. 404 */ 405 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 406 maccfg2 |= MACCFG2_IFMODE_GMII; 407 } else { 408 maccfg2 |= MACCFG2_IFMODE_MII; 409 ecntrl &= ~ECNTRL_R100M; 410 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 411 ecntrl |= ECNTRL_R100M; 412 } 413 } 414 415 /* 416 * If things are different, re-init things. 417 */ 418 if (maccfg1 != sc->sc_maccfg1 419 || maccfg2 != sc->sc_maccfg2 420 || ecntrl != sc->sc_ecntrl) { 421 if (sc->sc_if.if_flags & IFF_RUNNING) 422 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 423 sc->sc_maccfg1 = maccfg1; 424 sc->sc_maccfg2 = maccfg2; 425 sc->sc_ecntrl = ecntrl; 426 } 427 } 428 429 #if 0 430 static void 431 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 432 { 433 struct pq3etsec_softc * const sc = ifp->if_softc; 434 435 mii_pollstat(&sc->sc_mii); 436 ether_mediastatus(ifp, ifmr); 437 ifmr->ifm_status = sc->sc_mii.mii_media_status; 438 ifmr->ifm_active = sc->sc_mii.mii_media_active; 439 } 440 441 static int 442 pq3etsec_mediachange(struct ifnet *ifp) 443 { 444 struct pq3etsec_softc * const sc = ifp->if_softc; 445 446 if ((ifp->if_flags & IFF_UP) == 0) 447 return 0; 448 449 int rv = mii_mediachg(&sc->sc_mii); 450 return (rv == ENXIO) ? 0 : rv; 451 } 452 #endif 453 454 static void 455 pq3etsec_attach(device_t parent, device_t self, void *aux) 456 { 457 struct cpunode_softc * const psc = device_private(parent); 458 struct pq3etsec_softc * const sc = device_private(self); 459 struct cpunode_attach_args * const cna = aux; 460 struct cpunode_locators * const cnl = &cna->cna_locs; 461 int error; 462 463 psc->sc_children |= cna->cna_childmask; 464 sc->sc_dev = self; 465 sc->sc_bst = cna->cna_memt; 466 sc->sc_dmat = &booke_bus_dma_tag; 467 468 /* 469 * If we have a common MDIO bus, if all off instance 1. 470 */ 471 device_t miiself = (self->dv_cfdata->cf_flags & 0x100) 472 ? tsec_cd.cd_devs[0] 473 : self; 474 475 /* 476 * See if the phy is in the config file... 477 */ 478 if (self->dv_cfdata->cf_flags & 0x3f) { 479 sc->sc_phy_addr = (self->dv_cfdata->cf_flags & 0x3f) - 1; 480 } else { 481 unsigned char prop_name[20]; 482 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 483 cnl->cnl_instance); 484 sc->sc_phy_addr = board_info_get_number(prop_name); 485 } 486 aprint_normal(" phy %d", sc->sc_phy_addr); 487 488 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 489 &sc->sc_bsh); 490 if (error) { 491 aprint_error(": error mapping registers: %d\n", error); 492 return; 493 } 494 495 /* 496 * Assume firmware has aready set the mac address and fetch it 497 * before we reinit it. 498 */ 499 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 500 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 501 sc->sc_rctrl = RCTRL_DEFAULT; 502 sc->sc_maccfg2 = MACCFG2_DEFAULT; 503 504 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 505 size_t len; 506 const uint8_t *mac_addr = 507 board_info_get_data("tsec-mac-addr-base", &len); 508 KASSERT(len == ETHER_ADDR_LEN); 509 sc->sc_macstnaddr2 = 510 (mac_addr[1] << 24) 511 | (mac_addr[0] << 16); 512 sc->sc_macstnaddr1 = 513 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 514 | (mac_addr[4] << 16) 515 | (mac_addr[3] << 8) 516 | (mac_addr[2] << 0); 517 #if 0 518 aprint_error(": mac-address unknown\n"); 519 return; 520 #endif 521 } 522 523 char enaddr[ETHER_ADDR_LEN] = { 524 [0] = sc->sc_macstnaddr2 >> 16, 525 [1] = sc->sc_macstnaddr2 >> 24, 526 [2] = sc->sc_macstnaddr1 >> 0, 527 [3] = sc->sc_macstnaddr1 >> 8, 528 [4] = sc->sc_macstnaddr1 >> 16, 529 [5] = sc->sc_macstnaddr1 >> 24, 530 }; 531 532 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 533 if (error) { 534 aprint_error(": failed to init rxq: %d\n", error); 535 return; 536 } 537 538 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 539 if (error) { 540 aprint_error(": failed to init txq: %d\n", error); 541 return; 542 } 543 544 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 545 ETSEC_MAXRXMBUFS, ETSEC_MINRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 546 if (error) { 547 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 548 return; 549 } 550 551 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 552 ETSEC_MAXTXMBUFS, ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 553 if (error) { 554 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 555 return; 556 } 557 558 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 559 pq3etsec_tx_intr, sc); 560 if (sc->sc_tx_ih == NULL) { 561 aprint_error(": failed to establish tx interrupt: %d\n", 562 cnl->cnl_intrs[0]); 563 return; 564 } 565 566 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 567 pq3etsec_rx_intr, sc); 568 if (sc->sc_rx_ih == NULL) { 569 aprint_error(": failed to establish rx interrupt: %d\n", 570 cnl->cnl_intrs[1]); 571 return; 572 } 573 574 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 575 pq3etsec_error_intr, sc); 576 if (sc->sc_error_ih == NULL) { 577 aprint_error(": failed to establish error interrupt: %d\n", 578 cnl->cnl_intrs[2]); 579 return; 580 } 581 582 sc->sc_soft_ih = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 583 pq3etsec_soft_intr, sc); 584 if (sc->sc_soft_ih == NULL) { 585 aprint_error(": failed to establish soft interrupt\n"); 586 return; 587 } 588 589 aprint_normal("\n"); 590 591 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 592 593 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 594 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 595 596 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 597 ether_sprintf(enaddr)); 598 599 const char * const xname = device_xname(sc->sc_dev); 600 struct ethercom * const ec = &sc->sc_ec; 601 struct ifnet * const ifp = &ec->ec_if; 602 603 ec->ec_mii = &sc->sc_mii; 604 605 sc->sc_mii.mii_ifp = ifp; 606 sc->sc_mii.mii_readreg = pq3etsec_mii_readreg; 607 sc->sc_mii.mii_writereg = pq3etsec_mii_writereg; 608 sc->sc_mii.mii_statchg = pq3etsec_mii_statchg; 609 610 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 611 ether_mediastatus); 612 613 mii_attach(miiself, &sc->sc_mii, 0xffffffff, 614 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 615 616 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 617 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 618 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 619 } else { 620 callout_schedule(&sc->sc_mii_callout, hz); 621 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 622 } 623 624 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 625 | ETHERCAP_JUMBO_MTU; 626 627 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 628 ifp->if_softc = sc; 629 ifp->if_capabilities = IFCAP_ETSEC; 630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 631 ifp->if_ioctl = pq3etsec_ifioctl; 632 ifp->if_start = pq3etsec_ifstart; 633 ifp->if_watchdog = pq3etsec_ifwatchdog; 634 ifp->if_init = pq3etsec_ifinit; 635 ifp->if_stop = pq3etsec_ifstop; 636 IFQ_SET_READY(&ifp->if_snd); 637 638 pq3etsec_ifstop(ifp, true); 639 640 /* 641 * Attach the interface. 642 */ 643 if_attach(ifp); 644 ether_ifattach(ifp, enaddr); 645 646 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 647 NULL, xname, "rx stall"); 648 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 649 NULL, xname, "tx stall"); 650 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 651 NULL, xname, "tx intr"); 652 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 653 NULL, xname, "rx intr"); 654 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 655 NULL, xname, "error intr"); 656 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 657 NULL, xname, "soft intr"); 658 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 659 NULL, xname, "tx pause"); 660 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 661 NULL, xname, "rx pause"); 662 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 663 NULL, xname, "mii ticks"); 664 } 665 666 static uint64_t 667 pq3etsec_macaddr_create(const uint8_t *lladdr) 668 { 669 uint64_t macaddr = 0; 670 671 lladdr += ETHER_ADDR_LEN; 672 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 673 macaddr = (macaddr << 8) | *--lladdr; 674 } 675 return macaddr << 16; 676 } 677 678 static int 679 pq3etsec_ifinit(struct ifnet *ifp) 680 { 681 struct pq3etsec_softc * const sc = ifp->if_softc; 682 int error = 0; 683 684 sc->sc_maxfrm = max(ifp->if_mtu + 32, MCLBYTES); 685 if (ifp->if_mtu > ETHERMTU_JUMBO) 686 return error; 687 688 KASSERT(ifp->if_flags & IFF_UP); 689 690 /* 691 * Stop the interface (steps 1 to 4 in the Soft Reset and 692 * Reconfigurating Procedure. 693 */ 694 pq3etsec_ifstop(ifp, 0); 695 696 /* 697 * If our frame size has changed (or it's our first time through) 698 * destroy the existing transmit mapcache. 699 */ 700 if (sc->sc_tx_mapcache != NULL 701 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 702 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 703 sc->sc_tx_mapcache = NULL; 704 } 705 706 if (sc->sc_tx_mapcache == NULL) { 707 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 708 ETSEC_MAXTXMBUFS, ETSEC_MAXTXMBUFS, sc->sc_maxfrm, 709 ETSEC_NTXSEGS); 710 if (error) 711 return error; 712 } 713 714 sc->sc_ev_mii_ticks.ev_count++; 715 mii_tick(&sc->sc_mii); 716 717 if (ifp->if_flags & IFF_PROMISC) { 718 sc->sc_rctrl |= RCTRL_PROM; 719 } else { 720 sc->sc_rctrl &= ~RCTRL_PROM; 721 } 722 723 uint32_t rctrl_prsdep = 0; 724 sc->sc_rctrl &= ~(RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP); 725 if (VLAN_ATTACHED(&sc->sc_ec)) { 726 sc->sc_rctrl |= RCTRL_VLEX; 727 rctrl_prsdep = RCTRL_PRSDEP_L2; 728 } 729 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 730 sc->sc_rctrl |= RCTRL_IPCSEN; 731 rctrl_prsdep = RCTRL_PRSDEP_L3; 732 } 733 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 734 sc->sc_rctrl |= RCTRL_TUCSEN; 735 rctrl_prsdep = RCTRL_PRSDEP_L4; 736 } 737 sc->sc_rctrl |= rctrl_prsdep; 738 #if 0 739 if (sc->sc_rctrl & (RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP)) 740 aprint_normal_dev(sc->sc_dev, 741 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 742 sc->sc_rctrl, 743 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 744 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 745 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 746 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 747 #endif 748 749 sc->sc_tctrl &= ~(TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS); 750 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 751 sc->sc_tctrl |= TCTRL_VLINS; 752 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 753 sc->sc_tctrl |= TCTRL_IPCSEN; 754 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 755 sc->sc_tctrl |= TCTRL_TUCSEN; 756 #if 0 757 if (sc->sc_tctrl & (TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS)) 758 aprint_normal_dev(sc->sc_dev, 759 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 760 sc->sc_tctrl, 761 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 762 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 763 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 764 #endif 765 766 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN|MACCFG1_RX_EN); 767 768 const uint64_t macstnaddr = 769 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 770 771 sc->sc_imask = IEVENT_DPE; 772 773 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 774 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 775 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 776 777 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 778 pq3etsec_txq_reset(sc, &sc->sc_txq); 779 780 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 781 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 782 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 783 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 784 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 785 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 786 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 787 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 788 789 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 790 pq3etsec_mc_setup(sc); 791 792 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 793 etsec_write(sc, MRBLR, MCLBYTES); 794 795 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 796 sc->sc_dmactrl |= DMACTRL_DEFAULT; 797 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 798 799 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 800 etsec_write(sc, TQUEUE, TQUEUE_EN0); 801 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE|IEVENT_TXC; 802 803 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 804 805 /* 12. Enable receive queues in RQUEUE, */ 806 etsec_write(sc, RQUEUE, RQUEUE_EN0|RQUEUE_EX0); 807 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY|IEVENT_RXC; 808 809 /* and optionally set TOE functionality in RCTRL. */ 810 etsec_write(sc, RCTRL, sc->sc_rctrl); 811 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 812 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 813 sc->sc_rx_adjlen += sizeof(struct rxfcb); 814 815 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 816 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 817 818 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 819 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 820 821 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 822 sc->sc_dmactrl &= ~(DMACTRL_GRS|DMACTRL_GTS); 823 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 824 825 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 826 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 827 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 828 829 sc->sc_soft_flags = 0; 830 831 etsec_write(sc, IMASK, sc->sc_imask); 832 833 ifp->if_flags |= IFF_RUNNING; 834 835 return error; 836 } 837 838 static void 839 pq3etsec_ifstop(struct ifnet *ifp, int disable) 840 { 841 struct pq3etsec_softc * const sc = ifp->if_softc; 842 843 KASSERT(!cpu_intr_p()); 844 const uint32_t imask_gsc_mask = IEVENT_GTSC|IEVENT_GRSC; 845 /* 846 * Clear the GTSC and GRSC from the interrupt mask until 847 * we are ready for them. Then clear them from IEVENT, 848 * request the graceful shutdown, and then enable the 849 * GTSC and GRSC bits in the mask. This should cause the 850 * error interrupt to fire which will issue a wakeup to 851 * allow us to resume. 852 */ 853 854 /* 855 * 1. Set GRS/GTS bits in DMACTRL register 856 */ 857 sc->sc_dmactrl |= DMACTRL_GRS|DMACTRL_GTS; 858 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 859 etsec_write(sc, IEVENT, imask_gsc_mask); 860 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 861 862 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN|MACCFG1_RX_EN)) { 863 /* 864 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 865 */ 866 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 867 868 u_int timo = 1000; 869 uint32_t ievent = etsec_read(sc, IEVENT); 870 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 871 if (--timo == 0) { 872 aprint_error_dev(sc->sc_dev, 873 "WARNING: " 874 "request to stop failed (IEVENT=%#x)\n", 875 ievent); 876 break; 877 } 878 delay(10); 879 ievent = etsec_read(sc, IEVENT); 880 } 881 } 882 883 /* 884 * Now reset the controller. 885 * 886 * 3. Set SOFT_RESET bit in MACCFG1 register 887 * 4. Clear SOFT_RESET bit in MACCFG1 register 888 */ 889 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 890 etsec_write(sc, MACCFG1, 0); 891 etsec_write(sc, IMASK, 0); 892 etsec_write(sc, IEVENT, ~0); 893 sc->sc_imask = 0; 894 ifp->if_flags &= ~IFF_RUNNING; 895 896 uint32_t tbipa = etsec_read(sc, TBIPA); 897 if (tbipa == sc->sc_phy_addr) { 898 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 899 etsec_write(sc, TBIPA, 0x1f); 900 } 901 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 902 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 903 etsec_write(sc, MIIMCFG, miimcfg); 904 905 /* 906 * Let's consume any remaing transmitted packets. And if we are 907 * disabling the interface, purge ourselves of any untransmitted 908 * packets. But don't consume any received packets, just drop them. 909 * If we aren't disabling the interface, save the mbufs in the 910 * receive queue for reuse. 911 */ 912 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 913 pq3etsec_txq_consume(sc, &sc->sc_txq); 914 if (disable) { 915 pq3etsec_txq_purge(sc, &sc->sc_txq); 916 IF_PURGE(&ifp->if_snd); 917 } 918 } 919 920 static void 921 pq3etsec_ifwatchdog(struct ifnet *ifp) 922 { 923 } 924 925 static void 926 pq3etsec_mc_setup( 927 struct pq3etsec_softc *sc) 928 { 929 struct ethercom * const ec = &sc->sc_ec; 930 struct ifnet * const ifp = &sc->sc_if; 931 struct ether_multi *enm; 932 struct ether_multistep step; 933 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 934 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 935 936 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 937 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 938 939 ifp->if_flags &= ~IFF_ALLMULTI; 940 941 ETHER_FIRST_MULTI(step, ec, enm); 942 for (u_int i = 0; enm != NULL; ) { 943 const char *addr = enm->enm_addrlo; 944 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 945 ifp->if_flags |= IFF_ALLMULTI; 946 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 947 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 948 break; 949 } 950 if ((sc->sc_rctrl & RCTRL_EMEN) 951 && i < __arraycount(sc->sc_macaddrs)) { 952 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 953 } else { 954 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 955 #if 0 956 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 957 ether_sprintf(addr), crc, 958 crc >> crc_shift, 959 crc >> (crc_shift + 5), 960 (crc >> crc_shift) & 31, 961 1 << (((crc >> crc_shift) & 31) ^ 31)); 962 #endif 963 /* 964 * The documentation doesn't completely follow PowerPC 965 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 966 * is 0x7fa32d9b. By empirical testing, the 967 * corresponding hash bit is word 3, bit 31 (ppc bit 968 * order). Since 3 << 31 | 31 is 0x7f, we deduce 969 * H[0:2] selects the register while H[3:7] selects 970 * the bit (ppc bit order). 971 */ 972 crc >>= crc_shift; 973 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 974 } 975 ETHER_NEXT_MULTI(step, enm); 976 } 977 for (u_int i = 0; i < 8; i++) { 978 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 979 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 980 #if 0 981 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 982 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 983 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 984 i, GADDR(i), etsec_read(sc, GADDR(i))); 985 #endif 986 } 987 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 988 uint64_t macaddr = sc->sc_macaddrs[i]; 989 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 990 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 991 #if 0 992 if (macaddr) 993 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 994 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 995 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 996 #endif 997 } 998 } 999 1000 static int 1001 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1002 { 1003 struct pq3etsec_softc *sc = ifp->if_softc; 1004 struct ifreq * const ifr = data; 1005 const int s = splnet(); 1006 int error; 1007 1008 switch (cmd) { 1009 case SIOCSIFMEDIA: 1010 case SIOCGIFMEDIA: 1011 /* Flow control requires full-duplex mode. */ 1012 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1013 (ifr->ifr_media & IFM_FDX) == 0) 1014 ifr->ifr_media &= ~IFM_ETH_FMASK; 1015 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1016 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1017 /* We can do both TXPAUSE and RXPAUSE. */ 1018 ifr->ifr_media |= 1019 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1020 } 1021 } 1022 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1023 break; 1024 1025 default: 1026 error = ether_ioctl(ifp, cmd, data); 1027 if (error != ENETRESET) 1028 break; 1029 1030 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1031 error = 0; 1032 if (ifp->if_flags & IFF_RUNNING) 1033 pq3etsec_mc_setup(sc); 1034 break; 1035 } 1036 error = pq3etsec_ifinit(ifp); 1037 break; 1038 } 1039 1040 splx(s); 1041 return error; 1042 } 1043 1044 static void 1045 pq3etsec_rxq_desc_presync( 1046 struct pq3etsec_softc *sc, 1047 struct pq3etsec_rxqueue *rxq, 1048 volatile struct rxbd *rxbd, 1049 size_t count) 1050 { 1051 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1052 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1053 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1054 } 1055 1056 static void 1057 pq3etsec_rxq_desc_postsync( 1058 struct pq3etsec_softc *sc, 1059 struct pq3etsec_rxqueue *rxq, 1060 volatile struct rxbd *rxbd, 1061 size_t count) 1062 { 1063 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1064 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1065 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1066 } 1067 1068 static void 1069 pq3etsec_txq_desc_presync( 1070 struct pq3etsec_softc *sc, 1071 struct pq3etsec_txqueue *txq, 1072 volatile struct txbd *txbd, 1073 size_t count) 1074 { 1075 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1076 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1077 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1078 } 1079 1080 static void 1081 pq3etsec_txq_desc_postsync( 1082 struct pq3etsec_softc *sc, 1083 struct pq3etsec_txqueue *txq, 1084 volatile struct txbd *txbd, 1085 size_t count) 1086 { 1087 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1088 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1089 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1090 } 1091 1092 static bus_dmamap_t 1093 pq3etsec_mapcache_get( 1094 struct pq3etsec_softc *sc, 1095 struct pq3etsec_mapcache *dmc) 1096 { 1097 if (dmc->dmc_nmaps == 0) { 1098 bus_dmamap_t map; 1099 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1100 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1101 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &map); 1102 if (error) { 1103 aprint_error_dev(sc->sc_dev, 1104 "failed to allocate a %zuB map: %d\n", 1105 dmc->dmc_maxmapsize, error); 1106 return NULL; 1107 } 1108 return map; 1109 } 1110 1111 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1112 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1113 } 1114 1115 static void 1116 pq3etsec_mapcache_put( 1117 struct pq3etsec_softc *sc, 1118 struct pq3etsec_mapcache *dmc, 1119 bus_dmamap_t map) 1120 { 1121 KASSERT(map != NULL); 1122 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1123 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1124 } 1125 1126 static void 1127 pq3etsec_mapcache_destroy( 1128 struct pq3etsec_softc *sc, 1129 struct pq3etsec_mapcache *dmc) 1130 { 1131 const size_t dmc_size = 1132 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1133 1134 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1135 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1136 } 1137 kmem_free(dmc, dmc_size); 1138 } 1139 1140 static int 1141 pq3etsec_mapcache_create( 1142 struct pq3etsec_softc *sc, 1143 struct pq3etsec_mapcache **dmc_p, 1144 size_t maxmaps, 1145 size_t minmaps, 1146 size_t maxmapsize, 1147 size_t maxseg) 1148 { 1149 const size_t dmc_size = 1150 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1151 struct pq3etsec_mapcache * const dmc = kmem_zalloc(dmc_size, KM_SLEEP); 1152 1153 dmc->dmc_maxmaps = maxmaps; 1154 dmc->dmc_nmaps = minmaps; 1155 dmc->dmc_maxmapsize = maxmapsize; 1156 dmc->dmc_maxseg = maxseg; 1157 1158 for (u_int i = 0; i < minmaps; i++) { 1159 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1160 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1161 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1162 if (error) { 1163 aprint_error_dev(sc->sc_dev, 1164 "failed to creat dma map cache " 1165 "entry %u of %zu (max %zu): %d\n", 1166 i, minmaps, maxmaps, error); 1167 while (i-- > 0) { 1168 bus_dmamap_destroy(sc->sc_dmat, 1169 dmc->dmc_maps[i]); 1170 } 1171 kmem_free(dmc, dmc_size); 1172 return error; 1173 } 1174 KASSERT(dmc->dmc_maps[i] != NULL); 1175 } 1176 1177 *dmc_p = dmc; 1178 1179 return 0; 1180 } 1181 1182 #if 0 1183 static void 1184 pq3etsec_dmamem_free( 1185 bus_dma_tag_t dmat, 1186 size_t map_size, 1187 bus_dma_segment_t *seg, 1188 bus_dmamap_t map, 1189 void *kvap) 1190 { 1191 bus_dmamap_destroy(dmat, map); 1192 bus_dmamem_unmap(dmat, kvap, map_size); 1193 bus_dmamem_free(dmat, seg, 1); 1194 } 1195 #endif 1196 1197 static int 1198 pq3etsec_dmamem_alloc( 1199 bus_dma_tag_t dmat, 1200 size_t map_size, 1201 bus_dma_segment_t *seg, 1202 bus_dmamap_t *map, 1203 void **kvap) 1204 { 1205 int error; 1206 int nseg; 1207 1208 *kvap = NULL; 1209 *map = NULL; 1210 1211 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1212 seg, 1, &nseg, 0); 1213 if (error) 1214 return error; 1215 1216 KASSERT(nseg == 1); 1217 1218 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1219 BUS_DMA_COHERENT); 1220 if (error == 0) { 1221 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1222 map); 1223 if (error == 0) { 1224 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1225 NULL, 0); 1226 if (error == 0) 1227 return 0; 1228 bus_dmamap_destroy(dmat, *map); 1229 *map = NULL; 1230 } 1231 bus_dmamem_unmap(dmat, *kvap, map_size); 1232 *kvap = NULL; 1233 } 1234 bus_dmamem_free(dmat, seg, nseg); 1235 return 0; 1236 } 1237 1238 static struct mbuf * 1239 pq3etsec_rx_buf_alloc( 1240 struct pq3etsec_softc *sc) 1241 { 1242 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1243 if (m == NULL) { 1244 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1245 return NULL; 1246 } 1247 MCLGET(m, M_DONTWAIT); 1248 if ((m->m_flags & M_EXT) == 0) { 1249 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1250 m_freem(m); 1251 return NULL; 1252 } 1253 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1254 1255 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1256 if (map == NULL) { 1257 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1258 m_freem(m); 1259 return NULL; 1260 } 1261 M_SETCTX(m, map); 1262 m->m_len = m->m_pkthdr.len = MCLBYTES; 1263 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1264 BUS_DMA_READ|BUS_DMA_NOWAIT); 1265 if (error) { 1266 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1267 error); 1268 M_SETCTX(m, NULL); 1269 m_freem(m); 1270 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1271 return NULL; 1272 } 1273 KASSERT(map->dm_mapsize == MCLBYTES); 1274 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1275 BUS_DMASYNC_PREREAD); 1276 1277 return m; 1278 } 1279 1280 static void 1281 pq3etsec_rx_map_unload( 1282 struct pq3etsec_softc *sc, 1283 struct mbuf *m) 1284 { 1285 KASSERT(m); 1286 for (; m != NULL; m = m->m_next) { 1287 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1288 KASSERT(map); 1289 KASSERT(map->dm_mapsize == MCLBYTES); 1290 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1291 BUS_DMASYNC_POSTREAD); 1292 bus_dmamap_unload(sc->sc_dmat, map); 1293 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1294 M_SETCTX(m, NULL); 1295 } 1296 } 1297 1298 static bool 1299 pq3etsec_rxq_produce( 1300 struct pq3etsec_softc *sc, 1301 struct pq3etsec_rxqueue *rxq) 1302 { 1303 volatile struct rxbd *producer = rxq->rxq_producer; 1304 #if 0 1305 size_t inuse = rxq->rxq_inuse; 1306 #endif 1307 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1308 struct mbuf *m; 1309 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1310 if (m == NULL) { 1311 m = pq3etsec_rx_buf_alloc(sc); 1312 if (m == NULL) { 1313 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1314 break; 1315 } 1316 } 1317 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1318 KASSERT(map); 1319 1320 #ifdef ETSEC_DEBUG 1321 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1322 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1323 #endif 1324 1325 /* rxbd_len is write-only by the ETSEC */ 1326 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1327 membar_producer(); 1328 producer->rxbd_flags |= RXBD_E; 1329 if (__predict_false(rxq->rxq_mhead == NULL)) { 1330 KASSERT(producer == rxq->rxq_consumer); 1331 rxq->rxq_mconsumer = m; 1332 } 1333 *rxq->rxq_mtail = m; 1334 rxq->rxq_mtail = &m->m_next; 1335 m->m_len = MCLBYTES; 1336 m->m_next = NULL; 1337 rxq->rxq_inuse++; 1338 if (++producer == rxq->rxq_last) { 1339 membar_producer(); 1340 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1341 rxq->rxq_last - rxq->rxq_producer); 1342 producer = rxq->rxq_producer = rxq->rxq_first; 1343 } 1344 } 1345 if (producer != rxq->rxq_producer) { 1346 membar_producer(); 1347 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1348 producer - rxq->rxq_producer); 1349 rxq->rxq_producer = producer; 1350 } 1351 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1352 if (qhlt) { 1353 KASSERT(qhlt & rxq->rxq_qmask); 1354 sc->sc_ev_rx_stall.ev_count++; 1355 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1356 } 1357 #if 0 1358 aprint_normal_dev(sc->sc_dev, 1359 "%s: buffers inuse went from %zu to %zu\n", 1360 __func__, inuse, rxq->rxq_inuse); 1361 #endif 1362 return true; 1363 } 1364 1365 static bool 1366 pq3etsec_rx_offload( 1367 struct pq3etsec_softc *sc, 1368 struct mbuf *m, 1369 const struct rxfcb *fcb) 1370 { 1371 if (fcb->rxfcb_flags & RXFCB_VLN) { 1372 VLAN_INPUT_TAG(&sc->sc_if, m, fcb->rxfcb_vlctl, 1373 m_freem(m); return false); 1374 } 1375 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1376 || (fcb->rxfcb_flags & (RXFCB_CIP|RXFCB_CTU)) == 0) 1377 return true; 1378 int csum_flags = 0; 1379 if ((fcb->rxfcb_flags & (RXFCB_IP6|RXFCB_CIP)) == RXFCB_CIP) { 1380 csum_flags |= M_CSUM_IPv4; 1381 if (fcb->rxfcb_flags & RXFCB_EIP) 1382 csum_flags |= M_CSUM_IPv4_BAD; 1383 } 1384 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1385 int ipv_flags; 1386 if (fcb->rxfcb_flags & RXFCB_IP6) 1387 ipv_flags = M_CSUM_TCPv6|M_CSUM_UDPv6; 1388 else 1389 ipv_flags = M_CSUM_TCPv4|M_CSUM_UDPv4; 1390 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1391 csum_flags |= (M_CSUM_TCPv4|M_CSUM_TCPv6) & ipv_flags; 1392 } else { 1393 csum_flags |= (M_CSUM_UDPv4|M_CSUM_UDPv6) & ipv_flags; 1394 } 1395 if (fcb->rxfcb_flags & RXFCB_ETU) 1396 csum_flags |= M_CSUM_TCP_UDP_BAD; 1397 } 1398 1399 m->m_pkthdr.csum_flags = csum_flags; 1400 return true; 1401 } 1402 1403 static void 1404 pq3etsec_rx_input( 1405 struct pq3etsec_softc *sc, 1406 struct mbuf *m, 1407 uint16_t rxbd_flags) 1408 { 1409 struct ifnet * const ifp = &sc->sc_if; 1410 1411 pq3etsec_rx_map_unload(sc, m); 1412 1413 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1414 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1415 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1416 return; 1417 } 1418 m_adj(m, sc->sc_rx_adjlen); 1419 1420 if (rxbd_flags & RXBD_M) 1421 m->m_flags |= M_PROMISC; 1422 if (rxbd_flags & RXBD_BC) 1423 m->m_flags |= M_BCAST; 1424 if (rxbd_flags & RXBD_MC) 1425 m->m_flags |= M_MCAST; 1426 m->m_flags |= M_HASFCS; 1427 m->m_pkthdr.rcvif = &sc->sc_if; 1428 1429 ifp->if_ipackets++; 1430 ifp->if_ibytes += m->m_pkthdr.len; 1431 1432 /* 1433 * Let's give it to the network subsystm to deal with. 1434 */ 1435 int s = splnet(); 1436 bpf_mtap(ifp, m); 1437 (*ifp->if_input)(ifp, m); 1438 splx(s); 1439 } 1440 1441 static void 1442 pq3etsec_rxq_consume( 1443 struct pq3etsec_softc *sc, 1444 struct pq3etsec_rxqueue *rxq) 1445 { 1446 struct ifnet * const ifp = &sc->sc_if; 1447 volatile struct rxbd *consumer = rxq->rxq_consumer; 1448 size_t rxconsumed = 0; 1449 1450 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1451 1452 for (;;) { 1453 if (consumer == rxq->rxq_producer) { 1454 rxq->rxq_consumer = consumer; 1455 rxq->rxq_inuse -= rxconsumed; 1456 return; 1457 } 1458 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1459 const uint16_t rxbd_flags = consumer->rxbd_flags; 1460 if (rxbd_flags & RXBD_E) { 1461 rxq->rxq_consumer = consumer; 1462 rxq->rxq_inuse -= rxconsumed; 1463 return; 1464 } 1465 KASSERT(rxq->rxq_mconsumer != NULL); 1466 #ifdef ETSEC_DEBUG 1467 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1468 #endif 1469 #if 0 1470 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1471 __func__, 1472 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1473 mtod(rxq->rxq_mconsumer, int *)[0], 1474 mtod(rxq->rxq_mconsumer, int *)[1], 1475 mtod(rxq->rxq_mconsumer, int *)[2], 1476 mtod(rxq->rxq_mconsumer, int *)[3]); 1477 #endif 1478 /* 1479 * We own this packet again. Clear all flags except wrap. 1480 */ 1481 rxconsumed++; 1482 consumer->rxbd_flags = rxbd_flags & (RXBD_W|RXBD_I); 1483 1484 /* 1485 * If this descriptor has the LAST bit set and no errors, 1486 * it's a valid input packet. 1487 */ 1488 if ((rxbd_flags & (RXBD_L|RXBD_ERRORS)) == RXBD_L) { 1489 size_t rxbd_len = consumer->rxbd_len; 1490 struct mbuf *m = rxq->rxq_mhead; 1491 struct mbuf *m_last = rxq->rxq_mconsumer; 1492 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1493 rxq->rxq_mtail = &rxq->rxq_mhead; 1494 rxq->rxq_mconsumer = rxq->rxq_mhead; 1495 m_last->m_next = NULL; 1496 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1497 m->m_pkthdr.len = rxbd_len; 1498 pq3etsec_rx_input(sc, m, rxbd_flags); 1499 } else if (rxbd_flags & RXBD_L) { 1500 KASSERT(rxbd_flags & RXBD_ERRORS); 1501 struct mbuf *m; 1502 /* 1503 * We encountered an error, take the mbufs and add 1504 * then to the rx bufcache so we can reuse them. 1505 */ 1506 ifp->if_ierrors++; 1507 for (m = rxq->rxq_mhead; 1508 m != rxq->rxq_mconsumer; 1509 m = m->m_next) { 1510 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1511 } 1512 m = rxq->rxq_mconsumer; 1513 if ((rxq->rxq_mhead = m->m_next) == NULL) 1514 rxq->rxq_mtail = &rxq->rxq_mhead; 1515 rxq->rxq_mconsumer = m->m_next; 1516 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1517 } else { 1518 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1519 } 1520 #ifdef ETSEC_DEBUG 1521 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1522 #endif 1523 1524 /* 1525 * Wrap at the last entry! 1526 */ 1527 if (rxbd_flags & RXBD_W) { 1528 KASSERT(consumer + 1 == rxq->rxq_last); 1529 consumer = rxq->rxq_first; 1530 } else { 1531 consumer++; 1532 } 1533 #ifdef ETSEC_DEBUG 1534 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1535 #endif 1536 } 1537 } 1538 1539 static void 1540 pq3etsec_rxq_purge( 1541 struct pq3etsec_softc *sc, 1542 struct pq3etsec_rxqueue *rxq, 1543 bool discard) 1544 { 1545 struct mbuf *m; 1546 1547 if ((m = rxq->rxq_mhead) != NULL) { 1548 #ifdef ETSEC_DEBUG 1549 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1550 #endif 1551 1552 if (discard) { 1553 pq3etsec_rx_map_unload(sc, m); 1554 m_freem(m); 1555 } else { 1556 while (m != NULL) { 1557 struct mbuf *m0 = m->m_next; 1558 m->m_next = NULL; 1559 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1560 m = m0; 1561 } 1562 } 1563 1564 } 1565 1566 rxq->rxq_mconsumer = NULL; 1567 rxq->rxq_mhead = NULL; 1568 rxq->rxq_mtail = &rxq->rxq_mhead; 1569 rxq->rxq_inuse = 0; 1570 } 1571 1572 static void 1573 pq3etsec_rxq_reset( 1574 struct pq3etsec_softc *sc, 1575 struct pq3etsec_rxqueue *rxq) 1576 { 1577 /* 1578 * sync all the descriptors 1579 */ 1580 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1581 rxq->rxq_last - rxq->rxq_first); 1582 1583 /* 1584 * Make sure we own all descriptors in the ring. 1585 */ 1586 volatile struct rxbd *rxbd; 1587 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1588 rxbd->rxbd_flags = RXBD_I; 1589 } 1590 1591 /* 1592 * Last descriptor has the wrap flag. 1593 */ 1594 rxbd->rxbd_flags = RXBD_W|RXBD_I; 1595 1596 /* 1597 * Reset the producer consumer indexes. 1598 */ 1599 rxq->rxq_consumer = rxq->rxq_first; 1600 rxq->rxq_producer = rxq->rxq_first; 1601 rxq->rxq_inuse = 0; 1602 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1603 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1604 1605 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY; 1606 1607 /* 1608 * Restart the transmit at the first descriptor 1609 */ 1610 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1611 } 1612 1613 static int 1614 pq3etsec_rxq_attach( 1615 struct pq3etsec_softc *sc, 1616 struct pq3etsec_rxqueue *rxq, 1617 u_int qno) 1618 { 1619 size_t map_size = PAGE_SIZE; 1620 size_t desc_count = map_size / sizeof(struct rxbd); 1621 int error; 1622 void *descs; 1623 1624 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1625 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1626 if (error) 1627 return error; 1628 1629 memset(descs, 0, map_size); 1630 rxq->rxq_first = descs; 1631 rxq->rxq_last = rxq->rxq_first + desc_count; 1632 rxq->rxq_consumer = descs; 1633 rxq->rxq_producer = descs; 1634 1635 pq3etsec_rxq_purge(sc, rxq, true); 1636 pq3etsec_rxq_reset(sc, rxq); 1637 1638 rxq->rxq_reg_rbase = RBASEn(qno); 1639 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1640 1641 return 0; 1642 } 1643 1644 static bool 1645 pq3etsec_txq_active_p( 1646 struct pq3etsec_softc * const sc, 1647 struct pq3etsec_txqueue *txq) 1648 { 1649 return !IF_IS_EMPTY(&txq->txq_mbufs); 1650 } 1651 1652 static bool 1653 pq3etsec_txq_fillable_p( 1654 struct pq3etsec_softc * const sc, 1655 struct pq3etsec_txqueue *txq) 1656 { 1657 return txq->txq_free >= txq->txq_threshold; 1658 } 1659 1660 static int 1661 pq3etsec_txq_attach( 1662 struct pq3etsec_softc *sc, 1663 struct pq3etsec_txqueue *txq, 1664 u_int qno) 1665 { 1666 size_t map_size = PAGE_SIZE; 1667 size_t desc_count = map_size / sizeof(struct txbd); 1668 int error; 1669 void *descs; 1670 1671 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1672 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1673 if (error) 1674 return error; 1675 1676 memset(descs, 0, map_size); 1677 txq->txq_first = descs; 1678 txq->txq_last = txq->txq_first + desc_count; 1679 txq->txq_consumer = descs; 1680 txq->txq_producer = descs; 1681 1682 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1683 1684 txq->txq_reg_tbase = TBASEn(qno); 1685 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1686 1687 pq3etsec_txq_reset(sc, txq); 1688 1689 return 0; 1690 } 1691 1692 static int 1693 pq3etsec_txq_map_load( 1694 struct pq3etsec_softc *sc, 1695 struct pq3etsec_txqueue *txq, 1696 struct mbuf *m) 1697 { 1698 bus_dmamap_t map; 1699 int error; 1700 1701 map = M_GETCTX(m, bus_dmamap_t); 1702 if (map != NULL) 1703 return 0; 1704 1705 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1706 if (map == NULL) 1707 return ENOMEM; 1708 1709 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1710 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1711 if (error) 1712 return error; 1713 1714 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1715 BUS_DMASYNC_PREWRITE); 1716 M_SETCTX(m, map); 1717 return 0; 1718 } 1719 1720 static void 1721 pq3etsec_txq_map_unload( 1722 struct pq3etsec_softc *sc, 1723 struct pq3etsec_txqueue *txq, 1724 struct mbuf *m) 1725 { 1726 KASSERT(m); 1727 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1728 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1729 BUS_DMASYNC_POSTWRITE); 1730 bus_dmamap_unload(sc->sc_dmat, map); 1731 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1732 } 1733 1734 static bool 1735 pq3etsec_txq_produce( 1736 struct pq3etsec_softc *sc, 1737 struct pq3etsec_txqueue *txq, 1738 struct mbuf *m) 1739 { 1740 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1741 1742 if (map->dm_nsegs > txq->txq_free) 1743 return false; 1744 1745 /* 1746 * TCP Offload flag must be set in the first descriptor. 1747 */ 1748 volatile struct txbd *producer = txq->txq_producer; 1749 uint16_t last_flags = TXBD_L; 1750 uint16_t first_flags = TXBD_R 1751 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1752 1753 /* 1754 * If we've produced enough descriptors without consuming any 1755 * we need to ask for an interrupt to reclaim some. 1756 */ 1757 txq->txq_lastintr += map->dm_nsegs; 1758 if (txq->txq_lastintr >= txq->txq_threshold 1759 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1760 txq->txq_lastintr = 0; 1761 last_flags |= TXBD_I; 1762 } 1763 1764 #ifdef ETSEC_DEBUG 1765 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1766 #endif 1767 KASSERT(producer != txq->txq_last); 1768 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1769 producer->txbd_len = map->dm_segs[0].ds_len; 1770 1771 if (map->dm_nsegs > 1) { 1772 volatile struct txbd *start = producer + 1; 1773 size_t count = map->dm_nsegs - 1; 1774 for (u_int i = 1; i < map->dm_nsegs; i++) { 1775 if (__predict_false(++producer == txq->txq_last)) { 1776 producer = txq->txq_first; 1777 if (start < txq->txq_last) { 1778 pq3etsec_txq_desc_presync(sc, txq, 1779 start, txq->txq_last - start); 1780 count -= txq->txq_last - start; 1781 } 1782 start = txq->txq_first; 1783 } 1784 #ifdef ETSEC_DEBUG 1785 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1786 #endif 1787 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1788 producer->txbd_len = map->dm_segs[i].ds_len; 1789 producer->txbd_flags = TXBD_R 1790 | (producer->txbd_flags & TXBD_W) 1791 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1792 #if 0 1793 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1794 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1795 #endif 1796 } 1797 pq3etsec_txq_desc_presync(sc, txq, start, count); 1798 } else { 1799 first_flags |= last_flags; 1800 } 1801 1802 membar_producer(); 1803 txq->txq_producer->txbd_flags = 1804 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1805 #if 0 1806 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1807 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1808 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1809 #endif 1810 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1811 1812 /* 1813 * Reduce free count by the number of segments we consumed. 1814 */ 1815 txq->txq_free -= map->dm_nsegs; 1816 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 1817 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 1818 KASSERT(producer->txbd_flags & TXBD_L); 1819 #ifdef ETSEC_DEBUG 1820 txq->txq_lmbufs[producer - txq->txq_first] = m; 1821 #endif 1822 1823 #if 0 1824 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 1825 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 1826 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 1827 #endif 1828 1829 if (++producer == txq->txq_last) 1830 txq->txq_producer = txq->txq_first; 1831 else 1832 txq->txq_producer = producer; 1833 IF_ENQUEUE(&txq->txq_mbufs, m); 1834 1835 /* 1836 * Restart the transmitter. 1837 */ 1838 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 1839 1840 return true; 1841 } 1842 1843 static void 1844 pq3etsec_tx_offload( 1845 struct pq3etsec_softc *sc, 1846 struct pq3etsec_txqueue *txq, 1847 struct mbuf **mp) 1848 { 1849 struct mbuf *m = *mp; 1850 u_int csum_flags = m->m_pkthdr.csum_flags; 1851 struct m_tag *vtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m); 1852 1853 KASSERT(m->m_flags & M_PKTHDR); 1854 1855 /* 1856 * Let see if we are doing any offload first. 1857 */ 1858 if (csum_flags == 0 && vtag == 0) { 1859 m->m_flags &= ~M_HASFCB; 1860 return; 1861 } 1862 1863 uint16_t flags = 0; 1864 if (csum_flags & M_CSUM_IP) { 1865 flags |= TXFCB_IP 1866 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 1867 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 1868 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 1869 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 1870 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 1871 } 1872 if (vtag) { 1873 flags |= TXFCB_VLN; 1874 } 1875 if (flags == 0) { 1876 m->m_flags &= ~M_HASFCB; 1877 return; 1878 } 1879 1880 struct txfcb fcb; 1881 fcb.txfcb_flags = flags; 1882 if (csum_flags & M_CSUM_IPv4) 1883 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 1884 else 1885 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 1886 fcb.txfcb_l3os = ETHER_HDR_LEN; 1887 fcb.txfcb_phcs = 0; 1888 fcb.txfcb_vlctl = vtag ? VLAN_TAG_VALUE(vtag) & 0xffff : 0; 1889 1890 #if 0 1891 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 1892 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 1893 fcb.txfcb_phcs, fcb.txfcb_vlctl); 1894 #endif 1895 1896 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 1897 m->m_data -= sizeof(fcb); 1898 m->m_len += sizeof(fcb); 1899 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 1900 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 1901 m->m_data = m->m_pktdat; 1902 m->m_len += sizeof(fcb); 1903 } else { 1904 struct mbuf *mn; 1905 MGET(mn, M_DONTWAIT, m->m_type); 1906 if (mn == NULL) { 1907 if (csum_flags & M_CSUM_IP4) { 1908 #ifdef INET 1909 ip_undefer_csum(m, ETHER_HDR_LEN, 1910 csum_flags & M_CSUM_IP4); 1911 #else 1912 panic("%s: impossible M_CSUM flags %#x", 1913 device_xname(sc->sc_dev), csum_flags); 1914 #endif 1915 } else if (csum_flags & M_CSUM_IP6) { 1916 #ifdef INET6 1917 ip6_undefer_csum(m, ETHER_HDR_LEN, 1918 csum_flags & M_CSUM_IP6); 1919 #else 1920 panic("%s: impossible M_CSUM flags %#x", 1921 device_xname(sc->sc_dev), csum_flags); 1922 #endif 1923 } else if (vtag) { 1924 } 1925 1926 m->m_flags &= ~M_HASFCB; 1927 return; 1928 } 1929 1930 M_MOVE_PKTHDR(mn, m); 1931 mn->m_next = m; 1932 m = mn; 1933 MH_ALIGN(m, sizeof(fcb)); 1934 m->m_len = sizeof(fcb); 1935 *mp = m; 1936 } 1937 m->m_pkthdr.len += sizeof(fcb); 1938 m->m_flags |= M_HASFCB; 1939 *mtod(m, struct txfcb *) = fcb; 1940 return; 1941 } 1942 1943 static bool 1944 pq3etsec_txq_enqueue( 1945 struct pq3etsec_softc *sc, 1946 struct pq3etsec_txqueue *txq) 1947 { 1948 for (;;) { 1949 if (IF_QFULL(&txq->txq_mbufs)) 1950 return false; 1951 struct mbuf *m = txq->txq_next; 1952 if (m == NULL) { 1953 int s = splnet(); 1954 IF_DEQUEUE(&sc->sc_if.if_snd, m); 1955 splx(s); 1956 if (m == NULL) 1957 return true; 1958 M_SETCTX(m, NULL); 1959 pq3etsec_tx_offload(sc, txq, &m); 1960 } else { 1961 txq->txq_next = NULL; 1962 } 1963 int error = pq3etsec_txq_map_load(sc, txq, m); 1964 if (error) { 1965 aprint_error_dev(sc->sc_dev, 1966 "discarded packet due to " 1967 "dmamap load failure: %d\n", error); 1968 m_freem(m); 1969 continue; 1970 } 1971 KASSERT(txq->txq_next == NULL); 1972 if (!pq3etsec_txq_produce(sc, txq, m)) { 1973 txq->txq_next = m; 1974 return false; 1975 } 1976 KASSERT(txq->txq_next == NULL); 1977 } 1978 } 1979 1980 static bool 1981 pq3etsec_txq_consume( 1982 struct pq3etsec_softc *sc, 1983 struct pq3etsec_txqueue *txq) 1984 { 1985 struct ifnet * const ifp = &sc->sc_if; 1986 volatile struct txbd *consumer = txq->txq_consumer; 1987 size_t txfree = 0; 1988 1989 #if 0 1990 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 1991 #endif 1992 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 1993 1994 for (;;) { 1995 if (consumer == txq->txq_producer) { 1996 txq->txq_consumer = consumer; 1997 txq->txq_free += txfree; 1998 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 1999 #if 0 2000 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2001 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2002 #endif 2003 KASSERT(txq->txq_lastintr == 0); 2004 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2005 return true; 2006 } 2007 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2008 const uint16_t txbd_flags = consumer->txbd_flags; 2009 if (txbd_flags & TXBD_R) { 2010 txq->txq_consumer = consumer; 2011 txq->txq_free += txfree; 2012 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2013 #if 0 2014 printf("%s: freed %zu descriptors\n", 2015 __func__, txfree); 2016 #endif 2017 return pq3etsec_txq_fillable_p(sc, txq); 2018 } 2019 2020 /* 2021 * If this is the last descriptor in the chain, get the 2022 * mbuf, free its dmamap, and free the mbuf chain itself. 2023 */ 2024 if (txbd_flags & TXBD_L) { 2025 struct mbuf *m; 2026 2027 IF_DEQUEUE(&txq->txq_mbufs, m); 2028 #ifdef ETSEC_DEBUG 2029 KASSERTMSG(m == txq->txq_lmbufs[consumer-txq->txq_first], 2030 ("%s: %p [%u]: flags %#x m (%p) != %p (%p)", __func__, 2031 consumer, consumer - txq->txq_first, txbd_flags, 2032 m, &txq->txq_lmbufs[consumer-txq->txq_first], 2033 txq->txq_lmbufs[consumer-txq->txq_first])); 2034 #endif 2035 KASSERT(m); 2036 pq3etsec_txq_map_unload(sc, txq, m); 2037 #if 0 2038 printf("%s: mbuf %p: consumed a %u byte packet\n", 2039 __func__, m, m->m_pkthdr.len); 2040 #endif 2041 if (m->m_flags & M_HASFCB) 2042 m_adj(m, sizeof(struct txfcb)); 2043 ifp->if_opackets++; 2044 ifp->if_obytes += m->m_pkthdr.len; 2045 if (m->m_flags & M_MCAST) 2046 ifp->if_omcasts++; 2047 if (txbd_flags & TXBD_ERRORS) 2048 ifp->if_oerrors++; 2049 m_freem(m); 2050 #ifdef ETSEC_DEBUG 2051 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2052 #endif 2053 } else { 2054 #ifdef ETSEC_DEBUG 2055 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2056 #endif 2057 } 2058 2059 /* 2060 * We own this packet again. Clear all flags except wrap. 2061 */ 2062 txfree++; 2063 //consumer->txbd_flags = txbd_flags & TXBD_W; 2064 2065 /* 2066 * Wrap at the last entry! 2067 */ 2068 if (txbd_flags & TXBD_W) { 2069 KASSERT(consumer + 1 == txq->txq_last); 2070 consumer = txq->txq_first; 2071 } else { 2072 consumer++; 2073 KASSERT(consumer < txq->txq_last); 2074 } 2075 } 2076 } 2077 2078 static void 2079 pq3etsec_txq_purge( 2080 struct pq3etsec_softc *sc, 2081 struct pq3etsec_txqueue *txq) 2082 { 2083 struct mbuf *m; 2084 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2085 2086 for (;;) { 2087 IF_DEQUEUE(&txq->txq_mbufs, m); 2088 if (m == NULL) 2089 break; 2090 pq3etsec_txq_map_unload(sc, txq, m); 2091 m_freem(m); 2092 } 2093 if ((m = txq->txq_next) != NULL) { 2094 txq->txq_next = NULL; 2095 pq3etsec_txq_map_unload(sc, txq, m); 2096 m_freem(m); 2097 } 2098 #ifdef ETSEC_DEBUG 2099 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2100 #endif 2101 } 2102 2103 static void 2104 pq3etsec_txq_reset( 2105 struct pq3etsec_softc *sc, 2106 struct pq3etsec_txqueue *txq) 2107 { 2108 /* 2109 * sync all the descriptors 2110 */ 2111 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2112 txq->txq_last - txq->txq_first); 2113 2114 /* 2115 * Make sure we own all descriptors in the ring. 2116 */ 2117 volatile struct txbd *txbd; 2118 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2119 txbd->txbd_flags = 0; 2120 } 2121 2122 /* 2123 * Last descriptor has the wrap flag. 2124 */ 2125 txbd->txbd_flags = TXBD_W; 2126 2127 /* 2128 * Reset the producer consumer indexes. 2129 */ 2130 txq->txq_consumer = txq->txq_first; 2131 txq->txq_producer = txq->txq_first; 2132 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2133 txq->txq_threshold = txq->txq_free / 2; 2134 txq->txq_lastintr = 0; 2135 2136 /* 2137 * What do we want to get interrupted on? 2138 */ 2139 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE; 2140 2141 /* 2142 * Restart the transmit at the first descriptor 2143 */ 2144 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2145 } 2146 2147 static void 2148 pq3etsec_ifstart(struct ifnet *ifp) 2149 { 2150 struct pq3etsec_softc * const sc = ifp->if_softc; 2151 2152 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2153 softint_schedule(sc->sc_soft_ih); 2154 } 2155 2156 static void 2157 pq3etsec_tx_error( 2158 struct pq3etsec_softc * const sc) 2159 { 2160 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2161 2162 pq3etsec_txq_consume(sc, txq); 2163 2164 if (pq3etsec_txq_fillable_p(sc, txq)) 2165 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2166 if (sc->sc_txerrors & (IEVENT_LC|IEVENT_CRL|IEVENT_XFUN|IEVENT_BABT)) { 2167 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2168 } 2169 2170 if (pq3etsec_txq_active_p(sc, txq)) 2171 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2172 if (!pq3etsec_txq_enqueue(sc, txq)) { 2173 sc->sc_ev_tx_stall.ev_count++; 2174 sc->sc_if.if_flags |= IFF_OACTIVE; 2175 } 2176 2177 sc->sc_txerrors = 0; 2178 } 2179 2180 int 2181 pq3etsec_tx_intr(void *arg) 2182 { 2183 struct pq3etsec_softc * const sc = arg; 2184 2185 sc->sc_ev_tx_intr.ev_count++; 2186 2187 uint32_t ievent = etsec_read(sc, IEVENT); 2188 ievent &= IEVENT_TXF|IEVENT_TXB; 2189 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2190 2191 #if 0 2192 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2193 __func__, ievent, etsec_read(sc, IMASK)); 2194 #endif 2195 2196 if (ievent == 0) 2197 return 0; 2198 2199 sc->sc_imask &= ~(IEVENT_TXF|IEVENT_TXB); 2200 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2201 etsec_write(sc, IMASK, sc->sc_imask); 2202 softint_schedule(sc->sc_soft_ih); 2203 return 1; 2204 } 2205 2206 int 2207 pq3etsec_rx_intr(void *arg) 2208 { 2209 struct pq3etsec_softc * const sc = arg; 2210 2211 sc->sc_ev_rx_intr.ev_count++; 2212 2213 uint32_t ievent = etsec_read(sc, IEVENT); 2214 ievent &= IEVENT_RXF|IEVENT_RXB; 2215 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2216 if (ievent == 0) 2217 return 0; 2218 2219 #if 0 2220 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2221 #endif 2222 2223 sc->sc_imask &= ~(IEVENT_RXF|IEVENT_RXB); 2224 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2225 etsec_write(sc, IMASK, sc->sc_imask); 2226 softint_schedule(sc->sc_soft_ih); 2227 return 1; 2228 } 2229 2230 int 2231 pq3etsec_error_intr(void *arg) 2232 { 2233 struct pq3etsec_softc * const sc = arg; 2234 2235 sc->sc_ev_error_intr.ev_count++; 2236 2237 for (int rv = 0, soft_flags = 0;; rv = 1) { 2238 uint32_t ievent = etsec_read(sc, IEVENT); 2239 ievent &= ~(IEVENT_RXF|IEVENT_RXB|IEVENT_TXF|IEVENT_TXB); 2240 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2241 if (ievent == 0) { 2242 if (soft_flags) { 2243 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2244 softint_schedule(sc->sc_soft_ih); 2245 } 2246 return rv; 2247 } 2248 #if 0 2249 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2250 __func__, ievent, etsec_read(sc, IMASK)); 2251 #endif 2252 2253 if (ievent & (IEVENT_GRSC|IEVENT_GTSC)) { 2254 sc->sc_imask &= ~(IEVENT_GRSC|IEVENT_GTSC); 2255 etsec_write(sc, IMASK, sc->sc_imask); 2256 wakeup(sc); 2257 } 2258 if (ievent & (IEVENT_MMRD|IEVENT_MMWR)) { 2259 sc->sc_imask &= ~(IEVENT_MMRD|IEVENT_MMWR); 2260 etsec_write(sc, IMASK, sc->sc_imask); 2261 wakeup(&sc->sc_mii); 2262 } 2263 if (ievent & IEVENT_BSY) { 2264 soft_flags |= SOFT_RXBSY; 2265 sc->sc_imask &= ~IEVENT_BSY; 2266 etsec_write(sc, IMASK, sc->sc_imask); 2267 } 2268 if (ievent & IEVENT_TXE) { 2269 soft_flags |= SOFT_TXERROR; 2270 sc->sc_imask &= ~IEVENT_TXE; 2271 sc->sc_txerrors |= ievent; 2272 } 2273 if (ievent & IEVENT_TXC) { 2274 sc->sc_ev_tx_pause.ev_count++; 2275 } 2276 if (ievent & IEVENT_RXC) { 2277 sc->sc_ev_rx_pause.ev_count++; 2278 } 2279 if (ievent & IEVENT_DPE) { 2280 soft_flags |= SOFT_RESET; 2281 sc->sc_imask &= ~IEVENT_DPE; 2282 etsec_write(sc, IMASK, sc->sc_imask); 2283 } 2284 } 2285 } 2286 2287 void 2288 pq3etsec_soft_intr(void *arg) 2289 { 2290 struct pq3etsec_softc * const sc = arg; 2291 struct ifnet * const ifp = &sc->sc_if; 2292 2293 mutex_enter(sc->sc_lock); 2294 2295 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2296 2297 sc->sc_ev_soft_intr.ev_count++; 2298 2299 if (soft_flags & SOFT_RESET) { 2300 int s = splnet(); 2301 pq3etsec_ifinit(ifp); 2302 splx(s); 2303 soft_flags = 0; 2304 } 2305 2306 if (soft_flags & SOFT_RXBSY) { 2307 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2308 size_t threshold = 5 * rxq->rxq_threshold / 4; 2309 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2310 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2311 } else { 2312 sc->sc_imask |= IEVENT_BSY; 2313 } 2314 aprint_normal_dev(sc->sc_dev, 2315 "increasing receive buffers from %zu to %zu\n", 2316 rxq->rxq_threshold, threshold); 2317 rxq->rxq_threshold = threshold; 2318 } 2319 2320 if ((soft_flags & SOFT_TXINTR) 2321 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2322 /* 2323 * Let's do what we came here for. Consume transmitted 2324 * packets off the the transmit ring. 2325 */ 2326 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2327 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2328 sc->sc_ev_tx_stall.ev_count++; 2329 ifp->if_flags |= IFF_OACTIVE; 2330 } else { 2331 ifp->if_flags &= ~IFF_OACTIVE; 2332 } 2333 sc->sc_imask |= IEVENT_TXF; 2334 } 2335 2336 if (soft_flags & (SOFT_RXINTR|SOFT_RXBSY)) { 2337 /* 2338 * Let's consume 2339 */ 2340 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2341 sc->sc_imask |= IEVENT_RXF; 2342 } 2343 2344 if (soft_flags & SOFT_TXERROR) { 2345 pq3etsec_tx_error(sc); 2346 sc->sc_imask |= IEVENT_TXE; 2347 } 2348 2349 if (ifp->if_flags & IFF_RUNNING) { 2350 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2351 etsec_write(sc, IMASK, sc->sc_imask); 2352 } else { 2353 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2354 } 2355 2356 mutex_exit(sc->sc_lock); 2357 } 2358 2359 static void 2360 pq3etsec_mii_tick(void *arg) 2361 { 2362 struct pq3etsec_softc * const sc = arg; 2363 mutex_enter(sc->sc_lock); 2364 callout_ack(&sc->sc_mii_callout); 2365 sc->sc_ev_mii_ticks.ev_count++; 2366 #ifdef DEBUG 2367 uint64_t now = mftb(); 2368 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2369 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2370 __func__, now - sc->sc_mii_last_tick); 2371 callout_stop(&sc->sc_mii_callout); 2372 } 2373 #endif 2374 mii_tick(&sc->sc_mii); 2375 int s = splnet(); 2376 if (sc->sc_soft_flags & SOFT_RESET) 2377 softint_schedule(sc->sc_soft_ih); 2378 splx(s); 2379 callout_schedule(&sc->sc_mii_callout, hz); 2380 sc->sc_mii_last_tick = now; 2381 mutex_exit(sc->sc_lock); 2382 } 2383
Indexes created Thu Oct 02 14:10:14 GMT 2025