pq3etsec.c revision 1.21
1 /* $NetBSD: pq3etsec.c,v 1.21 2015/01/16 05:50:15 nonaka Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_inet.h" 38 #include "opt_mpc85xx.h" 39 40 #include <sys/cdefs.h> 41 42 __KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.21 2015/01/16 05:50:15 nonaka Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/cpu.h> 46 #include <sys/device.h> 47 #include <sys/mbuf.h> 48 #include <sys/ioctl.h> 49 #include <sys/intr.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/kmem.h> 53 #include <sys/proc.h> 54 #include <sys/atomic.h> 55 #include <sys/callout.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_ether.h> 60 #include <net/if_media.h> 61 62 #include <dev/mii/miivar.h> 63 64 #include <net/bpf.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/ip.h> 70 #include <netinet/in_offload.h> 71 #endif /* INET */ 72 #ifdef INET6 73 #include <netinet6/in6.h> 74 #include <netinet/ip6.h> 75 #endif 76 #include <netinet6/in6_offload.h> 77 78 79 #include <powerpc/spr.h> 80 #include <powerpc/booke/spr.h> 81 82 #include <powerpc/booke/cpuvar.h> 83 #include <powerpc/booke/e500var.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/etsecreg.h> 86 87 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 88 89 #define ETSEC_MAXTXMBUFS 30 90 #define ETSEC_NTXSEGS 30 91 #define ETSEC_MAXRXMBUFS 511 92 #define ETSEC_MINRXMBUFS 32 93 #define ETSEC_NRXSEGS 1 94 95 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 96 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx\ 97 |IFCAP_CSUM_UDPv4_Rx\ 98 |IFCAP_CSUM_TCPv6_Rx\ 99 |IFCAP_CSUM_UDPv6_Rx) 100 101 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 102 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx\ 103 |IFCAP_CSUM_UDPv4_Tx\ 104 |IFCAP_CSUM_TCPv6_Tx\ 105 |IFCAP_CSUM_UDPv6_Tx) 106 107 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN|IFCAP_RCTRL_TUCSEN\ 108 |IFCAP_TCTRL_IPCSEN|IFCAP_TCTRL_TUCSEN) 109 110 #define M_CSUM_IP (M_CSUM_CIP|M_CSUM_CTU) 111 #define M_CSUM_IP6 (M_CSUM_TCPv6|M_CSUM_UDPv6) 112 #define M_CSUM_TUP (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 113 #define M_CSUM_UDP (M_CSUM_UDPv4|M_CSUM_UDPv6) 114 #define M_CSUM_IP4 (M_CSUM_IPv4|M_CSUM_UDPv4|M_CSUM_TCPv4) 115 #define M_CSUM_CIP (M_CSUM_IPv4) 116 #define M_CSUM_CTU (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 117 118 struct pq3etsec_txqueue { 119 bus_dmamap_t txq_descmap; 120 volatile struct txbd *txq_consumer; 121 volatile struct txbd *txq_producer; 122 volatile struct txbd *txq_first; 123 volatile struct txbd *txq_last; 124 struct ifqueue txq_mbufs; 125 struct mbuf *txq_next; 126 #ifdef ETSEC_DEBUG 127 struct mbuf *txq_lmbufs[512]; 128 #endif 129 uint32_t txq_qmask; 130 uint32_t txq_free; 131 uint32_t txq_threshold; 132 uint32_t txq_lastintr; 133 bus_size_t txq_reg_tbase; 134 bus_dma_segment_t txq_descmap_seg; 135 }; 136 137 struct pq3etsec_rxqueue { 138 bus_dmamap_t rxq_descmap; 139 volatile struct rxbd *rxq_consumer; 140 volatile struct rxbd *rxq_producer; 141 volatile struct rxbd *rxq_first; 142 volatile struct rxbd *rxq_last; 143 struct mbuf *rxq_mhead; 144 struct mbuf **rxq_mtail; 145 struct mbuf *rxq_mconsumer; 146 #ifdef ETSEC_DEBUG 147 struct mbuf *rxq_mbufs[512]; 148 #endif 149 uint32_t rxq_qmask; 150 uint32_t rxq_inuse; 151 uint32_t rxq_threshold; 152 bus_size_t rxq_reg_rbase; 153 bus_size_t rxq_reg_rbptr; 154 bus_dma_segment_t rxq_descmap_seg; 155 }; 156 157 struct pq3etsec_mapcache { 158 u_int dmc_nmaps; 159 u_int dmc_maxseg; 160 u_int dmc_maxmaps; 161 u_int dmc_maxmapsize; 162 bus_dmamap_t dmc_maps[0]; 163 }; 164 165 struct pq3etsec_softc { 166 device_t sc_dev; 167 device_t sc_mdio_dev; 168 struct ethercom sc_ec; 169 #define sc_if sc_ec.ec_if 170 struct mii_data sc_mii; 171 bus_space_tag_t sc_bst; 172 bus_space_handle_t sc_bsh; 173 bus_space_handle_t sc_mdio_bsh; 174 bus_dma_tag_t sc_dmat; 175 int sc_phy_addr; 176 prop_dictionary_t sc_intrmap; 177 uint32_t sc_intrmask; 178 179 uint32_t sc_soft_flags; 180 #define SOFT_RESET 0x0001 181 #define SOFT_RXINTR 0x0010 182 #define SOFT_RXBSY 0x0020 183 #define SOFT_TXINTR 0x0100 184 #define SOFT_TXERROR 0x0200 185 186 struct pq3etsec_txqueue sc_txq; 187 struct pq3etsec_rxqueue sc_rxq; 188 uint32_t sc_txerrors; 189 uint32_t sc_rxerrors; 190 191 size_t sc_rx_adjlen; 192 193 /* 194 * Copies of various ETSEC registers. 195 */ 196 uint32_t sc_imask; 197 uint32_t sc_maccfg1; 198 uint32_t sc_maccfg2; 199 uint32_t sc_maxfrm; 200 uint32_t sc_ecntrl; 201 uint32_t sc_dmactrl; 202 uint32_t sc_macstnaddr1; 203 uint32_t sc_macstnaddr2; 204 uint32_t sc_tctrl; 205 uint32_t sc_rctrl; 206 uint32_t sc_gaddr[16]; 207 uint64_t sc_macaddrs[15]; 208 209 void *sc_tx_ih; 210 void *sc_rx_ih; 211 void *sc_error_ih; 212 void *sc_soft_ih; 213 214 kmutex_t *sc_lock; 215 216 struct evcnt sc_ev_tx_stall; 217 struct evcnt sc_ev_tx_intr; 218 struct evcnt sc_ev_rx_stall; 219 struct evcnt sc_ev_rx_intr; 220 struct evcnt sc_ev_error_intr; 221 struct evcnt sc_ev_soft_intr; 222 struct evcnt sc_ev_tx_pause; 223 struct evcnt sc_ev_rx_pause; 224 struct evcnt sc_ev_mii_ticks; 225 226 struct callout sc_mii_callout; 227 uint64_t sc_mii_last_tick; 228 229 struct ifqueue sc_rx_bufcache; 230 struct pq3etsec_mapcache *sc_rx_mapcache; 231 struct pq3etsec_mapcache *sc_tx_mapcache; 232 }; 233 234 struct pq3mdio_softc { 235 device_t mdio_dev; 236 237 kmutex_t *mdio_lock; 238 239 bus_space_tag_t mdio_bst; 240 bus_space_handle_t mdio_bsh; 241 }; 242 243 static int pq3etsec_match(device_t, cfdata_t, void *); 244 static void pq3etsec_attach(device_t, device_t, void *); 245 246 static int pq3mdio_match(device_t, cfdata_t, void *); 247 static void pq3mdio_attach(device_t, device_t, void *); 248 249 static void pq3etsec_ifstart(struct ifnet *); 250 static void pq3etsec_ifwatchdog(struct ifnet *); 251 static int pq3etsec_ifinit(struct ifnet *); 252 static void pq3etsec_ifstop(struct ifnet *, int); 253 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 254 255 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 256 struct pq3etsec_mapcache **, size_t, size_t, size_t); 257 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 258 struct pq3etsec_mapcache *); 259 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 260 struct pq3etsec_mapcache *); 261 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 262 struct pq3etsec_mapcache *, bus_dmamap_t); 263 264 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 265 struct pq3etsec_txqueue *, u_int); 266 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 267 struct pq3etsec_txqueue *); 268 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 269 struct pq3etsec_txqueue *); 270 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 271 struct pq3etsec_txqueue *); 272 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 273 struct pq3etsec_txqueue *, struct mbuf *m); 274 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 275 struct pq3etsec_txqueue *); 276 277 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 278 struct pq3etsec_rxqueue *, u_int); 279 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 280 struct pq3etsec_rxqueue *); 281 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 282 struct pq3etsec_rxqueue *, bool); 283 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 284 struct pq3etsec_rxqueue *); 285 286 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 287 288 static void pq3etsec_mii_tick(void *); 289 static int pq3etsec_rx_intr(void *); 290 static int pq3etsec_tx_intr(void *); 291 static int pq3etsec_error_intr(void *); 292 static void pq3etsec_soft_intr(void *); 293 294 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 295 pq3etsec_match, pq3etsec_attach, NULL, NULL); 296 297 CFATTACH_DECL_NEW(pq3mdio_tsec, sizeof(struct pq3mdio_softc), 298 pq3mdio_match, pq3mdio_attach, NULL, NULL); 299 300 CFATTACH_DECL_NEW(pq3mdio_cpunode, sizeof(struct pq3mdio_softc), 301 pq3mdio_match, pq3mdio_attach, NULL, NULL); 302 303 static inline uint32_t 304 etsec_mdio_read(struct pq3mdio_softc *mdio, bus_size_t off) 305 { 306 return bus_space_read_4(mdio->mdio_bst, mdio->mdio_bsh, off); 307 } 308 309 static inline void 310 etsec_mdio_write(struct pq3mdio_softc *mdio, bus_size_t off, uint32_t data) 311 { 312 bus_space_write_4(mdio->mdio_bst, mdio->mdio_bsh, off, data); 313 } 314 315 static inline uint32_t 316 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 317 { 318 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 319 } 320 321 static int 322 pq3mdio_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 323 { 324 return strcmp(cf->cf_name, "mdio") == 0; 325 } 326 327 static int 328 pq3mdio_match(device_t parent, cfdata_t cf, void *aux) 329 { 330 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 331 const bool p1025_p = (svr == (SVR_P1025v1 >> 16) 332 || svr == (SVR_P1016v1 >> 16)); 333 334 if (device_is_a(parent, "cpunode")) { 335 if (!p1025_p 336 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 337 return 0; 338 339 return 1; 340 } 341 342 if (device_is_a(parent, "tsec")) { 343 if (p1025_p 344 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 345 return 0; 346 347 return 1; 348 } 349 350 return 0; 351 } 352 353 static void 354 pq3mdio_attach(device_t parent, device_t self, void *aux) 355 { 356 struct pq3mdio_softc * const mdio = device_private(self); 357 struct cpunode_attach_args * const cna = aux; 358 struct cpunode_locators * const cnl = &cna->cna_locs; 359 360 mdio->mdio_dev = self; 361 mdio->mdio_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 362 363 if (device_is_a(parent, "cpunode")) { 364 struct cpunode_softc * const psc = device_private(parent); 365 psc->sc_children |= cna->cna_childmask; 366 367 mdio->mdio_bst = cna->cna_memt; 368 if (bus_space_map(mdio->mdio_bst, cnl->cnl_addr, 369 cnl->cnl_size, 0, &mdio->mdio_bsh) != 0) { 370 aprint_error(": error mapping registers @ %#x\n", 371 cnl->cnl_addr); 372 return; 373 } 374 } else { 375 struct pq3etsec_softc * const sc = device_private(parent); 376 377 KASSERT(device_is_a(parent, "tsec")); 378 KASSERTMSG(cnl->cnl_addr == ETSEC1_BASE 379 || cnl->cnl_addr == ETSEC2_BASE 380 || cnl->cnl_addr == ETSEC3_BASE 381 || cnl->cnl_addr == ETSEC4_BASE, 382 "unknown tsec addr %x", cnl->cnl_addr); 383 384 mdio->mdio_bst = sc->sc_bst; 385 mdio->mdio_bsh = sc->sc_bsh; 386 } 387 388 aprint_normal("\n"); 389 } 390 391 static int 392 pq3mdio_mii_readreg(device_t self, int phy, int reg) 393 { 394 struct pq3mdio_softc * const mdio = device_private(self); 395 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 396 397 mutex_enter(mdio->mdio_lock); 398 399 etsec_mdio_write(mdio, MIIMADD, 400 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 401 402 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 403 etsec_mdio_write(mdio, MIIMCOM, MIIMCOM_READ); 404 405 while (etsec_mdio_read(mdio, MIIMIND) != 0) { 406 delay(1); 407 } 408 int data = etsec_mdio_read(mdio, MIIMSTAT); 409 410 if (miimcom == MIIMCOM_SCAN) 411 etsec_mdio_write(mdio, MIIMCOM, miimcom); 412 413 #if 0 414 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 415 __func__, phy, reg, data); 416 #endif 417 mutex_exit(mdio->mdio_lock); 418 return data; 419 } 420 421 static void 422 pq3mdio_mii_writereg(device_t self, int phy, int reg, int data) 423 { 424 struct pq3mdio_softc * const mdio = device_private(self); 425 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 426 427 #if 0 428 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 429 __func__, phy, reg, data); 430 #endif 431 432 mutex_enter(mdio->mdio_lock); 433 434 etsec_mdio_write(mdio, MIIMADD, 435 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 436 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 437 etsec_mdio_write(mdio, MIIMCON, data); 438 439 int timo = 1000; /* 1ms */ 440 while ((etsec_mdio_read(mdio, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 441 delay(1); 442 } 443 444 if (miimcom == MIIMCOM_SCAN) 445 etsec_mdio_write(mdio, MIIMCOM, miimcom); 446 447 mutex_exit(mdio->mdio_lock); 448 } 449 450 static inline void 451 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 452 { 453 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 454 } 455 456 static void 457 pq3etsec_mii_statchg(struct ifnet *ifp) 458 { 459 struct pq3etsec_softc * const sc = ifp->if_softc; 460 struct mii_data * const mii = &sc->sc_mii; 461 462 uint32_t maccfg1 = sc->sc_maccfg1; 463 uint32_t maccfg2 = sc->sc_maccfg2; 464 uint32_t ecntrl = sc->sc_ecntrl; 465 466 maccfg1 &= ~(MACCFG1_TX_FLOW|MACCFG1_RX_FLOW); 467 maccfg2 &= ~(MACCFG2_IFMODE|MACCFG2_FD); 468 469 if (sc->sc_mii.mii_media_active & IFM_FDX) { 470 maccfg2 |= MACCFG2_FD; 471 } 472 473 /* 474 * Now deal with the flow control bits. 475 */ 476 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 477 && (mii->mii_media_active & IFM_ETH_FMASK)) { 478 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 479 maccfg1 |= MACCFG1_RX_FLOW; 480 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 481 maccfg1 |= MACCFG1_TX_FLOW; 482 } 483 484 /* 485 * Now deal with the speed. 486 */ 487 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 488 maccfg2 |= MACCFG2_IFMODE_GMII; 489 } else { 490 maccfg2 |= MACCFG2_IFMODE_MII; 491 ecntrl &= ~ECNTRL_R100M; 492 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 493 ecntrl |= ECNTRL_R100M; 494 } 495 } 496 497 /* 498 * If things are different, re-init things. 499 */ 500 if (maccfg1 != sc->sc_maccfg1 501 || maccfg2 != sc->sc_maccfg2 502 || ecntrl != sc->sc_ecntrl) { 503 if (sc->sc_if.if_flags & IFF_RUNNING) 504 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 505 sc->sc_maccfg1 = maccfg1; 506 sc->sc_maccfg2 = maccfg2; 507 sc->sc_ecntrl = ecntrl; 508 } 509 } 510 511 #if 0 512 static void 513 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 514 { 515 struct pq3etsec_softc * const sc = ifp->if_softc; 516 517 mii_pollstat(&sc->sc_mii); 518 ether_mediastatus(ifp, ifmr); 519 ifmr->ifm_status = sc->sc_mii.mii_media_status; 520 ifmr->ifm_active = sc->sc_mii.mii_media_active; 521 } 522 523 static int 524 pq3etsec_mediachange(struct ifnet *ifp) 525 { 526 struct pq3etsec_softc * const sc = ifp->if_softc; 527 528 if ((ifp->if_flags & IFF_UP) == 0) 529 return 0; 530 531 int rv = mii_mediachg(&sc->sc_mii); 532 return (rv == ENXIO) ? 0 : rv; 533 } 534 #endif 535 536 static int 537 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 538 { 539 540 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 541 return 0; 542 543 return 1; 544 } 545 546 static void 547 pq3etsec_attach(device_t parent, device_t self, void *aux) 548 { 549 struct cpunode_softc * const psc = device_private(parent); 550 struct pq3etsec_softc * const sc = device_private(self); 551 struct cpunode_attach_args * const cna = aux; 552 struct cpunode_locators * const cnl = &cna->cna_locs; 553 cfdata_t cf = device_cfdata(self); 554 int error; 555 556 psc->sc_children |= cna->cna_childmask; 557 sc->sc_dev = self; 558 sc->sc_bst = cna->cna_memt; 559 sc->sc_dmat = &booke_bus_dma_tag; 560 561 /* 562 * Pull out the mdio bus and phy we are supposed to use. 563 */ 564 const int mdio = cf->cf_loc[CPUNODECF_MDIO]; 565 const int phy = cf->cf_loc[CPUNODECF_PHY]; 566 if (mdio != CPUNODECF_MDIO_DEFAULT) 567 aprint_normal(" mdio %d", mdio); 568 569 /* 570 * See if the phy is in the config file... 571 */ 572 if (phy != CPUNODECF_PHY_DEFAULT) { 573 sc->sc_phy_addr = phy; 574 } else { 575 unsigned char prop_name[20]; 576 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 577 cnl->cnl_instance); 578 sc->sc_phy_addr = board_info_get_number(prop_name); 579 } 580 if (sc->sc_phy_addr != MII_PHY_ANY) 581 aprint_normal(" phy %d", sc->sc_phy_addr); 582 583 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 584 &sc->sc_bsh); 585 if (error) { 586 aprint_error(": error mapping registers: %d\n", error); 587 return; 588 } 589 590 /* 591 * Assume firmware has aready set the mac address and fetch it 592 * before we reinit it. 593 */ 594 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 595 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 596 sc->sc_rctrl = RCTRL_DEFAULT; 597 sc->sc_ecntrl = etsec_read(sc, ECNTRL); 598 sc->sc_maccfg1 = etsec_read(sc, MACCFG1); 599 sc->sc_maccfg2 = etsec_read(sc, MACCFG2) | MACCFG2_DEFAULT; 600 601 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 602 size_t len; 603 const uint8_t *mac_addr = 604 board_info_get_data("tsec-mac-addr-base", &len); 605 KASSERT(len == ETHER_ADDR_LEN); 606 sc->sc_macstnaddr2 = 607 (mac_addr[1] << 24) 608 | (mac_addr[0] << 16); 609 sc->sc_macstnaddr1 = 610 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 611 | (mac_addr[4] << 16) 612 | (mac_addr[3] << 8) 613 | (mac_addr[2] << 0); 614 #if 0 615 aprint_error(": mac-address unknown\n"); 616 return; 617 #endif 618 } 619 620 char enaddr[ETHER_ADDR_LEN] = { 621 [0] = sc->sc_macstnaddr2 >> 16, 622 [1] = sc->sc_macstnaddr2 >> 24, 623 [2] = sc->sc_macstnaddr1 >> 0, 624 [3] = sc->sc_macstnaddr1 >> 8, 625 [4] = sc->sc_macstnaddr1 >> 16, 626 [5] = sc->sc_macstnaddr1 >> 24, 627 }; 628 629 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 630 if (error) { 631 aprint_error(": failed to init rxq: %d\n", error); 632 return; 633 } 634 635 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 636 if (error) { 637 aprint_error(": failed to init txq: %d\n", error); 638 return; 639 } 640 641 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 642 ETSEC_MAXRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 643 if (error) { 644 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 645 return; 646 } 647 648 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 649 ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 650 if (error) { 651 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 652 return; 653 } 654 655 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 656 pq3etsec_tx_intr, sc); 657 if (sc->sc_tx_ih == NULL) { 658 aprint_error(": failed to establish tx interrupt: %d\n", 659 cnl->cnl_intrs[0]); 660 return; 661 } 662 663 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 664 pq3etsec_rx_intr, sc); 665 if (sc->sc_rx_ih == NULL) { 666 aprint_error(": failed to establish rx interrupt: %d\n", 667 cnl->cnl_intrs[1]); 668 return; 669 } 670 671 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 672 pq3etsec_error_intr, sc); 673 if (sc->sc_error_ih == NULL) { 674 aprint_error(": failed to establish error interrupt: %d\n", 675 cnl->cnl_intrs[2]); 676 return; 677 } 678 679 sc->sc_soft_ih = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 680 pq3etsec_soft_intr, sc); 681 if (sc->sc_soft_ih == NULL) { 682 aprint_error(": failed to establish soft interrupt\n"); 683 return; 684 } 685 686 /* 687 * If there was no MDIO 688 */ 689 if (mdio == CPUNODECF_MDIO_DEFAULT) { 690 aprint_normal("\n"); 691 cfdata_t mdio_cf = config_search_ia(pq3mdio_find, self, NULL, cna); 692 if (mdio_cf != NULL) { 693 sc->sc_mdio_dev = config_attach(self, mdio_cf, cna, NULL); 694 } 695 } else { 696 sc->sc_mdio_dev = device_find_by_driver_unit("mdio", mdio); 697 if (sc->sc_mdio_dev == NULL) { 698 aprint_error(": failed to locate mdio device\n"); 699 return; 700 } 701 aprint_normal("\n"); 702 } 703 704 etsec_write(sc, ATTR, ATTR_DEFAULT); 705 etsec_write(sc, ATTRELI, ATTRELI_DEFAULT); 706 707 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 708 709 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 710 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 711 712 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 713 ether_sprintf(enaddr)); 714 715 const char * const xname = device_xname(sc->sc_dev); 716 struct ethercom * const ec = &sc->sc_ec; 717 struct ifnet * const ifp = &ec->ec_if; 718 719 ec->ec_mii = &sc->sc_mii; 720 721 sc->sc_mii.mii_ifp = ifp; 722 sc->sc_mii.mii_readreg = pq3mdio_mii_readreg; 723 sc->sc_mii.mii_writereg = pq3mdio_mii_writereg; 724 sc->sc_mii.mii_statchg = pq3etsec_mii_statchg; 725 726 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 727 ether_mediastatus); 728 729 if (sc->sc_mdio_dev != NULL && sc->sc_phy_addr < 32) { 730 mii_attach(sc->sc_mdio_dev, &sc->sc_mii, 0xffffffff, 731 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 732 733 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 734 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 735 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 736 } else { 737 callout_schedule(&sc->sc_mii_callout, hz); 738 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 739 } 740 } else { 741 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 742 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX); 743 } 744 745 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 746 | ETHERCAP_JUMBO_MTU; 747 748 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 749 ifp->if_softc = sc; 750 ifp->if_capabilities = IFCAP_ETSEC; 751 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 752 ifp->if_ioctl = pq3etsec_ifioctl; 753 ifp->if_start = pq3etsec_ifstart; 754 ifp->if_watchdog = pq3etsec_ifwatchdog; 755 ifp->if_init = pq3etsec_ifinit; 756 ifp->if_stop = pq3etsec_ifstop; 757 IFQ_SET_READY(&ifp->if_snd); 758 759 pq3etsec_ifstop(ifp, true); 760 761 /* 762 * Attach the interface. 763 */ 764 if_initialize(ifp); 765 ether_ifattach(ifp, enaddr); 766 if_register(ifp); 767 768 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 769 NULL, xname, "rx stall"); 770 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 771 NULL, xname, "tx stall"); 772 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 773 NULL, xname, "tx intr"); 774 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 775 NULL, xname, "rx intr"); 776 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 777 NULL, xname, "error intr"); 778 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 779 NULL, xname, "soft intr"); 780 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 781 NULL, xname, "tx pause"); 782 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 783 NULL, xname, "rx pause"); 784 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 785 NULL, xname, "mii ticks"); 786 } 787 788 static uint64_t 789 pq3etsec_macaddr_create(const uint8_t *lladdr) 790 { 791 uint64_t macaddr = 0; 792 793 lladdr += ETHER_ADDR_LEN; 794 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 795 macaddr = (macaddr << 8) | *--lladdr; 796 } 797 return macaddr << 16; 798 } 799 800 static int 801 pq3etsec_ifinit(struct ifnet *ifp) 802 { 803 struct pq3etsec_softc * const sc = ifp->if_softc; 804 int error = 0; 805 806 sc->sc_maxfrm = max(ifp->if_mtu + 32, MCLBYTES); 807 if (ifp->if_mtu > ETHERMTU_JUMBO) 808 return error; 809 810 KASSERT(ifp->if_flags & IFF_UP); 811 812 /* 813 * Stop the interface (steps 1 to 4 in the Soft Reset and 814 * Reconfigurating Procedure. 815 */ 816 pq3etsec_ifstop(ifp, 0); 817 818 /* 819 * If our frame size has changed (or it's our first time through) 820 * destroy the existing transmit mapcache. 821 */ 822 if (sc->sc_tx_mapcache != NULL 823 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 824 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 825 sc->sc_tx_mapcache = NULL; 826 } 827 828 if (sc->sc_tx_mapcache == NULL) { 829 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 830 ETSEC_MAXTXMBUFS, sc->sc_maxfrm, ETSEC_NTXSEGS); 831 if (error) 832 return error; 833 } 834 835 sc->sc_ev_mii_ticks.ev_count++; 836 mii_tick(&sc->sc_mii); 837 838 if (ifp->if_flags & IFF_PROMISC) { 839 sc->sc_rctrl |= RCTRL_PROM; 840 } else { 841 sc->sc_rctrl &= ~RCTRL_PROM; 842 } 843 844 uint32_t rctrl_prsdep = 0; 845 sc->sc_rctrl &= ~(RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP); 846 if (VLAN_ATTACHED(&sc->sc_ec)) { 847 sc->sc_rctrl |= RCTRL_VLEX; 848 rctrl_prsdep = RCTRL_PRSDEP_L2; 849 } 850 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 851 sc->sc_rctrl |= RCTRL_IPCSEN; 852 rctrl_prsdep = RCTRL_PRSDEP_L3; 853 } 854 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 855 sc->sc_rctrl |= RCTRL_TUCSEN; 856 rctrl_prsdep = RCTRL_PRSDEP_L4; 857 } 858 sc->sc_rctrl |= rctrl_prsdep; 859 #if 0 860 if (sc->sc_rctrl & (RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP)) 861 aprint_normal_dev(sc->sc_dev, 862 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 863 sc->sc_rctrl, 864 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 865 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 866 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 867 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 868 #endif 869 870 sc->sc_tctrl &= ~(TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS); 871 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 872 sc->sc_tctrl |= TCTRL_VLINS; 873 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 874 sc->sc_tctrl |= TCTRL_IPCSEN; 875 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 876 sc->sc_tctrl |= TCTRL_TUCSEN; 877 #if 0 878 if (sc->sc_tctrl & (TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS)) 879 aprint_normal_dev(sc->sc_dev, 880 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 881 sc->sc_tctrl, 882 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 883 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 884 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 885 #endif 886 887 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN|MACCFG1_RX_EN); 888 889 const uint64_t macstnaddr = 890 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 891 892 sc->sc_imask = IEVENT_DPE; 893 894 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 895 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 896 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 897 898 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 899 pq3etsec_txq_reset(sc, &sc->sc_txq); 900 901 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 902 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 903 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 904 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 905 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 906 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 907 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 908 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 909 910 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 911 pq3etsec_mc_setup(sc); 912 913 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 914 etsec_write(sc, MRBLR, MCLBYTES); 915 916 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 917 sc->sc_dmactrl |= DMACTRL_DEFAULT; 918 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 919 920 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 921 etsec_write(sc, TQUEUE, TQUEUE_EN0); 922 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE|IEVENT_TXC; 923 924 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 925 926 /* 12. Enable receive queues in RQUEUE, */ 927 etsec_write(sc, RQUEUE, RQUEUE_EN0|RQUEUE_EX0); 928 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY|IEVENT_RXC; 929 930 /* and optionally set TOE functionality in RCTRL. */ 931 etsec_write(sc, RCTRL, sc->sc_rctrl); 932 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 933 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 934 sc->sc_rx_adjlen += sizeof(struct rxfcb); 935 936 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 937 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 938 939 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 940 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 941 942 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 943 sc->sc_dmactrl &= ~(DMACTRL_GRS|DMACTRL_GTS); 944 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 945 946 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 947 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 948 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 949 950 sc->sc_soft_flags = 0; 951 952 etsec_write(sc, IMASK, sc->sc_imask); 953 954 ifp->if_flags |= IFF_RUNNING; 955 956 return error; 957 } 958 959 static void 960 pq3etsec_ifstop(struct ifnet *ifp, int disable) 961 { 962 struct pq3etsec_softc * const sc = ifp->if_softc; 963 964 KASSERT(!cpu_intr_p()); 965 const uint32_t imask_gsc_mask = IEVENT_GTSC|IEVENT_GRSC; 966 /* 967 * Clear the GTSC and GRSC from the interrupt mask until 968 * we are ready for them. Then clear them from IEVENT, 969 * request the graceful shutdown, and then enable the 970 * GTSC and GRSC bits in the mask. This should cause the 971 * error interrupt to fire which will issue a wakeup to 972 * allow us to resume. 973 */ 974 975 /* 976 * 1. Set GRS/GTS bits in DMACTRL register 977 */ 978 sc->sc_dmactrl |= DMACTRL_GRS|DMACTRL_GTS; 979 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 980 etsec_write(sc, IEVENT, imask_gsc_mask); 981 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 982 983 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN|MACCFG1_RX_EN)) { 984 /* 985 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 986 */ 987 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 988 989 u_int timo = 1000; 990 uint32_t ievent = etsec_read(sc, IEVENT); 991 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 992 if (--timo == 0) { 993 aprint_error_dev(sc->sc_dev, 994 "WARNING: " 995 "request to stop failed (IEVENT=%#x)\n", 996 ievent); 997 break; 998 } 999 delay(10); 1000 ievent = etsec_read(sc, IEVENT); 1001 } 1002 } 1003 1004 /* 1005 * Now reset the controller. 1006 * 1007 * 3. Set SOFT_RESET bit in MACCFG1 register 1008 * 4. Clear SOFT_RESET bit in MACCFG1 register 1009 */ 1010 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 1011 etsec_write(sc, MACCFG1, 0); 1012 etsec_write(sc, IMASK, 0); 1013 etsec_write(sc, IEVENT, ~0); 1014 sc->sc_imask = 0; 1015 ifp->if_flags &= ~IFF_RUNNING; 1016 1017 uint32_t tbipa = etsec_read(sc, TBIPA); 1018 if (tbipa == sc->sc_phy_addr) { 1019 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 1020 etsec_write(sc, TBIPA, 0x1f); 1021 } 1022 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 1023 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 1024 etsec_write(sc, MIIMCFG, miimcfg); 1025 1026 /* 1027 * Let's consume any remaing transmitted packets. And if we are 1028 * disabling the interface, purge ourselves of any untransmitted 1029 * packets. But don't consume any received packets, just drop them. 1030 * If we aren't disabling the interface, save the mbufs in the 1031 * receive queue for reuse. 1032 */ 1033 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 1034 pq3etsec_txq_consume(sc, &sc->sc_txq); 1035 if (disable) { 1036 pq3etsec_txq_purge(sc, &sc->sc_txq); 1037 IFQ_PURGE(&ifp->if_snd); 1038 } 1039 } 1040 1041 static void 1042 pq3etsec_ifwatchdog(struct ifnet *ifp) 1043 { 1044 } 1045 1046 static void 1047 pq3etsec_mc_setup( 1048 struct pq3etsec_softc *sc) 1049 { 1050 struct ethercom * const ec = &sc->sc_ec; 1051 struct ifnet * const ifp = &sc->sc_if; 1052 struct ether_multi *enm; 1053 struct ether_multistep step; 1054 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 1055 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 1056 1057 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 1058 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1059 1060 ifp->if_flags &= ~IFF_ALLMULTI; 1061 1062 ETHER_FIRST_MULTI(step, ec, enm); 1063 for (u_int i = 0; enm != NULL; ) { 1064 const char *addr = enm->enm_addrlo; 1065 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1066 ifp->if_flags |= IFF_ALLMULTI; 1067 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 1068 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1069 break; 1070 } 1071 if ((sc->sc_rctrl & RCTRL_EMEN) 1072 && i < __arraycount(sc->sc_macaddrs)) { 1073 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 1074 } else { 1075 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1076 #if 0 1077 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 1078 ether_sprintf(addr), crc, 1079 crc >> crc_shift, 1080 crc >> (crc_shift + 5), 1081 (crc >> crc_shift) & 31, 1082 1 << (((crc >> crc_shift) & 31) ^ 31)); 1083 #endif 1084 /* 1085 * The documentation doesn't completely follow PowerPC 1086 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 1087 * is 0x7fa32d9b. By empirical testing, the 1088 * corresponding hash bit is word 3, bit 31 (ppc bit 1089 * order). Since 3 << 31 | 31 is 0x7f, we deduce 1090 * H[0:2] selects the register while H[3:7] selects 1091 * the bit (ppc bit order). 1092 */ 1093 crc >>= crc_shift; 1094 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 1095 } 1096 ETHER_NEXT_MULTI(step, enm); 1097 } 1098 for (u_int i = 0; i < 8; i++) { 1099 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 1100 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 1101 #if 0 1102 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 1103 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 1104 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 1105 i, GADDR(i), etsec_read(sc, GADDR(i))); 1106 #endif 1107 } 1108 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 1109 uint64_t macaddr = sc->sc_macaddrs[i]; 1110 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 1111 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 1112 #if 0 1113 if (macaddr) 1114 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 1115 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1116 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1117 #endif 1118 } 1119 } 1120 1121 static int 1122 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1123 { 1124 struct pq3etsec_softc *sc = ifp->if_softc; 1125 struct ifreq * const ifr = data; 1126 const int s = splnet(); 1127 int error; 1128 1129 switch (cmd) { 1130 case SIOCSIFMEDIA: 1131 case SIOCGIFMEDIA: 1132 /* Flow control requires full-duplex mode. */ 1133 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1134 (ifr->ifr_media & IFM_FDX) == 0) 1135 ifr->ifr_media &= ~IFM_ETH_FMASK; 1136 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1137 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1138 /* We can do both TXPAUSE and RXPAUSE. */ 1139 ifr->ifr_media |= 1140 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1141 } 1142 } 1143 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1144 break; 1145 1146 default: 1147 error = ether_ioctl(ifp, cmd, data); 1148 if (error != ENETRESET) 1149 break; 1150 1151 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1152 error = 0; 1153 if (ifp->if_flags & IFF_RUNNING) 1154 pq3etsec_mc_setup(sc); 1155 break; 1156 } 1157 error = pq3etsec_ifinit(ifp); 1158 break; 1159 } 1160 1161 splx(s); 1162 return error; 1163 } 1164 1165 static void 1166 pq3etsec_rxq_desc_presync( 1167 struct pq3etsec_softc *sc, 1168 struct pq3etsec_rxqueue *rxq, 1169 volatile struct rxbd *rxbd, 1170 size_t count) 1171 { 1172 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1173 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1174 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1175 } 1176 1177 static void 1178 pq3etsec_rxq_desc_postsync( 1179 struct pq3etsec_softc *sc, 1180 struct pq3etsec_rxqueue *rxq, 1181 volatile struct rxbd *rxbd, 1182 size_t count) 1183 { 1184 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1185 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1186 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1187 } 1188 1189 static void 1190 pq3etsec_txq_desc_presync( 1191 struct pq3etsec_softc *sc, 1192 struct pq3etsec_txqueue *txq, 1193 volatile struct txbd *txbd, 1194 size_t count) 1195 { 1196 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1197 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1198 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1199 } 1200 1201 static void 1202 pq3etsec_txq_desc_postsync( 1203 struct pq3etsec_softc *sc, 1204 struct pq3etsec_txqueue *txq, 1205 volatile struct txbd *txbd, 1206 size_t count) 1207 { 1208 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1209 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1210 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1211 } 1212 1213 static bus_dmamap_t 1214 pq3etsec_mapcache_get( 1215 struct pq3etsec_softc *sc, 1216 struct pq3etsec_mapcache *dmc) 1217 { 1218 KASSERT(dmc->dmc_nmaps > 0); 1219 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1220 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1221 } 1222 1223 static void 1224 pq3etsec_mapcache_put( 1225 struct pq3etsec_softc *sc, 1226 struct pq3etsec_mapcache *dmc, 1227 bus_dmamap_t map) 1228 { 1229 KASSERT(map != NULL); 1230 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1231 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1232 } 1233 1234 static void 1235 pq3etsec_mapcache_destroy( 1236 struct pq3etsec_softc *sc, 1237 struct pq3etsec_mapcache *dmc) 1238 { 1239 const size_t dmc_size = 1240 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1241 1242 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1243 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1244 } 1245 kmem_intr_free(dmc, dmc_size); 1246 } 1247 1248 static int 1249 pq3etsec_mapcache_create( 1250 struct pq3etsec_softc *sc, 1251 struct pq3etsec_mapcache **dmc_p, 1252 size_t maxmaps, 1253 size_t maxmapsize, 1254 size_t maxseg) 1255 { 1256 const size_t dmc_size = 1257 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1258 struct pq3etsec_mapcache * const dmc = 1259 kmem_intr_zalloc(dmc_size, KM_NOSLEEP); 1260 1261 dmc->dmc_maxmaps = maxmaps; 1262 dmc->dmc_nmaps = maxmaps; 1263 dmc->dmc_maxmapsize = maxmapsize; 1264 dmc->dmc_maxseg = maxseg; 1265 1266 for (u_int i = 0; i < maxmaps; i++) { 1267 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1268 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1269 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1270 if (error) { 1271 aprint_error_dev(sc->sc_dev, 1272 "failed to creat dma map cache " 1273 "entry %u of %zu: %d\n", 1274 i, maxmaps, error); 1275 while (i-- > 0) { 1276 bus_dmamap_destroy(sc->sc_dmat, 1277 dmc->dmc_maps[i]); 1278 } 1279 kmem_intr_free(dmc, dmc_size); 1280 return error; 1281 } 1282 KASSERT(dmc->dmc_maps[i] != NULL); 1283 } 1284 1285 *dmc_p = dmc; 1286 1287 return 0; 1288 } 1289 1290 #if 0 1291 static void 1292 pq3etsec_dmamem_free( 1293 bus_dma_tag_t dmat, 1294 size_t map_size, 1295 bus_dma_segment_t *seg, 1296 bus_dmamap_t map, 1297 void *kvap) 1298 { 1299 bus_dmamap_destroy(dmat, map); 1300 bus_dmamem_unmap(dmat, kvap, map_size); 1301 bus_dmamem_free(dmat, seg, 1); 1302 } 1303 #endif 1304 1305 static int 1306 pq3etsec_dmamem_alloc( 1307 bus_dma_tag_t dmat, 1308 size_t map_size, 1309 bus_dma_segment_t *seg, 1310 bus_dmamap_t *map, 1311 void **kvap) 1312 { 1313 int error; 1314 int nseg; 1315 1316 *kvap = NULL; 1317 *map = NULL; 1318 1319 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1320 seg, 1, &nseg, 0); 1321 if (error) 1322 return error; 1323 1324 KASSERT(nseg == 1); 1325 1326 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1327 BUS_DMA_COHERENT); 1328 if (error == 0) { 1329 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1330 map); 1331 if (error == 0) { 1332 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1333 NULL, 0); 1334 if (error == 0) 1335 return 0; 1336 bus_dmamap_destroy(dmat, *map); 1337 *map = NULL; 1338 } 1339 bus_dmamem_unmap(dmat, *kvap, map_size); 1340 *kvap = NULL; 1341 } 1342 bus_dmamem_free(dmat, seg, nseg); 1343 return 0; 1344 } 1345 1346 static struct mbuf * 1347 pq3etsec_rx_buf_alloc( 1348 struct pq3etsec_softc *sc) 1349 { 1350 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1351 if (m == NULL) { 1352 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1353 return NULL; 1354 } 1355 MCLGET(m, M_DONTWAIT); 1356 if ((m->m_flags & M_EXT) == 0) { 1357 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1358 m_freem(m); 1359 return NULL; 1360 } 1361 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1362 1363 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1364 if (map == NULL) { 1365 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1366 m_freem(m); 1367 return NULL; 1368 } 1369 M_SETCTX(m, map); 1370 m->m_len = m->m_pkthdr.len = MCLBYTES; 1371 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1372 BUS_DMA_READ|BUS_DMA_NOWAIT); 1373 if (error) { 1374 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1375 error); 1376 M_SETCTX(m, NULL); 1377 m_freem(m); 1378 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1379 return NULL; 1380 } 1381 KASSERT(map->dm_mapsize == MCLBYTES); 1382 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1383 BUS_DMASYNC_PREREAD); 1384 1385 return m; 1386 } 1387 1388 static void 1389 pq3etsec_rx_map_unload( 1390 struct pq3etsec_softc *sc, 1391 struct mbuf *m) 1392 { 1393 KASSERT(m); 1394 for (; m != NULL; m = m->m_next) { 1395 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1396 KASSERT(map); 1397 KASSERT(map->dm_mapsize == MCLBYTES); 1398 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1399 BUS_DMASYNC_POSTREAD); 1400 bus_dmamap_unload(sc->sc_dmat, map); 1401 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1402 M_SETCTX(m, NULL); 1403 } 1404 } 1405 1406 static bool 1407 pq3etsec_rxq_produce( 1408 struct pq3etsec_softc *sc, 1409 struct pq3etsec_rxqueue *rxq) 1410 { 1411 volatile struct rxbd *producer = rxq->rxq_producer; 1412 #if 0 1413 size_t inuse = rxq->rxq_inuse; 1414 #endif 1415 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1416 struct mbuf *m; 1417 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1418 if (m == NULL) { 1419 m = pq3etsec_rx_buf_alloc(sc); 1420 if (m == NULL) { 1421 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1422 break; 1423 } 1424 } 1425 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1426 KASSERT(map); 1427 1428 #ifdef ETSEC_DEBUG 1429 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1430 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1431 #endif 1432 1433 /* rxbd_len is write-only by the ETSEC */ 1434 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1435 membar_producer(); 1436 producer->rxbd_flags |= RXBD_E; 1437 if (__predict_false(rxq->rxq_mhead == NULL)) { 1438 KASSERT(producer == rxq->rxq_consumer); 1439 rxq->rxq_mconsumer = m; 1440 } 1441 *rxq->rxq_mtail = m; 1442 rxq->rxq_mtail = &m->m_next; 1443 m->m_len = MCLBYTES; 1444 m->m_next = NULL; 1445 rxq->rxq_inuse++; 1446 if (++producer == rxq->rxq_last) { 1447 membar_producer(); 1448 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1449 rxq->rxq_last - rxq->rxq_producer); 1450 producer = rxq->rxq_producer = rxq->rxq_first; 1451 } 1452 } 1453 if (producer != rxq->rxq_producer) { 1454 membar_producer(); 1455 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1456 producer - rxq->rxq_producer); 1457 rxq->rxq_producer = producer; 1458 } 1459 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1460 if (qhlt) { 1461 KASSERT(qhlt & rxq->rxq_qmask); 1462 sc->sc_ev_rx_stall.ev_count++; 1463 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1464 } 1465 #if 0 1466 aprint_normal_dev(sc->sc_dev, 1467 "%s: buffers inuse went from %zu to %zu\n", 1468 __func__, inuse, rxq->rxq_inuse); 1469 #endif 1470 return true; 1471 } 1472 1473 static bool 1474 pq3etsec_rx_offload( 1475 struct pq3etsec_softc *sc, 1476 struct mbuf *m, 1477 const struct rxfcb *fcb) 1478 { 1479 if (fcb->rxfcb_flags & RXFCB_VLN) { 1480 VLAN_INPUT_TAG(&sc->sc_if, m, fcb->rxfcb_vlctl, 1481 m_freem(m); return false); 1482 } 1483 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1484 || (fcb->rxfcb_flags & (RXFCB_CIP|RXFCB_CTU)) == 0) 1485 return true; 1486 int csum_flags = 0; 1487 if ((fcb->rxfcb_flags & (RXFCB_IP6|RXFCB_CIP)) == RXFCB_CIP) { 1488 csum_flags |= M_CSUM_IPv4; 1489 if (fcb->rxfcb_flags & RXFCB_EIP) 1490 csum_flags |= M_CSUM_IPv4_BAD; 1491 } 1492 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1493 int ipv_flags; 1494 if (fcb->rxfcb_flags & RXFCB_IP6) 1495 ipv_flags = M_CSUM_TCPv6|M_CSUM_UDPv6; 1496 else 1497 ipv_flags = M_CSUM_TCPv4|M_CSUM_UDPv4; 1498 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1499 csum_flags |= (M_CSUM_TCPv4|M_CSUM_TCPv6) & ipv_flags; 1500 } else { 1501 csum_flags |= (M_CSUM_UDPv4|M_CSUM_UDPv6) & ipv_flags; 1502 } 1503 if (fcb->rxfcb_flags & RXFCB_ETU) 1504 csum_flags |= M_CSUM_TCP_UDP_BAD; 1505 } 1506 1507 m->m_pkthdr.csum_flags = csum_flags; 1508 return true; 1509 } 1510 1511 static void 1512 pq3etsec_rx_input( 1513 struct pq3etsec_softc *sc, 1514 struct mbuf *m, 1515 uint16_t rxbd_flags) 1516 { 1517 struct ifnet * const ifp = &sc->sc_if; 1518 1519 pq3etsec_rx_map_unload(sc, m); 1520 1521 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1522 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1523 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1524 return; 1525 } 1526 m_adj(m, sc->sc_rx_adjlen); 1527 1528 if (rxbd_flags & RXBD_M) 1529 m->m_flags |= M_PROMISC; 1530 if (rxbd_flags & RXBD_BC) 1531 m->m_flags |= M_BCAST; 1532 if (rxbd_flags & RXBD_MC) 1533 m->m_flags |= M_MCAST; 1534 m->m_flags |= M_HASFCS; 1535 m->m_pkthdr.rcvif = &sc->sc_if; 1536 1537 ifp->if_ipackets++; 1538 ifp->if_ibytes += m->m_pkthdr.len; 1539 1540 /* 1541 * Let's give it to the network subsystm to deal with. 1542 */ 1543 int s = splnet(); 1544 bpf_mtap(ifp, m); 1545 (*ifp->if_input)(ifp, m); 1546 splx(s); 1547 } 1548 1549 static void 1550 pq3etsec_rxq_consume( 1551 struct pq3etsec_softc *sc, 1552 struct pq3etsec_rxqueue *rxq) 1553 { 1554 struct ifnet * const ifp = &sc->sc_if; 1555 volatile struct rxbd *consumer = rxq->rxq_consumer; 1556 size_t rxconsumed = 0; 1557 1558 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1559 1560 for (;;) { 1561 if (consumer == rxq->rxq_producer) { 1562 rxq->rxq_consumer = consumer; 1563 rxq->rxq_inuse -= rxconsumed; 1564 KASSERT(rxq->rxq_inuse == 0); 1565 return; 1566 } 1567 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1568 const uint16_t rxbd_flags = consumer->rxbd_flags; 1569 if (rxbd_flags & RXBD_E) { 1570 rxq->rxq_consumer = consumer; 1571 rxq->rxq_inuse -= rxconsumed; 1572 return; 1573 } 1574 KASSERT(rxq->rxq_mconsumer != NULL); 1575 #ifdef ETSEC_DEBUG 1576 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1577 #endif 1578 #if 0 1579 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1580 __func__, 1581 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1582 mtod(rxq->rxq_mconsumer, int *)[0], 1583 mtod(rxq->rxq_mconsumer, int *)[1], 1584 mtod(rxq->rxq_mconsumer, int *)[2], 1585 mtod(rxq->rxq_mconsumer, int *)[3]); 1586 #endif 1587 /* 1588 * We own this packet again. Clear all flags except wrap. 1589 */ 1590 rxconsumed++; 1591 consumer->rxbd_flags = rxbd_flags & (RXBD_W|RXBD_I); 1592 1593 /* 1594 * If this descriptor has the LAST bit set and no errors, 1595 * it's a valid input packet. 1596 */ 1597 if ((rxbd_flags & (RXBD_L|RXBD_ERRORS)) == RXBD_L) { 1598 size_t rxbd_len = consumer->rxbd_len; 1599 struct mbuf *m = rxq->rxq_mhead; 1600 struct mbuf *m_last = rxq->rxq_mconsumer; 1601 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1602 rxq->rxq_mtail = &rxq->rxq_mhead; 1603 rxq->rxq_mconsumer = rxq->rxq_mhead; 1604 m_last->m_next = NULL; 1605 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1606 m->m_pkthdr.len = rxbd_len; 1607 pq3etsec_rx_input(sc, m, rxbd_flags); 1608 } else if (rxbd_flags & RXBD_L) { 1609 KASSERT(rxbd_flags & RXBD_ERRORS); 1610 struct mbuf *m; 1611 /* 1612 * We encountered an error, take the mbufs and add 1613 * then to the rx bufcache so we can reuse them. 1614 */ 1615 ifp->if_ierrors++; 1616 for (m = rxq->rxq_mhead; 1617 m != rxq->rxq_mconsumer; 1618 m = m->m_next) { 1619 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1620 } 1621 m = rxq->rxq_mconsumer; 1622 if ((rxq->rxq_mhead = m->m_next) == NULL) 1623 rxq->rxq_mtail = &rxq->rxq_mhead; 1624 rxq->rxq_mconsumer = m->m_next; 1625 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1626 } else { 1627 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1628 } 1629 #ifdef ETSEC_DEBUG 1630 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1631 #endif 1632 1633 /* 1634 * Wrap at the last entry! 1635 */ 1636 if (rxbd_flags & RXBD_W) { 1637 KASSERT(consumer + 1 == rxq->rxq_last); 1638 consumer = rxq->rxq_first; 1639 } else { 1640 consumer++; 1641 } 1642 #ifdef ETSEC_DEBUG 1643 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1644 #endif 1645 } 1646 } 1647 1648 static void 1649 pq3etsec_rxq_purge( 1650 struct pq3etsec_softc *sc, 1651 struct pq3etsec_rxqueue *rxq, 1652 bool discard) 1653 { 1654 struct mbuf *m; 1655 1656 if ((m = rxq->rxq_mhead) != NULL) { 1657 #ifdef ETSEC_DEBUG 1658 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1659 #endif 1660 1661 if (discard) { 1662 pq3etsec_rx_map_unload(sc, m); 1663 m_freem(m); 1664 } else { 1665 while (m != NULL) { 1666 struct mbuf *m0 = m->m_next; 1667 m->m_next = NULL; 1668 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1669 m = m0; 1670 } 1671 } 1672 1673 } 1674 1675 rxq->rxq_mconsumer = NULL; 1676 rxq->rxq_mhead = NULL; 1677 rxq->rxq_mtail = &rxq->rxq_mhead; 1678 rxq->rxq_inuse = 0; 1679 } 1680 1681 static void 1682 pq3etsec_rxq_reset( 1683 struct pq3etsec_softc *sc, 1684 struct pq3etsec_rxqueue *rxq) 1685 { 1686 /* 1687 * sync all the descriptors 1688 */ 1689 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1690 rxq->rxq_last - rxq->rxq_first); 1691 1692 /* 1693 * Make sure we own all descriptors in the ring. 1694 */ 1695 volatile struct rxbd *rxbd; 1696 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1697 rxbd->rxbd_flags = RXBD_I; 1698 } 1699 1700 /* 1701 * Last descriptor has the wrap flag. 1702 */ 1703 rxbd->rxbd_flags = RXBD_W|RXBD_I; 1704 1705 /* 1706 * Reset the producer consumer indexes. 1707 */ 1708 rxq->rxq_consumer = rxq->rxq_first; 1709 rxq->rxq_producer = rxq->rxq_first; 1710 rxq->rxq_inuse = 0; 1711 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1712 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1713 1714 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY; 1715 1716 /* 1717 * Restart the transmit at the first descriptor 1718 */ 1719 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1720 } 1721 1722 static int 1723 pq3etsec_rxq_attach( 1724 struct pq3etsec_softc *sc, 1725 struct pq3etsec_rxqueue *rxq, 1726 u_int qno) 1727 { 1728 size_t map_size = PAGE_SIZE; 1729 size_t desc_count = map_size / sizeof(struct rxbd); 1730 int error; 1731 void *descs; 1732 1733 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1734 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1735 if (error) 1736 return error; 1737 1738 memset(descs, 0, map_size); 1739 rxq->rxq_first = descs; 1740 rxq->rxq_last = rxq->rxq_first + desc_count; 1741 rxq->rxq_consumer = descs; 1742 rxq->rxq_producer = descs; 1743 1744 pq3etsec_rxq_purge(sc, rxq, true); 1745 pq3etsec_rxq_reset(sc, rxq); 1746 1747 rxq->rxq_reg_rbase = RBASEn(qno); 1748 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1749 1750 return 0; 1751 } 1752 1753 static bool 1754 pq3etsec_txq_active_p( 1755 struct pq3etsec_softc * const sc, 1756 struct pq3etsec_txqueue *txq) 1757 { 1758 return !IF_IS_EMPTY(&txq->txq_mbufs); 1759 } 1760 1761 static bool 1762 pq3etsec_txq_fillable_p( 1763 struct pq3etsec_softc * const sc, 1764 struct pq3etsec_txqueue *txq) 1765 { 1766 return txq->txq_free >= txq->txq_threshold; 1767 } 1768 1769 static int 1770 pq3etsec_txq_attach( 1771 struct pq3etsec_softc *sc, 1772 struct pq3etsec_txqueue *txq, 1773 u_int qno) 1774 { 1775 size_t map_size = PAGE_SIZE; 1776 size_t desc_count = map_size / sizeof(struct txbd); 1777 int error; 1778 void *descs; 1779 1780 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1781 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1782 if (error) 1783 return error; 1784 1785 memset(descs, 0, map_size); 1786 txq->txq_first = descs; 1787 txq->txq_last = txq->txq_first + desc_count; 1788 txq->txq_consumer = descs; 1789 txq->txq_producer = descs; 1790 1791 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1792 1793 txq->txq_reg_tbase = TBASEn(qno); 1794 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1795 1796 pq3etsec_txq_reset(sc, txq); 1797 1798 return 0; 1799 } 1800 1801 static int 1802 pq3etsec_txq_map_load( 1803 struct pq3etsec_softc *sc, 1804 struct pq3etsec_txqueue *txq, 1805 struct mbuf *m) 1806 { 1807 bus_dmamap_t map; 1808 int error; 1809 1810 map = M_GETCTX(m, bus_dmamap_t); 1811 if (map != NULL) 1812 return 0; 1813 1814 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1815 if (map == NULL) 1816 return ENOMEM; 1817 1818 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1819 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1820 if (error) 1821 return error; 1822 1823 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1824 BUS_DMASYNC_PREWRITE); 1825 M_SETCTX(m, map); 1826 return 0; 1827 } 1828 1829 static void 1830 pq3etsec_txq_map_unload( 1831 struct pq3etsec_softc *sc, 1832 struct pq3etsec_txqueue *txq, 1833 struct mbuf *m) 1834 { 1835 KASSERT(m); 1836 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1837 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1838 BUS_DMASYNC_POSTWRITE); 1839 bus_dmamap_unload(sc->sc_dmat, map); 1840 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1841 } 1842 1843 static bool 1844 pq3etsec_txq_produce( 1845 struct pq3etsec_softc *sc, 1846 struct pq3etsec_txqueue *txq, 1847 struct mbuf *m) 1848 { 1849 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1850 1851 if (map->dm_nsegs > txq->txq_free) 1852 return false; 1853 1854 /* 1855 * TCP Offload flag must be set in the first descriptor. 1856 */ 1857 volatile struct txbd *producer = txq->txq_producer; 1858 uint16_t last_flags = TXBD_L; 1859 uint16_t first_flags = TXBD_R 1860 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1861 1862 /* 1863 * If we've produced enough descriptors without consuming any 1864 * we need to ask for an interrupt to reclaim some. 1865 */ 1866 txq->txq_lastintr += map->dm_nsegs; 1867 if (txq->txq_lastintr >= txq->txq_threshold 1868 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1869 txq->txq_lastintr = 0; 1870 last_flags |= TXBD_I; 1871 } 1872 1873 #ifdef ETSEC_DEBUG 1874 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1875 #endif 1876 KASSERT(producer != txq->txq_last); 1877 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1878 producer->txbd_len = map->dm_segs[0].ds_len; 1879 1880 if (map->dm_nsegs > 1) { 1881 volatile struct txbd *start = producer + 1; 1882 size_t count = map->dm_nsegs - 1; 1883 for (u_int i = 1; i < map->dm_nsegs; i++) { 1884 if (__predict_false(++producer == txq->txq_last)) { 1885 producer = txq->txq_first; 1886 if (start < txq->txq_last) { 1887 pq3etsec_txq_desc_presync(sc, txq, 1888 start, txq->txq_last - start); 1889 count -= txq->txq_last - start; 1890 } 1891 start = txq->txq_first; 1892 } 1893 #ifdef ETSEC_DEBUG 1894 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1895 #endif 1896 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1897 producer->txbd_len = map->dm_segs[i].ds_len; 1898 producer->txbd_flags = TXBD_R 1899 | (producer->txbd_flags & TXBD_W) 1900 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1901 #if 0 1902 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1903 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1904 #endif 1905 } 1906 pq3etsec_txq_desc_presync(sc, txq, start, count); 1907 } else { 1908 first_flags |= last_flags; 1909 } 1910 1911 membar_producer(); 1912 txq->txq_producer->txbd_flags = 1913 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1914 #if 0 1915 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1916 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1917 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1918 #endif 1919 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1920 1921 /* 1922 * Reduce free count by the number of segments we consumed. 1923 */ 1924 txq->txq_free -= map->dm_nsegs; 1925 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 1926 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 1927 KASSERT(producer->txbd_flags & TXBD_L); 1928 #ifdef ETSEC_DEBUG 1929 txq->txq_lmbufs[producer - txq->txq_first] = m; 1930 #endif 1931 1932 #if 0 1933 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 1934 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 1935 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 1936 #endif 1937 1938 if (++producer == txq->txq_last) 1939 txq->txq_producer = txq->txq_first; 1940 else 1941 txq->txq_producer = producer; 1942 IF_ENQUEUE(&txq->txq_mbufs, m); 1943 1944 /* 1945 * Restart the transmitter. 1946 */ 1947 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 1948 1949 return true; 1950 } 1951 1952 static void 1953 pq3etsec_tx_offload( 1954 struct pq3etsec_softc *sc, 1955 struct pq3etsec_txqueue *txq, 1956 struct mbuf **mp) 1957 { 1958 struct mbuf *m = *mp; 1959 u_int csum_flags = m->m_pkthdr.csum_flags; 1960 struct m_tag *vtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m); 1961 1962 KASSERT(m->m_flags & M_PKTHDR); 1963 1964 /* 1965 * Let see if we are doing any offload first. 1966 */ 1967 if (csum_flags == 0 && vtag == 0) { 1968 m->m_flags &= ~M_HASFCB; 1969 return; 1970 } 1971 1972 uint16_t flags = 0; 1973 if (csum_flags & M_CSUM_IP) { 1974 flags |= TXFCB_IP 1975 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 1976 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 1977 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 1978 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 1979 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 1980 } 1981 if (vtag) { 1982 flags |= TXFCB_VLN; 1983 } 1984 if (flags == 0) { 1985 m->m_flags &= ~M_HASFCB; 1986 return; 1987 } 1988 1989 struct txfcb fcb; 1990 fcb.txfcb_flags = flags; 1991 if (csum_flags & M_CSUM_IPv4) 1992 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 1993 else 1994 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 1995 fcb.txfcb_l3os = ETHER_HDR_LEN; 1996 fcb.txfcb_phcs = 0; 1997 fcb.txfcb_vlctl = vtag ? VLAN_TAG_VALUE(vtag) & 0xffff : 0; 1998 1999 #if 0 2000 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 2001 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 2002 fcb.txfcb_phcs, fcb.txfcb_vlctl); 2003 #endif 2004 2005 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 2006 m->m_data -= sizeof(fcb); 2007 m->m_len += sizeof(fcb); 2008 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 2009 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 2010 m->m_data = m->m_pktdat; 2011 m->m_len += sizeof(fcb); 2012 } else { 2013 struct mbuf *mn; 2014 MGET(mn, M_DONTWAIT, m->m_type); 2015 if (mn == NULL) { 2016 if (csum_flags & M_CSUM_IP4) { 2017 #ifdef INET 2018 ip_undefer_csum(m, ETHER_HDR_LEN, 2019 csum_flags & M_CSUM_IP4); 2020 #else 2021 panic("%s: impossible M_CSUM flags %#x", 2022 device_xname(sc->sc_dev), csum_flags); 2023 #endif 2024 } else if (csum_flags & M_CSUM_IP6) { 2025 #ifdef INET6 2026 ip6_undefer_csum(m, ETHER_HDR_LEN, 2027 csum_flags & M_CSUM_IP6); 2028 #else 2029 panic("%s: impossible M_CSUM flags %#x", 2030 device_xname(sc->sc_dev), csum_flags); 2031 #endif 2032 } else if (vtag) { 2033 } 2034 2035 m->m_flags &= ~M_HASFCB; 2036 return; 2037 } 2038 2039 M_MOVE_PKTHDR(mn, m); 2040 mn->m_next = m; 2041 m = mn; 2042 MH_ALIGN(m, sizeof(fcb)); 2043 m->m_len = sizeof(fcb); 2044 *mp = m; 2045 } 2046 m->m_pkthdr.len += sizeof(fcb); 2047 m->m_flags |= M_HASFCB; 2048 *mtod(m, struct txfcb *) = fcb; 2049 return; 2050 } 2051 2052 static bool 2053 pq3etsec_txq_enqueue( 2054 struct pq3etsec_softc *sc, 2055 struct pq3etsec_txqueue *txq) 2056 { 2057 for (;;) { 2058 if (IF_QFULL(&txq->txq_mbufs)) 2059 return false; 2060 struct mbuf *m = txq->txq_next; 2061 if (m == NULL) { 2062 int s = splnet(); 2063 IFQ_DEQUEUE(&sc->sc_if.if_snd, m); 2064 splx(s); 2065 if (m == NULL) 2066 return true; 2067 M_SETCTX(m, NULL); 2068 pq3etsec_tx_offload(sc, txq, &m); 2069 } else { 2070 txq->txq_next = NULL; 2071 } 2072 int error = pq3etsec_txq_map_load(sc, txq, m); 2073 if (error) { 2074 aprint_error_dev(sc->sc_dev, 2075 "discarded packet due to " 2076 "dmamap load failure: %d\n", error); 2077 m_freem(m); 2078 continue; 2079 } 2080 KASSERT(txq->txq_next == NULL); 2081 if (!pq3etsec_txq_produce(sc, txq, m)) { 2082 txq->txq_next = m; 2083 return false; 2084 } 2085 KASSERT(txq->txq_next == NULL); 2086 } 2087 } 2088 2089 static bool 2090 pq3etsec_txq_consume( 2091 struct pq3etsec_softc *sc, 2092 struct pq3etsec_txqueue *txq) 2093 { 2094 struct ifnet * const ifp = &sc->sc_if; 2095 volatile struct txbd *consumer = txq->txq_consumer; 2096 size_t txfree = 0; 2097 2098 #if 0 2099 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 2100 #endif 2101 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 2102 2103 for (;;) { 2104 if (consumer == txq->txq_producer) { 2105 txq->txq_consumer = consumer; 2106 txq->txq_free += txfree; 2107 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2108 #if 0 2109 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2110 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2111 #endif 2112 KASSERT(txq->txq_lastintr == 0); 2113 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2114 return true; 2115 } 2116 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2117 const uint16_t txbd_flags = consumer->txbd_flags; 2118 if (txbd_flags & TXBD_R) { 2119 txq->txq_consumer = consumer; 2120 txq->txq_free += txfree; 2121 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2122 #if 0 2123 printf("%s: freed %zu descriptors\n", 2124 __func__, txfree); 2125 #endif 2126 return pq3etsec_txq_fillable_p(sc, txq); 2127 } 2128 2129 /* 2130 * If this is the last descriptor in the chain, get the 2131 * mbuf, free its dmamap, and free the mbuf chain itself. 2132 */ 2133 if (txbd_flags & TXBD_L) { 2134 struct mbuf *m; 2135 2136 IF_DEQUEUE(&txq->txq_mbufs, m); 2137 #ifdef ETSEC_DEBUG 2138 KASSERTMSG( 2139 m == txq->txq_lmbufs[consumer-txq->txq_first], 2140 "%s: %p [%u]: flags %#x m (%p) != %p (%p)", 2141 __func__, consumer, consumer - txq->txq_first, 2142 txbd_flags, m, 2143 &txq->txq_lmbufs[consumer-txq->txq_first], 2144 txq->txq_lmbufs[consumer-txq->txq_first]); 2145 #endif 2146 KASSERT(m); 2147 pq3etsec_txq_map_unload(sc, txq, m); 2148 #if 0 2149 printf("%s: mbuf %p: consumed a %u byte packet\n", 2150 __func__, m, m->m_pkthdr.len); 2151 #endif 2152 if (m->m_flags & M_HASFCB) 2153 m_adj(m, sizeof(struct txfcb)); 2154 ifp->if_opackets++; 2155 ifp->if_obytes += m->m_pkthdr.len; 2156 if (m->m_flags & M_MCAST) 2157 ifp->if_omcasts++; 2158 if (txbd_flags & TXBD_ERRORS) 2159 ifp->if_oerrors++; 2160 m_freem(m); 2161 #ifdef ETSEC_DEBUG 2162 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2163 #endif 2164 } else { 2165 #ifdef ETSEC_DEBUG 2166 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2167 #endif 2168 } 2169 2170 /* 2171 * We own this packet again. Clear all flags except wrap. 2172 */ 2173 txfree++; 2174 //consumer->txbd_flags = txbd_flags & TXBD_W; 2175 2176 /* 2177 * Wrap at the last entry! 2178 */ 2179 if (txbd_flags & TXBD_W) { 2180 KASSERT(consumer + 1 == txq->txq_last); 2181 consumer = txq->txq_first; 2182 } else { 2183 consumer++; 2184 KASSERT(consumer < txq->txq_last); 2185 } 2186 } 2187 } 2188 2189 static void 2190 pq3etsec_txq_purge( 2191 struct pq3etsec_softc *sc, 2192 struct pq3etsec_txqueue *txq) 2193 { 2194 struct mbuf *m; 2195 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2196 2197 for (;;) { 2198 IF_DEQUEUE(&txq->txq_mbufs, m); 2199 if (m == NULL) 2200 break; 2201 pq3etsec_txq_map_unload(sc, txq, m); 2202 m_freem(m); 2203 } 2204 if ((m = txq->txq_next) != NULL) { 2205 txq->txq_next = NULL; 2206 pq3etsec_txq_map_unload(sc, txq, m); 2207 m_freem(m); 2208 } 2209 #ifdef ETSEC_DEBUG 2210 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2211 #endif 2212 } 2213 2214 static void 2215 pq3etsec_txq_reset( 2216 struct pq3etsec_softc *sc, 2217 struct pq3etsec_txqueue *txq) 2218 { 2219 /* 2220 * sync all the descriptors 2221 */ 2222 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2223 txq->txq_last - txq->txq_first); 2224 2225 /* 2226 * Make sure we own all descriptors in the ring. 2227 */ 2228 volatile struct txbd *txbd; 2229 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2230 txbd->txbd_flags = 0; 2231 } 2232 2233 /* 2234 * Last descriptor has the wrap flag. 2235 */ 2236 txbd->txbd_flags = TXBD_W; 2237 2238 /* 2239 * Reset the producer consumer indexes. 2240 */ 2241 txq->txq_consumer = txq->txq_first; 2242 txq->txq_producer = txq->txq_first; 2243 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2244 txq->txq_threshold = txq->txq_free / 2; 2245 txq->txq_lastintr = 0; 2246 2247 /* 2248 * What do we want to get interrupted on? 2249 */ 2250 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE; 2251 2252 /* 2253 * Restart the transmit at the first descriptor 2254 */ 2255 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2256 } 2257 2258 static void 2259 pq3etsec_ifstart(struct ifnet *ifp) 2260 { 2261 struct pq3etsec_softc * const sc = ifp->if_softc; 2262 2263 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2264 softint_schedule(sc->sc_soft_ih); 2265 } 2266 2267 static void 2268 pq3etsec_tx_error( 2269 struct pq3etsec_softc * const sc) 2270 { 2271 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2272 2273 pq3etsec_txq_consume(sc, txq); 2274 2275 if (pq3etsec_txq_fillable_p(sc, txq)) 2276 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2277 if (sc->sc_txerrors & (IEVENT_LC|IEVENT_CRL|IEVENT_XFUN|IEVENT_BABT)) { 2278 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2279 } 2280 2281 if (pq3etsec_txq_active_p(sc, txq)) 2282 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2283 if (!pq3etsec_txq_enqueue(sc, txq)) { 2284 sc->sc_ev_tx_stall.ev_count++; 2285 sc->sc_if.if_flags |= IFF_OACTIVE; 2286 } 2287 2288 sc->sc_txerrors = 0; 2289 } 2290 2291 int 2292 pq3etsec_tx_intr(void *arg) 2293 { 2294 struct pq3etsec_softc * const sc = arg; 2295 2296 sc->sc_ev_tx_intr.ev_count++; 2297 2298 uint32_t ievent = etsec_read(sc, IEVENT); 2299 ievent &= IEVENT_TXF|IEVENT_TXB; 2300 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2301 2302 #if 0 2303 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2304 __func__, ievent, etsec_read(sc, IMASK)); 2305 #endif 2306 2307 if (ievent == 0) 2308 return 0; 2309 2310 sc->sc_imask &= ~(IEVENT_TXF|IEVENT_TXB); 2311 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2312 etsec_write(sc, IMASK, sc->sc_imask); 2313 softint_schedule(sc->sc_soft_ih); 2314 return 1; 2315 } 2316 2317 int 2318 pq3etsec_rx_intr(void *arg) 2319 { 2320 struct pq3etsec_softc * const sc = arg; 2321 2322 sc->sc_ev_rx_intr.ev_count++; 2323 2324 uint32_t ievent = etsec_read(sc, IEVENT); 2325 ievent &= IEVENT_RXF|IEVENT_RXB; 2326 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2327 if (ievent == 0) 2328 return 0; 2329 2330 #if 0 2331 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2332 #endif 2333 2334 sc->sc_imask &= ~(IEVENT_RXF|IEVENT_RXB); 2335 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2336 etsec_write(sc, IMASK, sc->sc_imask); 2337 softint_schedule(sc->sc_soft_ih); 2338 return 1; 2339 } 2340 2341 int 2342 pq3etsec_error_intr(void *arg) 2343 { 2344 struct pq3etsec_softc * const sc = arg; 2345 2346 sc->sc_ev_error_intr.ev_count++; 2347 2348 for (int rv = 0, soft_flags = 0;; rv = 1) { 2349 uint32_t ievent = etsec_read(sc, IEVENT); 2350 ievent &= ~(IEVENT_RXF|IEVENT_RXB|IEVENT_TXF|IEVENT_TXB); 2351 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2352 if (ievent == 0) { 2353 if (soft_flags) { 2354 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2355 softint_schedule(sc->sc_soft_ih); 2356 } 2357 return rv; 2358 } 2359 #if 0 2360 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2361 __func__, ievent, etsec_read(sc, IMASK)); 2362 #endif 2363 2364 if (ievent & (IEVENT_GRSC|IEVENT_GTSC)) { 2365 sc->sc_imask &= ~(IEVENT_GRSC|IEVENT_GTSC); 2366 etsec_write(sc, IMASK, sc->sc_imask); 2367 wakeup(sc); 2368 } 2369 if (ievent & (IEVENT_MMRD|IEVENT_MMWR)) { 2370 sc->sc_imask &= ~(IEVENT_MMRD|IEVENT_MMWR); 2371 etsec_write(sc, IMASK, sc->sc_imask); 2372 wakeup(&sc->sc_mii); 2373 } 2374 if (ievent & IEVENT_BSY) { 2375 soft_flags |= SOFT_RXBSY; 2376 sc->sc_imask &= ~IEVENT_BSY; 2377 etsec_write(sc, IMASK, sc->sc_imask); 2378 } 2379 if (ievent & IEVENT_TXE) { 2380 soft_flags |= SOFT_TXERROR; 2381 sc->sc_imask &= ~IEVENT_TXE; 2382 sc->sc_txerrors |= ievent; 2383 } 2384 if (ievent & IEVENT_TXC) { 2385 sc->sc_ev_tx_pause.ev_count++; 2386 } 2387 if (ievent & IEVENT_RXC) { 2388 sc->sc_ev_rx_pause.ev_count++; 2389 } 2390 if (ievent & IEVENT_DPE) { 2391 soft_flags |= SOFT_RESET; 2392 sc->sc_imask &= ~IEVENT_DPE; 2393 etsec_write(sc, IMASK, sc->sc_imask); 2394 } 2395 } 2396 } 2397 2398 void 2399 pq3etsec_soft_intr(void *arg) 2400 { 2401 struct pq3etsec_softc * const sc = arg; 2402 struct ifnet * const ifp = &sc->sc_if; 2403 2404 mutex_enter(sc->sc_lock); 2405 2406 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2407 2408 sc->sc_ev_soft_intr.ev_count++; 2409 2410 if (soft_flags & SOFT_RESET) { 2411 int s = splnet(); 2412 pq3etsec_ifinit(ifp); 2413 splx(s); 2414 soft_flags = 0; 2415 } 2416 2417 if (soft_flags & SOFT_RXBSY) { 2418 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2419 size_t threshold = 5 * rxq->rxq_threshold / 4; 2420 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2421 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2422 } else { 2423 sc->sc_imask |= IEVENT_BSY; 2424 } 2425 aprint_normal_dev(sc->sc_dev, 2426 "increasing receive buffers from %zu to %zu\n", 2427 rxq->rxq_threshold, threshold); 2428 rxq->rxq_threshold = threshold; 2429 } 2430 2431 if ((soft_flags & SOFT_TXINTR) 2432 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2433 /* 2434 * Let's do what we came here for. Consume transmitted 2435 * packets off the the transmit ring. 2436 */ 2437 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2438 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2439 sc->sc_ev_tx_stall.ev_count++; 2440 ifp->if_flags |= IFF_OACTIVE; 2441 } else { 2442 ifp->if_flags &= ~IFF_OACTIVE; 2443 } 2444 sc->sc_imask |= IEVENT_TXF; 2445 } 2446 2447 if (soft_flags & (SOFT_RXINTR|SOFT_RXBSY)) { 2448 /* 2449 * Let's consume 2450 */ 2451 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2452 sc->sc_imask |= IEVENT_RXF; 2453 } 2454 2455 if (soft_flags & SOFT_TXERROR) { 2456 pq3etsec_tx_error(sc); 2457 sc->sc_imask |= IEVENT_TXE; 2458 } 2459 2460 if (ifp->if_flags & IFF_RUNNING) { 2461 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2462 etsec_write(sc, IMASK, sc->sc_imask); 2463 } else { 2464 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2465 } 2466 2467 mutex_exit(sc->sc_lock); 2468 } 2469 2470 static void 2471 pq3etsec_mii_tick(void *arg) 2472 { 2473 struct pq3etsec_softc * const sc = arg; 2474 mutex_enter(sc->sc_lock); 2475 callout_ack(&sc->sc_mii_callout); 2476 sc->sc_ev_mii_ticks.ev_count++; 2477 #ifdef DEBUG 2478 uint64_t now = mftb(); 2479 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2480 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2481 __func__, now - sc->sc_mii_last_tick); 2482 callout_stop(&sc->sc_mii_callout); 2483 } 2484 #endif 2485 mii_tick(&sc->sc_mii); 2486 int s = splnet(); 2487 if (sc->sc_soft_flags & SOFT_RESET) 2488 softint_schedule(sc->sc_soft_ih); 2489 splx(s); 2490 callout_schedule(&sc->sc_mii_callout, hz); 2491 #ifdef DEBUG 2492 sc->sc_mii_last_tick = now; 2493 #endif 2494 mutex_exit(sc->sc_lock); 2495 } 2496
Indexes created Tue Sep 30 11:09:46 GMT 2025