pq3etsec.c revision 1.40
1 /* $NetBSD: pq3etsec.c,v 1.40 2019/01/22 03:42:26 msaitoh Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_inet.h" 38 #include "opt_mpc85xx.h" 39 #include "opt_multiprocessor.h" 40 #include "opt_net_mpsafe.h" 41 42 #include <sys/cdefs.h> 43 44 __KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.40 2019/01/22 03:42:26 msaitoh Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/cpu.h> 48 #include <sys/device.h> 49 #include <sys/mbuf.h> 50 #include <sys/ioctl.h> 51 #include <sys/intr.h> 52 #include <sys/bus.h> 53 #include <sys/kernel.h> 54 #include <sys/kmem.h> 55 #include <sys/proc.h> 56 #include <sys/atomic.h> 57 #include <sys/callout.h> 58 #include <sys/sysctl.h> 59 60 #include <net/if.h> 61 #include <net/if_dl.h> 62 #include <net/if_ether.h> 63 #include <net/if_media.h> 64 65 #include <dev/mii/miivar.h> 66 67 #include <net/bpf.h> 68 69 #ifdef INET 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/ip.h> 73 #include <netinet/in_offload.h> 74 #endif /* INET */ 75 #ifdef INET6 76 #include <netinet6/in6.h> 77 #include <netinet/ip6.h> 78 #endif 79 #include <netinet6/in6_offload.h> 80 81 #include <powerpc/spr.h> 82 #include <powerpc/booke/spr.h> 83 84 #include <powerpc/booke/cpuvar.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/e500reg.h> 87 #include <powerpc/booke/etsecreg.h> 88 89 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 90 91 #define ETSEC_MAXTXMBUFS 30 92 #define ETSEC_NTXSEGS 30 93 #define ETSEC_MAXRXMBUFS 511 94 #define ETSEC_MINRXMBUFS 32 95 #define ETSEC_NRXSEGS 1 96 97 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 98 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx\ 99 |IFCAP_CSUM_UDPv4_Rx\ 100 |IFCAP_CSUM_TCPv6_Rx\ 101 |IFCAP_CSUM_UDPv6_Rx) 102 103 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 104 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx\ 105 |IFCAP_CSUM_UDPv4_Tx\ 106 |IFCAP_CSUM_TCPv6_Tx\ 107 |IFCAP_CSUM_UDPv6_Tx) 108 109 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN|IFCAP_RCTRL_TUCSEN\ 110 |IFCAP_TCTRL_IPCSEN|IFCAP_TCTRL_TUCSEN) 111 112 #define M_CSUM_IP (M_CSUM_CIP|M_CSUM_CTU) 113 #define M_CSUM_IP6 (M_CSUM_TCPv6|M_CSUM_UDPv6) 114 #define M_CSUM_TUP (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 115 #define M_CSUM_UDP (M_CSUM_UDPv4|M_CSUM_UDPv6) 116 #define M_CSUM_IP4 (M_CSUM_IPv4|M_CSUM_UDPv4|M_CSUM_TCPv4) 117 #define M_CSUM_CIP (M_CSUM_IPv4) 118 #define M_CSUM_CTU (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 119 120 struct pq3etsec_txqueue { 121 bus_dmamap_t txq_descmap; 122 volatile struct txbd *txq_consumer; 123 volatile struct txbd *txq_producer; 124 volatile struct txbd *txq_first; 125 volatile struct txbd *txq_last; 126 struct ifqueue txq_mbufs; 127 struct mbuf *txq_next; 128 #ifdef ETSEC_DEBUG 129 struct mbuf *txq_lmbufs[512]; 130 #endif 131 uint32_t txq_qmask; 132 uint32_t txq_free; 133 uint32_t txq_threshold; 134 uint32_t txq_lastintr; 135 bus_size_t txq_reg_tbase; 136 bus_dma_segment_t txq_descmap_seg; 137 }; 138 139 struct pq3etsec_rxqueue { 140 bus_dmamap_t rxq_descmap; 141 volatile struct rxbd *rxq_consumer; 142 volatile struct rxbd *rxq_producer; 143 volatile struct rxbd *rxq_first; 144 volatile struct rxbd *rxq_last; 145 struct mbuf *rxq_mhead; 146 struct mbuf **rxq_mtail; 147 struct mbuf *rxq_mconsumer; 148 #ifdef ETSEC_DEBUG 149 struct mbuf *rxq_mbufs[512]; 150 #endif 151 uint32_t rxq_qmask; 152 uint32_t rxq_inuse; 153 uint32_t rxq_threshold; 154 bus_size_t rxq_reg_rbase; 155 bus_size_t rxq_reg_rbptr; 156 bus_dma_segment_t rxq_descmap_seg; 157 }; 158 159 struct pq3etsec_mapcache { 160 u_int dmc_nmaps; 161 u_int dmc_maxseg; 162 u_int dmc_maxmaps; 163 u_int dmc_maxmapsize; 164 bus_dmamap_t dmc_maps[0]; 165 }; 166 167 struct pq3etsec_softc { 168 device_t sc_dev; 169 device_t sc_mdio_dev; 170 struct ethercom sc_ec; 171 #define sc_if sc_ec.ec_if 172 struct mii_data sc_mii; 173 bus_space_tag_t sc_bst; 174 bus_space_handle_t sc_bsh; 175 bus_space_handle_t sc_mdio_bsh; 176 bus_dma_tag_t sc_dmat; 177 int sc_phy_addr; 178 prop_dictionary_t sc_intrmap; 179 uint32_t sc_intrmask; 180 181 uint32_t sc_soft_flags; 182 #define SOFT_RESET 0x0001 183 #define SOFT_RXINTR 0x0010 184 #define SOFT_RXBSY 0x0020 185 #define SOFT_TXINTR 0x0100 186 #define SOFT_TXERROR 0x0200 187 188 struct pq3etsec_txqueue sc_txq; 189 struct pq3etsec_rxqueue sc_rxq; 190 uint32_t sc_txerrors; 191 uint32_t sc_rxerrors; 192 193 size_t sc_rx_adjlen; 194 195 /* 196 * Copies of various ETSEC registers. 197 */ 198 uint32_t sc_imask; 199 uint32_t sc_maccfg1; 200 uint32_t sc_maccfg2; 201 uint32_t sc_maxfrm; 202 uint32_t sc_ecntrl; 203 uint32_t sc_dmactrl; 204 uint32_t sc_macstnaddr1; 205 uint32_t sc_macstnaddr2; 206 uint32_t sc_tctrl; 207 uint32_t sc_rctrl; 208 uint32_t sc_gaddr[16]; 209 uint64_t sc_macaddrs[15]; 210 211 void *sc_tx_ih; 212 void *sc_rx_ih; 213 void *sc_error_ih; 214 void *sc_soft_ih; 215 216 kmutex_t *sc_lock; 217 kmutex_t *sc_hwlock; 218 219 struct evcnt sc_ev_tx_stall; 220 struct evcnt sc_ev_tx_intr; 221 struct evcnt sc_ev_rx_stall; 222 struct evcnt sc_ev_rx_intr; 223 struct evcnt sc_ev_error_intr; 224 struct evcnt sc_ev_soft_intr; 225 struct evcnt sc_ev_tx_pause; 226 struct evcnt sc_ev_rx_pause; 227 struct evcnt sc_ev_mii_ticks; 228 229 struct callout sc_mii_callout; 230 uint64_t sc_mii_last_tick; 231 232 struct ifqueue sc_rx_bufcache; 233 struct pq3etsec_mapcache *sc_rx_mapcache; 234 struct pq3etsec_mapcache *sc_tx_mapcache; 235 236 /* Interrupt Coalescing parameters */ 237 int sc_ic_rx_time; 238 int sc_ic_rx_count; 239 int sc_ic_tx_time; 240 int sc_ic_tx_count; 241 }; 242 243 #define ETSEC_IC_RX_ENABLED(sc) \ 244 ((sc)->sc_ic_rx_time != 0 && (sc)->sc_ic_rx_count != 0) 245 #define ETSEC_IC_TX_ENABLED(sc) \ 246 ((sc)->sc_ic_tx_time != 0 && (sc)->sc_ic_tx_count != 0) 247 248 struct pq3mdio_softc { 249 device_t mdio_dev; 250 251 kmutex_t *mdio_lock; 252 253 bus_space_tag_t mdio_bst; 254 bus_space_handle_t mdio_bsh; 255 }; 256 257 static int pq3etsec_match(device_t, cfdata_t, void *); 258 static void pq3etsec_attach(device_t, device_t, void *); 259 260 static int pq3mdio_match(device_t, cfdata_t, void *); 261 static void pq3mdio_attach(device_t, device_t, void *); 262 263 static void pq3etsec_ifstart(struct ifnet *); 264 static void pq3etsec_ifwatchdog(struct ifnet *); 265 static int pq3etsec_ifinit(struct ifnet *); 266 static void pq3etsec_ifstop(struct ifnet *, int); 267 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 268 269 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 270 struct pq3etsec_mapcache **, size_t, size_t, size_t); 271 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 272 struct pq3etsec_mapcache *); 273 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 274 struct pq3etsec_mapcache *); 275 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 276 struct pq3etsec_mapcache *, bus_dmamap_t); 277 278 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 279 struct pq3etsec_txqueue *, u_int); 280 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 281 struct pq3etsec_txqueue *); 282 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 283 struct pq3etsec_txqueue *); 284 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 285 struct pq3etsec_txqueue *); 286 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 287 struct pq3etsec_txqueue *, struct mbuf *m); 288 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 289 struct pq3etsec_txqueue *); 290 291 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 292 struct pq3etsec_rxqueue *, u_int); 293 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 294 struct pq3etsec_rxqueue *); 295 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 296 struct pq3etsec_rxqueue *, bool); 297 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 298 struct pq3etsec_rxqueue *); 299 300 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 301 302 static void pq3etsec_mii_tick(void *); 303 static int pq3etsec_rx_intr(void *); 304 static int pq3etsec_tx_intr(void *); 305 static int pq3etsec_error_intr(void *); 306 static void pq3etsec_soft_intr(void *); 307 308 static void pq3etsec_set_ic_rx(struct pq3etsec_softc *); 309 static void pq3etsec_set_ic_tx(struct pq3etsec_softc *); 310 311 static void pq3etsec_sysctl_setup(struct sysctllog **, struct pq3etsec_softc *); 312 313 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 314 pq3etsec_match, pq3etsec_attach, NULL, NULL); 315 316 CFATTACH_DECL_NEW(pq3mdio_tsec, sizeof(struct pq3mdio_softc), 317 pq3mdio_match, pq3mdio_attach, NULL, NULL); 318 319 CFATTACH_DECL_NEW(pq3mdio_cpunode, sizeof(struct pq3mdio_softc), 320 pq3mdio_match, pq3mdio_attach, NULL, NULL); 321 322 static inline uint32_t 323 etsec_mdio_read(struct pq3mdio_softc *mdio, bus_size_t off) 324 { 325 return bus_space_read_4(mdio->mdio_bst, mdio->mdio_bsh, off); 326 } 327 328 static inline void 329 etsec_mdio_write(struct pq3mdio_softc *mdio, bus_size_t off, uint32_t data) 330 { 331 bus_space_write_4(mdio->mdio_bst, mdio->mdio_bsh, off, data); 332 } 333 334 static inline uint32_t 335 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 336 { 337 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 338 } 339 340 static int 341 pq3mdio_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 342 { 343 return strcmp(cf->cf_name, "mdio") == 0; 344 } 345 346 static int 347 pq3mdio_match(device_t parent, cfdata_t cf, void *aux) 348 { 349 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 350 const bool p1025_p = (svr == (SVR_P1025v1 >> 16) 351 || svr == (SVR_P1016v1 >> 16)); 352 353 if (device_is_a(parent, "cpunode")) { 354 if (!p1025_p 355 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 356 return 0; 357 358 return 1; 359 } 360 361 if (device_is_a(parent, "tsec")) { 362 if (p1025_p 363 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 364 return 0; 365 366 return 1; 367 } 368 369 return 0; 370 } 371 372 static void 373 pq3mdio_attach(device_t parent, device_t self, void *aux) 374 { 375 struct pq3mdio_softc * const mdio = device_private(self); 376 struct cpunode_attach_args * const cna = aux; 377 struct cpunode_locators * const cnl = &cna->cna_locs; 378 379 mdio->mdio_dev = self; 380 mdio->mdio_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 381 382 if (device_is_a(parent, "cpunode")) { 383 struct cpunode_softc * const psc = device_private(parent); 384 psc->sc_children |= cna->cna_childmask; 385 386 mdio->mdio_bst = cna->cna_memt; 387 if (bus_space_map(mdio->mdio_bst, cnl->cnl_addr, 388 cnl->cnl_size, 0, &mdio->mdio_bsh) != 0) { 389 aprint_error(": error mapping registers @ %#x\n", 390 cnl->cnl_addr); 391 return; 392 } 393 } else { 394 struct pq3etsec_softc * const sc = device_private(parent); 395 396 KASSERT(device_is_a(parent, "tsec")); 397 KASSERTMSG(cnl->cnl_addr == ETSEC1_BASE 398 || cnl->cnl_addr == ETSEC2_BASE 399 || cnl->cnl_addr == ETSEC3_BASE 400 || cnl->cnl_addr == ETSEC4_BASE, 401 "unknown tsec addr %x", cnl->cnl_addr); 402 403 mdio->mdio_bst = sc->sc_bst; 404 mdio->mdio_bsh = sc->sc_bsh; 405 } 406 407 aprint_normal("\n"); 408 } 409 410 static int 411 pq3mdio_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 412 { 413 struct pq3mdio_softc * const mdio = device_private(self); 414 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 415 416 mutex_enter(mdio->mdio_lock); 417 418 etsec_mdio_write(mdio, MIIMADD, 419 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 420 421 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 422 etsec_mdio_write(mdio, MIIMCOM, MIIMCOM_READ); 423 424 while (etsec_mdio_read(mdio, MIIMIND) != 0) { 425 delay(1); 426 } 427 *val = etsec_mdio_read(mdio, MIIMSTAT) &0xffff; 428 429 if (miimcom == MIIMCOM_SCAN) 430 etsec_mdio_write(mdio, MIIMCOM, miimcom); 431 432 #if 0 433 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 434 __func__, phy, reg, data); 435 #endif 436 mutex_exit(mdio->mdio_lock); 437 return 0; 438 } 439 440 static int 441 pq3mdio_mii_writereg(device_t self, int phy, int reg, uint16_t data) 442 { 443 struct pq3mdio_softc * const mdio = device_private(self); 444 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 445 446 #if 0 447 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 448 __func__, phy, reg, data); 449 #endif 450 451 mutex_enter(mdio->mdio_lock); 452 453 etsec_mdio_write(mdio, MIIMADD, 454 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 455 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 456 etsec_mdio_write(mdio, MIIMCON, data); 457 458 int timo = 1000; /* 1ms */ 459 while ((etsec_mdio_read(mdio, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 460 delay(1); 461 } 462 463 if (miimcom == MIIMCOM_SCAN) 464 etsec_mdio_write(mdio, MIIMCOM, miimcom); 465 466 mutex_exit(mdio->mdio_lock); 467 468 return 0; 469 } 470 471 static inline void 472 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 473 { 474 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 475 } 476 477 static void 478 pq3etsec_mii_statchg(struct ifnet *ifp) 479 { 480 struct pq3etsec_softc * const sc = ifp->if_softc; 481 struct mii_data * const mii = &sc->sc_mii; 482 483 uint32_t maccfg1 = sc->sc_maccfg1; 484 uint32_t maccfg2 = sc->sc_maccfg2; 485 uint32_t ecntrl = sc->sc_ecntrl; 486 487 maccfg1 &= ~(MACCFG1_TX_FLOW|MACCFG1_RX_FLOW); 488 maccfg2 &= ~(MACCFG2_IFMODE|MACCFG2_FD); 489 490 if (sc->sc_mii.mii_media_active & IFM_FDX) { 491 maccfg2 |= MACCFG2_FD; 492 } 493 494 /* 495 * Now deal with the flow control bits. 496 */ 497 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 498 && (mii->mii_media_active & IFM_ETH_FMASK)) { 499 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 500 maccfg1 |= MACCFG1_RX_FLOW; 501 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 502 maccfg1 |= MACCFG1_TX_FLOW; 503 } 504 505 /* 506 * Now deal with the speed. 507 */ 508 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 509 maccfg2 |= MACCFG2_IFMODE_GMII; 510 } else { 511 maccfg2 |= MACCFG2_IFMODE_MII; 512 ecntrl &= ~ECNTRL_R100M; 513 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 514 ecntrl |= ECNTRL_R100M; 515 } 516 } 517 518 /* 519 * If things are different, re-init things. 520 */ 521 if (maccfg1 != sc->sc_maccfg1 522 || maccfg2 != sc->sc_maccfg2 523 || ecntrl != sc->sc_ecntrl) { 524 if (sc->sc_if.if_flags & IFF_RUNNING) 525 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 526 sc->sc_maccfg1 = maccfg1; 527 sc->sc_maccfg2 = maccfg2; 528 sc->sc_ecntrl = ecntrl; 529 } 530 } 531 532 #if 0 533 static void 534 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 535 { 536 struct pq3etsec_softc * const sc = ifp->if_softc; 537 538 mii_pollstat(&sc->sc_mii); 539 ether_mediastatus(ifp, ifmr); 540 ifmr->ifm_status = sc->sc_mii.mii_media_status; 541 ifmr->ifm_active = sc->sc_mii.mii_media_active; 542 } 543 544 static int 545 pq3etsec_mediachange(struct ifnet *ifp) 546 { 547 struct pq3etsec_softc * const sc = ifp->if_softc; 548 549 if ((ifp->if_flags & IFF_UP) == 0) 550 return 0; 551 552 int rv = mii_mediachg(&sc->sc_mii); 553 return (rv == ENXIO) ? 0 : rv; 554 } 555 #endif 556 557 static int 558 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 559 { 560 561 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 562 return 0; 563 564 return 1; 565 } 566 567 static void 568 pq3etsec_attach(device_t parent, device_t self, void *aux) 569 { 570 struct cpunode_softc * const psc = device_private(parent); 571 struct pq3etsec_softc * const sc = device_private(self); 572 struct cpunode_attach_args * const cna = aux; 573 struct cpunode_locators * const cnl = &cna->cna_locs; 574 cfdata_t cf = device_cfdata(self); 575 int error; 576 577 psc->sc_children |= cna->cna_childmask; 578 sc->sc_dev = self; 579 sc->sc_bst = cna->cna_memt; 580 sc->sc_dmat = &booke_bus_dma_tag; 581 582 /* 583 * Pull out the mdio bus and phy we are supposed to use. 584 */ 585 const int mdio = cf->cf_loc[CPUNODECF_MDIO]; 586 const int phy = cf->cf_loc[CPUNODECF_PHY]; 587 if (mdio != CPUNODECF_MDIO_DEFAULT) 588 aprint_normal(" mdio %d", mdio); 589 590 /* 591 * See if the phy is in the config file... 592 */ 593 if (phy != CPUNODECF_PHY_DEFAULT) { 594 sc->sc_phy_addr = phy; 595 } else { 596 unsigned char prop_name[20]; 597 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 598 cnl->cnl_instance); 599 sc->sc_phy_addr = board_info_get_number(prop_name); 600 } 601 if (sc->sc_phy_addr != MII_PHY_ANY) 602 aprint_normal(" phy %d", sc->sc_phy_addr); 603 604 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 605 &sc->sc_bsh); 606 if (error) { 607 aprint_error(": error mapping registers: %d\n", error); 608 return; 609 } 610 611 /* 612 * Assume firmware has aready set the mac address and fetch it 613 * before we reinit it. 614 */ 615 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 616 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 617 sc->sc_rctrl = RCTRL_DEFAULT; 618 sc->sc_ecntrl = etsec_read(sc, ECNTRL); 619 sc->sc_maccfg1 = etsec_read(sc, MACCFG1); 620 sc->sc_maccfg2 = etsec_read(sc, MACCFG2) | MACCFG2_DEFAULT; 621 622 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 623 size_t len; 624 const uint8_t *mac_addr = 625 board_info_get_data("tsec-mac-addr-base", &len); 626 KASSERT(len == ETHER_ADDR_LEN); 627 sc->sc_macstnaddr2 = 628 (mac_addr[1] << 24) 629 | (mac_addr[0] << 16); 630 sc->sc_macstnaddr1 = 631 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 632 | (mac_addr[4] << 16) 633 | (mac_addr[3] << 8) 634 | (mac_addr[2] << 0); 635 #if 0 636 aprint_error(": mac-address unknown\n"); 637 return; 638 #endif 639 } 640 641 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 642 sc->sc_hwlock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_VM); 643 644 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 645 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 646 647 /* Disable interrupts */ 648 etsec_write(sc, IMASK, 0); 649 650 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 651 if (error) { 652 aprint_error(": failed to init rxq: %d\n", error); 653 goto fail_1; 654 } 655 656 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 657 if (error) { 658 aprint_error(": failed to init txq: %d\n", error); 659 goto fail_2; 660 } 661 662 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 663 ETSEC_MAXRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 664 if (error) { 665 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 666 goto fail_3; 667 } 668 669 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 670 ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 671 if (error) { 672 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 673 goto fail_4; 674 } 675 676 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 677 pq3etsec_tx_intr, sc); 678 if (sc->sc_tx_ih == NULL) { 679 aprint_error(": failed to establish tx interrupt: %d\n", 680 cnl->cnl_intrs[0]); 681 goto fail_5; 682 } 683 684 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 685 pq3etsec_rx_intr, sc); 686 if (sc->sc_rx_ih == NULL) { 687 aprint_error(": failed to establish rx interrupt: %d\n", 688 cnl->cnl_intrs[1]); 689 goto fail_6; 690 } 691 692 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 693 pq3etsec_error_intr, sc); 694 if (sc->sc_error_ih == NULL) { 695 aprint_error(": failed to establish error interrupt: %d\n", 696 cnl->cnl_intrs[2]); 697 goto fail_7; 698 } 699 700 int softint_flags = SOFTINT_NET; 701 #if !defined(MULTIPROCESSOR) || defined(NET_MPSAFE) 702 softint_flags |= SOFTINT_MPSAFE; 703 #endif /* !MULTIPROCESSOR || NET_MPSAFE */ 704 sc->sc_soft_ih = softint_establish(softint_flags, 705 pq3etsec_soft_intr, sc); 706 if (sc->sc_soft_ih == NULL) { 707 aprint_error(": failed to establish soft interrupt\n"); 708 goto fail_8; 709 } 710 711 /* 712 * If there was no MDIO 713 */ 714 if (mdio == CPUNODECF_MDIO_DEFAULT) { 715 aprint_normal("\n"); 716 cfdata_t mdio_cf = config_search_ia(pq3mdio_find, self, NULL, cna); 717 if (mdio_cf != NULL) { 718 sc->sc_mdio_dev = config_attach(self, mdio_cf, cna, NULL); 719 } 720 } else { 721 sc->sc_mdio_dev = device_find_by_driver_unit("mdio", mdio); 722 if (sc->sc_mdio_dev == NULL) { 723 aprint_error(": failed to locate mdio device\n"); 724 goto fail_9; 725 } 726 aprint_normal("\n"); 727 } 728 729 etsec_write(sc, ATTR, ATTR_DEFAULT); 730 etsec_write(sc, ATTRELI, ATTRELI_DEFAULT); 731 732 /* Enable interrupt coalesing */ 733 sc->sc_ic_rx_time = 768; 734 sc->sc_ic_rx_count = 16; 735 sc->sc_ic_tx_time = 768; 736 sc->sc_ic_tx_count = 16; 737 pq3etsec_set_ic_rx(sc); 738 pq3etsec_set_ic_tx(sc); 739 740 char enaddr[ETHER_ADDR_LEN] = { 741 [0] = sc->sc_macstnaddr2 >> 16, 742 [1] = sc->sc_macstnaddr2 >> 24, 743 [2] = sc->sc_macstnaddr1 >> 0, 744 [3] = sc->sc_macstnaddr1 >> 8, 745 [4] = sc->sc_macstnaddr1 >> 16, 746 [5] = sc->sc_macstnaddr1 >> 24, 747 }; 748 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 749 ether_sprintf(enaddr)); 750 751 const char * const xname = device_xname(sc->sc_dev); 752 struct ethercom * const ec = &sc->sc_ec; 753 struct ifnet * const ifp = &ec->ec_if; 754 755 ec->ec_mii = &sc->sc_mii; 756 757 sc->sc_mii.mii_ifp = ifp; 758 sc->sc_mii.mii_readreg = pq3mdio_mii_readreg; 759 sc->sc_mii.mii_writereg = pq3mdio_mii_writereg; 760 sc->sc_mii.mii_statchg = pq3etsec_mii_statchg; 761 762 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 763 ether_mediastatus); 764 765 if (sc->sc_mdio_dev != NULL && sc->sc_phy_addr < 32) { 766 mii_attach(sc->sc_mdio_dev, &sc->sc_mii, 0xffffffff, 767 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 768 769 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 770 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 771 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 772 } else { 773 callout_schedule(&sc->sc_mii_callout, hz); 774 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 775 } 776 } else { 777 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 778 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX); 779 } 780 781 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 782 | ETHERCAP_JUMBO_MTU; 783 784 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 785 ifp->if_softc = sc; 786 ifp->if_capabilities = IFCAP_ETSEC; 787 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 788 ifp->if_ioctl = pq3etsec_ifioctl; 789 ifp->if_start = pq3etsec_ifstart; 790 ifp->if_watchdog = pq3etsec_ifwatchdog; 791 ifp->if_init = pq3etsec_ifinit; 792 ifp->if_stop = pq3etsec_ifstop; 793 IFQ_SET_READY(&ifp->if_snd); 794 795 /* 796 * Attach the interface. 797 */ 798 error = if_initialize(ifp); 799 if (error != 0) { 800 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 801 error); 802 goto fail_10; 803 } 804 pq3etsec_sysctl_setup(NULL, sc); 805 ether_ifattach(ifp, enaddr); 806 if_register(ifp); 807 808 pq3etsec_ifstop(ifp, true); 809 810 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 811 NULL, xname, "rx stall"); 812 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 813 NULL, xname, "tx stall"); 814 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 815 NULL, xname, "tx intr"); 816 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 817 NULL, xname, "rx intr"); 818 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 819 NULL, xname, "error intr"); 820 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 821 NULL, xname, "soft intr"); 822 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 823 NULL, xname, "tx pause"); 824 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 825 NULL, xname, "rx pause"); 826 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 827 NULL, xname, "mii ticks"); 828 return; 829 830 fail_10: 831 ifmedia_removeall(&sc->sc_mii.mii_media); 832 mii_detach(&sc->sc_mii, sc->sc_phy_addr, MII_OFFSET_ANY); 833 fail_9: 834 softint_disestablish(sc->sc_soft_ih); 835 fail_8: 836 intr_disestablish(sc->sc_error_ih); 837 fail_7: 838 intr_disestablish(sc->sc_rx_ih); 839 fail_6: 840 intr_disestablish(sc->sc_tx_ih); 841 fail_5: 842 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 843 fail_4: 844 pq3etsec_mapcache_destroy(sc, sc->sc_rx_mapcache); 845 fail_3: 846 #if 0 /* notyet */ 847 pq3etsec_txq_detach(sc); 848 #endif 849 fail_2: 850 #if 0 /* notyet */ 851 pq3etsec_rxq_detach(sc); 852 #endif 853 fail_1: 854 callout_destroy(&sc->sc_mii_callout); 855 mutex_obj_free(sc->sc_lock); 856 mutex_obj_free(sc->sc_hwlock); 857 bus_space_unmap(sc->sc_bst, sc->sc_bsh, cnl->cnl_size); 858 } 859 860 static uint64_t 861 pq3etsec_macaddr_create(const uint8_t *lladdr) 862 { 863 uint64_t macaddr = 0; 864 865 lladdr += ETHER_ADDR_LEN; 866 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 867 macaddr = (macaddr << 8) | *--lladdr; 868 } 869 return macaddr << 16; 870 } 871 872 static int 873 pq3etsec_ifinit(struct ifnet *ifp) 874 { 875 struct pq3etsec_softc * const sc = ifp->if_softc; 876 int error = 0; 877 878 sc->sc_maxfrm = uimax(ifp->if_mtu + 32, MCLBYTES); 879 if (ifp->if_mtu > ETHERMTU_JUMBO) 880 return error; 881 882 KASSERT(ifp->if_flags & IFF_UP); 883 884 /* 885 * Stop the interface (steps 1 to 4 in the Soft Reset and 886 * Reconfigurating Procedure. 887 */ 888 pq3etsec_ifstop(ifp, 0); 889 890 /* 891 * If our frame size has changed (or it's our first time through) 892 * destroy the existing transmit mapcache. 893 */ 894 if (sc->sc_tx_mapcache != NULL 895 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 896 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 897 sc->sc_tx_mapcache = NULL; 898 } 899 900 if (sc->sc_tx_mapcache == NULL) { 901 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 902 ETSEC_MAXTXMBUFS, sc->sc_maxfrm, ETSEC_NTXSEGS); 903 if (error) 904 return error; 905 } 906 907 sc->sc_ev_mii_ticks.ev_count++; 908 mii_tick(&sc->sc_mii); 909 910 if (ifp->if_flags & IFF_PROMISC) { 911 sc->sc_rctrl |= RCTRL_PROM; 912 } else { 913 sc->sc_rctrl &= ~RCTRL_PROM; 914 } 915 916 uint32_t rctrl_prsdep = 0; 917 sc->sc_rctrl &= ~(RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP); 918 if (VLAN_ATTACHED(&sc->sc_ec)) { 919 sc->sc_rctrl |= RCTRL_VLEX; 920 rctrl_prsdep = RCTRL_PRSDEP_L2; 921 } 922 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 923 sc->sc_rctrl |= RCTRL_IPCSEN; 924 rctrl_prsdep = RCTRL_PRSDEP_L3; 925 } 926 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 927 sc->sc_rctrl |= RCTRL_TUCSEN; 928 rctrl_prsdep = RCTRL_PRSDEP_L4; 929 } 930 sc->sc_rctrl |= rctrl_prsdep; 931 #if 0 932 if (sc->sc_rctrl & (RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP)) 933 aprint_normal_dev(sc->sc_dev, 934 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 935 sc->sc_rctrl, 936 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 937 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 938 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 939 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 940 #endif 941 942 sc->sc_tctrl &= ~(TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS); 943 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 944 sc->sc_tctrl |= TCTRL_VLINS; 945 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 946 sc->sc_tctrl |= TCTRL_IPCSEN; 947 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 948 sc->sc_tctrl |= TCTRL_TUCSEN; 949 #if 0 950 if (sc->sc_tctrl & (TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS)) 951 aprint_normal_dev(sc->sc_dev, 952 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 953 sc->sc_tctrl, 954 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 955 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 956 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 957 #endif 958 959 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN|MACCFG1_RX_EN); 960 961 const uint64_t macstnaddr = 962 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 963 964 sc->sc_imask = IEVENT_DPE; 965 966 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 967 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 968 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 969 970 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 971 pq3etsec_txq_reset(sc, &sc->sc_txq); 972 973 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 974 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 975 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 976 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 977 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 978 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 979 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 980 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 981 982 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 983 pq3etsec_mc_setup(sc); 984 985 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 986 etsec_write(sc, MRBLR, MCLBYTES); 987 988 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 989 sc->sc_dmactrl |= DMACTRL_DEFAULT; 990 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 991 992 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 993 etsec_write(sc, TQUEUE, TQUEUE_EN0); 994 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE|IEVENT_TXC; 995 996 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 997 998 /* 12. Enable receive queues in RQUEUE, */ 999 etsec_write(sc, RQUEUE, RQUEUE_EN0|RQUEUE_EX0); 1000 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY|IEVENT_RXC; 1001 1002 /* and optionally set TOE functionality in RCTRL. */ 1003 etsec_write(sc, RCTRL, sc->sc_rctrl); 1004 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 1005 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 1006 sc->sc_rx_adjlen += sizeof(struct rxfcb); 1007 1008 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 1009 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 1010 1011 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 1012 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 1013 1014 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 1015 sc->sc_dmactrl &= ~(DMACTRL_GRS|DMACTRL_GTS); 1016 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1017 1018 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 1019 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1020 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1021 1022 sc->sc_soft_flags = 0; 1023 1024 etsec_write(sc, IMASK, sc->sc_imask); 1025 1026 ifp->if_flags |= IFF_RUNNING; 1027 1028 return error; 1029 } 1030 1031 static void 1032 pq3etsec_ifstop(struct ifnet *ifp, int disable) 1033 { 1034 struct pq3etsec_softc * const sc = ifp->if_softc; 1035 1036 KASSERT(!cpu_intr_p()); 1037 const uint32_t imask_gsc_mask = IEVENT_GTSC|IEVENT_GRSC; 1038 /* 1039 * Clear the GTSC and GRSC from the interrupt mask until 1040 * we are ready for them. Then clear them from IEVENT, 1041 * request the graceful shutdown, and then enable the 1042 * GTSC and GRSC bits in the mask. This should cause the 1043 * error interrupt to fire which will issue a wakeup to 1044 * allow us to resume. 1045 */ 1046 1047 /* 1048 * 1. Set GRS/GTS bits in DMACTRL register 1049 */ 1050 sc->sc_dmactrl |= DMACTRL_GRS|DMACTRL_GTS; 1051 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 1052 etsec_write(sc, IEVENT, imask_gsc_mask); 1053 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1054 1055 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN|MACCFG1_RX_EN)) { 1056 /* 1057 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 1058 */ 1059 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 1060 1061 u_int timo = 1000; 1062 uint32_t ievent = etsec_read(sc, IEVENT); 1063 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 1064 if (--timo == 0) { 1065 aprint_error_dev(sc->sc_dev, 1066 "WARNING: " 1067 "request to stop failed (IEVENT=%#x)\n", 1068 ievent); 1069 break; 1070 } 1071 delay(10); 1072 ievent = etsec_read(sc, IEVENT); 1073 } 1074 } 1075 1076 /* 1077 * Now reset the controller. 1078 * 1079 * 3. Set SOFT_RESET bit in MACCFG1 register 1080 * 4. Clear SOFT_RESET bit in MACCFG1 register 1081 */ 1082 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 1083 etsec_write(sc, MACCFG1, 0); 1084 etsec_write(sc, IMASK, 0); 1085 etsec_write(sc, IEVENT, ~0); 1086 sc->sc_imask = 0; 1087 ifp->if_flags &= ~IFF_RUNNING; 1088 1089 uint32_t tbipa = etsec_read(sc, TBIPA); 1090 if (tbipa == sc->sc_phy_addr) { 1091 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 1092 etsec_write(sc, TBIPA, 0x1f); 1093 } 1094 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 1095 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 1096 etsec_write(sc, MIIMCFG, miimcfg); 1097 1098 /* 1099 * Let's consume any remaing transmitted packets. And if we are 1100 * disabling the interface, purge ourselves of any untransmitted 1101 * packets. But don't consume any received packets, just drop them. 1102 * If we aren't disabling the interface, save the mbufs in the 1103 * receive queue for reuse. 1104 */ 1105 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 1106 pq3etsec_txq_consume(sc, &sc->sc_txq); 1107 if (disable) { 1108 pq3etsec_txq_purge(sc, &sc->sc_txq); 1109 IFQ_PURGE(&ifp->if_snd); 1110 } 1111 } 1112 1113 static void 1114 pq3etsec_ifwatchdog(struct ifnet *ifp) 1115 { 1116 } 1117 1118 static void 1119 pq3etsec_mc_setup( 1120 struct pq3etsec_softc *sc) 1121 { 1122 struct ethercom * const ec = &sc->sc_ec; 1123 struct ifnet * const ifp = &sc->sc_if; 1124 struct ether_multi *enm; 1125 struct ether_multistep step; 1126 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 1127 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 1128 1129 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 1130 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1131 1132 ifp->if_flags &= ~IFF_ALLMULTI; 1133 1134 ETHER_FIRST_MULTI(step, ec, enm); 1135 for (u_int i = 0; enm != NULL; ) { 1136 const char *addr = enm->enm_addrlo; 1137 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1138 ifp->if_flags |= IFF_ALLMULTI; 1139 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 1140 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1141 break; 1142 } 1143 if ((sc->sc_rctrl & RCTRL_EMEN) 1144 && i < __arraycount(sc->sc_macaddrs)) { 1145 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 1146 } else { 1147 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1148 #if 0 1149 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 1150 ether_sprintf(addr), crc, 1151 crc >> crc_shift, 1152 crc >> (crc_shift + 5), 1153 (crc >> crc_shift) & 31, 1154 1 << (((crc >> crc_shift) & 31) ^ 31)); 1155 #endif 1156 /* 1157 * The documentation doesn't completely follow PowerPC 1158 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 1159 * is 0x7fa32d9b. By empirical testing, the 1160 * corresponding hash bit is word 3, bit 31 (ppc bit 1161 * order). Since 3 << 31 | 31 is 0x7f, we deduce 1162 * H[0:2] selects the register while H[3:7] selects 1163 * the bit (ppc bit order). 1164 */ 1165 crc >>= crc_shift; 1166 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 1167 } 1168 ETHER_NEXT_MULTI(step, enm); 1169 } 1170 for (u_int i = 0; i < 8; i++) { 1171 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 1172 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 1173 #if 0 1174 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 1175 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 1176 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 1177 i, GADDR(i), etsec_read(sc, GADDR(i))); 1178 #endif 1179 } 1180 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 1181 uint64_t macaddr = sc->sc_macaddrs[i]; 1182 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 1183 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 1184 #if 0 1185 if (macaddr) 1186 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 1187 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1188 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1189 #endif 1190 } 1191 } 1192 1193 static int 1194 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1195 { 1196 struct pq3etsec_softc *sc = ifp->if_softc; 1197 struct ifreq * const ifr = data; 1198 const int s = splnet(); 1199 int error; 1200 1201 switch (cmd) { 1202 case SIOCSIFMEDIA: 1203 case SIOCGIFMEDIA: 1204 /* Flow control requires full-duplex mode. */ 1205 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1206 (ifr->ifr_media & IFM_FDX) == 0) 1207 ifr->ifr_media &= ~IFM_ETH_FMASK; 1208 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1209 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1210 /* We can do both TXPAUSE and RXPAUSE. */ 1211 ifr->ifr_media |= 1212 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1213 } 1214 } 1215 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1216 break; 1217 1218 default: 1219 error = ether_ioctl(ifp, cmd, data); 1220 if (error != ENETRESET) 1221 break; 1222 1223 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1224 error = 0; 1225 if (ifp->if_flags & IFF_RUNNING) 1226 pq3etsec_mc_setup(sc); 1227 break; 1228 } 1229 error = pq3etsec_ifinit(ifp); 1230 break; 1231 } 1232 1233 splx(s); 1234 return error; 1235 } 1236 1237 static void 1238 pq3etsec_rxq_desc_presync( 1239 struct pq3etsec_softc *sc, 1240 struct pq3etsec_rxqueue *rxq, 1241 volatile struct rxbd *rxbd, 1242 size_t count) 1243 { 1244 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1245 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1246 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1247 } 1248 1249 static void 1250 pq3etsec_rxq_desc_postsync( 1251 struct pq3etsec_softc *sc, 1252 struct pq3etsec_rxqueue *rxq, 1253 volatile struct rxbd *rxbd, 1254 size_t count) 1255 { 1256 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1257 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1258 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1259 } 1260 1261 static void 1262 pq3etsec_txq_desc_presync( 1263 struct pq3etsec_softc *sc, 1264 struct pq3etsec_txqueue *txq, 1265 volatile struct txbd *txbd, 1266 size_t count) 1267 { 1268 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1269 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1270 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1271 } 1272 1273 static void 1274 pq3etsec_txq_desc_postsync( 1275 struct pq3etsec_softc *sc, 1276 struct pq3etsec_txqueue *txq, 1277 volatile struct txbd *txbd, 1278 size_t count) 1279 { 1280 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1281 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1282 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1283 } 1284 1285 static bus_dmamap_t 1286 pq3etsec_mapcache_get( 1287 struct pq3etsec_softc *sc, 1288 struct pq3etsec_mapcache *dmc) 1289 { 1290 KASSERT(dmc->dmc_nmaps > 0); 1291 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1292 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1293 } 1294 1295 static void 1296 pq3etsec_mapcache_put( 1297 struct pq3etsec_softc *sc, 1298 struct pq3etsec_mapcache *dmc, 1299 bus_dmamap_t map) 1300 { 1301 KASSERT(map != NULL); 1302 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1303 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1304 } 1305 1306 static void 1307 pq3etsec_mapcache_destroy( 1308 struct pq3etsec_softc *sc, 1309 struct pq3etsec_mapcache *dmc) 1310 { 1311 const size_t dmc_size = 1312 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1313 1314 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1315 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1316 } 1317 kmem_intr_free(dmc, dmc_size); 1318 } 1319 1320 static int 1321 pq3etsec_mapcache_create( 1322 struct pq3etsec_softc *sc, 1323 struct pq3etsec_mapcache **dmc_p, 1324 size_t maxmaps, 1325 size_t maxmapsize, 1326 size_t maxseg) 1327 { 1328 const size_t dmc_size = 1329 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1330 struct pq3etsec_mapcache * const dmc = 1331 kmem_intr_zalloc(dmc_size, KM_NOSLEEP); 1332 1333 dmc->dmc_maxmaps = maxmaps; 1334 dmc->dmc_nmaps = maxmaps; 1335 dmc->dmc_maxmapsize = maxmapsize; 1336 dmc->dmc_maxseg = maxseg; 1337 1338 for (u_int i = 0; i < maxmaps; i++) { 1339 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1340 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1341 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1342 if (error) { 1343 aprint_error_dev(sc->sc_dev, 1344 "failed to creat dma map cache " 1345 "entry %u of %zu: %d\n", 1346 i, maxmaps, error); 1347 while (i-- > 0) { 1348 bus_dmamap_destroy(sc->sc_dmat, 1349 dmc->dmc_maps[i]); 1350 } 1351 kmem_intr_free(dmc, dmc_size); 1352 return error; 1353 } 1354 KASSERT(dmc->dmc_maps[i] != NULL); 1355 } 1356 1357 *dmc_p = dmc; 1358 1359 return 0; 1360 } 1361 1362 #if 0 1363 static void 1364 pq3etsec_dmamem_free( 1365 bus_dma_tag_t dmat, 1366 size_t map_size, 1367 bus_dma_segment_t *seg, 1368 bus_dmamap_t map, 1369 void *kvap) 1370 { 1371 bus_dmamap_destroy(dmat, map); 1372 bus_dmamem_unmap(dmat, kvap, map_size); 1373 bus_dmamem_free(dmat, seg, 1); 1374 } 1375 #endif 1376 1377 static int 1378 pq3etsec_dmamem_alloc( 1379 bus_dma_tag_t dmat, 1380 size_t map_size, 1381 bus_dma_segment_t *seg, 1382 bus_dmamap_t *map, 1383 void **kvap) 1384 { 1385 int error; 1386 int nseg; 1387 1388 *kvap = NULL; 1389 *map = NULL; 1390 1391 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1392 seg, 1, &nseg, 0); 1393 if (error) 1394 return error; 1395 1396 KASSERT(nseg == 1); 1397 1398 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1399 BUS_DMA_COHERENT); 1400 if (error == 0) { 1401 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1402 map); 1403 if (error == 0) { 1404 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1405 NULL, 0); 1406 if (error == 0) 1407 return 0; 1408 bus_dmamap_destroy(dmat, *map); 1409 *map = NULL; 1410 } 1411 bus_dmamem_unmap(dmat, *kvap, map_size); 1412 *kvap = NULL; 1413 } 1414 bus_dmamem_free(dmat, seg, nseg); 1415 return 0; 1416 } 1417 1418 static struct mbuf * 1419 pq3etsec_rx_buf_alloc( 1420 struct pq3etsec_softc *sc) 1421 { 1422 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1423 if (m == NULL) { 1424 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1425 return NULL; 1426 } 1427 MCLGET(m, M_DONTWAIT); 1428 if ((m->m_flags & M_EXT) == 0) { 1429 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1430 m_freem(m); 1431 return NULL; 1432 } 1433 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1434 1435 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1436 if (map == NULL) { 1437 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1438 m_freem(m); 1439 return NULL; 1440 } 1441 M_SETCTX(m, map); 1442 m->m_len = m->m_pkthdr.len = MCLBYTES; 1443 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1444 BUS_DMA_READ|BUS_DMA_NOWAIT); 1445 if (error) { 1446 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1447 error); 1448 M_SETCTX(m, NULL); 1449 m_freem(m); 1450 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1451 return NULL; 1452 } 1453 KASSERT(map->dm_mapsize == MCLBYTES); 1454 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1455 BUS_DMASYNC_PREREAD); 1456 1457 return m; 1458 } 1459 1460 static void 1461 pq3etsec_rx_map_unload( 1462 struct pq3etsec_softc *sc, 1463 struct mbuf *m) 1464 { 1465 KASSERT(m); 1466 for (; m != NULL; m = m->m_next) { 1467 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1468 KASSERT(map); 1469 KASSERT(map->dm_mapsize == MCLBYTES); 1470 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1471 BUS_DMASYNC_POSTREAD); 1472 bus_dmamap_unload(sc->sc_dmat, map); 1473 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1474 M_SETCTX(m, NULL); 1475 } 1476 } 1477 1478 static bool 1479 pq3etsec_rxq_produce( 1480 struct pq3etsec_softc *sc, 1481 struct pq3etsec_rxqueue *rxq) 1482 { 1483 volatile struct rxbd *producer = rxq->rxq_producer; 1484 #if 0 1485 size_t inuse = rxq->rxq_inuse; 1486 #endif 1487 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1488 struct mbuf *m; 1489 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1490 if (m == NULL) { 1491 m = pq3etsec_rx_buf_alloc(sc); 1492 if (m == NULL) { 1493 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1494 break; 1495 } 1496 } 1497 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1498 KASSERT(map); 1499 1500 #ifdef ETSEC_DEBUG 1501 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1502 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1503 #endif 1504 1505 /* rxbd_len is write-only by the ETSEC */ 1506 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1507 membar_producer(); 1508 producer->rxbd_flags |= RXBD_E; 1509 if (__predict_false(rxq->rxq_mhead == NULL)) { 1510 KASSERT(producer == rxq->rxq_consumer); 1511 rxq->rxq_mconsumer = m; 1512 } 1513 *rxq->rxq_mtail = m; 1514 rxq->rxq_mtail = &m->m_next; 1515 m->m_len = MCLBYTES; 1516 m->m_next = NULL; 1517 rxq->rxq_inuse++; 1518 if (++producer == rxq->rxq_last) { 1519 membar_producer(); 1520 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1521 rxq->rxq_last - rxq->rxq_producer); 1522 producer = rxq->rxq_producer = rxq->rxq_first; 1523 } 1524 } 1525 if (producer != rxq->rxq_producer) { 1526 membar_producer(); 1527 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1528 producer - rxq->rxq_producer); 1529 rxq->rxq_producer = producer; 1530 } 1531 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1532 if (qhlt) { 1533 KASSERT(qhlt & rxq->rxq_qmask); 1534 sc->sc_ev_rx_stall.ev_count++; 1535 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1536 } 1537 #if 0 1538 aprint_normal_dev(sc->sc_dev, 1539 "%s: buffers inuse went from %zu to %zu\n", 1540 __func__, inuse, rxq->rxq_inuse); 1541 #endif 1542 return true; 1543 } 1544 1545 static bool 1546 pq3etsec_rx_offload( 1547 struct pq3etsec_softc *sc, 1548 struct mbuf *m, 1549 const struct rxfcb *fcb) 1550 { 1551 if (fcb->rxfcb_flags & RXFCB_VLN) { 1552 vlan_set_tag(m, fcb->rxfcb_vlctl); 1553 } 1554 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1555 || (fcb->rxfcb_flags & (RXFCB_CIP|RXFCB_CTU)) == 0) 1556 return true; 1557 int csum_flags = 0; 1558 if ((fcb->rxfcb_flags & (RXFCB_IP6|RXFCB_CIP)) == RXFCB_CIP) { 1559 csum_flags |= M_CSUM_IPv4; 1560 if (fcb->rxfcb_flags & RXFCB_EIP) 1561 csum_flags |= M_CSUM_IPv4_BAD; 1562 } 1563 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1564 int ipv_flags; 1565 if (fcb->rxfcb_flags & RXFCB_IP6) 1566 ipv_flags = M_CSUM_TCPv6|M_CSUM_UDPv6; 1567 else 1568 ipv_flags = M_CSUM_TCPv4|M_CSUM_UDPv4; 1569 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1570 csum_flags |= (M_CSUM_TCPv4|M_CSUM_TCPv6) & ipv_flags; 1571 } else { 1572 csum_flags |= (M_CSUM_UDPv4|M_CSUM_UDPv6) & ipv_flags; 1573 } 1574 if (fcb->rxfcb_flags & RXFCB_ETU) 1575 csum_flags |= M_CSUM_TCP_UDP_BAD; 1576 } 1577 1578 m->m_pkthdr.csum_flags = csum_flags; 1579 return true; 1580 } 1581 1582 static void 1583 pq3etsec_rx_input( 1584 struct pq3etsec_softc *sc, 1585 struct mbuf *m, 1586 uint16_t rxbd_flags) 1587 { 1588 struct ifnet * const ifp = &sc->sc_if; 1589 1590 pq3etsec_rx_map_unload(sc, m); 1591 1592 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1593 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1594 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1595 return; 1596 } 1597 m_adj(m, sc->sc_rx_adjlen); 1598 1599 if (rxbd_flags & RXBD_M) 1600 m->m_flags |= M_PROMISC; 1601 if (rxbd_flags & RXBD_BC) 1602 m->m_flags |= M_BCAST; 1603 if (rxbd_flags & RXBD_MC) 1604 m->m_flags |= M_MCAST; 1605 m->m_flags |= M_HASFCS; 1606 m_set_rcvif(m, &sc->sc_if); 1607 1608 ifp->if_ibytes += m->m_pkthdr.len; 1609 1610 /* 1611 * Let's give it to the network subsystm to deal with. 1612 */ 1613 int s = splnet(); 1614 if_input(ifp, m); 1615 splx(s); 1616 } 1617 1618 static void 1619 pq3etsec_rxq_consume( 1620 struct pq3etsec_softc *sc, 1621 struct pq3etsec_rxqueue *rxq) 1622 { 1623 struct ifnet * const ifp = &sc->sc_if; 1624 volatile struct rxbd *consumer = rxq->rxq_consumer; 1625 size_t rxconsumed = 0; 1626 1627 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1628 1629 for (;;) { 1630 if (consumer == rxq->rxq_producer) { 1631 rxq->rxq_consumer = consumer; 1632 rxq->rxq_inuse -= rxconsumed; 1633 KASSERT(rxq->rxq_inuse == 0); 1634 return; 1635 } 1636 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1637 const uint16_t rxbd_flags = consumer->rxbd_flags; 1638 if (rxbd_flags & RXBD_E) { 1639 rxq->rxq_consumer = consumer; 1640 rxq->rxq_inuse -= rxconsumed; 1641 return; 1642 } 1643 KASSERT(rxq->rxq_mconsumer != NULL); 1644 #ifdef ETSEC_DEBUG 1645 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1646 #endif 1647 #if 0 1648 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1649 __func__, 1650 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1651 mtod(rxq->rxq_mconsumer, int *)[0], 1652 mtod(rxq->rxq_mconsumer, int *)[1], 1653 mtod(rxq->rxq_mconsumer, int *)[2], 1654 mtod(rxq->rxq_mconsumer, int *)[3]); 1655 #endif 1656 /* 1657 * We own this packet again. Clear all flags except wrap. 1658 */ 1659 rxconsumed++; 1660 consumer->rxbd_flags = rxbd_flags & (RXBD_W|RXBD_I); 1661 1662 /* 1663 * If this descriptor has the LAST bit set and no errors, 1664 * it's a valid input packet. 1665 */ 1666 if ((rxbd_flags & (RXBD_L|RXBD_ERRORS)) == RXBD_L) { 1667 size_t rxbd_len = consumer->rxbd_len; 1668 struct mbuf *m = rxq->rxq_mhead; 1669 struct mbuf *m_last = rxq->rxq_mconsumer; 1670 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1671 rxq->rxq_mtail = &rxq->rxq_mhead; 1672 rxq->rxq_mconsumer = rxq->rxq_mhead; 1673 m_last->m_next = NULL; 1674 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1675 m->m_pkthdr.len = rxbd_len; 1676 pq3etsec_rx_input(sc, m, rxbd_flags); 1677 } else if (rxbd_flags & RXBD_L) { 1678 KASSERT(rxbd_flags & RXBD_ERRORS); 1679 struct mbuf *m; 1680 /* 1681 * We encountered an error, take the mbufs and add 1682 * then to the rx bufcache so we can reuse them. 1683 */ 1684 ifp->if_ierrors++; 1685 for (m = rxq->rxq_mhead; 1686 m != rxq->rxq_mconsumer; 1687 m = m->m_next) { 1688 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1689 } 1690 m = rxq->rxq_mconsumer; 1691 if ((rxq->rxq_mhead = m->m_next) == NULL) 1692 rxq->rxq_mtail = &rxq->rxq_mhead; 1693 rxq->rxq_mconsumer = m->m_next; 1694 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1695 } else { 1696 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1697 } 1698 #ifdef ETSEC_DEBUG 1699 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1700 #endif 1701 1702 /* 1703 * Wrap at the last entry! 1704 */ 1705 if (rxbd_flags & RXBD_W) { 1706 KASSERT(consumer + 1 == rxq->rxq_last); 1707 consumer = rxq->rxq_first; 1708 } else { 1709 consumer++; 1710 } 1711 #ifdef ETSEC_DEBUG 1712 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1713 #endif 1714 } 1715 } 1716 1717 static void 1718 pq3etsec_rxq_purge( 1719 struct pq3etsec_softc *sc, 1720 struct pq3etsec_rxqueue *rxq, 1721 bool discard) 1722 { 1723 struct mbuf *m; 1724 1725 if ((m = rxq->rxq_mhead) != NULL) { 1726 #ifdef ETSEC_DEBUG 1727 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1728 #endif 1729 1730 if (discard) { 1731 pq3etsec_rx_map_unload(sc, m); 1732 m_freem(m); 1733 } else { 1734 while (m != NULL) { 1735 struct mbuf *m0 = m->m_next; 1736 m->m_next = NULL; 1737 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1738 m = m0; 1739 } 1740 } 1741 1742 } 1743 1744 rxq->rxq_mconsumer = NULL; 1745 rxq->rxq_mhead = NULL; 1746 rxq->rxq_mtail = &rxq->rxq_mhead; 1747 rxq->rxq_inuse = 0; 1748 } 1749 1750 static void 1751 pq3etsec_rxq_reset( 1752 struct pq3etsec_softc *sc, 1753 struct pq3etsec_rxqueue *rxq) 1754 { 1755 /* 1756 * sync all the descriptors 1757 */ 1758 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1759 rxq->rxq_last - rxq->rxq_first); 1760 1761 /* 1762 * Make sure we own all descriptors in the ring. 1763 */ 1764 volatile struct rxbd *rxbd; 1765 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1766 rxbd->rxbd_flags = RXBD_I; 1767 } 1768 1769 /* 1770 * Last descriptor has the wrap flag. 1771 */ 1772 rxbd->rxbd_flags = RXBD_W|RXBD_I; 1773 1774 /* 1775 * Reset the producer consumer indexes. 1776 */ 1777 rxq->rxq_consumer = rxq->rxq_first; 1778 rxq->rxq_producer = rxq->rxq_first; 1779 rxq->rxq_inuse = 0; 1780 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1781 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1782 1783 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY; 1784 1785 /* 1786 * Restart the transmit at the first descriptor 1787 */ 1788 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1789 } 1790 1791 static int 1792 pq3etsec_rxq_attach( 1793 struct pq3etsec_softc *sc, 1794 struct pq3etsec_rxqueue *rxq, 1795 u_int qno) 1796 { 1797 size_t map_size = PAGE_SIZE; 1798 size_t desc_count = map_size / sizeof(struct rxbd); 1799 int error; 1800 void *descs; 1801 1802 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1803 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1804 if (error) 1805 return error; 1806 1807 memset(descs, 0, map_size); 1808 rxq->rxq_first = descs; 1809 rxq->rxq_last = rxq->rxq_first + desc_count; 1810 rxq->rxq_consumer = descs; 1811 rxq->rxq_producer = descs; 1812 1813 pq3etsec_rxq_purge(sc, rxq, true); 1814 pq3etsec_rxq_reset(sc, rxq); 1815 1816 rxq->rxq_reg_rbase = RBASEn(qno); 1817 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1818 1819 return 0; 1820 } 1821 1822 static bool 1823 pq3etsec_txq_active_p( 1824 struct pq3etsec_softc * const sc, 1825 struct pq3etsec_txqueue *txq) 1826 { 1827 return !IF_IS_EMPTY(&txq->txq_mbufs); 1828 } 1829 1830 static bool 1831 pq3etsec_txq_fillable_p( 1832 struct pq3etsec_softc * const sc, 1833 struct pq3etsec_txqueue *txq) 1834 { 1835 return txq->txq_free >= txq->txq_threshold; 1836 } 1837 1838 static int 1839 pq3etsec_txq_attach( 1840 struct pq3etsec_softc *sc, 1841 struct pq3etsec_txqueue *txq, 1842 u_int qno) 1843 { 1844 size_t map_size = PAGE_SIZE; 1845 size_t desc_count = map_size / sizeof(struct txbd); 1846 int error; 1847 void *descs; 1848 1849 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1850 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1851 if (error) 1852 return error; 1853 1854 memset(descs, 0, map_size); 1855 txq->txq_first = descs; 1856 txq->txq_last = txq->txq_first + desc_count; 1857 txq->txq_consumer = descs; 1858 txq->txq_producer = descs; 1859 1860 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1861 1862 txq->txq_reg_tbase = TBASEn(qno); 1863 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1864 1865 pq3etsec_txq_reset(sc, txq); 1866 1867 return 0; 1868 } 1869 1870 static int 1871 pq3etsec_txq_map_load( 1872 struct pq3etsec_softc *sc, 1873 struct pq3etsec_txqueue *txq, 1874 struct mbuf *m) 1875 { 1876 bus_dmamap_t map; 1877 int error; 1878 1879 map = M_GETCTX(m, bus_dmamap_t); 1880 if (map != NULL) 1881 return 0; 1882 1883 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1884 if (map == NULL) 1885 return ENOMEM; 1886 1887 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1888 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1889 if (error) 1890 return error; 1891 1892 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1893 BUS_DMASYNC_PREWRITE); 1894 M_SETCTX(m, map); 1895 return 0; 1896 } 1897 1898 static void 1899 pq3etsec_txq_map_unload( 1900 struct pq3etsec_softc *sc, 1901 struct pq3etsec_txqueue *txq, 1902 struct mbuf *m) 1903 { 1904 KASSERT(m); 1905 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1906 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1907 BUS_DMASYNC_POSTWRITE); 1908 bus_dmamap_unload(sc->sc_dmat, map); 1909 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1910 } 1911 1912 static bool 1913 pq3etsec_txq_produce( 1914 struct pq3etsec_softc *sc, 1915 struct pq3etsec_txqueue *txq, 1916 struct mbuf *m) 1917 { 1918 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1919 1920 if (map->dm_nsegs > txq->txq_free) 1921 return false; 1922 1923 /* 1924 * TCP Offload flag must be set in the first descriptor. 1925 */ 1926 volatile struct txbd *producer = txq->txq_producer; 1927 uint16_t last_flags = TXBD_L; 1928 uint16_t first_flags = TXBD_R 1929 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1930 1931 /* 1932 * If we've produced enough descriptors without consuming any 1933 * we need to ask for an interrupt to reclaim some. 1934 */ 1935 txq->txq_lastintr += map->dm_nsegs; 1936 if (ETSEC_IC_TX_ENABLED(sc) 1937 || txq->txq_lastintr >= txq->txq_threshold 1938 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1939 txq->txq_lastintr = 0; 1940 last_flags |= TXBD_I; 1941 } 1942 1943 #ifdef ETSEC_DEBUG 1944 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1945 #endif 1946 KASSERT(producer != txq->txq_last); 1947 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1948 producer->txbd_len = map->dm_segs[0].ds_len; 1949 1950 if (map->dm_nsegs > 1) { 1951 volatile struct txbd *start = producer + 1; 1952 size_t count = map->dm_nsegs - 1; 1953 for (u_int i = 1; i < map->dm_nsegs; i++) { 1954 if (__predict_false(++producer == txq->txq_last)) { 1955 producer = txq->txq_first; 1956 if (start < txq->txq_last) { 1957 pq3etsec_txq_desc_presync(sc, txq, 1958 start, txq->txq_last - start); 1959 count -= txq->txq_last - start; 1960 } 1961 start = txq->txq_first; 1962 } 1963 #ifdef ETSEC_DEBUG 1964 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1965 #endif 1966 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1967 producer->txbd_len = map->dm_segs[i].ds_len; 1968 producer->txbd_flags = TXBD_R 1969 | (producer->txbd_flags & TXBD_W) 1970 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1971 #if 0 1972 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1973 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1974 #endif 1975 } 1976 pq3etsec_txq_desc_presync(sc, txq, start, count); 1977 } else { 1978 first_flags |= last_flags; 1979 } 1980 1981 membar_producer(); 1982 txq->txq_producer->txbd_flags = 1983 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1984 #if 0 1985 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1986 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1987 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1988 #endif 1989 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1990 1991 /* 1992 * Reduce free count by the number of segments we consumed. 1993 */ 1994 txq->txq_free -= map->dm_nsegs; 1995 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 1996 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 1997 KASSERT(producer->txbd_flags & TXBD_L); 1998 #ifdef ETSEC_DEBUG 1999 txq->txq_lmbufs[producer - txq->txq_first] = m; 2000 #endif 2001 2002 #if 0 2003 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 2004 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 2005 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 2006 #endif 2007 2008 if (++producer == txq->txq_last) 2009 txq->txq_producer = txq->txq_first; 2010 else 2011 txq->txq_producer = producer; 2012 IF_ENQUEUE(&txq->txq_mbufs, m); 2013 2014 /* 2015 * Restart the transmitter. 2016 */ 2017 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 2018 2019 return true; 2020 } 2021 2022 static void 2023 pq3etsec_tx_offload( 2024 struct pq3etsec_softc *sc, 2025 struct pq3etsec_txqueue *txq, 2026 struct mbuf **mp) 2027 { 2028 struct mbuf *m = *mp; 2029 u_int csum_flags = m->m_pkthdr.csum_flags; 2030 bool have_vtag; 2031 uint16_t vtag; 2032 2033 KASSERT(m->m_flags & M_PKTHDR); 2034 2035 have_vtag = vlan_has_tag(m); 2036 vtag = (have_vtag) ? vlan_get_tag(m) : 0; 2037 2038 /* 2039 * Let see if we are doing any offload first. 2040 */ 2041 if (csum_flags == 0 && !have_vtag) { 2042 m->m_flags &= ~M_HASFCB; 2043 return; 2044 } 2045 2046 uint16_t flags = 0; 2047 if (csum_flags & M_CSUM_IP) { 2048 flags |= TXFCB_IP 2049 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 2050 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 2051 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 2052 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 2053 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 2054 } 2055 if (have_vtag) { 2056 flags |= TXFCB_VLN; 2057 } 2058 if (flags == 0) { 2059 m->m_flags &= ~M_HASFCB; 2060 return; 2061 } 2062 2063 struct txfcb fcb; 2064 fcb.txfcb_flags = flags; 2065 if (csum_flags & M_CSUM_IPv4) 2066 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2067 else 2068 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2069 fcb.txfcb_l3os = ETHER_HDR_LEN; 2070 fcb.txfcb_phcs = 0; 2071 fcb.txfcb_vlctl = vtag; 2072 2073 #if 0 2074 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 2075 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 2076 fcb.txfcb_phcs, fcb.txfcb_vlctl); 2077 #endif 2078 2079 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 2080 m->m_data -= sizeof(fcb); 2081 m->m_len += sizeof(fcb); 2082 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 2083 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 2084 m->m_data = m->m_pktdat; 2085 m->m_len += sizeof(fcb); 2086 } else { 2087 struct mbuf *mn; 2088 MGET(mn, M_DONTWAIT, m->m_type); 2089 if (mn == NULL) { 2090 if (csum_flags & M_CSUM_IP4) { 2091 #ifdef INET 2092 in_undefer_cksum(m, ETHER_HDR_LEN, 2093 csum_flags & M_CSUM_IP4); 2094 #else 2095 panic("%s: impossible M_CSUM flags %#x", 2096 device_xname(sc->sc_dev), csum_flags); 2097 #endif 2098 } else if (csum_flags & M_CSUM_IP6) { 2099 #ifdef INET6 2100 in6_undefer_cksum(m, ETHER_HDR_LEN, 2101 csum_flags & M_CSUM_IP6); 2102 #else 2103 panic("%s: impossible M_CSUM flags %#x", 2104 device_xname(sc->sc_dev), csum_flags); 2105 #endif 2106 } 2107 2108 m->m_flags &= ~M_HASFCB; 2109 return; 2110 } 2111 2112 m_move_pkthdr(mn, m); 2113 mn->m_next = m; 2114 m = mn; 2115 m_align(m, sizeof(fcb)); 2116 m->m_len = sizeof(fcb); 2117 *mp = m; 2118 } 2119 m->m_pkthdr.len += sizeof(fcb); 2120 m->m_flags |= M_HASFCB; 2121 *mtod(m, struct txfcb *) = fcb; 2122 return; 2123 } 2124 2125 static bool 2126 pq3etsec_txq_enqueue( 2127 struct pq3etsec_softc *sc, 2128 struct pq3etsec_txqueue *txq) 2129 { 2130 for (;;) { 2131 if (IF_QFULL(&txq->txq_mbufs)) 2132 return false; 2133 struct mbuf *m = txq->txq_next; 2134 if (m == NULL) { 2135 int s = splnet(); 2136 IFQ_DEQUEUE(&sc->sc_if.if_snd, m); 2137 splx(s); 2138 if (m == NULL) 2139 return true; 2140 M_SETCTX(m, NULL); 2141 pq3etsec_tx_offload(sc, txq, &m); 2142 } else { 2143 txq->txq_next = NULL; 2144 } 2145 int error = pq3etsec_txq_map_load(sc, txq, m); 2146 if (error) { 2147 aprint_error_dev(sc->sc_dev, 2148 "discarded packet due to " 2149 "dmamap load failure: %d\n", error); 2150 m_freem(m); 2151 continue; 2152 } 2153 KASSERT(txq->txq_next == NULL); 2154 if (!pq3etsec_txq_produce(sc, txq, m)) { 2155 txq->txq_next = m; 2156 return false; 2157 } 2158 KASSERT(txq->txq_next == NULL); 2159 } 2160 } 2161 2162 static bool 2163 pq3etsec_txq_consume( 2164 struct pq3etsec_softc *sc, 2165 struct pq3etsec_txqueue *txq) 2166 { 2167 struct ifnet * const ifp = &sc->sc_if; 2168 volatile struct txbd *consumer = txq->txq_consumer; 2169 size_t txfree = 0; 2170 2171 #if 0 2172 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 2173 #endif 2174 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 2175 2176 for (;;) { 2177 if (consumer == txq->txq_producer) { 2178 txq->txq_consumer = consumer; 2179 txq->txq_free += txfree; 2180 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2181 #if 0 2182 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2183 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2184 #endif 2185 KASSERT(txq->txq_lastintr == 0); 2186 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2187 return true; 2188 } 2189 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2190 const uint16_t txbd_flags = consumer->txbd_flags; 2191 if (txbd_flags & TXBD_R) { 2192 txq->txq_consumer = consumer; 2193 txq->txq_free += txfree; 2194 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2195 #if 0 2196 printf("%s: freed %zu descriptors\n", 2197 __func__, txfree); 2198 #endif 2199 return pq3etsec_txq_fillable_p(sc, txq); 2200 } 2201 2202 /* 2203 * If this is the last descriptor in the chain, get the 2204 * mbuf, free its dmamap, and free the mbuf chain itself. 2205 */ 2206 if (txbd_flags & TXBD_L) { 2207 struct mbuf *m; 2208 2209 IF_DEQUEUE(&txq->txq_mbufs, m); 2210 #ifdef ETSEC_DEBUG 2211 KASSERTMSG( 2212 m == txq->txq_lmbufs[consumer-txq->txq_first], 2213 "%s: %p [%u]: flags %#x m (%p) != %p (%p)", 2214 __func__, consumer, consumer - txq->txq_first, 2215 txbd_flags, m, 2216 &txq->txq_lmbufs[consumer-txq->txq_first], 2217 txq->txq_lmbufs[consumer-txq->txq_first]); 2218 #endif 2219 KASSERT(m); 2220 pq3etsec_txq_map_unload(sc, txq, m); 2221 #if 0 2222 printf("%s: mbuf %p: consumed a %u byte packet\n", 2223 __func__, m, m->m_pkthdr.len); 2224 #endif 2225 if (m->m_flags & M_HASFCB) 2226 m_adj(m, sizeof(struct txfcb)); 2227 bpf_mtap(ifp, m, BPF_D_OUT); 2228 ifp->if_opackets++; 2229 ifp->if_obytes += m->m_pkthdr.len; 2230 if (m->m_flags & M_MCAST) 2231 ifp->if_omcasts++; 2232 if (txbd_flags & TXBD_ERRORS) 2233 ifp->if_oerrors++; 2234 m_freem(m); 2235 #ifdef ETSEC_DEBUG 2236 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2237 #endif 2238 } else { 2239 #ifdef ETSEC_DEBUG 2240 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2241 #endif 2242 } 2243 2244 /* 2245 * We own this packet again. Clear all flags except wrap. 2246 */ 2247 txfree++; 2248 //consumer->txbd_flags = txbd_flags & TXBD_W; 2249 2250 /* 2251 * Wrap at the last entry! 2252 */ 2253 if (txbd_flags & TXBD_W) { 2254 KASSERT(consumer + 1 == txq->txq_last); 2255 consumer = txq->txq_first; 2256 } else { 2257 consumer++; 2258 KASSERT(consumer < txq->txq_last); 2259 } 2260 } 2261 } 2262 2263 static void 2264 pq3etsec_txq_purge( 2265 struct pq3etsec_softc *sc, 2266 struct pq3etsec_txqueue *txq) 2267 { 2268 struct mbuf *m; 2269 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2270 2271 for (;;) { 2272 IF_DEQUEUE(&txq->txq_mbufs, m); 2273 if (m == NULL) 2274 break; 2275 pq3etsec_txq_map_unload(sc, txq, m); 2276 m_freem(m); 2277 } 2278 if ((m = txq->txq_next) != NULL) { 2279 txq->txq_next = NULL; 2280 pq3etsec_txq_map_unload(sc, txq, m); 2281 m_freem(m); 2282 } 2283 #ifdef ETSEC_DEBUG 2284 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2285 #endif 2286 } 2287 2288 static void 2289 pq3etsec_txq_reset( 2290 struct pq3etsec_softc *sc, 2291 struct pq3etsec_txqueue *txq) 2292 { 2293 /* 2294 * sync all the descriptors 2295 */ 2296 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2297 txq->txq_last - txq->txq_first); 2298 2299 /* 2300 * Make sure we own all descriptors in the ring. 2301 */ 2302 volatile struct txbd *txbd; 2303 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2304 txbd->txbd_flags = 0; 2305 } 2306 2307 /* 2308 * Last descriptor has the wrap flag. 2309 */ 2310 txbd->txbd_flags = TXBD_W; 2311 2312 /* 2313 * Reset the producer consumer indexes. 2314 */ 2315 txq->txq_consumer = txq->txq_first; 2316 txq->txq_producer = txq->txq_first; 2317 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2318 txq->txq_threshold = txq->txq_free / 2; 2319 txq->txq_lastintr = 0; 2320 2321 /* 2322 * What do we want to get interrupted on? 2323 */ 2324 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE; 2325 2326 /* 2327 * Restart the transmit at the first descriptor 2328 */ 2329 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2330 } 2331 2332 static void 2333 pq3etsec_ifstart(struct ifnet *ifp) 2334 { 2335 struct pq3etsec_softc * const sc = ifp->if_softc; 2336 2337 if (__predict_false((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)) { 2338 return; 2339 } 2340 2341 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2342 softint_schedule(sc->sc_soft_ih); 2343 } 2344 2345 static void 2346 pq3etsec_tx_error( 2347 struct pq3etsec_softc * const sc) 2348 { 2349 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2350 2351 pq3etsec_txq_consume(sc, txq); 2352 2353 if (pq3etsec_txq_fillable_p(sc, txq)) 2354 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2355 if (sc->sc_txerrors & (IEVENT_LC|IEVENT_CRL|IEVENT_XFUN|IEVENT_BABT)) { 2356 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2357 } 2358 2359 if (pq3etsec_txq_active_p(sc, txq)) 2360 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2361 if (!pq3etsec_txq_enqueue(sc, txq)) { 2362 sc->sc_ev_tx_stall.ev_count++; 2363 sc->sc_if.if_flags |= IFF_OACTIVE; 2364 } 2365 2366 sc->sc_txerrors = 0; 2367 } 2368 2369 int 2370 pq3etsec_tx_intr(void *arg) 2371 { 2372 struct pq3etsec_softc * const sc = arg; 2373 2374 mutex_enter(sc->sc_hwlock); 2375 2376 sc->sc_ev_tx_intr.ev_count++; 2377 2378 uint32_t ievent = etsec_read(sc, IEVENT); 2379 ievent &= IEVENT_TXF|IEVENT_TXB; 2380 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2381 2382 #if 0 2383 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2384 __func__, ievent, etsec_read(sc, IMASK)); 2385 #endif 2386 2387 if (ievent == 0) { 2388 mutex_exit(sc->sc_hwlock); 2389 return 0; 2390 } 2391 2392 sc->sc_imask &= ~(IEVENT_TXF|IEVENT_TXB); 2393 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2394 etsec_write(sc, IMASK, sc->sc_imask); 2395 softint_schedule(sc->sc_soft_ih); 2396 2397 mutex_exit(sc->sc_hwlock); 2398 2399 return 1; 2400 } 2401 2402 int 2403 pq3etsec_rx_intr(void *arg) 2404 { 2405 struct pq3etsec_softc * const sc = arg; 2406 2407 mutex_enter(sc->sc_hwlock); 2408 2409 sc->sc_ev_rx_intr.ev_count++; 2410 2411 uint32_t ievent = etsec_read(sc, IEVENT); 2412 ievent &= IEVENT_RXF|IEVENT_RXB; 2413 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2414 if (ievent == 0) { 2415 mutex_exit(sc->sc_hwlock); 2416 return 0; 2417 } 2418 2419 #if 0 2420 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2421 #endif 2422 2423 sc->sc_imask &= ~(IEVENT_RXF|IEVENT_RXB); 2424 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2425 etsec_write(sc, IMASK, sc->sc_imask); 2426 softint_schedule(sc->sc_soft_ih); 2427 2428 mutex_exit(sc->sc_hwlock); 2429 2430 return 1; 2431 } 2432 2433 int 2434 pq3etsec_error_intr(void *arg) 2435 { 2436 struct pq3etsec_softc * const sc = arg; 2437 2438 mutex_enter(sc->sc_hwlock); 2439 2440 sc->sc_ev_error_intr.ev_count++; 2441 2442 for (int rv = 0, soft_flags = 0;; rv = 1) { 2443 uint32_t ievent = etsec_read(sc, IEVENT); 2444 ievent &= ~(IEVENT_RXF|IEVENT_RXB|IEVENT_TXF|IEVENT_TXB); 2445 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2446 if (ievent == 0) { 2447 if (soft_flags) { 2448 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2449 softint_schedule(sc->sc_soft_ih); 2450 } 2451 mutex_exit(sc->sc_hwlock); 2452 return rv; 2453 } 2454 #if 0 2455 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2456 __func__, ievent, etsec_read(sc, IMASK)); 2457 #endif 2458 2459 if (ievent & (IEVENT_GRSC|IEVENT_GTSC)) { 2460 sc->sc_imask &= ~(IEVENT_GRSC|IEVENT_GTSC); 2461 etsec_write(sc, IMASK, sc->sc_imask); 2462 wakeup(sc); 2463 } 2464 if (ievent & (IEVENT_MMRD|IEVENT_MMWR)) { 2465 sc->sc_imask &= ~(IEVENT_MMRD|IEVENT_MMWR); 2466 etsec_write(sc, IMASK, sc->sc_imask); 2467 wakeup(&sc->sc_mii); 2468 } 2469 if (ievent & IEVENT_BSY) { 2470 soft_flags |= SOFT_RXBSY; 2471 sc->sc_imask &= ~IEVENT_BSY; 2472 etsec_write(sc, IMASK, sc->sc_imask); 2473 } 2474 if (ievent & IEVENT_TXE) { 2475 soft_flags |= SOFT_TXERROR; 2476 sc->sc_imask &= ~IEVENT_TXE; 2477 sc->sc_txerrors |= ievent; 2478 } 2479 if (ievent & IEVENT_TXC) { 2480 sc->sc_ev_tx_pause.ev_count++; 2481 } 2482 if (ievent & IEVENT_RXC) { 2483 sc->sc_ev_rx_pause.ev_count++; 2484 } 2485 if (ievent & IEVENT_DPE) { 2486 soft_flags |= SOFT_RESET; 2487 sc->sc_imask &= ~IEVENT_DPE; 2488 etsec_write(sc, IMASK, sc->sc_imask); 2489 } 2490 } 2491 } 2492 2493 void 2494 pq3etsec_soft_intr(void *arg) 2495 { 2496 struct pq3etsec_softc * const sc = arg; 2497 struct ifnet * const ifp = &sc->sc_if; 2498 uint32_t imask = 0; 2499 2500 mutex_enter(sc->sc_lock); 2501 2502 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2503 2504 sc->sc_ev_soft_intr.ev_count++; 2505 2506 if (soft_flags & SOFT_RESET) { 2507 int s = splnet(); 2508 pq3etsec_ifinit(ifp); 2509 splx(s); 2510 soft_flags = 0; 2511 } 2512 2513 if (soft_flags & SOFT_RXBSY) { 2514 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2515 size_t threshold = 5 * rxq->rxq_threshold / 4; 2516 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2517 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2518 } else { 2519 imask |= IEVENT_BSY; 2520 } 2521 aprint_normal_dev(sc->sc_dev, 2522 "increasing receive buffers from %zu to %zu\n", 2523 rxq->rxq_threshold, threshold); 2524 rxq->rxq_threshold = threshold; 2525 } 2526 2527 if ((soft_flags & SOFT_TXINTR) 2528 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2529 /* 2530 * Let's do what we came here for. Consume transmitted 2531 * packets off the the transmit ring. 2532 */ 2533 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2534 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2535 sc->sc_ev_tx_stall.ev_count++; 2536 ifp->if_flags |= IFF_OACTIVE; 2537 } else { 2538 ifp->if_flags &= ~IFF_OACTIVE; 2539 } 2540 imask |= IEVENT_TXF; 2541 } 2542 2543 if (soft_flags & (SOFT_RXINTR|SOFT_RXBSY)) { 2544 /* 2545 * Let's consume 2546 */ 2547 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2548 imask |= IEVENT_RXF; 2549 } 2550 2551 if (soft_flags & SOFT_TXERROR) { 2552 pq3etsec_tx_error(sc); 2553 imask |= IEVENT_TXE; 2554 } 2555 2556 if (ifp->if_flags & IFF_RUNNING) { 2557 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2558 mutex_spin_enter(sc->sc_hwlock); 2559 sc->sc_imask |= imask; 2560 etsec_write(sc, IMASK, sc->sc_imask); 2561 mutex_spin_exit(sc->sc_hwlock); 2562 } else { 2563 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2564 } 2565 2566 mutex_exit(sc->sc_lock); 2567 } 2568 2569 static void 2570 pq3etsec_mii_tick(void *arg) 2571 { 2572 struct pq3etsec_softc * const sc = arg; 2573 mutex_enter(sc->sc_lock); 2574 callout_ack(&sc->sc_mii_callout); 2575 sc->sc_ev_mii_ticks.ev_count++; 2576 #ifdef DEBUG 2577 uint64_t now = mftb(); 2578 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2579 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2580 __func__, now - sc->sc_mii_last_tick); 2581 callout_stop(&sc->sc_mii_callout); 2582 } 2583 #endif 2584 mii_tick(&sc->sc_mii); 2585 int s = splnet(); 2586 if (sc->sc_soft_flags & SOFT_RESET) 2587 softint_schedule(sc->sc_soft_ih); 2588 splx(s); 2589 callout_schedule(&sc->sc_mii_callout, hz); 2590 #ifdef DEBUG 2591 sc->sc_mii_last_tick = now; 2592 #endif 2593 mutex_exit(sc->sc_lock); 2594 } 2595 2596 static void 2597 pq3etsec_set_ic_rx(struct pq3etsec_softc *sc) 2598 { 2599 uint32_t reg; 2600 2601 if (ETSEC_IC_RX_ENABLED(sc)) { 2602 reg = RXIC_ICEN; 2603 reg |= RXIC_ICFT_SET(sc->sc_ic_rx_count); 2604 reg |= RXIC_ICTT_SET(sc->sc_ic_rx_time); 2605 } else { 2606 /* Disable RX interrupt coalescing */ 2607 reg = 0; 2608 } 2609 2610 etsec_write(sc, RXIC, reg); 2611 } 2612 2613 static void 2614 pq3etsec_set_ic_tx(struct pq3etsec_softc *sc) 2615 { 2616 uint32_t reg; 2617 2618 if (ETSEC_IC_TX_ENABLED(sc)) { 2619 reg = TXIC_ICEN; 2620 reg |= TXIC_ICFT_SET(sc->sc_ic_tx_count); 2621 reg |= TXIC_ICTT_SET(sc->sc_ic_tx_time); 2622 } else { 2623 /* Disable TX interrupt coalescing */ 2624 reg = 0; 2625 } 2626 2627 etsec_write(sc, TXIC, reg); 2628 } 2629 2630 /* 2631 * sysctl 2632 */ 2633 static int 2634 pq3etsec_sysctl_ic_time_helper(SYSCTLFN_ARGS, int *valuep) 2635 { 2636 struct sysctlnode node = *rnode; 2637 struct pq3etsec_softc *sc = rnode->sysctl_data; 2638 int value = *valuep; 2639 int error; 2640 2641 node.sysctl_data = &value; 2642 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2643 if (error != 0 || newp == NULL) 2644 return error; 2645 2646 if (value < 0 || value > 65535) 2647 return EINVAL; 2648 2649 mutex_enter(sc->sc_lock); 2650 *valuep = value; 2651 if (valuep == &sc->sc_ic_rx_time) 2652 pq3etsec_set_ic_rx(sc); 2653 else 2654 pq3etsec_set_ic_tx(sc); 2655 mutex_exit(sc->sc_lock); 2656 2657 return 0; 2658 } 2659 2660 static int 2661 pq3etsec_sysctl_ic_count_helper(SYSCTLFN_ARGS, int *valuep) 2662 { 2663 struct sysctlnode node = *rnode; 2664 struct pq3etsec_softc *sc = rnode->sysctl_data; 2665 int value = *valuep; 2666 int error; 2667 2668 node.sysctl_data = &value; 2669 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2670 if (error != 0 || newp == NULL) 2671 return error; 2672 2673 if (value < 0 || value > 255) 2674 return EINVAL; 2675 2676 mutex_enter(sc->sc_lock); 2677 *valuep = value; 2678 if (valuep == &sc->sc_ic_rx_count) 2679 pq3etsec_set_ic_rx(sc); 2680 else 2681 pq3etsec_set_ic_tx(sc); 2682 mutex_exit(sc->sc_lock); 2683 2684 return 0; 2685 } 2686 2687 static int 2688 pq3etsec_sysctl_ic_rx_time_helper(SYSCTLFN_ARGS) 2689 { 2690 struct pq3etsec_softc *sc = rnode->sysctl_data; 2691 2692 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2693 &sc->sc_ic_rx_time); 2694 } 2695 2696 static int 2697 pq3etsec_sysctl_ic_rx_count_helper(SYSCTLFN_ARGS) 2698 { 2699 struct pq3etsec_softc *sc = rnode->sysctl_data; 2700 2701 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2702 &sc->sc_ic_rx_count); 2703 } 2704 2705 static int 2706 pq3etsec_sysctl_ic_tx_time_helper(SYSCTLFN_ARGS) 2707 { 2708 struct pq3etsec_softc *sc = rnode->sysctl_data; 2709 2710 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2711 &sc->sc_ic_tx_time); 2712 } 2713 2714 static int 2715 pq3etsec_sysctl_ic_tx_count_helper(SYSCTLFN_ARGS) 2716 { 2717 struct pq3etsec_softc *sc = rnode->sysctl_data; 2718 2719 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2720 &sc->sc_ic_tx_count); 2721 } 2722 2723 static void pq3etsec_sysctl_setup(struct sysctllog **clog, 2724 struct pq3etsec_softc *sc) 2725 { 2726 const struct sysctlnode *cnode, *rnode; 2727 2728 if (sysctl_createv(clog, 0, NULL, &rnode, 2729 CTLFLAG_PERMANENT, 2730 CTLTYPE_NODE, device_xname(sc->sc_dev), 2731 SYSCTL_DESCR("TSEC interface"), 2732 NULL, 0, NULL, 0, 2733 CTL_HW, CTL_CREATE, CTL_EOL) != 0) 2734 goto bad; 2735 2736 if (sysctl_createv(clog, 0, &rnode, &rnode, 2737 CTLFLAG_PERMANENT, 2738 CTLTYPE_NODE, "int_coal", 2739 SYSCTL_DESCR("Interrupts coalescing"), 2740 NULL, 0, NULL, 0, 2741 CTL_CREATE, CTL_EOL) != 0) 2742 goto bad; 2743 2744 if (sysctl_createv(clog, 0, &rnode, &cnode, 2745 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 2746 CTLTYPE_INT, "rx_time", 2747 SYSCTL_DESCR("RX time threshold (0-65535)"), 2748 pq3etsec_sysctl_ic_rx_time_helper, 0, (void *)sc, 0, 2749 CTL_CREATE, CTL_EOL) != 0) 2750 goto bad; 2751 2752 if (sysctl_createv(clog, 0, &rnode, &cnode, 2753 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 2754 CTLTYPE_INT, "rx_count", 2755 SYSCTL_DESCR("RX frame count threshold (0-255)"), 2756 pq3etsec_sysctl_ic_rx_count_helper, 0, (void *)sc, 0, 2757 CTL_CREATE, CTL_EOL) != 0) 2758 goto bad; 2759 2760 if (sysctl_createv(clog, 0, &rnode, &cnode, 2761 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 2762 CTLTYPE_INT, "tx_time", 2763 SYSCTL_DESCR("TX time threshold (0-65535)"), 2764 pq3etsec_sysctl_ic_tx_time_helper, 0, (void *)sc, 0, 2765 CTL_CREATE, CTL_EOL) != 0) 2766 goto bad; 2767 2768 if (sysctl_createv(clog, 0, &rnode, &cnode, 2769 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 2770 CTLTYPE_INT, "tx_count", 2771 SYSCTL_DESCR("TX frame count threshold (0-255)"), 2772 pq3etsec_sysctl_ic_tx_count_helper, 0, (void *)sc, 0, 2773 CTL_CREATE, CTL_EOL) != 0) 2774 goto bad; 2775 2776 return; 2777 2778 bad: 2779 aprint_error_dev(sc->sc_dev, "could not attach sysctl nodes\n"); 2780 } 2781
Indexes created Tue Sep 30 17:09:57 GMT 2025