pq3etsec.c revision 1.43
1 /* $NetBSD: pq3etsec.c,v 1.43 2019/04/26 06:33:33 msaitoh Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_inet.h" 38 #include "opt_mpc85xx.h" 39 #include "opt_multiprocessor.h" 40 #include "opt_net_mpsafe.h" 41 42 #include <sys/cdefs.h> 43 44 __KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.43 2019/04/26 06:33:33 msaitoh Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/cpu.h> 48 #include <sys/device.h> 49 #include <sys/mbuf.h> 50 #include <sys/ioctl.h> 51 #include <sys/intr.h> 52 #include <sys/bus.h> 53 #include <sys/kernel.h> 54 #include <sys/kmem.h> 55 #include <sys/proc.h> 56 #include <sys/atomic.h> 57 #include <sys/callout.h> 58 #include <sys/sysctl.h> 59 60 #include <net/if.h> 61 #include <net/if_dl.h> 62 #include <net/if_ether.h> 63 #include <net/if_media.h> 64 #include <net/bpf.h> 65 66 #include <dev/mii/miivar.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/ip.h> 72 #include <netinet/in_offload.h> 73 #endif /* INET */ 74 #ifdef INET6 75 #include <netinet6/in6.h> 76 #include <netinet/ip6.h> 77 #endif 78 #include <netinet6/in6_offload.h> 79 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 #include <powerpc/booke/cpuvar.h> 83 #include <powerpc/booke/e500var.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/etsecreg.h> 86 87 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 88 89 #define ETSEC_MAXTXMBUFS 30 90 #define ETSEC_NTXSEGS 30 91 #define ETSEC_MAXRXMBUFS 511 92 #define ETSEC_MINRXMBUFS 32 93 #define ETSEC_NRXSEGS 1 94 95 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 96 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx\ 97 |IFCAP_CSUM_UDPv4_Rx\ 98 |IFCAP_CSUM_TCPv6_Rx\ 99 |IFCAP_CSUM_UDPv6_Rx) 100 101 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 102 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx\ 103 |IFCAP_CSUM_UDPv4_Tx\ 104 |IFCAP_CSUM_TCPv6_Tx\ 105 |IFCAP_CSUM_UDPv6_Tx) 106 107 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN|IFCAP_RCTRL_TUCSEN\ 108 |IFCAP_TCTRL_IPCSEN|IFCAP_TCTRL_TUCSEN) 109 110 #define M_CSUM_IP (M_CSUM_CIP|M_CSUM_CTU) 111 #define M_CSUM_IP6 (M_CSUM_TCPv6|M_CSUM_UDPv6) 112 #define M_CSUM_TUP (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 113 #define M_CSUM_UDP (M_CSUM_UDPv4|M_CSUM_UDPv6) 114 #define M_CSUM_IP4 (M_CSUM_IPv4|M_CSUM_UDPv4|M_CSUM_TCPv4) 115 #define M_CSUM_CIP (M_CSUM_IPv4) 116 #define M_CSUM_CTU (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 117 118 struct pq3etsec_txqueue { 119 bus_dmamap_t txq_descmap; 120 volatile struct txbd *txq_consumer; 121 volatile struct txbd *txq_producer; 122 volatile struct txbd *txq_first; 123 volatile struct txbd *txq_last; 124 struct ifqueue txq_mbufs; 125 struct mbuf *txq_next; 126 #ifdef ETSEC_DEBUG 127 struct mbuf *txq_lmbufs[512]; 128 #endif 129 uint32_t txq_qmask; 130 uint32_t txq_free; 131 uint32_t txq_threshold; 132 uint32_t txq_lastintr; 133 bus_size_t txq_reg_tbase; 134 bus_dma_segment_t txq_descmap_seg; 135 }; 136 137 struct pq3etsec_rxqueue { 138 bus_dmamap_t rxq_descmap; 139 volatile struct rxbd *rxq_consumer; 140 volatile struct rxbd *rxq_producer; 141 volatile struct rxbd *rxq_first; 142 volatile struct rxbd *rxq_last; 143 struct mbuf *rxq_mhead; 144 struct mbuf **rxq_mtail; 145 struct mbuf *rxq_mconsumer; 146 #ifdef ETSEC_DEBUG 147 struct mbuf *rxq_mbufs[512]; 148 #endif 149 uint32_t rxq_qmask; 150 uint32_t rxq_inuse; 151 uint32_t rxq_threshold; 152 bus_size_t rxq_reg_rbase; 153 bus_size_t rxq_reg_rbptr; 154 bus_dma_segment_t rxq_descmap_seg; 155 }; 156 157 struct pq3etsec_mapcache { 158 u_int dmc_nmaps; 159 u_int dmc_maxseg; 160 u_int dmc_maxmaps; 161 u_int dmc_maxmapsize; 162 bus_dmamap_t dmc_maps[0]; 163 }; 164 165 struct pq3etsec_softc { 166 device_t sc_dev; 167 device_t sc_mdio_dev; 168 struct ethercom sc_ec; 169 #define sc_if sc_ec.ec_if 170 struct mii_data sc_mii; 171 bus_space_tag_t sc_bst; 172 bus_space_handle_t sc_bsh; 173 bus_space_handle_t sc_mdio_bsh; 174 bus_dma_tag_t sc_dmat; 175 int sc_phy_addr; 176 prop_dictionary_t sc_intrmap; 177 uint32_t sc_intrmask; 178 179 uint32_t sc_soft_flags; 180 #define SOFT_RESET 0x0001 181 #define SOFT_RXINTR 0x0010 182 #define SOFT_RXBSY 0x0020 183 #define SOFT_TXINTR 0x0100 184 #define SOFT_TXERROR 0x0200 185 186 struct pq3etsec_txqueue sc_txq; 187 struct pq3etsec_rxqueue sc_rxq; 188 uint32_t sc_txerrors; 189 uint32_t sc_rxerrors; 190 191 size_t sc_rx_adjlen; 192 193 /* 194 * Copies of various ETSEC registers. 195 */ 196 uint32_t sc_imask; 197 uint32_t sc_maccfg1; 198 uint32_t sc_maccfg2; 199 uint32_t sc_maxfrm; 200 uint32_t sc_ecntrl; 201 uint32_t sc_dmactrl; 202 uint32_t sc_macstnaddr1; 203 uint32_t sc_macstnaddr2; 204 uint32_t sc_tctrl; 205 uint32_t sc_rctrl; 206 uint32_t sc_gaddr[16]; 207 uint64_t sc_macaddrs[15]; 208 209 void *sc_tx_ih; 210 void *sc_rx_ih; 211 void *sc_error_ih; 212 void *sc_soft_ih; 213 214 kmutex_t *sc_lock; 215 kmutex_t *sc_hwlock; 216 217 struct evcnt sc_ev_tx_stall; 218 struct evcnt sc_ev_tx_intr; 219 struct evcnt sc_ev_rx_stall; 220 struct evcnt sc_ev_rx_intr; 221 struct evcnt sc_ev_error_intr; 222 struct evcnt sc_ev_soft_intr; 223 struct evcnt sc_ev_tx_pause; 224 struct evcnt sc_ev_rx_pause; 225 struct evcnt sc_ev_mii_ticks; 226 227 struct callout sc_mii_callout; 228 uint64_t sc_mii_last_tick; 229 230 struct ifqueue sc_rx_bufcache; 231 struct pq3etsec_mapcache *sc_rx_mapcache; 232 struct pq3etsec_mapcache *sc_tx_mapcache; 233 234 /* Interrupt Coalescing parameters */ 235 int sc_ic_rx_time; 236 int sc_ic_rx_count; 237 int sc_ic_tx_time; 238 int sc_ic_tx_count; 239 }; 240 241 #define ETSEC_IC_RX_ENABLED(sc) \ 242 ((sc)->sc_ic_rx_time != 0 && (sc)->sc_ic_rx_count != 0) 243 #define ETSEC_IC_TX_ENABLED(sc) \ 244 ((sc)->sc_ic_tx_time != 0 && (sc)->sc_ic_tx_count != 0) 245 246 struct pq3mdio_softc { 247 device_t mdio_dev; 248 249 kmutex_t *mdio_lock; 250 251 bus_space_tag_t mdio_bst; 252 bus_space_handle_t mdio_bsh; 253 }; 254 255 static int pq3etsec_match(device_t, cfdata_t, void *); 256 static void pq3etsec_attach(device_t, device_t, void *); 257 258 static int pq3mdio_match(device_t, cfdata_t, void *); 259 static void pq3mdio_attach(device_t, device_t, void *); 260 261 static void pq3etsec_ifstart(struct ifnet *); 262 static void pq3etsec_ifwatchdog(struct ifnet *); 263 static int pq3etsec_ifinit(struct ifnet *); 264 static void pq3etsec_ifstop(struct ifnet *, int); 265 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 266 267 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 268 struct pq3etsec_mapcache **, size_t, size_t, size_t); 269 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 270 struct pq3etsec_mapcache *); 271 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 272 struct pq3etsec_mapcache *); 273 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 274 struct pq3etsec_mapcache *, bus_dmamap_t); 275 276 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 277 struct pq3etsec_txqueue *, u_int); 278 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 279 struct pq3etsec_txqueue *); 280 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 281 struct pq3etsec_txqueue *); 282 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 283 struct pq3etsec_txqueue *); 284 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 285 struct pq3etsec_txqueue *, struct mbuf *m); 286 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 287 struct pq3etsec_txqueue *); 288 289 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 290 struct pq3etsec_rxqueue *, u_int); 291 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 292 struct pq3etsec_rxqueue *); 293 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 294 struct pq3etsec_rxqueue *, bool); 295 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 296 struct pq3etsec_rxqueue *); 297 298 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 299 300 static void pq3etsec_mii_tick(void *); 301 static int pq3etsec_rx_intr(void *); 302 static int pq3etsec_tx_intr(void *); 303 static int pq3etsec_error_intr(void *); 304 static void pq3etsec_soft_intr(void *); 305 306 static void pq3etsec_set_ic_rx(struct pq3etsec_softc *); 307 static void pq3etsec_set_ic_tx(struct pq3etsec_softc *); 308 309 static void pq3etsec_sysctl_setup(struct sysctllog **, struct pq3etsec_softc *); 310 311 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 312 pq3etsec_match, pq3etsec_attach, NULL, NULL); 313 314 CFATTACH_DECL_NEW(pq3mdio_tsec, sizeof(struct pq3mdio_softc), 315 pq3mdio_match, pq3mdio_attach, NULL, NULL); 316 317 CFATTACH_DECL_NEW(pq3mdio_cpunode, sizeof(struct pq3mdio_softc), 318 pq3mdio_match, pq3mdio_attach, NULL, NULL); 319 320 static inline uint32_t 321 etsec_mdio_read(struct pq3mdio_softc *mdio, bus_size_t off) 322 { 323 return bus_space_read_4(mdio->mdio_bst, mdio->mdio_bsh, off); 324 } 325 326 static inline void 327 etsec_mdio_write(struct pq3mdio_softc *mdio, bus_size_t off, uint32_t data) 328 { 329 bus_space_write_4(mdio->mdio_bst, mdio->mdio_bsh, off, data); 330 } 331 332 static inline uint32_t 333 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 334 { 335 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 336 } 337 338 static int 339 pq3mdio_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 340 { 341 return strcmp(cf->cf_name, "mdio") == 0; 342 } 343 344 static int 345 pq3mdio_match(device_t parent, cfdata_t cf, void *aux) 346 { 347 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 348 const bool p1025_p = (svr == (SVR_P1025v1 >> 16) 349 || svr == (SVR_P1016v1 >> 16)); 350 351 if (device_is_a(parent, "cpunode")) { 352 if (!p1025_p 353 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 354 return 0; 355 356 return 1; 357 } 358 359 if (device_is_a(parent, "tsec")) { 360 if (p1025_p 361 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 362 return 0; 363 364 return 1; 365 } 366 367 return 0; 368 } 369 370 static void 371 pq3mdio_attach(device_t parent, device_t self, void *aux) 372 { 373 struct pq3mdio_softc * const mdio = device_private(self); 374 struct cpunode_attach_args * const cna = aux; 375 struct cpunode_locators * const cnl = &cna->cna_locs; 376 377 mdio->mdio_dev = self; 378 mdio->mdio_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 379 380 if (device_is_a(parent, "cpunode")) { 381 struct cpunode_softc * const psc = device_private(parent); 382 psc->sc_children |= cna->cna_childmask; 383 384 mdio->mdio_bst = cna->cna_memt; 385 if (bus_space_map(mdio->mdio_bst, cnl->cnl_addr, 386 cnl->cnl_size, 0, &mdio->mdio_bsh) != 0) { 387 aprint_error(": error mapping registers @ %#x\n", 388 cnl->cnl_addr); 389 return; 390 } 391 } else { 392 struct pq3etsec_softc * const sc = device_private(parent); 393 394 KASSERT(device_is_a(parent, "tsec")); 395 KASSERTMSG(cnl->cnl_addr == ETSEC1_BASE 396 || cnl->cnl_addr == ETSEC2_BASE 397 || cnl->cnl_addr == ETSEC3_BASE 398 || cnl->cnl_addr == ETSEC4_BASE, 399 "unknown tsec addr %x", cnl->cnl_addr); 400 401 mdio->mdio_bst = sc->sc_bst; 402 mdio->mdio_bsh = sc->sc_bsh; 403 } 404 405 aprint_normal("\n"); 406 } 407 408 static int 409 pq3mdio_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 410 { 411 struct pq3mdio_softc * const mdio = device_private(self); 412 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 413 414 mutex_enter(mdio->mdio_lock); 415 416 etsec_mdio_write(mdio, MIIMADD, 417 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 418 419 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 420 etsec_mdio_write(mdio, MIIMCOM, MIIMCOM_READ); 421 422 while (etsec_mdio_read(mdio, MIIMIND) != 0) { 423 delay(1); 424 } 425 *val = etsec_mdio_read(mdio, MIIMSTAT) &0xffff; 426 427 if (miimcom == MIIMCOM_SCAN) 428 etsec_mdio_write(mdio, MIIMCOM, miimcom); 429 430 #if 0 431 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 432 __func__, phy, reg, data); 433 #endif 434 mutex_exit(mdio->mdio_lock); 435 return 0; 436 } 437 438 static int 439 pq3mdio_mii_writereg(device_t self, int phy, int reg, uint16_t data) 440 { 441 struct pq3mdio_softc * const mdio = device_private(self); 442 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 443 444 #if 0 445 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 446 __func__, phy, reg, data); 447 #endif 448 449 mutex_enter(mdio->mdio_lock); 450 451 etsec_mdio_write(mdio, MIIMADD, 452 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 453 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 454 etsec_mdio_write(mdio, MIIMCON, data); 455 456 int timo = 1000; /* 1ms */ 457 while ((etsec_mdio_read(mdio, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 458 delay(1); 459 } 460 461 if (miimcom == MIIMCOM_SCAN) 462 etsec_mdio_write(mdio, MIIMCOM, miimcom); 463 464 mutex_exit(mdio->mdio_lock); 465 466 return 0; 467 } 468 469 static inline void 470 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 471 { 472 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 473 } 474 475 static void 476 pq3etsec_mii_statchg(struct ifnet *ifp) 477 { 478 struct pq3etsec_softc * const sc = ifp->if_softc; 479 struct mii_data * const mii = &sc->sc_mii; 480 481 uint32_t maccfg1 = sc->sc_maccfg1; 482 uint32_t maccfg2 = sc->sc_maccfg2; 483 uint32_t ecntrl = sc->sc_ecntrl; 484 485 maccfg1 &= ~(MACCFG1_TX_FLOW|MACCFG1_RX_FLOW); 486 maccfg2 &= ~(MACCFG2_IFMODE|MACCFG2_FD); 487 488 if (sc->sc_mii.mii_media_active & IFM_FDX) { 489 maccfg2 |= MACCFG2_FD; 490 } 491 492 /* 493 * Now deal with the flow control bits. 494 */ 495 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 496 && (mii->mii_media_active & IFM_ETH_FMASK)) { 497 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 498 maccfg1 |= MACCFG1_RX_FLOW; 499 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 500 maccfg1 |= MACCFG1_TX_FLOW; 501 } 502 503 /* 504 * Now deal with the speed. 505 */ 506 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 507 maccfg2 |= MACCFG2_IFMODE_GMII; 508 } else { 509 maccfg2 |= MACCFG2_IFMODE_MII; 510 ecntrl &= ~ECNTRL_R100M; 511 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 512 ecntrl |= ECNTRL_R100M; 513 } 514 } 515 516 /* 517 * If things are different, re-init things. 518 */ 519 if (maccfg1 != sc->sc_maccfg1 520 || maccfg2 != sc->sc_maccfg2 521 || ecntrl != sc->sc_ecntrl) { 522 if (sc->sc_if.if_flags & IFF_RUNNING) 523 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 524 sc->sc_maccfg1 = maccfg1; 525 sc->sc_maccfg2 = maccfg2; 526 sc->sc_ecntrl = ecntrl; 527 } 528 } 529 530 #if 0 531 static void 532 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 533 { 534 struct pq3etsec_softc * const sc = ifp->if_softc; 535 536 mii_pollstat(&sc->sc_mii); 537 ether_mediastatus(ifp, ifmr); 538 ifmr->ifm_status = sc->sc_mii.mii_media_status; 539 ifmr->ifm_active = sc->sc_mii.mii_media_active; 540 } 541 542 static int 543 pq3etsec_mediachange(struct ifnet *ifp) 544 { 545 struct pq3etsec_softc * const sc = ifp->if_softc; 546 547 if ((ifp->if_flags & IFF_UP) == 0) 548 return 0; 549 550 int rv = mii_mediachg(&sc->sc_mii); 551 return (rv == ENXIO) ? 0 : rv; 552 } 553 #endif 554 555 static int 556 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 557 { 558 559 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 560 return 0; 561 562 return 1; 563 } 564 565 static void 566 pq3etsec_attach(device_t parent, device_t self, void *aux) 567 { 568 struct cpunode_softc * const psc = device_private(parent); 569 struct pq3etsec_softc * const sc = device_private(self); 570 struct cpunode_attach_args * const cna = aux; 571 struct cpunode_locators * const cnl = &cna->cna_locs; 572 cfdata_t cf = device_cfdata(self); 573 int error; 574 575 psc->sc_children |= cna->cna_childmask; 576 sc->sc_dev = self; 577 sc->sc_bst = cna->cna_memt; 578 sc->sc_dmat = &booke_bus_dma_tag; 579 580 /* 581 * Pull out the mdio bus and phy we are supposed to use. 582 */ 583 const int mdio = cf->cf_loc[CPUNODECF_MDIO]; 584 const int phy = cf->cf_loc[CPUNODECF_PHY]; 585 if (mdio != CPUNODECF_MDIO_DEFAULT) 586 aprint_normal(" mdio %d", mdio); 587 588 /* 589 * See if the phy is in the config file... 590 */ 591 if (phy != CPUNODECF_PHY_DEFAULT) { 592 sc->sc_phy_addr = phy; 593 } else { 594 unsigned char prop_name[20]; 595 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 596 cnl->cnl_instance); 597 sc->sc_phy_addr = board_info_get_number(prop_name); 598 } 599 if (sc->sc_phy_addr != MII_PHY_ANY) 600 aprint_normal(" phy %d", sc->sc_phy_addr); 601 602 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 603 &sc->sc_bsh); 604 if (error) { 605 aprint_error(": error mapping registers: %d\n", error); 606 return; 607 } 608 609 /* 610 * Assume firmware has aready set the mac address and fetch it 611 * before we reinit it. 612 */ 613 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 614 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 615 sc->sc_rctrl = RCTRL_DEFAULT; 616 sc->sc_ecntrl = etsec_read(sc, ECNTRL); 617 sc->sc_maccfg1 = etsec_read(sc, MACCFG1); 618 sc->sc_maccfg2 = etsec_read(sc, MACCFG2) | MACCFG2_DEFAULT; 619 620 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 621 size_t len; 622 const uint8_t *mac_addr = 623 board_info_get_data("tsec-mac-addr-base", &len); 624 KASSERT(len == ETHER_ADDR_LEN); 625 sc->sc_macstnaddr2 = 626 (mac_addr[1] << 24) 627 | (mac_addr[0] << 16); 628 sc->sc_macstnaddr1 = 629 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 630 | (mac_addr[4] << 16) 631 | (mac_addr[3] << 8) 632 | (mac_addr[2] << 0); 633 #if 0 634 aprint_error(": mac-address unknown\n"); 635 return; 636 #endif 637 } 638 639 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 640 sc->sc_hwlock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_VM); 641 642 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 643 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 644 645 /* Disable interrupts */ 646 etsec_write(sc, IMASK, 0); 647 648 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 649 if (error) { 650 aprint_error(": failed to init rxq: %d\n", error); 651 goto fail_1; 652 } 653 654 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 655 if (error) { 656 aprint_error(": failed to init txq: %d\n", error); 657 goto fail_2; 658 } 659 660 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 661 ETSEC_MAXRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 662 if (error) { 663 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 664 goto fail_3; 665 } 666 667 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 668 ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 669 if (error) { 670 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 671 goto fail_4; 672 } 673 674 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 675 pq3etsec_tx_intr, sc); 676 if (sc->sc_tx_ih == NULL) { 677 aprint_error(": failed to establish tx interrupt: %d\n", 678 cnl->cnl_intrs[0]); 679 goto fail_5; 680 } 681 682 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 683 pq3etsec_rx_intr, sc); 684 if (sc->sc_rx_ih == NULL) { 685 aprint_error(": failed to establish rx interrupt: %d\n", 686 cnl->cnl_intrs[1]); 687 goto fail_6; 688 } 689 690 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 691 pq3etsec_error_intr, sc); 692 if (sc->sc_error_ih == NULL) { 693 aprint_error(": failed to establish error interrupt: %d\n", 694 cnl->cnl_intrs[2]); 695 goto fail_7; 696 } 697 698 int softint_flags = SOFTINT_NET; 699 #if !defined(MULTIPROCESSOR) || defined(NET_MPSAFE) 700 softint_flags |= SOFTINT_MPSAFE; 701 #endif /* !MULTIPROCESSOR || NET_MPSAFE */ 702 sc->sc_soft_ih = softint_establish(softint_flags, 703 pq3etsec_soft_intr, sc); 704 if (sc->sc_soft_ih == NULL) { 705 aprint_error(": failed to establish soft interrupt\n"); 706 goto fail_8; 707 } 708 709 /* 710 * If there was no MDIO 711 */ 712 if (mdio == CPUNODECF_MDIO_DEFAULT) { 713 aprint_normal("\n"); 714 cfdata_t mdio_cf = config_search_ia(pq3mdio_find, self, NULL, cna); 715 if (mdio_cf != NULL) { 716 sc->sc_mdio_dev = config_attach(self, mdio_cf, cna, NULL); 717 } 718 } else { 719 sc->sc_mdio_dev = device_find_by_driver_unit("mdio", mdio); 720 if (sc->sc_mdio_dev == NULL) { 721 aprint_error(": failed to locate mdio device\n"); 722 goto fail_9; 723 } 724 aprint_normal("\n"); 725 } 726 727 etsec_write(sc, ATTR, ATTR_DEFAULT); 728 etsec_write(sc, ATTRELI, ATTRELI_DEFAULT); 729 730 /* Enable interrupt coalesing */ 731 sc->sc_ic_rx_time = 768; 732 sc->sc_ic_rx_count = 16; 733 sc->sc_ic_tx_time = 768; 734 sc->sc_ic_tx_count = 16; 735 pq3etsec_set_ic_rx(sc); 736 pq3etsec_set_ic_tx(sc); 737 738 char enaddr[ETHER_ADDR_LEN] = { 739 [0] = sc->sc_macstnaddr2 >> 16, 740 [1] = sc->sc_macstnaddr2 >> 24, 741 [2] = sc->sc_macstnaddr1 >> 0, 742 [3] = sc->sc_macstnaddr1 >> 8, 743 [4] = sc->sc_macstnaddr1 >> 16, 744 [5] = sc->sc_macstnaddr1 >> 24, 745 }; 746 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 747 ether_sprintf(enaddr)); 748 749 const char * const xname = device_xname(sc->sc_dev); 750 struct ethercom * const ec = &sc->sc_ec; 751 struct ifnet * const ifp = &ec->ec_if; 752 753 ec->ec_mii = &sc->sc_mii; 754 755 sc->sc_mii.mii_ifp = ifp; 756 sc->sc_mii.mii_readreg = pq3mdio_mii_readreg; 757 sc->sc_mii.mii_writereg = pq3mdio_mii_writereg; 758 sc->sc_mii.mii_statchg = pq3etsec_mii_statchg; 759 760 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 761 ether_mediastatus); 762 763 if (sc->sc_mdio_dev != NULL && sc->sc_phy_addr < 32) { 764 mii_attach(sc->sc_mdio_dev, &sc->sc_mii, 0xffffffff, 765 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 766 767 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 768 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 769 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 770 } else { 771 callout_schedule(&sc->sc_mii_callout, hz); 772 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 773 } 774 } else { 775 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 776 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX); 777 } 778 779 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 780 | ETHERCAP_JUMBO_MTU; 781 782 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 783 ifp->if_softc = sc; 784 ifp->if_capabilities = IFCAP_ETSEC; 785 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 786 ifp->if_ioctl = pq3etsec_ifioctl; 787 ifp->if_start = pq3etsec_ifstart; 788 ifp->if_watchdog = pq3etsec_ifwatchdog; 789 ifp->if_init = pq3etsec_ifinit; 790 ifp->if_stop = pq3etsec_ifstop; 791 IFQ_SET_READY(&ifp->if_snd); 792 793 /* 794 * Attach the interface. 795 */ 796 error = if_initialize(ifp); 797 if (error != 0) { 798 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 799 error); 800 goto fail_10; 801 } 802 pq3etsec_sysctl_setup(NULL, sc); 803 ether_ifattach(ifp, enaddr); 804 if_register(ifp); 805 806 pq3etsec_ifstop(ifp, true); 807 808 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 809 NULL, xname, "rx stall"); 810 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 811 NULL, xname, "tx stall"); 812 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 813 NULL, xname, "tx intr"); 814 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 815 NULL, xname, "rx intr"); 816 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 817 NULL, xname, "error intr"); 818 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 819 NULL, xname, "soft intr"); 820 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 821 NULL, xname, "tx pause"); 822 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 823 NULL, xname, "rx pause"); 824 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 825 NULL, xname, "mii ticks"); 826 return; 827 828 fail_10: 829 ifmedia_removeall(&sc->sc_mii.mii_media); 830 mii_detach(&sc->sc_mii, sc->sc_phy_addr, MII_OFFSET_ANY); 831 fail_9: 832 softint_disestablish(sc->sc_soft_ih); 833 fail_8: 834 intr_disestablish(sc->sc_error_ih); 835 fail_7: 836 intr_disestablish(sc->sc_rx_ih); 837 fail_6: 838 intr_disestablish(sc->sc_tx_ih); 839 fail_5: 840 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 841 fail_4: 842 pq3etsec_mapcache_destroy(sc, sc->sc_rx_mapcache); 843 fail_3: 844 #if 0 /* notyet */ 845 pq3etsec_txq_detach(sc); 846 #endif 847 fail_2: 848 #if 0 /* notyet */ 849 pq3etsec_rxq_detach(sc); 850 #endif 851 fail_1: 852 callout_destroy(&sc->sc_mii_callout); 853 mutex_obj_free(sc->sc_lock); 854 mutex_obj_free(sc->sc_hwlock); 855 bus_space_unmap(sc->sc_bst, sc->sc_bsh, cnl->cnl_size); 856 } 857 858 static uint64_t 859 pq3etsec_macaddr_create(const uint8_t *lladdr) 860 { 861 uint64_t macaddr = 0; 862 863 lladdr += ETHER_ADDR_LEN; 864 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 865 macaddr = (macaddr << 8) | *--lladdr; 866 } 867 return macaddr << 16; 868 } 869 870 static int 871 pq3etsec_ifinit(struct ifnet *ifp) 872 { 873 struct pq3etsec_softc * const sc = ifp->if_softc; 874 int error = 0; 875 876 sc->sc_maxfrm = uimax(ifp->if_mtu + 32, MCLBYTES); 877 if (ifp->if_mtu > ETHERMTU_JUMBO) 878 return error; 879 880 KASSERT(ifp->if_flags & IFF_UP); 881 882 /* 883 * Stop the interface (steps 1 to 4 in the Soft Reset and 884 * Reconfigurating Procedure. 885 */ 886 pq3etsec_ifstop(ifp, 0); 887 888 /* 889 * If our frame size has changed (or it's our first time through) 890 * destroy the existing transmit mapcache. 891 */ 892 if (sc->sc_tx_mapcache != NULL 893 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 894 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 895 sc->sc_tx_mapcache = NULL; 896 } 897 898 if (sc->sc_tx_mapcache == NULL) { 899 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 900 ETSEC_MAXTXMBUFS, sc->sc_maxfrm, ETSEC_NTXSEGS); 901 if (error) 902 return error; 903 } 904 905 sc->sc_ev_mii_ticks.ev_count++; 906 mii_tick(&sc->sc_mii); 907 908 if (ifp->if_flags & IFF_PROMISC) { 909 sc->sc_rctrl |= RCTRL_PROM; 910 } else { 911 sc->sc_rctrl &= ~RCTRL_PROM; 912 } 913 914 uint32_t rctrl_prsdep = 0; 915 sc->sc_rctrl &= ~(RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP); 916 if (VLAN_ATTACHED(&sc->sc_ec)) { 917 sc->sc_rctrl |= RCTRL_VLEX; 918 rctrl_prsdep = RCTRL_PRSDEP_L2; 919 } 920 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 921 sc->sc_rctrl |= RCTRL_IPCSEN; 922 rctrl_prsdep = RCTRL_PRSDEP_L3; 923 } 924 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 925 sc->sc_rctrl |= RCTRL_TUCSEN; 926 rctrl_prsdep = RCTRL_PRSDEP_L4; 927 } 928 sc->sc_rctrl |= rctrl_prsdep; 929 #if 0 930 if (sc->sc_rctrl & (RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP)) 931 aprint_normal_dev(sc->sc_dev, 932 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 933 sc->sc_rctrl, 934 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 935 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 936 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 937 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 938 #endif 939 940 sc->sc_tctrl &= ~(TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS); 941 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 942 sc->sc_tctrl |= TCTRL_VLINS; 943 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 944 sc->sc_tctrl |= TCTRL_IPCSEN; 945 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 946 sc->sc_tctrl |= TCTRL_TUCSEN; 947 #if 0 948 if (sc->sc_tctrl & (TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS)) 949 aprint_normal_dev(sc->sc_dev, 950 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 951 sc->sc_tctrl, 952 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 953 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 954 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 955 #endif 956 957 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN|MACCFG1_RX_EN); 958 959 const uint64_t macstnaddr = 960 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 961 962 sc->sc_imask = IEVENT_DPE; 963 964 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 965 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 966 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 967 968 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 969 pq3etsec_txq_reset(sc, &sc->sc_txq); 970 971 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 972 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 973 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 974 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 975 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 976 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 977 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 978 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 979 980 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 981 pq3etsec_mc_setup(sc); 982 983 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 984 etsec_write(sc, MRBLR, MCLBYTES); 985 986 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 987 sc->sc_dmactrl |= DMACTRL_DEFAULT; 988 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 989 990 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 991 etsec_write(sc, TQUEUE, TQUEUE_EN0); 992 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE|IEVENT_TXC; 993 994 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 995 996 /* 12. Enable receive queues in RQUEUE, */ 997 etsec_write(sc, RQUEUE, RQUEUE_EN0|RQUEUE_EX0); 998 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY|IEVENT_RXC; 999 1000 /* and optionally set TOE functionality in RCTRL. */ 1001 etsec_write(sc, RCTRL, sc->sc_rctrl); 1002 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 1003 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 1004 sc->sc_rx_adjlen += sizeof(struct rxfcb); 1005 1006 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 1007 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 1008 1009 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 1010 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 1011 1012 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 1013 sc->sc_dmactrl &= ~(DMACTRL_GRS|DMACTRL_GTS); 1014 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1015 1016 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 1017 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1018 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1019 1020 sc->sc_soft_flags = 0; 1021 1022 etsec_write(sc, IMASK, sc->sc_imask); 1023 1024 ifp->if_flags |= IFF_RUNNING; 1025 1026 return error; 1027 } 1028 1029 static void 1030 pq3etsec_ifstop(struct ifnet *ifp, int disable) 1031 { 1032 struct pq3etsec_softc * const sc = ifp->if_softc; 1033 1034 KASSERT(!cpu_intr_p()); 1035 const uint32_t imask_gsc_mask = IEVENT_GTSC|IEVENT_GRSC; 1036 /* 1037 * Clear the GTSC and GRSC from the interrupt mask until 1038 * we are ready for them. Then clear them from IEVENT, 1039 * request the graceful shutdown, and then enable the 1040 * GTSC and GRSC bits in the mask. This should cause the 1041 * error interrupt to fire which will issue a wakeup to 1042 * allow us to resume. 1043 */ 1044 1045 /* 1046 * 1. Set GRS/GTS bits in DMACTRL register 1047 */ 1048 sc->sc_dmactrl |= DMACTRL_GRS|DMACTRL_GTS; 1049 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 1050 etsec_write(sc, IEVENT, imask_gsc_mask); 1051 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1052 1053 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN|MACCFG1_RX_EN)) { 1054 /* 1055 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 1056 */ 1057 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 1058 1059 u_int timo = 1000; 1060 uint32_t ievent = etsec_read(sc, IEVENT); 1061 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 1062 if (--timo == 0) { 1063 aprint_error_dev(sc->sc_dev, 1064 "WARNING: " 1065 "request to stop failed (IEVENT=%#x)\n", 1066 ievent); 1067 break; 1068 } 1069 delay(10); 1070 ievent = etsec_read(sc, IEVENT); 1071 } 1072 } 1073 1074 /* 1075 * Now reset the controller. 1076 * 1077 * 3. Set SOFT_RESET bit in MACCFG1 register 1078 * 4. Clear SOFT_RESET bit in MACCFG1 register 1079 */ 1080 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 1081 etsec_write(sc, MACCFG1, 0); 1082 etsec_write(sc, IMASK, 0); 1083 etsec_write(sc, IEVENT, ~0); 1084 sc->sc_imask = 0; 1085 ifp->if_flags &= ~IFF_RUNNING; 1086 1087 uint32_t tbipa = etsec_read(sc, TBIPA); 1088 if (tbipa == sc->sc_phy_addr) { 1089 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 1090 etsec_write(sc, TBIPA, 0x1f); 1091 } 1092 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 1093 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 1094 etsec_write(sc, MIIMCFG, miimcfg); 1095 1096 /* 1097 * Let's consume any remaing transmitted packets. And if we are 1098 * disabling the interface, purge ourselves of any untransmitted 1099 * packets. But don't consume any received packets, just drop them. 1100 * If we aren't disabling the interface, save the mbufs in the 1101 * receive queue for reuse. 1102 */ 1103 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 1104 pq3etsec_txq_consume(sc, &sc->sc_txq); 1105 if (disable) { 1106 pq3etsec_txq_purge(sc, &sc->sc_txq); 1107 IFQ_PURGE(&ifp->if_snd); 1108 } 1109 } 1110 1111 static void 1112 pq3etsec_ifwatchdog(struct ifnet *ifp) 1113 { 1114 } 1115 1116 static void 1117 pq3etsec_mc_setup( 1118 struct pq3etsec_softc *sc) 1119 { 1120 struct ethercom * const ec = &sc->sc_ec; 1121 struct ifnet * const ifp = &sc->sc_if; 1122 struct ether_multi *enm; 1123 struct ether_multistep step; 1124 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 1125 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 1126 1127 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 1128 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1129 1130 ifp->if_flags &= ~IFF_ALLMULTI; 1131 1132 ETHER_FIRST_MULTI(step, ec, enm); 1133 for (u_int i = 0; enm != NULL; ) { 1134 const char *addr = enm->enm_addrlo; 1135 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1136 ifp->if_flags |= IFF_ALLMULTI; 1137 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 1138 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1139 break; 1140 } 1141 if ((sc->sc_rctrl & RCTRL_EMEN) 1142 && i < __arraycount(sc->sc_macaddrs)) { 1143 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 1144 } else { 1145 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1146 #if 0 1147 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 1148 ether_sprintf(addr), crc, 1149 crc >> crc_shift, 1150 crc >> (crc_shift + 5), 1151 (crc >> crc_shift) & 31, 1152 1 << (((crc >> crc_shift) & 31) ^ 31)); 1153 #endif 1154 /* 1155 * The documentation doesn't completely follow PowerPC 1156 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 1157 * is 0x7fa32d9b. By empirical testing, the 1158 * corresponding hash bit is word 3, bit 31 (ppc bit 1159 * order). Since 3 << 31 | 31 is 0x7f, we deduce 1160 * H[0:2] selects the register while H[3:7] selects 1161 * the bit (ppc bit order). 1162 */ 1163 crc >>= crc_shift; 1164 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 1165 } 1166 ETHER_NEXT_MULTI(step, enm); 1167 } 1168 for (u_int i = 0; i < 8; i++) { 1169 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 1170 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 1171 #if 0 1172 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 1173 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 1174 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 1175 i, GADDR(i), etsec_read(sc, GADDR(i))); 1176 #endif 1177 } 1178 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 1179 uint64_t macaddr = sc->sc_macaddrs[i]; 1180 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 1181 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 1182 #if 0 1183 if (macaddr) 1184 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 1185 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1186 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1187 #endif 1188 } 1189 } 1190 1191 static int 1192 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1193 { 1194 struct pq3etsec_softc *sc = ifp->if_softc; 1195 struct ifreq * const ifr = data; 1196 const int s = splnet(); 1197 int error; 1198 1199 switch (cmd) { 1200 case SIOCSIFMEDIA: 1201 /* Flow control requires full-duplex mode. */ 1202 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1203 (ifr->ifr_media & IFM_FDX) == 0) 1204 ifr->ifr_media &= ~IFM_ETH_FMASK; 1205 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1206 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1207 /* We can do both TXPAUSE and RXPAUSE. */ 1208 ifr->ifr_media |= 1209 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1210 } 1211 } 1212 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1213 break; 1214 1215 default: 1216 error = ether_ioctl(ifp, cmd, data); 1217 if (error != ENETRESET) 1218 break; 1219 1220 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1221 error = 0; 1222 if (ifp->if_flags & IFF_RUNNING) 1223 pq3etsec_mc_setup(sc); 1224 break; 1225 } 1226 error = pq3etsec_ifinit(ifp); 1227 break; 1228 } 1229 1230 splx(s); 1231 return error; 1232 } 1233 1234 static void 1235 pq3etsec_rxq_desc_presync( 1236 struct pq3etsec_softc *sc, 1237 struct pq3etsec_rxqueue *rxq, 1238 volatile struct rxbd *rxbd, 1239 size_t count) 1240 { 1241 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1242 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1243 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1244 } 1245 1246 static void 1247 pq3etsec_rxq_desc_postsync( 1248 struct pq3etsec_softc *sc, 1249 struct pq3etsec_rxqueue *rxq, 1250 volatile struct rxbd *rxbd, 1251 size_t count) 1252 { 1253 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1254 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1255 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1256 } 1257 1258 static void 1259 pq3etsec_txq_desc_presync( 1260 struct pq3etsec_softc *sc, 1261 struct pq3etsec_txqueue *txq, 1262 volatile struct txbd *txbd, 1263 size_t count) 1264 { 1265 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1266 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1267 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1268 } 1269 1270 static void 1271 pq3etsec_txq_desc_postsync( 1272 struct pq3etsec_softc *sc, 1273 struct pq3etsec_txqueue *txq, 1274 volatile struct txbd *txbd, 1275 size_t count) 1276 { 1277 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1278 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1279 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1280 } 1281 1282 static bus_dmamap_t 1283 pq3etsec_mapcache_get( 1284 struct pq3etsec_softc *sc, 1285 struct pq3etsec_mapcache *dmc) 1286 { 1287 KASSERT(dmc->dmc_nmaps > 0); 1288 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1289 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1290 } 1291 1292 static void 1293 pq3etsec_mapcache_put( 1294 struct pq3etsec_softc *sc, 1295 struct pq3etsec_mapcache *dmc, 1296 bus_dmamap_t map) 1297 { 1298 KASSERT(map != NULL); 1299 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1300 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1301 } 1302 1303 static void 1304 pq3etsec_mapcache_destroy( 1305 struct pq3etsec_softc *sc, 1306 struct pq3etsec_mapcache *dmc) 1307 { 1308 const size_t dmc_size = 1309 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1310 1311 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1312 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1313 } 1314 kmem_intr_free(dmc, dmc_size); 1315 } 1316 1317 static int 1318 pq3etsec_mapcache_create( 1319 struct pq3etsec_softc *sc, 1320 struct pq3etsec_mapcache **dmc_p, 1321 size_t maxmaps, 1322 size_t maxmapsize, 1323 size_t maxseg) 1324 { 1325 const size_t dmc_size = 1326 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1327 struct pq3etsec_mapcache * const dmc = 1328 kmem_intr_zalloc(dmc_size, KM_NOSLEEP); 1329 1330 dmc->dmc_maxmaps = maxmaps; 1331 dmc->dmc_nmaps = maxmaps; 1332 dmc->dmc_maxmapsize = maxmapsize; 1333 dmc->dmc_maxseg = maxseg; 1334 1335 for (u_int i = 0; i < maxmaps; i++) { 1336 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1337 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1338 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1339 if (error) { 1340 aprint_error_dev(sc->sc_dev, 1341 "failed to creat dma map cache " 1342 "entry %u of %zu: %d\n", 1343 i, maxmaps, error); 1344 while (i-- > 0) { 1345 bus_dmamap_destroy(sc->sc_dmat, 1346 dmc->dmc_maps[i]); 1347 } 1348 kmem_intr_free(dmc, dmc_size); 1349 return error; 1350 } 1351 KASSERT(dmc->dmc_maps[i] != NULL); 1352 } 1353 1354 *dmc_p = dmc; 1355 1356 return 0; 1357 } 1358 1359 #if 0 1360 static void 1361 pq3etsec_dmamem_free( 1362 bus_dma_tag_t dmat, 1363 size_t map_size, 1364 bus_dma_segment_t *seg, 1365 bus_dmamap_t map, 1366 void *kvap) 1367 { 1368 bus_dmamap_destroy(dmat, map); 1369 bus_dmamem_unmap(dmat, kvap, map_size); 1370 bus_dmamem_free(dmat, seg, 1); 1371 } 1372 #endif 1373 1374 static int 1375 pq3etsec_dmamem_alloc( 1376 bus_dma_tag_t dmat, 1377 size_t map_size, 1378 bus_dma_segment_t *seg, 1379 bus_dmamap_t *map, 1380 void **kvap) 1381 { 1382 int error; 1383 int nseg; 1384 1385 *kvap = NULL; 1386 *map = NULL; 1387 1388 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1389 seg, 1, &nseg, 0); 1390 if (error) 1391 return error; 1392 1393 KASSERT(nseg == 1); 1394 1395 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1396 BUS_DMA_COHERENT); 1397 if (error == 0) { 1398 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1399 map); 1400 if (error == 0) { 1401 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1402 NULL, 0); 1403 if (error == 0) 1404 return 0; 1405 bus_dmamap_destroy(dmat, *map); 1406 *map = NULL; 1407 } 1408 bus_dmamem_unmap(dmat, *kvap, map_size); 1409 *kvap = NULL; 1410 } 1411 bus_dmamem_free(dmat, seg, nseg); 1412 return 0; 1413 } 1414 1415 static struct mbuf * 1416 pq3etsec_rx_buf_alloc( 1417 struct pq3etsec_softc *sc) 1418 { 1419 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1420 if (m == NULL) { 1421 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1422 return NULL; 1423 } 1424 MCLGET(m, M_DONTWAIT); 1425 if ((m->m_flags & M_EXT) == 0) { 1426 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1427 m_freem(m); 1428 return NULL; 1429 } 1430 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1431 1432 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1433 if (map == NULL) { 1434 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1435 m_freem(m); 1436 return NULL; 1437 } 1438 M_SETCTX(m, map); 1439 m->m_len = m->m_pkthdr.len = MCLBYTES; 1440 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1441 BUS_DMA_READ|BUS_DMA_NOWAIT); 1442 if (error) { 1443 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1444 error); 1445 M_SETCTX(m, NULL); 1446 m_freem(m); 1447 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1448 return NULL; 1449 } 1450 KASSERT(map->dm_mapsize == MCLBYTES); 1451 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1452 BUS_DMASYNC_PREREAD); 1453 1454 return m; 1455 } 1456 1457 static void 1458 pq3etsec_rx_map_unload( 1459 struct pq3etsec_softc *sc, 1460 struct mbuf *m) 1461 { 1462 KASSERT(m); 1463 for (; m != NULL; m = m->m_next) { 1464 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1465 KASSERT(map); 1466 KASSERT(map->dm_mapsize == MCLBYTES); 1467 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1468 BUS_DMASYNC_POSTREAD); 1469 bus_dmamap_unload(sc->sc_dmat, map); 1470 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1471 M_SETCTX(m, NULL); 1472 } 1473 } 1474 1475 static bool 1476 pq3etsec_rxq_produce( 1477 struct pq3etsec_softc *sc, 1478 struct pq3etsec_rxqueue *rxq) 1479 { 1480 volatile struct rxbd *producer = rxq->rxq_producer; 1481 #if 0 1482 size_t inuse = rxq->rxq_inuse; 1483 #endif 1484 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1485 struct mbuf *m; 1486 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1487 if (m == NULL) { 1488 m = pq3etsec_rx_buf_alloc(sc); 1489 if (m == NULL) { 1490 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1491 break; 1492 } 1493 } 1494 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1495 KASSERT(map); 1496 1497 #ifdef ETSEC_DEBUG 1498 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1499 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1500 #endif 1501 1502 /* rxbd_len is write-only by the ETSEC */ 1503 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1504 membar_producer(); 1505 producer->rxbd_flags |= RXBD_E; 1506 if (__predict_false(rxq->rxq_mhead == NULL)) { 1507 KASSERT(producer == rxq->rxq_consumer); 1508 rxq->rxq_mconsumer = m; 1509 } 1510 *rxq->rxq_mtail = m; 1511 rxq->rxq_mtail = &m->m_next; 1512 m->m_len = MCLBYTES; 1513 m->m_next = NULL; 1514 rxq->rxq_inuse++; 1515 if (++producer == rxq->rxq_last) { 1516 membar_producer(); 1517 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1518 rxq->rxq_last - rxq->rxq_producer); 1519 producer = rxq->rxq_producer = rxq->rxq_first; 1520 } 1521 } 1522 if (producer != rxq->rxq_producer) { 1523 membar_producer(); 1524 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1525 producer - rxq->rxq_producer); 1526 rxq->rxq_producer = producer; 1527 } 1528 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1529 if (qhlt) { 1530 KASSERT(qhlt & rxq->rxq_qmask); 1531 sc->sc_ev_rx_stall.ev_count++; 1532 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1533 } 1534 #if 0 1535 aprint_normal_dev(sc->sc_dev, 1536 "%s: buffers inuse went from %zu to %zu\n", 1537 __func__, inuse, rxq->rxq_inuse); 1538 #endif 1539 return true; 1540 } 1541 1542 static bool 1543 pq3etsec_rx_offload( 1544 struct pq3etsec_softc *sc, 1545 struct mbuf *m, 1546 const struct rxfcb *fcb) 1547 { 1548 if (fcb->rxfcb_flags & RXFCB_VLN) { 1549 vlan_set_tag(m, fcb->rxfcb_vlctl); 1550 } 1551 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1552 || (fcb->rxfcb_flags & (RXFCB_CIP|RXFCB_CTU)) == 0) 1553 return true; 1554 int csum_flags = 0; 1555 if ((fcb->rxfcb_flags & (RXFCB_IP6|RXFCB_CIP)) == RXFCB_CIP) { 1556 csum_flags |= M_CSUM_IPv4; 1557 if (fcb->rxfcb_flags & RXFCB_EIP) 1558 csum_flags |= M_CSUM_IPv4_BAD; 1559 } 1560 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1561 int ipv_flags; 1562 if (fcb->rxfcb_flags & RXFCB_IP6) 1563 ipv_flags = M_CSUM_TCPv6|M_CSUM_UDPv6; 1564 else 1565 ipv_flags = M_CSUM_TCPv4|M_CSUM_UDPv4; 1566 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1567 csum_flags |= (M_CSUM_TCPv4|M_CSUM_TCPv6) & ipv_flags; 1568 } else { 1569 csum_flags |= (M_CSUM_UDPv4|M_CSUM_UDPv6) & ipv_flags; 1570 } 1571 if (fcb->rxfcb_flags & RXFCB_ETU) 1572 csum_flags |= M_CSUM_TCP_UDP_BAD; 1573 } 1574 1575 m->m_pkthdr.csum_flags = csum_flags; 1576 return true; 1577 } 1578 1579 static void 1580 pq3etsec_rx_input( 1581 struct pq3etsec_softc *sc, 1582 struct mbuf *m, 1583 uint16_t rxbd_flags) 1584 { 1585 struct ifnet * const ifp = &sc->sc_if; 1586 1587 pq3etsec_rx_map_unload(sc, m); 1588 1589 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1590 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1591 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1592 return; 1593 } 1594 m_adj(m, sc->sc_rx_adjlen); 1595 1596 if (rxbd_flags & RXBD_M) 1597 m->m_flags |= M_PROMISC; 1598 if (rxbd_flags & RXBD_BC) 1599 m->m_flags |= M_BCAST; 1600 if (rxbd_flags & RXBD_MC) 1601 m->m_flags |= M_MCAST; 1602 m->m_flags |= M_HASFCS; 1603 m_set_rcvif(m, &sc->sc_if); 1604 1605 ifp->if_ibytes += m->m_pkthdr.len; 1606 1607 /* 1608 * Let's give it to the network subsystm to deal with. 1609 */ 1610 int s = splnet(); 1611 if_input(ifp, m); 1612 splx(s); 1613 } 1614 1615 static void 1616 pq3etsec_rxq_consume( 1617 struct pq3etsec_softc *sc, 1618 struct pq3etsec_rxqueue *rxq) 1619 { 1620 struct ifnet * const ifp = &sc->sc_if; 1621 volatile struct rxbd *consumer = rxq->rxq_consumer; 1622 size_t rxconsumed = 0; 1623 1624 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1625 1626 for (;;) { 1627 if (consumer == rxq->rxq_producer) { 1628 rxq->rxq_consumer = consumer; 1629 rxq->rxq_inuse -= rxconsumed; 1630 KASSERT(rxq->rxq_inuse == 0); 1631 return; 1632 } 1633 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1634 const uint16_t rxbd_flags = consumer->rxbd_flags; 1635 if (rxbd_flags & RXBD_E) { 1636 rxq->rxq_consumer = consumer; 1637 rxq->rxq_inuse -= rxconsumed; 1638 return; 1639 } 1640 KASSERT(rxq->rxq_mconsumer != NULL); 1641 #ifdef ETSEC_DEBUG 1642 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1643 #endif 1644 #if 0 1645 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1646 __func__, 1647 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1648 mtod(rxq->rxq_mconsumer, int *)[0], 1649 mtod(rxq->rxq_mconsumer, int *)[1], 1650 mtod(rxq->rxq_mconsumer, int *)[2], 1651 mtod(rxq->rxq_mconsumer, int *)[3]); 1652 #endif 1653 /* 1654 * We own this packet again. Clear all flags except wrap. 1655 */ 1656 rxconsumed++; 1657 consumer->rxbd_flags = rxbd_flags & (RXBD_W|RXBD_I); 1658 1659 /* 1660 * If this descriptor has the LAST bit set and no errors, 1661 * it's a valid input packet. 1662 */ 1663 if ((rxbd_flags & (RXBD_L|RXBD_ERRORS)) == RXBD_L) { 1664 size_t rxbd_len = consumer->rxbd_len; 1665 struct mbuf *m = rxq->rxq_mhead; 1666 struct mbuf *m_last = rxq->rxq_mconsumer; 1667 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1668 rxq->rxq_mtail = &rxq->rxq_mhead; 1669 rxq->rxq_mconsumer = rxq->rxq_mhead; 1670 m_last->m_next = NULL; 1671 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1672 m->m_pkthdr.len = rxbd_len; 1673 pq3etsec_rx_input(sc, m, rxbd_flags); 1674 } else if (rxbd_flags & RXBD_L) { 1675 KASSERT(rxbd_flags & RXBD_ERRORS); 1676 struct mbuf *m; 1677 /* 1678 * We encountered an error, take the mbufs and add 1679 * then to the rx bufcache so we can reuse them. 1680 */ 1681 ifp->if_ierrors++; 1682 for (m = rxq->rxq_mhead; 1683 m != rxq->rxq_mconsumer; 1684 m = m->m_next) { 1685 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1686 } 1687 m = rxq->rxq_mconsumer; 1688 if ((rxq->rxq_mhead = m->m_next) == NULL) 1689 rxq->rxq_mtail = &rxq->rxq_mhead; 1690 rxq->rxq_mconsumer = m->m_next; 1691 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1692 } else { 1693 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1694 } 1695 #ifdef ETSEC_DEBUG 1696 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1697 #endif 1698 1699 /* 1700 * Wrap at the last entry! 1701 */ 1702 if (rxbd_flags & RXBD_W) { 1703 KASSERT(consumer + 1 == rxq->rxq_last); 1704 consumer = rxq->rxq_first; 1705 } else { 1706 consumer++; 1707 } 1708 #ifdef ETSEC_DEBUG 1709 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1710 #endif 1711 } 1712 } 1713 1714 static void 1715 pq3etsec_rxq_purge( 1716 struct pq3etsec_softc *sc, 1717 struct pq3etsec_rxqueue *rxq, 1718 bool discard) 1719 { 1720 struct mbuf *m; 1721 1722 if ((m = rxq->rxq_mhead) != NULL) { 1723 #ifdef ETSEC_DEBUG 1724 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1725 #endif 1726 1727 if (discard) { 1728 pq3etsec_rx_map_unload(sc, m); 1729 m_freem(m); 1730 } else { 1731 while (m != NULL) { 1732 struct mbuf *m0 = m->m_next; 1733 m->m_next = NULL; 1734 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1735 m = m0; 1736 } 1737 } 1738 } 1739 1740 rxq->rxq_mconsumer = NULL; 1741 rxq->rxq_mhead = NULL; 1742 rxq->rxq_mtail = &rxq->rxq_mhead; 1743 rxq->rxq_inuse = 0; 1744 } 1745 1746 static void 1747 pq3etsec_rxq_reset( 1748 struct pq3etsec_softc *sc, 1749 struct pq3etsec_rxqueue *rxq) 1750 { 1751 /* 1752 * sync all the descriptors 1753 */ 1754 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1755 rxq->rxq_last - rxq->rxq_first); 1756 1757 /* 1758 * Make sure we own all descriptors in the ring. 1759 */ 1760 volatile struct rxbd *rxbd; 1761 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1762 rxbd->rxbd_flags = RXBD_I; 1763 } 1764 1765 /* 1766 * Last descriptor has the wrap flag. 1767 */ 1768 rxbd->rxbd_flags = RXBD_W|RXBD_I; 1769 1770 /* 1771 * Reset the producer consumer indexes. 1772 */ 1773 rxq->rxq_consumer = rxq->rxq_first; 1774 rxq->rxq_producer = rxq->rxq_first; 1775 rxq->rxq_inuse = 0; 1776 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1777 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1778 1779 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY; 1780 1781 /* 1782 * Restart the transmit at the first descriptor 1783 */ 1784 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1785 } 1786 1787 static int 1788 pq3etsec_rxq_attach( 1789 struct pq3etsec_softc *sc, 1790 struct pq3etsec_rxqueue *rxq, 1791 u_int qno) 1792 { 1793 size_t map_size = PAGE_SIZE; 1794 size_t desc_count = map_size / sizeof(struct rxbd); 1795 int error; 1796 void *descs; 1797 1798 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1799 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1800 if (error) 1801 return error; 1802 1803 memset(descs, 0, map_size); 1804 rxq->rxq_first = descs; 1805 rxq->rxq_last = rxq->rxq_first + desc_count; 1806 rxq->rxq_consumer = descs; 1807 rxq->rxq_producer = descs; 1808 1809 pq3etsec_rxq_purge(sc, rxq, true); 1810 pq3etsec_rxq_reset(sc, rxq); 1811 1812 rxq->rxq_reg_rbase = RBASEn(qno); 1813 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1814 1815 return 0; 1816 } 1817 1818 static bool 1819 pq3etsec_txq_active_p( 1820 struct pq3etsec_softc * const sc, 1821 struct pq3etsec_txqueue *txq) 1822 { 1823 return !IF_IS_EMPTY(&txq->txq_mbufs); 1824 } 1825 1826 static bool 1827 pq3etsec_txq_fillable_p( 1828 struct pq3etsec_softc * const sc, 1829 struct pq3etsec_txqueue *txq) 1830 { 1831 return txq->txq_free >= txq->txq_threshold; 1832 } 1833 1834 static int 1835 pq3etsec_txq_attach( 1836 struct pq3etsec_softc *sc, 1837 struct pq3etsec_txqueue *txq, 1838 u_int qno) 1839 { 1840 size_t map_size = PAGE_SIZE; 1841 size_t desc_count = map_size / sizeof(struct txbd); 1842 int error; 1843 void *descs; 1844 1845 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1846 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1847 if (error) 1848 return error; 1849 1850 memset(descs, 0, map_size); 1851 txq->txq_first = descs; 1852 txq->txq_last = txq->txq_first + desc_count; 1853 txq->txq_consumer = descs; 1854 txq->txq_producer = descs; 1855 1856 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1857 1858 txq->txq_reg_tbase = TBASEn(qno); 1859 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1860 1861 pq3etsec_txq_reset(sc, txq); 1862 1863 return 0; 1864 } 1865 1866 static int 1867 pq3etsec_txq_map_load( 1868 struct pq3etsec_softc *sc, 1869 struct pq3etsec_txqueue *txq, 1870 struct mbuf *m) 1871 { 1872 bus_dmamap_t map; 1873 int error; 1874 1875 map = M_GETCTX(m, bus_dmamap_t); 1876 if (map != NULL) 1877 return 0; 1878 1879 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1880 if (map == NULL) 1881 return ENOMEM; 1882 1883 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1884 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1885 if (error) 1886 return error; 1887 1888 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1889 BUS_DMASYNC_PREWRITE); 1890 M_SETCTX(m, map); 1891 return 0; 1892 } 1893 1894 static void 1895 pq3etsec_txq_map_unload( 1896 struct pq3etsec_softc *sc, 1897 struct pq3etsec_txqueue *txq, 1898 struct mbuf *m) 1899 { 1900 KASSERT(m); 1901 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1902 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1903 BUS_DMASYNC_POSTWRITE); 1904 bus_dmamap_unload(sc->sc_dmat, map); 1905 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1906 } 1907 1908 static bool 1909 pq3etsec_txq_produce( 1910 struct pq3etsec_softc *sc, 1911 struct pq3etsec_txqueue *txq, 1912 struct mbuf *m) 1913 { 1914 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1915 1916 if (map->dm_nsegs > txq->txq_free) 1917 return false; 1918 1919 /* 1920 * TCP Offload flag must be set in the first descriptor. 1921 */ 1922 volatile struct txbd *producer = txq->txq_producer; 1923 uint16_t last_flags = TXBD_L; 1924 uint16_t first_flags = TXBD_R 1925 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1926 1927 /* 1928 * If we've produced enough descriptors without consuming any 1929 * we need to ask for an interrupt to reclaim some. 1930 */ 1931 txq->txq_lastintr += map->dm_nsegs; 1932 if (ETSEC_IC_TX_ENABLED(sc) 1933 || txq->txq_lastintr >= txq->txq_threshold 1934 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1935 txq->txq_lastintr = 0; 1936 last_flags |= TXBD_I; 1937 } 1938 1939 #ifdef ETSEC_DEBUG 1940 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1941 #endif 1942 KASSERT(producer != txq->txq_last); 1943 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1944 producer->txbd_len = map->dm_segs[0].ds_len; 1945 1946 if (map->dm_nsegs > 1) { 1947 volatile struct txbd *start = producer + 1; 1948 size_t count = map->dm_nsegs - 1; 1949 for (u_int i = 1; i < map->dm_nsegs; i++) { 1950 if (__predict_false(++producer == txq->txq_last)) { 1951 producer = txq->txq_first; 1952 if (start < txq->txq_last) { 1953 pq3etsec_txq_desc_presync(sc, txq, 1954 start, txq->txq_last - start); 1955 count -= txq->txq_last - start; 1956 } 1957 start = txq->txq_first; 1958 } 1959 #ifdef ETSEC_DEBUG 1960 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1961 #endif 1962 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1963 producer->txbd_len = map->dm_segs[i].ds_len; 1964 producer->txbd_flags = TXBD_R 1965 | (producer->txbd_flags & TXBD_W) 1966 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1967 #if 0 1968 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1969 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1970 #endif 1971 } 1972 pq3etsec_txq_desc_presync(sc, txq, start, count); 1973 } else { 1974 first_flags |= last_flags; 1975 } 1976 1977 membar_producer(); 1978 txq->txq_producer->txbd_flags = 1979 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1980 #if 0 1981 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1982 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1983 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1984 #endif 1985 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1986 1987 /* 1988 * Reduce free count by the number of segments we consumed. 1989 */ 1990 txq->txq_free -= map->dm_nsegs; 1991 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 1992 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 1993 KASSERT(producer->txbd_flags & TXBD_L); 1994 #ifdef ETSEC_DEBUG 1995 txq->txq_lmbufs[producer - txq->txq_first] = m; 1996 #endif 1997 1998 #if 0 1999 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 2000 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 2001 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 2002 #endif 2003 2004 if (++producer == txq->txq_last) 2005 txq->txq_producer = txq->txq_first; 2006 else 2007 txq->txq_producer = producer; 2008 IF_ENQUEUE(&txq->txq_mbufs, m); 2009 2010 /* 2011 * Restart the transmitter. 2012 */ 2013 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 2014 2015 return true; 2016 } 2017 2018 static void 2019 pq3etsec_tx_offload( 2020 struct pq3etsec_softc *sc, 2021 struct pq3etsec_txqueue *txq, 2022 struct mbuf **mp) 2023 { 2024 struct mbuf *m = *mp; 2025 u_int csum_flags = m->m_pkthdr.csum_flags; 2026 bool have_vtag; 2027 uint16_t vtag; 2028 2029 KASSERT(m->m_flags & M_PKTHDR); 2030 2031 have_vtag = vlan_has_tag(m); 2032 vtag = (have_vtag) ? vlan_get_tag(m) : 0; 2033 2034 /* 2035 * Let see if we are doing any offload first. 2036 */ 2037 if (csum_flags == 0 && !have_vtag) { 2038 m->m_flags &= ~M_HASFCB; 2039 return; 2040 } 2041 2042 uint16_t flags = 0; 2043 if (csum_flags & M_CSUM_IP) { 2044 flags |= TXFCB_IP 2045 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 2046 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 2047 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 2048 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 2049 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 2050 } 2051 if (have_vtag) { 2052 flags |= TXFCB_VLN; 2053 } 2054 if (flags == 0) { 2055 m->m_flags &= ~M_HASFCB; 2056 return; 2057 } 2058 2059 struct txfcb fcb; 2060 fcb.txfcb_flags = flags; 2061 if (csum_flags & M_CSUM_IPv4) 2062 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2063 else 2064 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2065 fcb.txfcb_l3os = ETHER_HDR_LEN; 2066 fcb.txfcb_phcs = 0; 2067 fcb.txfcb_vlctl = vtag; 2068 2069 #if 0 2070 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 2071 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 2072 fcb.txfcb_phcs, fcb.txfcb_vlctl); 2073 #endif 2074 2075 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 2076 m->m_data -= sizeof(fcb); 2077 m->m_len += sizeof(fcb); 2078 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 2079 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 2080 m->m_data = m->m_pktdat; 2081 m->m_len += sizeof(fcb); 2082 } else { 2083 struct mbuf *mn; 2084 MGET(mn, M_DONTWAIT, m->m_type); 2085 if (mn == NULL) { 2086 if (csum_flags & M_CSUM_IP4) { 2087 #ifdef INET 2088 in_undefer_cksum(m, ETHER_HDR_LEN, 2089 csum_flags & M_CSUM_IP4); 2090 #else 2091 panic("%s: impossible M_CSUM flags %#x", 2092 device_xname(sc->sc_dev), csum_flags); 2093 #endif 2094 } else if (csum_flags & M_CSUM_IP6) { 2095 #ifdef INET6 2096 in6_undefer_cksum(m, ETHER_HDR_LEN, 2097 csum_flags & M_CSUM_IP6); 2098 #else 2099 panic("%s: impossible M_CSUM flags %#x", 2100 device_xname(sc->sc_dev), csum_flags); 2101 #endif 2102 } 2103 2104 m->m_flags &= ~M_HASFCB; 2105 return; 2106 } 2107 2108 m_move_pkthdr(mn, m); 2109 mn->m_next = m; 2110 m = mn; 2111 m_align(m, sizeof(fcb)); 2112 m->m_len = sizeof(fcb); 2113 *mp = m; 2114 } 2115 m->m_pkthdr.len += sizeof(fcb); 2116 m->m_flags |= M_HASFCB; 2117 *mtod(m, struct txfcb *) = fcb; 2118 return; 2119 } 2120 2121 static bool 2122 pq3etsec_txq_enqueue( 2123 struct pq3etsec_softc *sc, 2124 struct pq3etsec_txqueue *txq) 2125 { 2126 for (;;) { 2127 if (IF_QFULL(&txq->txq_mbufs)) 2128 return false; 2129 struct mbuf *m = txq->txq_next; 2130 if (m == NULL) { 2131 int s = splnet(); 2132 IFQ_DEQUEUE(&sc->sc_if.if_snd, m); 2133 splx(s); 2134 if (m == NULL) 2135 return true; 2136 M_SETCTX(m, NULL); 2137 pq3etsec_tx_offload(sc, txq, &m); 2138 } else { 2139 txq->txq_next = NULL; 2140 } 2141 int error = pq3etsec_txq_map_load(sc, txq, m); 2142 if (error) { 2143 aprint_error_dev(sc->sc_dev, 2144 "discarded packet due to " 2145 "dmamap load failure: %d\n", error); 2146 m_freem(m); 2147 continue; 2148 } 2149 KASSERT(txq->txq_next == NULL); 2150 if (!pq3etsec_txq_produce(sc, txq, m)) { 2151 txq->txq_next = m; 2152 return false; 2153 } 2154 KASSERT(txq->txq_next == NULL); 2155 } 2156 } 2157 2158 static bool 2159 pq3etsec_txq_consume( 2160 struct pq3etsec_softc *sc, 2161 struct pq3etsec_txqueue *txq) 2162 { 2163 struct ifnet * const ifp = &sc->sc_if; 2164 volatile struct txbd *consumer = txq->txq_consumer; 2165 size_t txfree = 0; 2166 2167 #if 0 2168 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 2169 #endif 2170 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 2171 2172 for (;;) { 2173 if (consumer == txq->txq_producer) { 2174 txq->txq_consumer = consumer; 2175 txq->txq_free += txfree; 2176 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2177 #if 0 2178 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2179 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2180 #endif 2181 KASSERT(txq->txq_lastintr == 0); 2182 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2183 return true; 2184 } 2185 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2186 const uint16_t txbd_flags = consumer->txbd_flags; 2187 if (txbd_flags & TXBD_R) { 2188 txq->txq_consumer = consumer; 2189 txq->txq_free += txfree; 2190 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2191 #if 0 2192 printf("%s: freed %zu descriptors\n", 2193 __func__, txfree); 2194 #endif 2195 return pq3etsec_txq_fillable_p(sc, txq); 2196 } 2197 2198 /* 2199 * If this is the last descriptor in the chain, get the 2200 * mbuf, free its dmamap, and free the mbuf chain itself. 2201 */ 2202 if (txbd_flags & TXBD_L) { 2203 struct mbuf *m; 2204 2205 IF_DEQUEUE(&txq->txq_mbufs, m); 2206 #ifdef ETSEC_DEBUG 2207 KASSERTMSG( 2208 m == txq->txq_lmbufs[consumer-txq->txq_first], 2209 "%s: %p [%u]: flags %#x m (%p) != %p (%p)", 2210 __func__, consumer, consumer - txq->txq_first, 2211 txbd_flags, m, 2212 &txq->txq_lmbufs[consumer-txq->txq_first], 2213 txq->txq_lmbufs[consumer-txq->txq_first]); 2214 #endif 2215 KASSERT(m); 2216 pq3etsec_txq_map_unload(sc, txq, m); 2217 #if 0 2218 printf("%s: mbuf %p: consumed a %u byte packet\n", 2219 __func__, m, m->m_pkthdr.len); 2220 #endif 2221 if (m->m_flags & M_HASFCB) 2222 m_adj(m, sizeof(struct txfcb)); 2223 bpf_mtap(ifp, m, BPF_D_OUT); 2224 ifp->if_opackets++; 2225 ifp->if_obytes += m->m_pkthdr.len; 2226 if (m->m_flags & M_MCAST) 2227 ifp->if_omcasts++; 2228 if (txbd_flags & TXBD_ERRORS) 2229 ifp->if_oerrors++; 2230 m_freem(m); 2231 #ifdef ETSEC_DEBUG 2232 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2233 #endif 2234 } else { 2235 #ifdef ETSEC_DEBUG 2236 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2237 #endif 2238 } 2239 2240 /* 2241 * We own this packet again. Clear all flags except wrap. 2242 */ 2243 txfree++; 2244 //consumer->txbd_flags = txbd_flags & TXBD_W; 2245 2246 /* 2247 * Wrap at the last entry! 2248 */ 2249 if (txbd_flags & TXBD_W) { 2250 KASSERT(consumer + 1 == txq->txq_last); 2251 consumer = txq->txq_first; 2252 } else { 2253 consumer++; 2254 KASSERT(consumer < txq->txq_last); 2255 } 2256 } 2257 } 2258 2259 static void 2260 pq3etsec_txq_purge( 2261 struct pq3etsec_softc *sc, 2262 struct pq3etsec_txqueue *txq) 2263 { 2264 struct mbuf *m; 2265 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2266 2267 for (;;) { 2268 IF_DEQUEUE(&txq->txq_mbufs, m); 2269 if (m == NULL) 2270 break; 2271 pq3etsec_txq_map_unload(sc, txq, m); 2272 m_freem(m); 2273 } 2274 if ((m = txq->txq_next) != NULL) { 2275 txq->txq_next = NULL; 2276 pq3etsec_txq_map_unload(sc, txq, m); 2277 m_freem(m); 2278 } 2279 #ifdef ETSEC_DEBUG 2280 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2281 #endif 2282 } 2283 2284 static void 2285 pq3etsec_txq_reset( 2286 struct pq3etsec_softc *sc, 2287 struct pq3etsec_txqueue *txq) 2288 { 2289 /* 2290 * sync all the descriptors 2291 */ 2292 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2293 txq->txq_last - txq->txq_first); 2294 2295 /* 2296 * Make sure we own all descriptors in the ring. 2297 */ 2298 volatile struct txbd *txbd; 2299 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2300 txbd->txbd_flags = 0; 2301 } 2302 2303 /* 2304 * Last descriptor has the wrap flag. 2305 */ 2306 txbd->txbd_flags = TXBD_W; 2307 2308 /* 2309 * Reset the producer consumer indexes. 2310 */ 2311 txq->txq_consumer = txq->txq_first; 2312 txq->txq_producer = txq->txq_first; 2313 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2314 txq->txq_threshold = txq->txq_free / 2; 2315 txq->txq_lastintr = 0; 2316 2317 /* 2318 * What do we want to get interrupted on? 2319 */ 2320 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE; 2321 2322 /* 2323 * Restart the transmit at the first descriptor 2324 */ 2325 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2326 } 2327 2328 static void 2329 pq3etsec_ifstart(struct ifnet *ifp) 2330 { 2331 struct pq3etsec_softc * const sc = ifp->if_softc; 2332 2333 if (__predict_false((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)) { 2334 return; 2335 } 2336 2337 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2338 softint_schedule(sc->sc_soft_ih); 2339 } 2340 2341 static void 2342 pq3etsec_tx_error( 2343 struct pq3etsec_softc * const sc) 2344 { 2345 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2346 2347 pq3etsec_txq_consume(sc, txq); 2348 2349 if (pq3etsec_txq_fillable_p(sc, txq)) 2350 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2351 if (sc->sc_txerrors & (IEVENT_LC|IEVENT_CRL|IEVENT_XFUN|IEVENT_BABT)) { 2352 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2353 } 2354 2355 if (pq3etsec_txq_active_p(sc, txq)) 2356 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2357 if (!pq3etsec_txq_enqueue(sc, txq)) { 2358 sc->sc_ev_tx_stall.ev_count++; 2359 sc->sc_if.if_flags |= IFF_OACTIVE; 2360 } 2361 2362 sc->sc_txerrors = 0; 2363 } 2364 2365 int 2366 pq3etsec_tx_intr(void *arg) 2367 { 2368 struct pq3etsec_softc * const sc = arg; 2369 2370 mutex_enter(sc->sc_hwlock); 2371 2372 sc->sc_ev_tx_intr.ev_count++; 2373 2374 uint32_t ievent = etsec_read(sc, IEVENT); 2375 ievent &= IEVENT_TXF|IEVENT_TXB; 2376 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2377 2378 #if 0 2379 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2380 __func__, ievent, etsec_read(sc, IMASK)); 2381 #endif 2382 2383 if (ievent == 0) { 2384 mutex_exit(sc->sc_hwlock); 2385 return 0; 2386 } 2387 2388 sc->sc_imask &= ~(IEVENT_TXF|IEVENT_TXB); 2389 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2390 etsec_write(sc, IMASK, sc->sc_imask); 2391 softint_schedule(sc->sc_soft_ih); 2392 2393 mutex_exit(sc->sc_hwlock); 2394 2395 return 1; 2396 } 2397 2398 int 2399 pq3etsec_rx_intr(void *arg) 2400 { 2401 struct pq3etsec_softc * const sc = arg; 2402 2403 mutex_enter(sc->sc_hwlock); 2404 2405 sc->sc_ev_rx_intr.ev_count++; 2406 2407 uint32_t ievent = etsec_read(sc, IEVENT); 2408 ievent &= IEVENT_RXF|IEVENT_RXB; 2409 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2410 if (ievent == 0) { 2411 mutex_exit(sc->sc_hwlock); 2412 return 0; 2413 } 2414 2415 #if 0 2416 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2417 #endif 2418 2419 sc->sc_imask &= ~(IEVENT_RXF|IEVENT_RXB); 2420 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2421 etsec_write(sc, IMASK, sc->sc_imask); 2422 softint_schedule(sc->sc_soft_ih); 2423 2424 mutex_exit(sc->sc_hwlock); 2425 2426 return 1; 2427 } 2428 2429 int 2430 pq3etsec_error_intr(void *arg) 2431 { 2432 struct pq3etsec_softc * const sc = arg; 2433 2434 mutex_enter(sc->sc_hwlock); 2435 2436 sc->sc_ev_error_intr.ev_count++; 2437 2438 for (int rv = 0, soft_flags = 0;; rv = 1) { 2439 uint32_t ievent = etsec_read(sc, IEVENT); 2440 ievent &= ~(IEVENT_RXF|IEVENT_RXB|IEVENT_TXF|IEVENT_TXB); 2441 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2442 if (ievent == 0) { 2443 if (soft_flags) { 2444 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2445 softint_schedule(sc->sc_soft_ih); 2446 } 2447 mutex_exit(sc->sc_hwlock); 2448 return rv; 2449 } 2450 #if 0 2451 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2452 __func__, ievent, etsec_read(sc, IMASK)); 2453 #endif 2454 2455 if (ievent & (IEVENT_GRSC|IEVENT_GTSC)) { 2456 sc->sc_imask &= ~(IEVENT_GRSC|IEVENT_GTSC); 2457 etsec_write(sc, IMASK, sc->sc_imask); 2458 wakeup(sc); 2459 } 2460 if (ievent & (IEVENT_MMRD|IEVENT_MMWR)) { 2461 sc->sc_imask &= ~(IEVENT_MMRD|IEVENT_MMWR); 2462 etsec_write(sc, IMASK, sc->sc_imask); 2463 wakeup(&sc->sc_mii); 2464 } 2465 if (ievent & IEVENT_BSY) { 2466 soft_flags |= SOFT_RXBSY; 2467 sc->sc_imask &= ~IEVENT_BSY; 2468 etsec_write(sc, IMASK, sc->sc_imask); 2469 } 2470 if (ievent & IEVENT_TXE) { 2471 soft_flags |= SOFT_TXERROR; 2472 sc->sc_imask &= ~IEVENT_TXE; 2473 sc->sc_txerrors |= ievent; 2474 } 2475 if (ievent & IEVENT_TXC) { 2476 sc->sc_ev_tx_pause.ev_count++; 2477 } 2478 if (ievent & IEVENT_RXC) { 2479 sc->sc_ev_rx_pause.ev_count++; 2480 } 2481 if (ievent & IEVENT_DPE) { 2482 soft_flags |= SOFT_RESET; 2483 sc->sc_imask &= ~IEVENT_DPE; 2484 etsec_write(sc, IMASK, sc->sc_imask); 2485 } 2486 } 2487 } 2488 2489 void 2490 pq3etsec_soft_intr(void *arg) 2491 { 2492 struct pq3etsec_softc * const sc = arg; 2493 struct ifnet * const ifp = &sc->sc_if; 2494 uint32_t imask = 0; 2495 2496 mutex_enter(sc->sc_lock); 2497 2498 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2499 2500 sc->sc_ev_soft_intr.ev_count++; 2501 2502 if (soft_flags & SOFT_RESET) { 2503 int s = splnet(); 2504 pq3etsec_ifinit(ifp); 2505 splx(s); 2506 soft_flags = 0; 2507 } 2508 2509 if (soft_flags & SOFT_RXBSY) { 2510 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2511 size_t threshold = 5 * rxq->rxq_threshold / 4; 2512 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2513 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2514 } else { 2515 imask |= IEVENT_BSY; 2516 } 2517 aprint_normal_dev(sc->sc_dev, 2518 "increasing receive buffers from %zu to %zu\n", 2519 rxq->rxq_threshold, threshold); 2520 rxq->rxq_threshold = threshold; 2521 } 2522 2523 if ((soft_flags & SOFT_TXINTR) 2524 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2525 /* 2526 * Let's do what we came here for. Consume transmitted 2527 * packets off the transmit ring. 2528 */ 2529 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2530 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2531 sc->sc_ev_tx_stall.ev_count++; 2532 ifp->if_flags |= IFF_OACTIVE; 2533 } else { 2534 ifp->if_flags &= ~IFF_OACTIVE; 2535 } 2536 imask |= IEVENT_TXF; 2537 } 2538 2539 if (soft_flags & (SOFT_RXINTR|SOFT_RXBSY)) { 2540 /* Let's consume */ 2541 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2542 imask |= IEVENT_RXF; 2543 } 2544 2545 if (soft_flags & SOFT_TXERROR) { 2546 pq3etsec_tx_error(sc); 2547 imask |= IEVENT_TXE; 2548 } 2549 2550 if (ifp->if_flags & IFF_RUNNING) { 2551 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2552 mutex_spin_enter(sc->sc_hwlock); 2553 sc->sc_imask |= imask; 2554 etsec_write(sc, IMASK, sc->sc_imask); 2555 mutex_spin_exit(sc->sc_hwlock); 2556 } else { 2557 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2558 } 2559 2560 mutex_exit(sc->sc_lock); 2561 } 2562 2563 static void 2564 pq3etsec_mii_tick(void *arg) 2565 { 2566 struct pq3etsec_softc * const sc = arg; 2567 mutex_enter(sc->sc_lock); 2568 callout_ack(&sc->sc_mii_callout); 2569 sc->sc_ev_mii_ticks.ev_count++; 2570 #ifdef DEBUG 2571 uint64_t now = mftb(); 2572 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2573 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2574 __func__, now - sc->sc_mii_last_tick); 2575 callout_stop(&sc->sc_mii_callout); 2576 } 2577 #endif 2578 mii_tick(&sc->sc_mii); 2579 int s = splnet(); 2580 if (sc->sc_soft_flags & SOFT_RESET) 2581 softint_schedule(sc->sc_soft_ih); 2582 splx(s); 2583 callout_schedule(&sc->sc_mii_callout, hz); 2584 #ifdef DEBUG 2585 sc->sc_mii_last_tick = now; 2586 #endif 2587 mutex_exit(sc->sc_lock); 2588 } 2589 2590 static void 2591 pq3etsec_set_ic_rx(struct pq3etsec_softc *sc) 2592 { 2593 uint32_t reg; 2594 2595 if (ETSEC_IC_RX_ENABLED(sc)) { 2596 reg = RXIC_ICEN; 2597 reg |= RXIC_ICFT_SET(sc->sc_ic_rx_count); 2598 reg |= RXIC_ICTT_SET(sc->sc_ic_rx_time); 2599 } else { 2600 /* Disable RX interrupt coalescing */ 2601 reg = 0; 2602 } 2603 2604 etsec_write(sc, RXIC, reg); 2605 } 2606 2607 static void 2608 pq3etsec_set_ic_tx(struct pq3etsec_softc *sc) 2609 { 2610 uint32_t reg; 2611 2612 if (ETSEC_IC_TX_ENABLED(sc)) { 2613 reg = TXIC_ICEN; 2614 reg |= TXIC_ICFT_SET(sc->sc_ic_tx_count); 2615 reg |= TXIC_ICTT_SET(sc->sc_ic_tx_time); 2616 } else { 2617 /* Disable TX interrupt coalescing */ 2618 reg = 0; 2619 } 2620 2621 etsec_write(sc, TXIC, reg); 2622 } 2623 2624 /* 2625 * sysctl 2626 */ 2627 static int 2628 pq3etsec_sysctl_ic_time_helper(SYSCTLFN_ARGS, int *valuep) 2629 { 2630 struct sysctlnode node = *rnode; 2631 struct pq3etsec_softc *sc = rnode->sysctl_data; 2632 int value = *valuep; 2633 int error; 2634 2635 node.sysctl_data = &value; 2636 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2637 if (error != 0 || newp == NULL) 2638 return error; 2639 2640 if (value < 0 || value > 65535) 2641 return EINVAL; 2642 2643 mutex_enter(sc->sc_lock); 2644 *valuep = value; 2645 if (valuep == &sc->sc_ic_rx_time) 2646 pq3etsec_set_ic_rx(sc); 2647 else 2648 pq3etsec_set_ic_tx(sc); 2649 mutex_exit(sc->sc_lock); 2650 2651 return 0; 2652 } 2653 2654 static int 2655 pq3etsec_sysctl_ic_count_helper(SYSCTLFN_ARGS, int *valuep) 2656 { 2657 struct sysctlnode node = *rnode; 2658 struct pq3etsec_softc *sc = rnode->sysctl_data; 2659 int value = *valuep; 2660 int error; 2661 2662 node.sysctl_data = &value; 2663 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2664 if (error != 0 || newp == NULL) 2665 return error; 2666 2667 if (value < 0 || value > 255) 2668 return EINVAL; 2669 2670 mutex_enter(sc->sc_lock); 2671 *valuep = value; 2672 if (valuep == &sc->sc_ic_rx_count) 2673 pq3etsec_set_ic_rx(sc); 2674 else 2675 pq3etsec_set_ic_tx(sc); 2676 mutex_exit(sc->sc_lock); 2677 2678 return 0; 2679 } 2680 2681 static int 2682 pq3etsec_sysctl_ic_rx_time_helper(SYSCTLFN_ARGS) 2683 { 2684 struct pq3etsec_softc *sc = rnode->sysctl_data; 2685 2686 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2687 &sc->sc_ic_rx_time); 2688 } 2689 2690 static int 2691 pq3etsec_sysctl_ic_rx_count_helper(SYSCTLFN_ARGS) 2692 { 2693 struct pq3etsec_softc *sc = rnode->sysctl_data; 2694 2695 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2696 &sc->sc_ic_rx_count); 2697 } 2698 2699 static int 2700 pq3etsec_sysctl_ic_tx_time_helper(SYSCTLFN_ARGS) 2701 { 2702 struct pq3etsec_softc *sc = rnode->sysctl_data; 2703 2704 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2705 &sc->sc_ic_tx_time); 2706 } 2707 2708 static int 2709 pq3etsec_sysctl_ic_tx_count_helper(SYSCTLFN_ARGS) 2710 { 2711 struct pq3etsec_softc *sc = rnode->sysctl_data; 2712 2713 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2714 &sc->sc_ic_tx_count); 2715 } 2716 2717 static void pq3etsec_sysctl_setup(struct sysctllog **clog, 2718 struct pq3etsec_softc *sc) 2719 { 2720 const struct sysctlnode *cnode, *rnode; 2721 2722 if (sysctl_createv(clog, 0, NULL, &rnode, 2723 CTLFLAG_PERMANENT, 2724 CTLTYPE_NODE, device_xname(sc->sc_dev), 2725 SYSCTL_DESCR("TSEC interface"), 2726 NULL, 0, NULL, 0, 2727 CTL_HW, CTL_CREATE, CTL_EOL) != 0) 2728 goto bad; 2729 2730 if (sysctl_createv(clog, 0, &rnode, &rnode, 2731 CTLFLAG_PERMANENT, 2732 CTLTYPE_NODE, "int_coal", 2733 SYSCTL_DESCR("Interrupts coalescing"), 2734 NULL, 0, NULL, 0, 2735 CTL_CREATE, CTL_EOL) != 0) 2736 goto bad; 2737 2738 if (sysctl_createv(clog, 0, &rnode, &cnode, 2739 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 2740 CTLTYPE_INT, "rx_time", 2741 SYSCTL_DESCR("RX time threshold (0-65535)"), 2742 pq3etsec_sysctl_ic_rx_time_helper, 0, (void *)sc, 0, 2743 CTL_CREATE, CTL_EOL) != 0) 2744 goto bad; 2745 2746 if (sysctl_createv(clog, 0, &rnode, &cnode, 2747 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 2748 CTLTYPE_INT, "rx_count", 2749 SYSCTL_DESCR("RX frame count threshold (0-255)"), 2750 pq3etsec_sysctl_ic_rx_count_helper, 0, (void *)sc, 0, 2751 CTL_CREATE, CTL_EOL) != 0) 2752 goto bad; 2753 2754 if (sysctl_createv(clog, 0, &rnode, &cnode, 2755 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 2756 CTLTYPE_INT, "tx_time", 2757 SYSCTL_DESCR("TX time threshold (0-65535)"), 2758 pq3etsec_sysctl_ic_tx_time_helper, 0, (void *)sc, 0, 2759 CTL_CREATE, CTL_EOL) != 0) 2760 goto bad; 2761 2762 if (sysctl_createv(clog, 0, &rnode, &cnode, 2763 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 2764 CTLTYPE_INT, "tx_count", 2765 SYSCTL_DESCR("TX frame count threshold (0-255)"), 2766 pq3etsec_sysctl_ic_tx_count_helper, 0, (void *)sc, 0, 2767 CTL_CREATE, CTL_EOL) != 0) 2768 goto bad; 2769 2770 return; 2771 2772 bad: 2773 aprint_error_dev(sc->sc_dev, "could not attach sysctl nodes\n"); 2774 } 2775
Indexes created Tue Sep 30 11:09:46 GMT 2025