pq3etsec.c revision 1.50.2.1
1 /* $NetBSD: pq3etsec.c,v 1.50.2.1 2021/04/03 22:28:34 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.50.2.1 2021/04/03 22:28:34 thorpej Exp $"); 39 40 #ifdef _KERNEL_OPT 41 #include "opt_inet.h" 42 #include "opt_mpc85xx.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_net_mpsafe.h" 45 #endif 46 47 #include <sys/param.h> 48 #include <sys/cpu.h> 49 #include <sys/device.h> 50 #include <sys/mbuf.h> 51 #include <sys/ioctl.h> 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/atomic.h> 58 #include <sys/callout.h> 59 #include <sys/sysctl.h> 60 61 #include <sys/rndsource.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/bpf.h> 68 69 #include <dev/mii/miivar.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/ip.h> 75 #include <netinet/in_offload.h> 76 #endif /* INET */ 77 #ifdef INET6 78 #include <netinet6/in6.h> 79 #include <netinet/ip6.h> 80 #endif 81 #include <netinet6/in6_offload.h> 82 83 #include <powerpc/spr.h> 84 #include <powerpc/booke/spr.h> 85 #include <powerpc/booke/cpuvar.h> 86 #include <powerpc/booke/e500var.h> 87 #include <powerpc/booke/e500reg.h> 88 #include <powerpc/booke/etsecreg.h> 89 90 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 91 92 #define ETSEC_MAXTXMBUFS 30 93 #define ETSEC_NTXSEGS 30 94 #define ETSEC_MAXRXMBUFS 511 95 #define ETSEC_MINRXMBUFS 32 96 #define ETSEC_NRXSEGS 1 97 98 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 99 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx \ 100 | IFCAP_CSUM_UDPv4_Rx \ 101 | IFCAP_CSUM_TCPv6_Rx \ 102 | IFCAP_CSUM_UDPv6_Rx) 103 104 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 105 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx \ 106 | IFCAP_CSUM_UDPv4_Tx \ 107 | IFCAP_CSUM_TCPv6_Tx \ 108 | IFCAP_CSUM_UDPv6_Tx) 109 110 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN | IFCAP_RCTRL_TUCSEN \ 111 | IFCAP_TCTRL_IPCSEN | IFCAP_TCTRL_TUCSEN) 112 113 #define M_CSUM_IP (M_CSUM_CIP | M_CSUM_CTU) 114 #define M_CSUM_IP6 (M_CSUM_TCPv6 | M_CSUM_UDPv6) 115 #define M_CSUM_TUP (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6) 116 #define M_CSUM_UDP (M_CSUM_UDPv4 | M_CSUM_UDPv6) 117 #define M_CSUM_IP4 (M_CSUM_IPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4) 118 #define M_CSUM_CIP (M_CSUM_IPv4) 119 #define M_CSUM_CTU (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6) 120 121 struct pq3etsec_txqueue { 122 bus_dmamap_t txq_descmap; 123 volatile struct txbd *txq_consumer; 124 volatile struct txbd *txq_producer; 125 volatile struct txbd *txq_first; 126 volatile struct txbd *txq_last; 127 struct ifqueue txq_mbufs; 128 struct mbuf *txq_next; 129 #ifdef ETSEC_DEBUG 130 struct mbuf *txq_lmbufs[512]; 131 #endif 132 uint32_t txq_qmask; 133 uint32_t txq_free; 134 uint32_t txq_threshold; 135 uint32_t txq_lastintr; 136 bus_size_t txq_reg_tbase; 137 bus_dma_segment_t txq_descmap_seg; 138 }; 139 140 struct pq3etsec_rxqueue { 141 bus_dmamap_t rxq_descmap; 142 volatile struct rxbd *rxq_consumer; 143 volatile struct rxbd *rxq_producer; 144 volatile struct rxbd *rxq_first; 145 volatile struct rxbd *rxq_last; 146 struct mbuf *rxq_mhead; 147 struct mbuf **rxq_mtail; 148 struct mbuf *rxq_mconsumer; 149 #ifdef ETSEC_DEBUG 150 struct mbuf *rxq_mbufs[512]; 151 #endif 152 uint32_t rxq_qmask; 153 uint32_t rxq_inuse; 154 uint32_t rxq_threshold; 155 bus_size_t rxq_reg_rbase; 156 bus_size_t rxq_reg_rbptr; 157 bus_dma_segment_t rxq_descmap_seg; 158 }; 159 160 struct pq3etsec_mapcache { 161 u_int dmc_nmaps; 162 u_int dmc_maxseg; 163 u_int dmc_maxmaps; 164 u_int dmc_maxmapsize; 165 bus_dmamap_t dmc_maps[0]; 166 }; 167 168 struct pq3etsec_softc { 169 device_t sc_dev; 170 device_t sc_mdio_dev; 171 struct ethercom sc_ec; 172 #define sc_if sc_ec.ec_if 173 struct mii_data sc_mii; 174 bus_space_tag_t sc_bst; 175 bus_space_handle_t sc_bsh; 176 bus_space_handle_t sc_mdio_bsh; 177 bus_dma_tag_t sc_dmat; 178 int sc_phy_addr; 179 prop_dictionary_t sc_intrmap; 180 uint32_t sc_intrmask; 181 182 uint32_t sc_soft_flags; 183 #define SOFT_RESET 0x0001 184 #define SOFT_RXINTR 0x0010 185 #define SOFT_RXBSY 0x0020 186 #define SOFT_TXINTR 0x0100 187 #define SOFT_TXERROR 0x0200 188 189 struct pq3etsec_txqueue sc_txq; 190 struct pq3etsec_rxqueue sc_rxq; 191 uint32_t sc_txerrors; 192 uint32_t sc_rxerrors; 193 194 size_t sc_rx_adjlen; 195 196 /* 197 * Copies of various ETSEC registers. 198 */ 199 uint32_t sc_imask; 200 uint32_t sc_maccfg1; 201 uint32_t sc_maccfg2; 202 uint32_t sc_maxfrm; 203 uint32_t sc_ecntrl; 204 uint32_t sc_dmactrl; 205 uint32_t sc_macstnaddr1; 206 uint32_t sc_macstnaddr2; 207 uint32_t sc_tctrl; 208 uint32_t sc_rctrl; 209 uint32_t sc_gaddr[16]; 210 uint64_t sc_macaddrs[15]; 211 212 void *sc_tx_ih; 213 void *sc_rx_ih; 214 void *sc_error_ih; 215 void *sc_soft_ih; 216 217 kmutex_t *sc_lock; 218 kmutex_t *sc_hwlock; 219 220 struct evcnt sc_ev_tx_stall; 221 struct evcnt sc_ev_tx_intr; 222 struct evcnt sc_ev_rx_stall; 223 struct evcnt sc_ev_rx_intr; 224 struct evcnt sc_ev_error_intr; 225 struct evcnt sc_ev_soft_intr; 226 struct evcnt sc_ev_tx_pause; 227 struct evcnt sc_ev_rx_pause; 228 struct evcnt sc_ev_mii_ticks; 229 230 struct callout sc_mii_callout; 231 uint64_t sc_mii_last_tick; 232 233 struct ifqueue sc_rx_bufcache; 234 struct pq3etsec_mapcache *sc_rx_mapcache; 235 struct pq3etsec_mapcache *sc_tx_mapcache; 236 237 /* Interrupt Coalescing parameters */ 238 int sc_ic_rx_time; 239 int sc_ic_rx_count; 240 int sc_ic_tx_time; 241 int sc_ic_tx_count; 242 243 krndsource_t rnd_source; 244 }; 245 246 #define ETSEC_IC_RX_ENABLED(sc) \ 247 ((sc)->sc_ic_rx_time != 0 && (sc)->sc_ic_rx_count != 0) 248 #define ETSEC_IC_TX_ENABLED(sc) \ 249 ((sc)->sc_ic_tx_time != 0 && (sc)->sc_ic_tx_count != 0) 250 251 struct pq3mdio_softc { 252 device_t mdio_dev; 253 254 kmutex_t *mdio_lock; 255 256 bus_space_tag_t mdio_bst; 257 bus_space_handle_t mdio_bsh; 258 }; 259 260 static int pq3etsec_match(device_t, cfdata_t, void *); 261 static void pq3etsec_attach(device_t, device_t, void *); 262 263 static int pq3mdio_match(device_t, cfdata_t, void *); 264 static void pq3mdio_attach(device_t, device_t, void *); 265 266 static void pq3etsec_ifstart(struct ifnet *); 267 static void pq3etsec_ifwatchdog(struct ifnet *); 268 static int pq3etsec_ifinit(struct ifnet *); 269 static void pq3etsec_ifstop(struct ifnet *, int); 270 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 271 272 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 273 struct pq3etsec_mapcache **, size_t, size_t, size_t); 274 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 275 struct pq3etsec_mapcache *); 276 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 277 struct pq3etsec_mapcache *); 278 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 279 struct pq3etsec_mapcache *, bus_dmamap_t); 280 281 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 282 struct pq3etsec_txqueue *, u_int); 283 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 284 struct pq3etsec_txqueue *); 285 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 286 struct pq3etsec_txqueue *); 287 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 288 struct pq3etsec_txqueue *); 289 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 290 struct pq3etsec_txqueue *, struct mbuf *m); 291 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 292 struct pq3etsec_txqueue *); 293 294 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 295 struct pq3etsec_rxqueue *, u_int); 296 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 297 struct pq3etsec_rxqueue *); 298 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 299 struct pq3etsec_rxqueue *, bool); 300 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 301 struct pq3etsec_rxqueue *); 302 303 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 304 305 static void pq3etsec_mii_tick(void *); 306 static int pq3etsec_rx_intr(void *); 307 static int pq3etsec_tx_intr(void *); 308 static int pq3etsec_error_intr(void *); 309 static void pq3etsec_soft_intr(void *); 310 311 static void pq3etsec_set_ic_rx(struct pq3etsec_softc *); 312 static void pq3etsec_set_ic_tx(struct pq3etsec_softc *); 313 314 static void pq3etsec_sysctl_setup(struct sysctllog **, struct pq3etsec_softc *); 315 316 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 317 pq3etsec_match, pq3etsec_attach, NULL, NULL); 318 319 CFATTACH_DECL_NEW(pq3mdio_tsec, sizeof(struct pq3mdio_softc), 320 pq3mdio_match, pq3mdio_attach, NULL, NULL); 321 322 CFATTACH_DECL_NEW(pq3mdio_cpunode, sizeof(struct pq3mdio_softc), 323 pq3mdio_match, pq3mdio_attach, NULL, NULL); 324 325 static inline uint32_t 326 etsec_mdio_read(struct pq3mdio_softc *mdio, bus_size_t off) 327 { 328 return bus_space_read_4(mdio->mdio_bst, mdio->mdio_bsh, off); 329 } 330 331 static inline void 332 etsec_mdio_write(struct pq3mdio_softc *mdio, bus_size_t off, uint32_t data) 333 { 334 bus_space_write_4(mdio->mdio_bst, mdio->mdio_bsh, off, data); 335 } 336 337 static inline uint32_t 338 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 339 { 340 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 341 } 342 343 static int 344 pq3mdio_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 345 { 346 return strcmp(cf->cf_name, "mdio") == 0; 347 } 348 349 static int 350 pq3mdio_match(device_t parent, cfdata_t cf, void *aux) 351 { 352 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 353 const bool p1025_p = (svr == (SVR_P1025v1 >> 16) 354 || svr == (SVR_P1016v1 >> 16)); 355 356 if (device_is_a(parent, "cpunode")) { 357 if (!p1025_p 358 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 359 return 0; 360 361 return 1; 362 } 363 364 if (device_is_a(parent, "tsec")) { 365 if (p1025_p 366 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 367 return 0; 368 369 return 1; 370 } 371 372 return 0; 373 } 374 375 static void 376 pq3mdio_attach(device_t parent, device_t self, void *aux) 377 { 378 struct pq3mdio_softc * const mdio = device_private(self); 379 struct cpunode_attach_args * const cna = aux; 380 struct cpunode_locators * const cnl = &cna->cna_locs; 381 382 mdio->mdio_dev = self; 383 mdio->mdio_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 384 385 if (device_is_a(parent, "cpunode")) { 386 struct cpunode_softc * const psc = device_private(parent); 387 psc->sc_children |= cna->cna_childmask; 388 389 mdio->mdio_bst = cna->cna_memt; 390 if (bus_space_map(mdio->mdio_bst, cnl->cnl_addr, 391 cnl->cnl_size, 0, &mdio->mdio_bsh) != 0) { 392 aprint_error(": error mapping registers @ %#x\n", 393 cnl->cnl_addr); 394 return; 395 } 396 } else { 397 struct pq3etsec_softc * const sc = device_private(parent); 398 399 KASSERT(device_is_a(parent, "tsec")); 400 KASSERTMSG(cnl->cnl_addr == ETSEC1_BASE 401 || cnl->cnl_addr == ETSEC2_BASE 402 || cnl->cnl_addr == ETSEC3_BASE 403 || cnl->cnl_addr == ETSEC4_BASE, 404 "unknown tsec addr %x", cnl->cnl_addr); 405 406 mdio->mdio_bst = sc->sc_bst; 407 mdio->mdio_bsh = sc->sc_bsh; 408 } 409 410 aprint_normal("\n"); 411 } 412 413 static int 414 pq3mdio_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 415 { 416 struct pq3mdio_softc * const mdio = device_private(self); 417 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 418 419 mutex_enter(mdio->mdio_lock); 420 421 etsec_mdio_write(mdio, MIIMADD, 422 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 423 424 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 425 etsec_mdio_write(mdio, MIIMCOM, MIIMCOM_READ); 426 427 while (etsec_mdio_read(mdio, MIIMIND) != 0) { 428 delay(1); 429 } 430 *val = etsec_mdio_read(mdio, MIIMSTAT) &0xffff; 431 432 if (miimcom == MIIMCOM_SCAN) 433 etsec_mdio_write(mdio, MIIMCOM, miimcom); 434 435 #if 0 436 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 437 __func__, phy, reg, data); 438 #endif 439 mutex_exit(mdio->mdio_lock); 440 return 0; 441 } 442 443 static int 444 pq3mdio_mii_writereg(device_t self, int phy, int reg, uint16_t data) 445 { 446 struct pq3mdio_softc * const mdio = device_private(self); 447 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 448 449 #if 0 450 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 451 __func__, phy, reg, data); 452 #endif 453 454 mutex_enter(mdio->mdio_lock); 455 456 etsec_mdio_write(mdio, MIIMADD, 457 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 458 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 459 etsec_mdio_write(mdio, MIIMCON, data); 460 461 int timo = 1000; /* 1ms */ 462 while ((etsec_mdio_read(mdio, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 463 delay(1); 464 } 465 466 if (miimcom == MIIMCOM_SCAN) 467 etsec_mdio_write(mdio, MIIMCOM, miimcom); 468 469 mutex_exit(mdio->mdio_lock); 470 471 return 0; 472 } 473 474 static inline void 475 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 476 { 477 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 478 } 479 480 static void 481 pq3etsec_mii_statchg(struct ifnet *ifp) 482 { 483 struct pq3etsec_softc * const sc = ifp->if_softc; 484 struct mii_data * const mii = &sc->sc_mii; 485 486 uint32_t maccfg1 = sc->sc_maccfg1; 487 uint32_t maccfg2 = sc->sc_maccfg2; 488 uint32_t ecntrl = sc->sc_ecntrl; 489 490 maccfg1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 491 maccfg2 &= ~(MACCFG2_IFMODE | MACCFG2_FD); 492 493 if (sc->sc_mii.mii_media_active & IFM_FDX) { 494 maccfg2 |= MACCFG2_FD; 495 } 496 497 /* 498 * Now deal with the flow control bits. 499 */ 500 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 501 && (mii->mii_media_active & IFM_ETH_FMASK)) { 502 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 503 maccfg1 |= MACCFG1_RX_FLOW; 504 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 505 maccfg1 |= MACCFG1_TX_FLOW; 506 } 507 508 /* 509 * Now deal with the speed. 510 */ 511 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 512 maccfg2 |= MACCFG2_IFMODE_GMII; 513 } else { 514 maccfg2 |= MACCFG2_IFMODE_MII; 515 ecntrl &= ~ECNTRL_R100M; 516 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 517 ecntrl |= ECNTRL_R100M; 518 } 519 } 520 521 /* 522 * If things are different, re-init things. 523 */ 524 if (maccfg1 != sc->sc_maccfg1 525 || maccfg2 != sc->sc_maccfg2 526 || ecntrl != sc->sc_ecntrl) { 527 if (sc->sc_if.if_flags & IFF_RUNNING) 528 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 529 sc->sc_maccfg1 = maccfg1; 530 sc->sc_maccfg2 = maccfg2; 531 sc->sc_ecntrl = ecntrl; 532 } 533 } 534 535 #if 0 536 static void 537 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 538 { 539 struct pq3etsec_softc * const sc = ifp->if_softc; 540 541 mii_pollstat(&sc->sc_mii); 542 ether_mediastatus(ifp, ifmr); 543 ifmr->ifm_status = sc->sc_mii.mii_media_status; 544 ifmr->ifm_active = sc->sc_mii.mii_media_active; 545 } 546 547 static int 548 pq3etsec_mediachange(struct ifnet *ifp) 549 { 550 struct pq3etsec_softc * const sc = ifp->if_softc; 551 552 if ((ifp->if_flags & IFF_UP) == 0) 553 return 0; 554 555 int rv = mii_mediachg(&sc->sc_mii); 556 return (rv == ENXIO) ? 0 : rv; 557 } 558 #endif 559 560 static int 561 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 562 { 563 564 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 565 return 0; 566 567 return 1; 568 } 569 570 static void 571 pq3etsec_attach(device_t parent, device_t self, void *aux) 572 { 573 struct cpunode_softc * const psc = device_private(parent); 574 struct pq3etsec_softc * const sc = device_private(self); 575 struct mii_data * const mii = &sc->sc_mii; 576 struct cpunode_attach_args * const cna = aux; 577 struct cpunode_locators * const cnl = &cna->cna_locs; 578 cfdata_t cf = device_cfdata(self); 579 int error; 580 581 psc->sc_children |= cna->cna_childmask; 582 sc->sc_dev = self; 583 sc->sc_bst = cna->cna_memt; 584 sc->sc_dmat = &booke_bus_dma_tag; 585 586 /* 587 * Pull out the mdio bus and phy we are supposed to use. 588 */ 589 const int mdio = cf->cf_loc[CPUNODECF_MDIO]; 590 const int phy = cf->cf_loc[CPUNODECF_PHY]; 591 if (mdio != CPUNODECF_MDIO_DEFAULT) 592 aprint_normal(" mdio %d", mdio); 593 594 /* 595 * See if the phy is in the config file... 596 */ 597 if (phy != CPUNODECF_PHY_DEFAULT) { 598 sc->sc_phy_addr = phy; 599 } else { 600 unsigned char prop_name[20]; 601 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 602 cnl->cnl_instance); 603 sc->sc_phy_addr = board_info_get_number(prop_name); 604 } 605 if (sc->sc_phy_addr != MII_PHY_ANY) 606 aprint_normal(" phy %d", sc->sc_phy_addr); 607 608 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 609 &sc->sc_bsh); 610 if (error) { 611 aprint_error(": error mapping registers: %d\n", error); 612 return; 613 } 614 615 /* 616 * Assume firmware has aready set the mac address and fetch it 617 * before we reinit it. 618 */ 619 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 620 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 621 sc->sc_rctrl = RCTRL_DEFAULT; 622 sc->sc_ecntrl = etsec_read(sc, ECNTRL); 623 sc->sc_maccfg1 = etsec_read(sc, MACCFG1); 624 sc->sc_maccfg2 = etsec_read(sc, MACCFG2) | MACCFG2_DEFAULT; 625 626 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 627 size_t len; 628 const uint8_t *mac_addr = 629 board_info_get_data("tsec-mac-addr-base", &len); 630 KASSERT(len == ETHER_ADDR_LEN); 631 sc->sc_macstnaddr2 = 632 (mac_addr[1] << 24) 633 | (mac_addr[0] << 16); 634 sc->sc_macstnaddr1 = 635 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 636 | (mac_addr[4] << 16) 637 | (mac_addr[3] << 8) 638 | (mac_addr[2] << 0); 639 #if 0 640 aprint_error(": mac-address unknown\n"); 641 return; 642 #endif 643 } 644 645 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 646 sc->sc_hwlock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_VM); 647 648 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 649 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 650 651 /* Disable interrupts */ 652 etsec_write(sc, IMASK, 0); 653 654 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 655 if (error) { 656 aprint_error(": failed to init rxq: %d\n", error); 657 goto fail_1; 658 } 659 660 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 661 if (error) { 662 aprint_error(": failed to init txq: %d\n", error); 663 goto fail_2; 664 } 665 666 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 667 ETSEC_MAXRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 668 if (error) { 669 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 670 goto fail_3; 671 } 672 673 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 674 ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 675 if (error) { 676 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 677 goto fail_4; 678 } 679 680 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 681 pq3etsec_tx_intr, sc); 682 if (sc->sc_tx_ih == NULL) { 683 aprint_error(": failed to establish tx interrupt: %d\n", 684 cnl->cnl_intrs[0]); 685 goto fail_5; 686 } 687 688 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 689 pq3etsec_rx_intr, sc); 690 if (sc->sc_rx_ih == NULL) { 691 aprint_error(": failed to establish rx interrupt: %d\n", 692 cnl->cnl_intrs[1]); 693 goto fail_6; 694 } 695 696 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 697 pq3etsec_error_intr, sc); 698 if (sc->sc_error_ih == NULL) { 699 aprint_error(": failed to establish error interrupt: %d\n", 700 cnl->cnl_intrs[2]); 701 goto fail_7; 702 } 703 704 int softint_flags = SOFTINT_NET; 705 #if !defined(MULTIPROCESSOR) || defined(NET_MPSAFE) 706 softint_flags |= SOFTINT_MPSAFE; 707 #endif /* !MULTIPROCESSOR || NET_MPSAFE */ 708 sc->sc_soft_ih = softint_establish(softint_flags, 709 pq3etsec_soft_intr, sc); 710 if (sc->sc_soft_ih == NULL) { 711 aprint_error(": failed to establish soft interrupt\n"); 712 goto fail_8; 713 } 714 715 /* 716 * If there was no MDIO 717 */ 718 if (mdio == CPUNODECF_MDIO_DEFAULT) { 719 aprint_normal("\n"); 720 cfdata_t mdio_cf = config_search_ia(pq3mdio_find, self, NULL, cna); 721 if (mdio_cf != NULL) { 722 sc->sc_mdio_dev = config_attach(self, mdio_cf, cna, NULL); 723 } 724 } else { 725 sc->sc_mdio_dev = device_find_by_driver_unit("mdio", mdio); 726 if (sc->sc_mdio_dev == NULL) { 727 aprint_error(": failed to locate mdio device\n"); 728 goto fail_9; 729 } 730 aprint_normal("\n"); 731 } 732 733 etsec_write(sc, ATTR, ATTR_DEFAULT); 734 etsec_write(sc, ATTRELI, ATTRELI_DEFAULT); 735 736 /* Enable interrupt coalesing */ 737 sc->sc_ic_rx_time = 768; 738 sc->sc_ic_rx_count = 16; 739 sc->sc_ic_tx_time = 768; 740 sc->sc_ic_tx_count = 16; 741 pq3etsec_set_ic_rx(sc); 742 pq3etsec_set_ic_tx(sc); 743 744 char enaddr[ETHER_ADDR_LEN] = { 745 [0] = sc->sc_macstnaddr2 >> 16, 746 [1] = sc->sc_macstnaddr2 >> 24, 747 [2] = sc->sc_macstnaddr1 >> 0, 748 [3] = sc->sc_macstnaddr1 >> 8, 749 [4] = sc->sc_macstnaddr1 >> 16, 750 [5] = sc->sc_macstnaddr1 >> 24, 751 }; 752 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 753 ether_sprintf(enaddr)); 754 755 const char * const xname = device_xname(sc->sc_dev); 756 struct ethercom * const ec = &sc->sc_ec; 757 struct ifnet * const ifp = &ec->ec_if; 758 759 ec->ec_mii = mii; 760 761 mii->mii_ifp = ifp; 762 mii->mii_readreg = pq3mdio_mii_readreg; 763 mii->mii_writereg = pq3mdio_mii_writereg; 764 mii->mii_statchg = pq3etsec_mii_statchg; 765 766 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 767 768 if (sc->sc_mdio_dev != NULL && sc->sc_phy_addr < 32) { 769 mii_attach(sc->sc_mdio_dev, mii, 0xffffffff, 770 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 771 772 if (LIST_FIRST(&mii->mii_phys) == NULL) { 773 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 774 0, NULL); 775 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 776 } else { 777 callout_schedule(&sc->sc_mii_callout, hz); 778 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 779 } 780 } else { 781 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 782 0, NULL); 783 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_1000_T | IFM_FDX); 784 } 785 786 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 787 | ETHERCAP_JUMBO_MTU; 788 ec->ec_capenable = ETHERCAP_VLAN_HWTAGGING; 789 790 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 791 ifp->if_softc = sc; 792 ifp->if_capabilities = IFCAP_ETSEC; 793 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 794 ifp->if_ioctl = pq3etsec_ifioctl; 795 ifp->if_start = pq3etsec_ifstart; 796 ifp->if_watchdog = pq3etsec_ifwatchdog; 797 ifp->if_init = pq3etsec_ifinit; 798 ifp->if_stop = pq3etsec_ifstop; 799 IFQ_SET_READY(&ifp->if_snd); 800 801 /* 802 * Attach the interface. 803 */ 804 error = if_initialize(ifp); 805 if (error != 0) { 806 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 807 error); 808 goto fail_10; 809 } 810 pq3etsec_sysctl_setup(NULL, sc); 811 if_attach(ifp); 812 if_deferred_start_init(ifp, NULL); 813 ether_ifattach(ifp, enaddr); 814 815 rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, 816 RND_FLAG_DEFAULT); 817 818 pq3etsec_ifstop(ifp, true); 819 820 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 821 NULL, xname, "rx stall"); 822 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 823 NULL, xname, "tx stall"); 824 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 825 NULL, xname, "tx intr"); 826 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 827 NULL, xname, "rx intr"); 828 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 829 NULL, xname, "error intr"); 830 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 831 NULL, xname, "soft intr"); 832 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 833 NULL, xname, "tx pause"); 834 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 835 NULL, xname, "rx pause"); 836 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 837 NULL, xname, "mii ticks"); 838 return; 839 840 fail_10: 841 ifmedia_removeall(&mii->mii_media); 842 mii_detach(mii, sc->sc_phy_addr, MII_OFFSET_ANY); 843 fail_9: 844 softint_disestablish(sc->sc_soft_ih); 845 fail_8: 846 intr_disestablish(sc->sc_error_ih); 847 fail_7: 848 intr_disestablish(sc->sc_rx_ih); 849 fail_6: 850 intr_disestablish(sc->sc_tx_ih); 851 fail_5: 852 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 853 fail_4: 854 pq3etsec_mapcache_destroy(sc, sc->sc_rx_mapcache); 855 fail_3: 856 #if 0 /* notyet */ 857 pq3etsec_txq_detach(sc); 858 #endif 859 fail_2: 860 #if 0 /* notyet */ 861 pq3etsec_rxq_detach(sc); 862 #endif 863 fail_1: 864 callout_destroy(&sc->sc_mii_callout); 865 mutex_obj_free(sc->sc_lock); 866 mutex_obj_free(sc->sc_hwlock); 867 bus_space_unmap(sc->sc_bst, sc->sc_bsh, cnl->cnl_size); 868 } 869 870 static uint64_t 871 pq3etsec_macaddr_create(const uint8_t *lladdr) 872 { 873 uint64_t macaddr = 0; 874 875 lladdr += ETHER_ADDR_LEN; 876 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 877 macaddr = (macaddr << 8) | *--lladdr; 878 } 879 return macaddr << 16; 880 } 881 882 static int 883 pq3etsec_ifinit(struct ifnet *ifp) 884 { 885 struct pq3etsec_softc * const sc = ifp->if_softc; 886 int error = 0; 887 888 sc->sc_maxfrm = uimax(ifp->if_mtu + 32, MCLBYTES); 889 if (ifp->if_mtu > ETHERMTU_JUMBO) 890 return error; 891 892 KASSERT(ifp->if_flags & IFF_UP); 893 894 /* 895 * Stop the interface (steps 1 to 4 in the Soft Reset and 896 * Reconfigurating Procedure. 897 */ 898 pq3etsec_ifstop(ifp, 0); 899 900 /* 901 * If our frame size has changed (or it's our first time through) 902 * destroy the existing transmit mapcache. 903 */ 904 if (sc->sc_tx_mapcache != NULL 905 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 906 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 907 sc->sc_tx_mapcache = NULL; 908 } 909 910 if (sc->sc_tx_mapcache == NULL) { 911 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 912 ETSEC_MAXTXMBUFS, sc->sc_maxfrm, ETSEC_NTXSEGS); 913 if (error) 914 return error; 915 } 916 917 sc->sc_ev_mii_ticks.ev_count++; 918 mii_tick(&sc->sc_mii); 919 920 if (ifp->if_flags & IFF_PROMISC) { 921 sc->sc_rctrl |= RCTRL_PROM; 922 } else { 923 sc->sc_rctrl &= ~RCTRL_PROM; 924 } 925 926 uint32_t rctrl_prsdep = 0; 927 sc->sc_rctrl &= 928 ~(RCTRL_IPCSEN | RCTRL_TUCSEN | RCTRL_VLEX | RCTRL_PRSDEP); 929 if (VLAN_ATTACHED(&sc->sc_ec)) { 930 sc->sc_rctrl |= RCTRL_VLEX; 931 rctrl_prsdep = RCTRL_PRSDEP_L2; 932 } 933 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 934 sc->sc_rctrl |= RCTRL_IPCSEN; 935 rctrl_prsdep = RCTRL_PRSDEP_L3; 936 } 937 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 938 sc->sc_rctrl |= RCTRL_TUCSEN; 939 rctrl_prsdep = RCTRL_PRSDEP_L4; 940 } 941 sc->sc_rctrl |= rctrl_prsdep; 942 #if 0 943 if (sc->sc_rctrl 944 & (RCTRL_IPCSEN | RCTRL_TUCSEN | RCTRL_VLEX | RCTRL_PRSDEP)) 945 aprint_normal_dev(sc->sc_dev, 946 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 947 sc->sc_rctrl, 948 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 949 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 950 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 951 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 952 #endif 953 954 sc->sc_tctrl &= ~(TCTRL_IPCSEN | TCTRL_TUCSEN | TCTRL_VLINS); 955 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 956 sc->sc_tctrl |= TCTRL_VLINS; 957 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 958 sc->sc_tctrl |= TCTRL_IPCSEN; 959 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 960 sc->sc_tctrl |= TCTRL_TUCSEN; 961 #if 0 962 if (sc->sc_tctrl & (TCTRL_IPCSEN | TCTRL_TUCSEN | TCTRL_VLINS)) 963 aprint_normal_dev(sc->sc_dev, 964 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 965 sc->sc_tctrl, 966 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 967 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 968 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 969 #endif 970 971 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 972 973 const uint64_t macstnaddr = 974 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 975 976 sc->sc_imask = IEVENT_DPE; 977 978 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 979 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 980 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 981 982 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 983 pq3etsec_txq_reset(sc, &sc->sc_txq); 984 985 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 986 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 987 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 988 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 989 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 990 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 991 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 992 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 993 994 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 995 pq3etsec_mc_setup(sc); 996 997 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 998 etsec_write(sc, MRBLR, MCLBYTES); 999 1000 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 1001 sc->sc_dmactrl |= DMACTRL_DEFAULT; 1002 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1003 1004 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 1005 etsec_write(sc, TQUEUE, TQUEUE_EN0); 1006 sc->sc_imask |= IEVENT_TXF | IEVENT_TXE | IEVENT_TXC; 1007 1008 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 1009 1010 /* 12. Enable receive queues in RQUEUE, */ 1011 etsec_write(sc, RQUEUE, RQUEUE_EN0 | RQUEUE_EX0); 1012 sc->sc_imask |= IEVENT_RXF | IEVENT_BSY | IEVENT_RXC; 1013 1014 /* and optionally set TOE functionality in RCTRL. */ 1015 etsec_write(sc, RCTRL, sc->sc_rctrl); 1016 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 1017 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 1018 sc->sc_rx_adjlen += sizeof(struct rxfcb); 1019 1020 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 1021 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 1022 1023 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 1024 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 1025 1026 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 1027 sc->sc_dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 1028 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1029 1030 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 1031 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1032 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1033 1034 sc->sc_soft_flags = 0; 1035 1036 etsec_write(sc, IMASK, sc->sc_imask); 1037 1038 ifp->if_flags |= IFF_RUNNING; 1039 1040 return error; 1041 } 1042 1043 static void 1044 pq3etsec_ifstop(struct ifnet *ifp, int disable) 1045 { 1046 struct pq3etsec_softc * const sc = ifp->if_softc; 1047 1048 KASSERT(!cpu_intr_p()); 1049 const uint32_t imask_gsc_mask = IEVENT_GTSC | IEVENT_GRSC; 1050 /* 1051 * Clear the GTSC and GRSC from the interrupt mask until 1052 * we are ready for them. Then clear them from IEVENT, 1053 * request the graceful shutdown, and then enable the 1054 * GTSC and GRSC bits in the mask. This should cause the 1055 * error interrupt to fire which will issue a wakeup to 1056 * allow us to resume. 1057 */ 1058 1059 /* 1060 * 1. Set GRS/GTS bits in DMACTRL register 1061 */ 1062 sc->sc_dmactrl |= DMACTRL_GRS | DMACTRL_GTS; 1063 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 1064 etsec_write(sc, IEVENT, imask_gsc_mask); 1065 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1066 1067 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN | MACCFG1_RX_EN)) { 1068 /* 1069 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 1070 */ 1071 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 1072 1073 u_int timo = 1000; 1074 uint32_t ievent = etsec_read(sc, IEVENT); 1075 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 1076 if (--timo == 0) { 1077 aprint_error_dev(sc->sc_dev, 1078 "WARNING: " 1079 "request to stop failed (IEVENT=%#x)\n", 1080 ievent); 1081 break; 1082 } 1083 delay(10); 1084 ievent = etsec_read(sc, IEVENT); 1085 } 1086 } 1087 1088 /* 1089 * Now reset the controller. 1090 * 1091 * 3. Set SOFT_RESET bit in MACCFG1 register 1092 * 4. Clear SOFT_RESET bit in MACCFG1 register 1093 */ 1094 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 1095 etsec_write(sc, MACCFG1, 0); 1096 etsec_write(sc, IMASK, 0); 1097 etsec_write(sc, IEVENT, ~0); 1098 sc->sc_imask = 0; 1099 ifp->if_flags &= ~IFF_RUNNING; 1100 1101 uint32_t tbipa = etsec_read(sc, TBIPA); 1102 if (tbipa == sc->sc_phy_addr) { 1103 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 1104 etsec_write(sc, TBIPA, 0x1f); 1105 } 1106 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 1107 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 1108 etsec_write(sc, MIIMCFG, miimcfg); 1109 1110 /* 1111 * Let's consume any remaing transmitted packets. And if we are 1112 * disabling the interface, purge ourselves of any untransmitted 1113 * packets. But don't consume any received packets, just drop them. 1114 * If we aren't disabling the interface, save the mbufs in the 1115 * receive queue for reuse. 1116 */ 1117 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 1118 pq3etsec_txq_consume(sc, &sc->sc_txq); 1119 if (disable) { 1120 pq3etsec_txq_purge(sc, &sc->sc_txq); 1121 IFQ_PURGE(&ifp->if_snd); 1122 } 1123 } 1124 1125 static void 1126 pq3etsec_ifwatchdog(struct ifnet *ifp) 1127 { 1128 } 1129 1130 static void 1131 pq3etsec_mc_setup( 1132 struct pq3etsec_softc *sc) 1133 { 1134 struct ethercom * const ec = &sc->sc_ec; 1135 struct ifnet * const ifp = &sc->sc_if; 1136 struct ether_multi *enm; 1137 struct ether_multistep step; 1138 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 1139 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 1140 1141 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 1142 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1143 1144 ifp->if_flags &= ~IFF_ALLMULTI; 1145 1146 ETHER_LOCK(ec); 1147 ETHER_FIRST_MULTI(step, ec, enm); 1148 for (u_int i = 0; enm != NULL; ) { 1149 const char *addr = enm->enm_addrlo; 1150 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1151 ifp->if_flags |= IFF_ALLMULTI; 1152 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 1153 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1154 break; 1155 } 1156 if ((sc->sc_rctrl & RCTRL_EMEN) 1157 && i < __arraycount(sc->sc_macaddrs)) { 1158 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 1159 } else { 1160 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1161 #if 0 1162 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 1163 ether_sprintf(addr), crc, 1164 crc >> crc_shift, 1165 crc >> (crc_shift + 5), 1166 (crc >> crc_shift) & 31, 1167 1 << (((crc >> crc_shift) & 31) ^ 31)); 1168 #endif 1169 /* 1170 * The documentation doesn't completely follow PowerPC 1171 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 1172 * is 0x7fa32d9b. By empirical testing, the 1173 * corresponding hash bit is word 3, bit 31 (ppc bit 1174 * order). Since 3 << 31 | 31 is 0x7f, we deduce 1175 * H[0:2] selects the register while H[3:7] selects 1176 * the bit (ppc bit order). 1177 */ 1178 crc >>= crc_shift; 1179 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 1180 } 1181 ETHER_NEXT_MULTI(step, enm); 1182 } 1183 ETHER_UNLOCK(ec); 1184 for (u_int i = 0; i < 8; i++) { 1185 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 1186 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 1187 #if 0 1188 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 1189 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 1190 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 1191 i, GADDR(i), etsec_read(sc, GADDR(i))); 1192 #endif 1193 } 1194 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 1195 uint64_t macaddr = sc->sc_macaddrs[i]; 1196 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 1197 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 1198 #if 0 1199 if (macaddr) 1200 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 1201 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1202 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1203 #endif 1204 } 1205 } 1206 1207 static int 1208 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1209 { 1210 struct pq3etsec_softc *sc = ifp->if_softc; 1211 struct ifreq * const ifr = data; 1212 const int s = splnet(); 1213 int error; 1214 1215 switch (cmd) { 1216 case SIOCSIFMEDIA: 1217 /* Flow control requires full-duplex mode. */ 1218 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1219 (ifr->ifr_media & IFM_FDX) == 0) 1220 ifr->ifr_media &= ~IFM_ETH_FMASK; 1221 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1222 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1223 /* We can do both TXPAUSE and RXPAUSE. */ 1224 ifr->ifr_media |= 1225 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1226 } 1227 } 1228 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1229 break; 1230 1231 default: 1232 error = ether_ioctl(ifp, cmd, data); 1233 if (error != ENETRESET) 1234 break; 1235 1236 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1237 error = 0; 1238 if (ifp->if_flags & IFF_RUNNING) 1239 pq3etsec_mc_setup(sc); 1240 break; 1241 } 1242 error = pq3etsec_ifinit(ifp); 1243 break; 1244 } 1245 1246 splx(s); 1247 return error; 1248 } 1249 1250 static void 1251 pq3etsec_rxq_desc_presync( 1252 struct pq3etsec_softc *sc, 1253 struct pq3etsec_rxqueue *rxq, 1254 volatile struct rxbd *rxbd, 1255 size_t count) 1256 { 1257 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1258 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1259 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1260 } 1261 1262 static void 1263 pq3etsec_rxq_desc_postsync( 1264 struct pq3etsec_softc *sc, 1265 struct pq3etsec_rxqueue *rxq, 1266 volatile struct rxbd *rxbd, 1267 size_t count) 1268 { 1269 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1270 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1271 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1272 } 1273 1274 static void 1275 pq3etsec_txq_desc_presync( 1276 struct pq3etsec_softc *sc, 1277 struct pq3etsec_txqueue *txq, 1278 volatile struct txbd *txbd, 1279 size_t count) 1280 { 1281 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1282 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1283 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1284 } 1285 1286 static void 1287 pq3etsec_txq_desc_postsync( 1288 struct pq3etsec_softc *sc, 1289 struct pq3etsec_txqueue *txq, 1290 volatile struct txbd *txbd, 1291 size_t count) 1292 { 1293 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1294 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1295 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1296 } 1297 1298 static bus_dmamap_t 1299 pq3etsec_mapcache_get( 1300 struct pq3etsec_softc *sc, 1301 struct pq3etsec_mapcache *dmc) 1302 { 1303 KASSERT(dmc->dmc_nmaps > 0); 1304 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1305 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1306 } 1307 1308 static void 1309 pq3etsec_mapcache_put( 1310 struct pq3etsec_softc *sc, 1311 struct pq3etsec_mapcache *dmc, 1312 bus_dmamap_t map) 1313 { 1314 KASSERT(map != NULL); 1315 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1316 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1317 } 1318 1319 static void 1320 pq3etsec_mapcache_destroy( 1321 struct pq3etsec_softc *sc, 1322 struct pq3etsec_mapcache *dmc) 1323 { 1324 const size_t dmc_size = 1325 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1326 1327 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1328 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1329 } 1330 kmem_intr_free(dmc, dmc_size); 1331 } 1332 1333 static int 1334 pq3etsec_mapcache_create( 1335 struct pq3etsec_softc *sc, 1336 struct pq3etsec_mapcache **dmc_p, 1337 size_t maxmaps, 1338 size_t maxmapsize, 1339 size_t maxseg) 1340 { 1341 const size_t dmc_size = 1342 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1343 struct pq3etsec_mapcache * const dmc = 1344 kmem_intr_zalloc(dmc_size, KM_NOSLEEP); 1345 1346 dmc->dmc_maxmaps = maxmaps; 1347 dmc->dmc_nmaps = maxmaps; 1348 dmc->dmc_maxmapsize = maxmapsize; 1349 dmc->dmc_maxseg = maxseg; 1350 1351 for (u_int i = 0; i < maxmaps; i++) { 1352 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1353 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1354 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1355 if (error) { 1356 aprint_error_dev(sc->sc_dev, 1357 "failed to creat dma map cache " 1358 "entry %u of %zu: %d\n", 1359 i, maxmaps, error); 1360 while (i-- > 0) { 1361 bus_dmamap_destroy(sc->sc_dmat, 1362 dmc->dmc_maps[i]); 1363 } 1364 kmem_intr_free(dmc, dmc_size); 1365 return error; 1366 } 1367 KASSERT(dmc->dmc_maps[i] != NULL); 1368 } 1369 1370 *dmc_p = dmc; 1371 1372 return 0; 1373 } 1374 1375 #if 0 1376 static void 1377 pq3etsec_dmamem_free( 1378 bus_dma_tag_t dmat, 1379 size_t map_size, 1380 bus_dma_segment_t *seg, 1381 bus_dmamap_t map, 1382 void *kvap) 1383 { 1384 bus_dmamap_destroy(dmat, map); 1385 bus_dmamem_unmap(dmat, kvap, map_size); 1386 bus_dmamem_free(dmat, seg, 1); 1387 } 1388 #endif 1389 1390 static int 1391 pq3etsec_dmamem_alloc( 1392 bus_dma_tag_t dmat, 1393 size_t map_size, 1394 bus_dma_segment_t *seg, 1395 bus_dmamap_t *map, 1396 void **kvap) 1397 { 1398 int error; 1399 int nseg; 1400 1401 *kvap = NULL; 1402 *map = NULL; 1403 1404 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1405 seg, 1, &nseg, 0); 1406 if (error) 1407 return error; 1408 1409 KASSERT(nseg == 1); 1410 1411 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1412 BUS_DMA_COHERENT); 1413 if (error == 0) { 1414 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1415 map); 1416 if (error == 0) { 1417 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1418 NULL, 0); 1419 if (error == 0) 1420 return 0; 1421 bus_dmamap_destroy(dmat, *map); 1422 *map = NULL; 1423 } 1424 bus_dmamem_unmap(dmat, *kvap, map_size); 1425 *kvap = NULL; 1426 } 1427 bus_dmamem_free(dmat, seg, nseg); 1428 return 0; 1429 } 1430 1431 static struct mbuf * 1432 pq3etsec_rx_buf_alloc( 1433 struct pq3etsec_softc *sc) 1434 { 1435 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1436 if (m == NULL) { 1437 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1438 return NULL; 1439 } 1440 MCLGET(m, M_DONTWAIT); 1441 if ((m->m_flags & M_EXT) == 0) { 1442 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1443 m_freem(m); 1444 return NULL; 1445 } 1446 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1447 1448 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1449 if (map == NULL) { 1450 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1451 m_freem(m); 1452 return NULL; 1453 } 1454 M_SETCTX(m, map); 1455 m->m_len = m->m_pkthdr.len = MCLBYTES; 1456 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1457 BUS_DMA_READ | BUS_DMA_NOWAIT); 1458 if (error) { 1459 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1460 error); 1461 M_SETCTX(m, NULL); 1462 m_freem(m); 1463 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1464 return NULL; 1465 } 1466 KASSERT(map->dm_mapsize == MCLBYTES); 1467 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1468 BUS_DMASYNC_PREREAD); 1469 1470 return m; 1471 } 1472 1473 static void 1474 pq3etsec_rx_map_unload( 1475 struct pq3etsec_softc *sc, 1476 struct mbuf *m) 1477 { 1478 KASSERT(m); 1479 for (; m != NULL; m = m->m_next) { 1480 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1481 KASSERT(map); 1482 KASSERT(map->dm_mapsize == MCLBYTES); 1483 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1484 BUS_DMASYNC_POSTREAD); 1485 bus_dmamap_unload(sc->sc_dmat, map); 1486 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1487 M_SETCTX(m, NULL); 1488 } 1489 } 1490 1491 static bool 1492 pq3etsec_rxq_produce( 1493 struct pq3etsec_softc *sc, 1494 struct pq3etsec_rxqueue *rxq) 1495 { 1496 volatile struct rxbd *producer = rxq->rxq_producer; 1497 #if 0 1498 size_t inuse = rxq->rxq_inuse; 1499 #endif 1500 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1501 struct mbuf *m; 1502 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1503 if (m == NULL) { 1504 m = pq3etsec_rx_buf_alloc(sc); 1505 if (m == NULL) { 1506 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1507 break; 1508 } 1509 } 1510 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1511 KASSERT(map); 1512 1513 #ifdef ETSEC_DEBUG 1514 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1515 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1516 #endif 1517 1518 /* rxbd_len is write-only by the ETSEC */ 1519 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1520 membar_producer(); 1521 producer->rxbd_flags |= RXBD_E; 1522 if (__predict_false(rxq->rxq_mhead == NULL)) { 1523 KASSERT(producer == rxq->rxq_consumer); 1524 rxq->rxq_mconsumer = m; 1525 } 1526 *rxq->rxq_mtail = m; 1527 rxq->rxq_mtail = &m->m_next; 1528 m->m_len = MCLBYTES; 1529 m->m_next = NULL; 1530 rxq->rxq_inuse++; 1531 if (++producer == rxq->rxq_last) { 1532 membar_producer(); 1533 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1534 rxq->rxq_last - rxq->rxq_producer); 1535 producer = rxq->rxq_producer = rxq->rxq_first; 1536 } 1537 } 1538 if (producer != rxq->rxq_producer) { 1539 membar_producer(); 1540 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1541 producer - rxq->rxq_producer); 1542 rxq->rxq_producer = producer; 1543 } 1544 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1545 if (qhlt) { 1546 KASSERT(qhlt & rxq->rxq_qmask); 1547 sc->sc_ev_rx_stall.ev_count++; 1548 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1549 } 1550 #if 0 1551 aprint_normal_dev(sc->sc_dev, 1552 "%s: buffers inuse went from %zu to %zu\n", 1553 __func__, inuse, rxq->rxq_inuse); 1554 #endif 1555 return true; 1556 } 1557 1558 static bool 1559 pq3etsec_rx_offload( 1560 struct pq3etsec_softc *sc, 1561 struct mbuf *m, 1562 const struct rxfcb *fcb) 1563 { 1564 if (fcb->rxfcb_flags & RXFCB_VLN) { 1565 vlan_set_tag(m, fcb->rxfcb_vlctl); 1566 } 1567 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1568 || (fcb->rxfcb_flags & (RXFCB_CIP | RXFCB_CTU)) == 0) 1569 return true; 1570 int csum_flags = 0; 1571 if ((fcb->rxfcb_flags & (RXFCB_IP6 | RXFCB_CIP)) == RXFCB_CIP) { 1572 csum_flags |= M_CSUM_IPv4; 1573 if (fcb->rxfcb_flags & RXFCB_EIP) 1574 csum_flags |= M_CSUM_IPv4_BAD; 1575 } 1576 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1577 int ipv_flags; 1578 if (fcb->rxfcb_flags & RXFCB_IP6) 1579 ipv_flags = M_CSUM_TCPv6 | M_CSUM_UDPv6; 1580 else 1581 ipv_flags = M_CSUM_TCPv4 | M_CSUM_UDPv4; 1582 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1583 csum_flags |= (M_CSUM_TCPv4 |M_CSUM_TCPv6) & ipv_flags; 1584 } else { 1585 csum_flags |= (M_CSUM_UDPv4 |M_CSUM_UDPv6) & ipv_flags; 1586 } 1587 if (fcb->rxfcb_flags & RXFCB_ETU) 1588 csum_flags |= M_CSUM_TCP_UDP_BAD; 1589 } 1590 1591 m->m_pkthdr.csum_flags = csum_flags; 1592 return true; 1593 } 1594 1595 static void 1596 pq3etsec_rx_input( 1597 struct pq3etsec_softc *sc, 1598 struct mbuf *m, 1599 uint16_t rxbd_flags) 1600 { 1601 struct ifnet * const ifp = &sc->sc_if; 1602 1603 pq3etsec_rx_map_unload(sc, m); 1604 1605 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1606 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1607 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1608 return; 1609 } 1610 m_adj(m, sc->sc_rx_adjlen); 1611 1612 if (rxbd_flags & RXBD_M) 1613 m->m_flags |= M_PROMISC; 1614 if (rxbd_flags & RXBD_BC) 1615 m->m_flags |= M_BCAST; 1616 if (rxbd_flags & RXBD_MC) 1617 m->m_flags |= M_MCAST; 1618 m->m_flags |= M_HASFCS; 1619 m_set_rcvif(m, &sc->sc_if); 1620 1621 /* 1622 * Let's give it to the network subsystm to deal with. 1623 */ 1624 if_percpuq_enqueue(ifp->if_percpuq, m); 1625 } 1626 1627 static void 1628 pq3etsec_rxq_consume( 1629 struct pq3etsec_softc *sc, 1630 struct pq3etsec_rxqueue *rxq) 1631 { 1632 struct ifnet * const ifp = &sc->sc_if; 1633 volatile struct rxbd *consumer = rxq->rxq_consumer; 1634 size_t rxconsumed = 0; 1635 1636 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1637 1638 for (;;) { 1639 if (consumer == rxq->rxq_producer) { 1640 rxq->rxq_consumer = consumer; 1641 rxq->rxq_inuse -= rxconsumed; 1642 KASSERT(rxq->rxq_inuse == 0); 1643 return; 1644 } 1645 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1646 const uint16_t rxbd_flags = consumer->rxbd_flags; 1647 if (rxbd_flags & RXBD_E) { 1648 rxq->rxq_consumer = consumer; 1649 rxq->rxq_inuse -= rxconsumed; 1650 return; 1651 } 1652 KASSERT(rxq->rxq_mconsumer != NULL); 1653 #ifdef ETSEC_DEBUG 1654 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1655 #endif 1656 #if 0 1657 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1658 __func__, 1659 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1660 mtod(rxq->rxq_mconsumer, int *)[0], 1661 mtod(rxq->rxq_mconsumer, int *)[1], 1662 mtod(rxq->rxq_mconsumer, int *)[2], 1663 mtod(rxq->rxq_mconsumer, int *)[3]); 1664 #endif 1665 /* 1666 * We own this packet again. Clear all flags except wrap. 1667 */ 1668 rxconsumed++; 1669 consumer->rxbd_flags = rxbd_flags & (RXBD_W | RXBD_I); 1670 1671 /* 1672 * If this descriptor has the LAST bit set and no errors, 1673 * it's a valid input packet. 1674 */ 1675 if ((rxbd_flags & (RXBD_L | RXBD_ERRORS)) == RXBD_L) { 1676 size_t rxbd_len = consumer->rxbd_len; 1677 struct mbuf *m = rxq->rxq_mhead; 1678 struct mbuf *m_last = rxq->rxq_mconsumer; 1679 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1680 rxq->rxq_mtail = &rxq->rxq_mhead; 1681 rxq->rxq_mconsumer = rxq->rxq_mhead; 1682 m_last->m_next = NULL; 1683 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1684 m->m_pkthdr.len = rxbd_len; 1685 pq3etsec_rx_input(sc, m, rxbd_flags); 1686 } else if (rxbd_flags & RXBD_L) { 1687 KASSERT(rxbd_flags & RXBD_ERRORS); 1688 struct mbuf *m; 1689 /* 1690 * We encountered an error, take the mbufs and add 1691 * then to the rx bufcache so we can reuse them. 1692 */ 1693 if_statinc(ifp, if_ierrors); 1694 for (m = rxq->rxq_mhead; 1695 m != rxq->rxq_mconsumer; 1696 m = m->m_next) { 1697 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1698 } 1699 m = rxq->rxq_mconsumer; 1700 if ((rxq->rxq_mhead = m->m_next) == NULL) 1701 rxq->rxq_mtail = &rxq->rxq_mhead; 1702 rxq->rxq_mconsumer = m->m_next; 1703 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1704 } else { 1705 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1706 } 1707 #ifdef ETSEC_DEBUG 1708 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1709 #endif 1710 1711 /* 1712 * Wrap at the last entry! 1713 */ 1714 if (rxbd_flags & RXBD_W) { 1715 KASSERT(consumer + 1 == rxq->rxq_last); 1716 consumer = rxq->rxq_first; 1717 } else { 1718 consumer++; 1719 } 1720 #ifdef ETSEC_DEBUG 1721 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1722 #endif 1723 } 1724 1725 if (rxconsumed != 0) 1726 rnd_add_uint32(&sc->rnd_source, rxconsumed); 1727 } 1728 1729 static void 1730 pq3etsec_rxq_purge( 1731 struct pq3etsec_softc *sc, 1732 struct pq3etsec_rxqueue *rxq, 1733 bool discard) 1734 { 1735 struct mbuf *m; 1736 1737 if ((m = rxq->rxq_mhead) != NULL) { 1738 #ifdef ETSEC_DEBUG 1739 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1740 #endif 1741 1742 if (discard) { 1743 pq3etsec_rx_map_unload(sc, m); 1744 m_freem(m); 1745 } else { 1746 while (m != NULL) { 1747 struct mbuf *m0 = m->m_next; 1748 m->m_next = NULL; 1749 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1750 m = m0; 1751 } 1752 } 1753 } 1754 1755 rxq->rxq_mconsumer = NULL; 1756 rxq->rxq_mhead = NULL; 1757 rxq->rxq_mtail = &rxq->rxq_mhead; 1758 rxq->rxq_inuse = 0; 1759 } 1760 1761 static void 1762 pq3etsec_rxq_reset( 1763 struct pq3etsec_softc *sc, 1764 struct pq3etsec_rxqueue *rxq) 1765 { 1766 /* 1767 * sync all the descriptors 1768 */ 1769 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1770 rxq->rxq_last - rxq->rxq_first); 1771 1772 /* 1773 * Make sure we own all descriptors in the ring. 1774 */ 1775 volatile struct rxbd *rxbd; 1776 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1777 rxbd->rxbd_flags = RXBD_I; 1778 } 1779 1780 /* 1781 * Last descriptor has the wrap flag. 1782 */ 1783 rxbd->rxbd_flags = RXBD_W | RXBD_I; 1784 1785 /* 1786 * Reset the producer consumer indexes. 1787 */ 1788 rxq->rxq_consumer = rxq->rxq_first; 1789 rxq->rxq_producer = rxq->rxq_first; 1790 rxq->rxq_inuse = 0; 1791 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1792 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1793 1794 sc->sc_imask |= IEVENT_RXF | IEVENT_BSY; 1795 1796 /* 1797 * Restart the transmit at the first descriptor 1798 */ 1799 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1800 } 1801 1802 static int 1803 pq3etsec_rxq_attach( 1804 struct pq3etsec_softc *sc, 1805 struct pq3etsec_rxqueue *rxq, 1806 u_int qno) 1807 { 1808 size_t map_size = PAGE_SIZE; 1809 size_t desc_count = map_size / sizeof(struct rxbd); 1810 int error; 1811 void *descs; 1812 1813 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1814 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1815 if (error) 1816 return error; 1817 1818 memset(descs, 0, map_size); 1819 rxq->rxq_first = descs; 1820 rxq->rxq_last = rxq->rxq_first + desc_count; 1821 rxq->rxq_consumer = descs; 1822 rxq->rxq_producer = descs; 1823 1824 pq3etsec_rxq_purge(sc, rxq, true); 1825 pq3etsec_rxq_reset(sc, rxq); 1826 1827 rxq->rxq_reg_rbase = RBASEn(qno); 1828 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1829 1830 return 0; 1831 } 1832 1833 static bool 1834 pq3etsec_txq_active_p( 1835 struct pq3etsec_softc * const sc, 1836 struct pq3etsec_txqueue *txq) 1837 { 1838 return !IF_IS_EMPTY(&txq->txq_mbufs); 1839 } 1840 1841 static bool 1842 pq3etsec_txq_fillable_p( 1843 struct pq3etsec_softc * const sc, 1844 struct pq3etsec_txqueue *txq) 1845 { 1846 return txq->txq_free >= txq->txq_threshold; 1847 } 1848 1849 static int 1850 pq3etsec_txq_attach( 1851 struct pq3etsec_softc *sc, 1852 struct pq3etsec_txqueue *txq, 1853 u_int qno) 1854 { 1855 size_t map_size = PAGE_SIZE; 1856 size_t desc_count = map_size / sizeof(struct txbd); 1857 int error; 1858 void *descs; 1859 1860 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1861 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1862 if (error) 1863 return error; 1864 1865 memset(descs, 0, map_size); 1866 txq->txq_first = descs; 1867 txq->txq_last = txq->txq_first + desc_count; 1868 txq->txq_consumer = descs; 1869 txq->txq_producer = descs; 1870 1871 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1872 1873 txq->txq_reg_tbase = TBASEn(qno); 1874 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1875 1876 pq3etsec_txq_reset(sc, txq); 1877 1878 return 0; 1879 } 1880 1881 static int 1882 pq3etsec_txq_map_load( 1883 struct pq3etsec_softc *sc, 1884 struct pq3etsec_txqueue *txq, 1885 struct mbuf *m) 1886 { 1887 bus_dmamap_t map; 1888 int error; 1889 1890 map = M_GETCTX(m, bus_dmamap_t); 1891 if (map != NULL) 1892 return 0; 1893 1894 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1895 if (map == NULL) 1896 return ENOMEM; 1897 1898 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1899 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1900 if (error) 1901 return error; 1902 1903 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1904 BUS_DMASYNC_PREWRITE); 1905 M_SETCTX(m, map); 1906 return 0; 1907 } 1908 1909 static void 1910 pq3etsec_txq_map_unload( 1911 struct pq3etsec_softc *sc, 1912 struct pq3etsec_txqueue *txq, 1913 struct mbuf *m) 1914 { 1915 KASSERT(m); 1916 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1917 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1918 BUS_DMASYNC_POSTWRITE); 1919 bus_dmamap_unload(sc->sc_dmat, map); 1920 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1921 } 1922 1923 static bool 1924 pq3etsec_txq_produce( 1925 struct pq3etsec_softc *sc, 1926 struct pq3etsec_txqueue *txq, 1927 struct mbuf *m) 1928 { 1929 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1930 1931 if (map->dm_nsegs > txq->txq_free) 1932 return false; 1933 1934 /* 1935 * TCP Offload flag must be set in the first descriptor. 1936 */ 1937 volatile struct txbd *producer = txq->txq_producer; 1938 uint16_t last_flags = TXBD_L; 1939 uint16_t first_flags = TXBD_R 1940 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1941 1942 /* 1943 * If we've produced enough descriptors without consuming any 1944 * we need to ask for an interrupt to reclaim some. 1945 */ 1946 txq->txq_lastintr += map->dm_nsegs; 1947 if (ETSEC_IC_TX_ENABLED(sc) 1948 || txq->txq_lastintr >= txq->txq_threshold 1949 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1950 txq->txq_lastintr = 0; 1951 last_flags |= TXBD_I; 1952 } 1953 1954 #ifdef ETSEC_DEBUG 1955 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1956 #endif 1957 KASSERT(producer != txq->txq_last); 1958 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1959 producer->txbd_len = map->dm_segs[0].ds_len; 1960 1961 if (map->dm_nsegs > 1) { 1962 volatile struct txbd *start = producer + 1; 1963 size_t count = map->dm_nsegs - 1; 1964 for (u_int i = 1; i < map->dm_nsegs; i++) { 1965 if (__predict_false(++producer == txq->txq_last)) { 1966 producer = txq->txq_first; 1967 if (start < txq->txq_last) { 1968 pq3etsec_txq_desc_presync(sc, txq, 1969 start, txq->txq_last - start); 1970 count -= txq->txq_last - start; 1971 } 1972 start = txq->txq_first; 1973 } 1974 #ifdef ETSEC_DEBUG 1975 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1976 #endif 1977 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1978 producer->txbd_len = map->dm_segs[i].ds_len; 1979 producer->txbd_flags = TXBD_R 1980 | (producer->txbd_flags & TXBD_W) 1981 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1982 #if 0 1983 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1984 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1985 #endif 1986 } 1987 pq3etsec_txq_desc_presync(sc, txq, start, count); 1988 } else { 1989 first_flags |= last_flags; 1990 } 1991 1992 membar_producer(); 1993 txq->txq_producer->txbd_flags = 1994 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1995 #if 0 1996 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1997 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1998 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1999 #endif 2000 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 2001 2002 /* 2003 * Reduce free count by the number of segments we consumed. 2004 */ 2005 txq->txq_free -= map->dm_nsegs; 2006 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 2007 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 2008 KASSERT(producer->txbd_flags & TXBD_L); 2009 #ifdef ETSEC_DEBUG 2010 txq->txq_lmbufs[producer - txq->txq_first] = m; 2011 #endif 2012 2013 #if 0 2014 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 2015 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 2016 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 2017 #endif 2018 2019 if (++producer == txq->txq_last) 2020 txq->txq_producer = txq->txq_first; 2021 else 2022 txq->txq_producer = producer; 2023 IF_ENQUEUE(&txq->txq_mbufs, m); 2024 2025 /* 2026 * Restart the transmitter. 2027 */ 2028 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 2029 2030 return true; 2031 } 2032 2033 static void 2034 pq3etsec_tx_offload( 2035 struct pq3etsec_softc *sc, 2036 struct pq3etsec_txqueue *txq, 2037 struct mbuf **mp) 2038 { 2039 struct mbuf *m = *mp; 2040 u_int csum_flags = m->m_pkthdr.csum_flags; 2041 bool have_vtag; 2042 uint16_t vtag; 2043 2044 KASSERT(m->m_flags & M_PKTHDR); 2045 2046 have_vtag = vlan_has_tag(m); 2047 vtag = (have_vtag) ? vlan_get_tag(m) : 0; 2048 2049 /* 2050 * Let see if we are doing any offload first. 2051 */ 2052 if (csum_flags == 0 && !have_vtag) { 2053 m->m_flags &= ~M_HASFCB; 2054 return; 2055 } 2056 2057 uint16_t flags = 0; 2058 if (csum_flags & M_CSUM_IP) { 2059 flags |= TXFCB_IP 2060 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 2061 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 2062 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 2063 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 2064 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 2065 } 2066 if (have_vtag) { 2067 flags |= TXFCB_VLN; 2068 } 2069 if (flags == 0) { 2070 m->m_flags &= ~M_HASFCB; 2071 return; 2072 } 2073 2074 struct txfcb fcb; 2075 fcb.txfcb_flags = flags; 2076 if (csum_flags & M_CSUM_IPv4) 2077 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2078 else 2079 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2080 fcb.txfcb_l3os = ETHER_HDR_LEN; 2081 fcb.txfcb_phcs = 0; 2082 fcb.txfcb_vlctl = vtag; 2083 2084 #if 0 2085 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 2086 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 2087 fcb.txfcb_phcs, fcb.txfcb_vlctl); 2088 #endif 2089 2090 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 2091 m->m_data -= sizeof(fcb); 2092 m->m_len += sizeof(fcb); 2093 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 2094 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 2095 m->m_data = m->m_pktdat; 2096 m->m_len += sizeof(fcb); 2097 } else { 2098 struct mbuf *mn; 2099 MGET(mn, M_DONTWAIT, m->m_type); 2100 if (mn == NULL) { 2101 if (csum_flags & M_CSUM_IP4) { 2102 #ifdef INET 2103 in_undefer_cksum(m, ETHER_HDR_LEN, 2104 csum_flags & M_CSUM_IP4); 2105 #else 2106 panic("%s: impossible M_CSUM flags %#x", 2107 device_xname(sc->sc_dev), csum_flags); 2108 #endif 2109 } else if (csum_flags & M_CSUM_IP6) { 2110 #ifdef INET6 2111 in6_undefer_cksum(m, ETHER_HDR_LEN, 2112 csum_flags & M_CSUM_IP6); 2113 #else 2114 panic("%s: impossible M_CSUM flags %#x", 2115 device_xname(sc->sc_dev), csum_flags); 2116 #endif 2117 } 2118 2119 m->m_flags &= ~M_HASFCB; 2120 return; 2121 } 2122 2123 m_move_pkthdr(mn, m); 2124 mn->m_next = m; 2125 m = mn; 2126 m_align(m, sizeof(fcb)); 2127 m->m_len = sizeof(fcb); 2128 *mp = m; 2129 } 2130 m->m_pkthdr.len += sizeof(fcb); 2131 m->m_flags |= M_HASFCB; 2132 *mtod(m, struct txfcb *) = fcb; 2133 return; 2134 } 2135 2136 static bool 2137 pq3etsec_txq_enqueue( 2138 struct pq3etsec_softc *sc, 2139 struct pq3etsec_txqueue *txq) 2140 { 2141 for (;;) { 2142 if (IF_QFULL(&txq->txq_mbufs)) 2143 return false; 2144 struct mbuf *m = txq->txq_next; 2145 if (m == NULL) { 2146 int s = splnet(); 2147 IFQ_DEQUEUE(&sc->sc_if.if_snd, m); 2148 splx(s); 2149 if (m == NULL) 2150 return true; 2151 M_SETCTX(m, NULL); 2152 pq3etsec_tx_offload(sc, txq, &m); 2153 } else { 2154 txq->txq_next = NULL; 2155 } 2156 int error = pq3etsec_txq_map_load(sc, txq, m); 2157 if (error) { 2158 aprint_error_dev(sc->sc_dev, 2159 "discarded packet due to " 2160 "dmamap load failure: %d\n", error); 2161 m_freem(m); 2162 continue; 2163 } 2164 KASSERT(txq->txq_next == NULL); 2165 if (!pq3etsec_txq_produce(sc, txq, m)) { 2166 txq->txq_next = m; 2167 return false; 2168 } 2169 KASSERT(txq->txq_next == NULL); 2170 } 2171 } 2172 2173 static bool 2174 pq3etsec_txq_consume( 2175 struct pq3etsec_softc *sc, 2176 struct pq3etsec_txqueue *txq) 2177 { 2178 struct ifnet * const ifp = &sc->sc_if; 2179 volatile struct txbd *consumer = txq->txq_consumer; 2180 size_t txfree = 0; 2181 2182 #if 0 2183 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 2184 #endif 2185 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 2186 2187 for (;;) { 2188 if (consumer == txq->txq_producer) { 2189 txq->txq_consumer = consumer; 2190 txq->txq_free += txfree; 2191 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2192 #if 0 2193 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2194 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2195 #endif 2196 KASSERT(txq->txq_lastintr == 0); 2197 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2198 return true; 2199 } 2200 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2201 const uint16_t txbd_flags = consumer->txbd_flags; 2202 if (txbd_flags & TXBD_R) { 2203 txq->txq_consumer = consumer; 2204 txq->txq_free += txfree; 2205 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2206 #if 0 2207 printf("%s: freed %zu descriptors\n", 2208 __func__, txfree); 2209 #endif 2210 return pq3etsec_txq_fillable_p(sc, txq); 2211 } 2212 2213 /* 2214 * If this is the last descriptor in the chain, get the 2215 * mbuf, free its dmamap, and free the mbuf chain itself. 2216 */ 2217 if (txbd_flags & TXBD_L) { 2218 struct mbuf *m; 2219 2220 IF_DEQUEUE(&txq->txq_mbufs, m); 2221 #ifdef ETSEC_DEBUG 2222 KASSERTMSG( 2223 m == txq->txq_lmbufs[consumer-txq->txq_first], 2224 "%s: %p [%u]: flags %#x m (%p) != %p (%p)", 2225 __func__, consumer, consumer - txq->txq_first, 2226 txbd_flags, m, 2227 &txq->txq_lmbufs[consumer-txq->txq_first], 2228 txq->txq_lmbufs[consumer-txq->txq_first]); 2229 #endif 2230 KASSERT(m); 2231 pq3etsec_txq_map_unload(sc, txq, m); 2232 #if 0 2233 printf("%s: mbuf %p: consumed a %u byte packet\n", 2234 __func__, m, m->m_pkthdr.len); 2235 #endif 2236 if (m->m_flags & M_HASFCB) 2237 m_adj(m, sizeof(struct txfcb)); 2238 bpf_mtap(ifp, m, BPF_D_OUT); 2239 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2240 if_statinc_ref(nsr, if_opackets); 2241 if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len); 2242 if (m->m_flags & M_MCAST) 2243 if_statinc_ref(nsr, if_omcasts); 2244 if (txbd_flags & TXBD_ERRORS) 2245 if_statinc_ref(nsr, if_oerrors); 2246 IF_STAT_PUTREF(ifp); 2247 m_freem(m); 2248 #ifdef ETSEC_DEBUG 2249 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2250 #endif 2251 } else { 2252 #ifdef ETSEC_DEBUG 2253 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2254 #endif 2255 } 2256 2257 /* 2258 * We own this packet again. Clear all flags except wrap. 2259 */ 2260 txfree++; 2261 //consumer->txbd_flags = txbd_flags & TXBD_W; 2262 2263 /* 2264 * Wrap at the last entry! 2265 */ 2266 if (txbd_flags & TXBD_W) { 2267 KASSERT(consumer + 1 == txq->txq_last); 2268 consumer = txq->txq_first; 2269 } else { 2270 consumer++; 2271 KASSERT(consumer < txq->txq_last); 2272 } 2273 } 2274 2275 if (txfree != 0) 2276 rnd_add_uint32(&sc->rnd_source, txfree); 2277 } 2278 2279 static void 2280 pq3etsec_txq_purge( 2281 struct pq3etsec_softc *sc, 2282 struct pq3etsec_txqueue *txq) 2283 { 2284 struct mbuf *m; 2285 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2286 2287 for (;;) { 2288 IF_DEQUEUE(&txq->txq_mbufs, m); 2289 if (m == NULL) 2290 break; 2291 pq3etsec_txq_map_unload(sc, txq, m); 2292 m_freem(m); 2293 } 2294 if ((m = txq->txq_next) != NULL) { 2295 txq->txq_next = NULL; 2296 pq3etsec_txq_map_unload(sc, txq, m); 2297 m_freem(m); 2298 } 2299 #ifdef ETSEC_DEBUG 2300 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2301 #endif 2302 } 2303 2304 static void 2305 pq3etsec_txq_reset( 2306 struct pq3etsec_softc *sc, 2307 struct pq3etsec_txqueue *txq) 2308 { 2309 /* 2310 * sync all the descriptors 2311 */ 2312 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2313 txq->txq_last - txq->txq_first); 2314 2315 /* 2316 * Make sure we own all descriptors in the ring. 2317 */ 2318 volatile struct txbd *txbd; 2319 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2320 txbd->txbd_flags = 0; 2321 } 2322 2323 /* 2324 * Last descriptor has the wrap flag. 2325 */ 2326 txbd->txbd_flags = TXBD_W; 2327 2328 /* 2329 * Reset the producer consumer indexes. 2330 */ 2331 txq->txq_consumer = txq->txq_first; 2332 txq->txq_producer = txq->txq_first; 2333 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2334 txq->txq_threshold = txq->txq_free / 2; 2335 txq->txq_lastintr = 0; 2336 2337 /* 2338 * What do we want to get interrupted on? 2339 */ 2340 sc->sc_imask |= IEVENT_TXF | IEVENT_TXE; 2341 2342 /* 2343 * Restart the transmit at the first descriptor 2344 */ 2345 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2346 } 2347 2348 static void 2349 pq3etsec_ifstart(struct ifnet *ifp) 2350 { 2351 struct pq3etsec_softc * const sc = ifp->if_softc; 2352 2353 if (__predict_false((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)) { 2354 return; 2355 } 2356 2357 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2358 softint_schedule(sc->sc_soft_ih); 2359 } 2360 2361 static void 2362 pq3etsec_tx_error( 2363 struct pq3etsec_softc * const sc) 2364 { 2365 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2366 2367 pq3etsec_txq_consume(sc, txq); 2368 2369 if (pq3etsec_txq_fillable_p(sc, txq)) 2370 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2371 if (sc->sc_txerrors 2372 & (IEVENT_LC | IEVENT_CRL | IEVENT_XFUN | IEVENT_BABT)) { 2373 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2374 } 2375 2376 if (pq3etsec_txq_active_p(sc, txq)) 2377 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2378 if (!pq3etsec_txq_enqueue(sc, txq)) { 2379 sc->sc_ev_tx_stall.ev_count++; 2380 sc->sc_if.if_flags |= IFF_OACTIVE; 2381 } 2382 2383 sc->sc_txerrors = 0; 2384 } 2385 2386 int 2387 pq3etsec_tx_intr(void *arg) 2388 { 2389 struct pq3etsec_softc * const sc = arg; 2390 2391 mutex_enter(sc->sc_hwlock); 2392 2393 sc->sc_ev_tx_intr.ev_count++; 2394 2395 uint32_t ievent = etsec_read(sc, IEVENT); 2396 ievent &= IEVENT_TXF | IEVENT_TXB; 2397 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2398 2399 #if 0 2400 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2401 __func__, ievent, etsec_read(sc, IMASK)); 2402 #endif 2403 2404 if (ievent == 0) { 2405 mutex_exit(sc->sc_hwlock); 2406 return 0; 2407 } 2408 2409 sc->sc_imask &= ~(IEVENT_TXF | IEVENT_TXB); 2410 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2411 etsec_write(sc, IMASK, sc->sc_imask); 2412 softint_schedule(sc->sc_soft_ih); 2413 2414 mutex_exit(sc->sc_hwlock); 2415 2416 return 1; 2417 } 2418 2419 int 2420 pq3etsec_rx_intr(void *arg) 2421 { 2422 struct pq3etsec_softc * const sc = arg; 2423 2424 mutex_enter(sc->sc_hwlock); 2425 2426 sc->sc_ev_rx_intr.ev_count++; 2427 2428 uint32_t ievent = etsec_read(sc, IEVENT); 2429 ievent &= IEVENT_RXF | IEVENT_RXB; 2430 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2431 if (ievent == 0) { 2432 mutex_exit(sc->sc_hwlock); 2433 return 0; 2434 } 2435 2436 #if 0 2437 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2438 #endif 2439 2440 sc->sc_imask &= ~(IEVENT_RXF | IEVENT_RXB); 2441 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2442 etsec_write(sc, IMASK, sc->sc_imask); 2443 softint_schedule(sc->sc_soft_ih); 2444 2445 mutex_exit(sc->sc_hwlock); 2446 2447 return 1; 2448 } 2449 2450 int 2451 pq3etsec_error_intr(void *arg) 2452 { 2453 struct pq3etsec_softc * const sc = arg; 2454 2455 mutex_enter(sc->sc_hwlock); 2456 2457 sc->sc_ev_error_intr.ev_count++; 2458 2459 for (int rv = 0, soft_flags = 0;; rv = 1) { 2460 uint32_t ievent = etsec_read(sc, IEVENT); 2461 ievent &= ~(IEVENT_RXF | IEVENT_RXB | IEVENT_TXF | IEVENT_TXB); 2462 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2463 if (ievent == 0) { 2464 if (soft_flags) { 2465 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2466 softint_schedule(sc->sc_soft_ih); 2467 } 2468 mutex_exit(sc->sc_hwlock); 2469 return rv; 2470 } 2471 #if 0 2472 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2473 __func__, ievent, etsec_read(sc, IMASK)); 2474 #endif 2475 2476 if (ievent & (IEVENT_GRSC | IEVENT_GTSC)) { 2477 sc->sc_imask &= ~(IEVENT_GRSC | IEVENT_GTSC); 2478 etsec_write(sc, IMASK, sc->sc_imask); 2479 wakeup(sc); 2480 } 2481 if (ievent & (IEVENT_MMRD | IEVENT_MMWR)) { 2482 sc->sc_imask &= ~(IEVENT_MMRD | IEVENT_MMWR); 2483 etsec_write(sc, IMASK, sc->sc_imask); 2484 wakeup(&sc->sc_mii); 2485 } 2486 if (ievent & IEVENT_BSY) { 2487 soft_flags |= SOFT_RXBSY; 2488 sc->sc_imask &= ~IEVENT_BSY; 2489 etsec_write(sc, IMASK, sc->sc_imask); 2490 } 2491 if (ievent & IEVENT_TXE) { 2492 soft_flags |= SOFT_TXERROR; 2493 sc->sc_imask &= ~IEVENT_TXE; 2494 sc->sc_txerrors |= ievent; 2495 } 2496 if (ievent & IEVENT_TXC) { 2497 sc->sc_ev_tx_pause.ev_count++; 2498 } 2499 if (ievent & IEVENT_RXC) { 2500 sc->sc_ev_rx_pause.ev_count++; 2501 } 2502 if (ievent & IEVENT_DPE) { 2503 soft_flags |= SOFT_RESET; 2504 sc->sc_imask &= ~IEVENT_DPE; 2505 etsec_write(sc, IMASK, sc->sc_imask); 2506 } 2507 } 2508 } 2509 2510 void 2511 pq3etsec_soft_intr(void *arg) 2512 { 2513 struct pq3etsec_softc * const sc = arg; 2514 struct ifnet * const ifp = &sc->sc_if; 2515 uint32_t imask = 0; 2516 2517 mutex_enter(sc->sc_lock); 2518 2519 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2520 2521 sc->sc_ev_soft_intr.ev_count++; 2522 2523 if (soft_flags & SOFT_RESET) { 2524 int s = splnet(); 2525 pq3etsec_ifinit(ifp); 2526 splx(s); 2527 soft_flags = 0; 2528 } 2529 2530 if (soft_flags & SOFT_RXBSY) { 2531 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2532 size_t threshold = 5 * rxq->rxq_threshold / 4; 2533 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2534 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2535 } else { 2536 imask |= IEVENT_BSY; 2537 } 2538 aprint_normal_dev(sc->sc_dev, 2539 "increasing receive buffers from %zu to %zu\n", 2540 rxq->rxq_threshold, threshold); 2541 rxq->rxq_threshold = threshold; 2542 } 2543 2544 if ((soft_flags & SOFT_TXINTR) 2545 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2546 /* 2547 * Let's do what we came here for. Consume transmitted 2548 * packets off the transmit ring. 2549 */ 2550 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2551 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2552 sc->sc_ev_tx_stall.ev_count++; 2553 ifp->if_flags |= IFF_OACTIVE; 2554 } else { 2555 ifp->if_flags &= ~IFF_OACTIVE; 2556 } 2557 imask |= IEVENT_TXF; 2558 } 2559 2560 if (soft_flags & (SOFT_RXINTR | SOFT_RXBSY)) { 2561 /* Let's consume */ 2562 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2563 imask |= IEVENT_RXF; 2564 } 2565 2566 if (soft_flags & SOFT_TXERROR) { 2567 pq3etsec_tx_error(sc); 2568 imask |= IEVENT_TXE; 2569 } 2570 2571 if (ifp->if_flags & IFF_RUNNING) { 2572 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2573 mutex_spin_enter(sc->sc_hwlock); 2574 sc->sc_imask |= imask; 2575 etsec_write(sc, IMASK, sc->sc_imask); 2576 mutex_spin_exit(sc->sc_hwlock); 2577 } else { 2578 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2579 } 2580 2581 mutex_exit(sc->sc_lock); 2582 } 2583 2584 static void 2585 pq3etsec_mii_tick(void *arg) 2586 { 2587 struct pq3etsec_softc * const sc = arg; 2588 mutex_enter(sc->sc_lock); 2589 callout_ack(&sc->sc_mii_callout); 2590 sc->sc_ev_mii_ticks.ev_count++; 2591 #ifdef DEBUG 2592 uint64_t now = mftb(); 2593 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2594 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2595 __func__, now - sc->sc_mii_last_tick); 2596 callout_stop(&sc->sc_mii_callout); 2597 } 2598 #endif 2599 mii_tick(&sc->sc_mii); 2600 int s = splnet(); 2601 if (sc->sc_soft_flags & SOFT_RESET) 2602 softint_schedule(sc->sc_soft_ih); 2603 splx(s); 2604 callout_schedule(&sc->sc_mii_callout, hz); 2605 #ifdef DEBUG 2606 sc->sc_mii_last_tick = now; 2607 #endif 2608 mutex_exit(sc->sc_lock); 2609 } 2610 2611 static void 2612 pq3etsec_set_ic_rx(struct pq3etsec_softc *sc) 2613 { 2614 uint32_t reg; 2615 2616 if (ETSEC_IC_RX_ENABLED(sc)) { 2617 reg = RXIC_ICEN; 2618 reg |= RXIC_ICFT_SET(sc->sc_ic_rx_count); 2619 reg |= RXIC_ICTT_SET(sc->sc_ic_rx_time); 2620 } else { 2621 /* Disable RX interrupt coalescing */ 2622 reg = 0; 2623 } 2624 2625 etsec_write(sc, RXIC, reg); 2626 } 2627 2628 static void 2629 pq3etsec_set_ic_tx(struct pq3etsec_softc *sc) 2630 { 2631 uint32_t reg; 2632 2633 if (ETSEC_IC_TX_ENABLED(sc)) { 2634 reg = TXIC_ICEN; 2635 reg |= TXIC_ICFT_SET(sc->sc_ic_tx_count); 2636 reg |= TXIC_ICTT_SET(sc->sc_ic_tx_time); 2637 } else { 2638 /* Disable TX interrupt coalescing */ 2639 reg = 0; 2640 } 2641 2642 etsec_write(sc, TXIC, reg); 2643 } 2644 2645 /* 2646 * sysctl 2647 */ 2648 static int 2649 pq3etsec_sysctl_ic_time_helper(SYSCTLFN_ARGS, int *valuep) 2650 { 2651 struct sysctlnode node = *rnode; 2652 struct pq3etsec_softc *sc = rnode->sysctl_data; 2653 int value = *valuep; 2654 int error; 2655 2656 node.sysctl_data = &value; 2657 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2658 if (error != 0 || newp == NULL) 2659 return error; 2660 2661 if (value < 0 || value > 65535) 2662 return EINVAL; 2663 2664 mutex_enter(sc->sc_lock); 2665 *valuep = value; 2666 if (valuep == &sc->sc_ic_rx_time) 2667 pq3etsec_set_ic_rx(sc); 2668 else 2669 pq3etsec_set_ic_tx(sc); 2670 mutex_exit(sc->sc_lock); 2671 2672 return 0; 2673 } 2674 2675 static int 2676 pq3etsec_sysctl_ic_count_helper(SYSCTLFN_ARGS, int *valuep) 2677 { 2678 struct sysctlnode node = *rnode; 2679 struct pq3etsec_softc *sc = rnode->sysctl_data; 2680 int value = *valuep; 2681 int error; 2682 2683 node.sysctl_data = &value; 2684 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2685 if (error != 0 || newp == NULL) 2686 return error; 2687 2688 if (value < 0 || value > 255) 2689 return EINVAL; 2690 2691 mutex_enter(sc->sc_lock); 2692 *valuep = value; 2693 if (valuep == &sc->sc_ic_rx_count) 2694 pq3etsec_set_ic_rx(sc); 2695 else 2696 pq3etsec_set_ic_tx(sc); 2697 mutex_exit(sc->sc_lock); 2698 2699 return 0; 2700 } 2701 2702 static int 2703 pq3etsec_sysctl_ic_rx_time_helper(SYSCTLFN_ARGS) 2704 { 2705 struct pq3etsec_softc *sc = rnode->sysctl_data; 2706 2707 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2708 &sc->sc_ic_rx_time); 2709 } 2710 2711 static int 2712 pq3etsec_sysctl_ic_rx_count_helper(SYSCTLFN_ARGS) 2713 { 2714 struct pq3etsec_softc *sc = rnode->sysctl_data; 2715 2716 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2717 &sc->sc_ic_rx_count); 2718 } 2719 2720 static int 2721 pq3etsec_sysctl_ic_tx_time_helper(SYSCTLFN_ARGS) 2722 { 2723 struct pq3etsec_softc *sc = rnode->sysctl_data; 2724 2725 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2726 &sc->sc_ic_tx_time); 2727 } 2728 2729 static int 2730 pq3etsec_sysctl_ic_tx_count_helper(SYSCTLFN_ARGS) 2731 { 2732 struct pq3etsec_softc *sc = rnode->sysctl_data; 2733 2734 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2735 &sc->sc_ic_tx_count); 2736 } 2737 2738 static void pq3etsec_sysctl_setup(struct sysctllog **clog, 2739 struct pq3etsec_softc *sc) 2740 { 2741 const struct sysctlnode *cnode, *rnode; 2742 2743 if (sysctl_createv(clog, 0, NULL, &rnode, 2744 CTLFLAG_PERMANENT, 2745 CTLTYPE_NODE, device_xname(sc->sc_dev), 2746 SYSCTL_DESCR("TSEC interface"), 2747 NULL, 0, NULL, 0, 2748 CTL_HW, CTL_CREATE, CTL_EOL) != 0) 2749 goto bad; 2750 2751 if (sysctl_createv(clog, 0, &rnode, &rnode, 2752 CTLFLAG_PERMANENT, 2753 CTLTYPE_NODE, "int_coal", 2754 SYSCTL_DESCR("Interrupts coalescing"), 2755 NULL, 0, NULL, 0, 2756 CTL_CREATE, CTL_EOL) != 0) 2757 goto bad; 2758 2759 if (sysctl_createv(clog, 0, &rnode, &cnode, 2760 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2761 CTLTYPE_INT, "rx_time", 2762 SYSCTL_DESCR("RX time threshold (0-65535)"), 2763 pq3etsec_sysctl_ic_rx_time_helper, 0, (void *)sc, 0, 2764 CTL_CREATE, CTL_EOL) != 0) 2765 goto bad; 2766 2767 if (sysctl_createv(clog, 0, &rnode, &cnode, 2768 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2769 CTLTYPE_INT, "rx_count", 2770 SYSCTL_DESCR("RX frame count threshold (0-255)"), 2771 pq3etsec_sysctl_ic_rx_count_helper, 0, (void *)sc, 0, 2772 CTL_CREATE, CTL_EOL) != 0) 2773 goto bad; 2774 2775 if (sysctl_createv(clog, 0, &rnode, &cnode, 2776 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2777 CTLTYPE_INT, "tx_time", 2778 SYSCTL_DESCR("TX time threshold (0-65535)"), 2779 pq3etsec_sysctl_ic_tx_time_helper, 0, (void *)sc, 0, 2780 CTL_CREATE, CTL_EOL) != 0) 2781 goto bad; 2782 2783 if (sysctl_createv(clog, 0, &rnode, &cnode, 2784 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2785 CTLTYPE_INT, "tx_count", 2786 SYSCTL_DESCR("TX frame count threshold (0-255)"), 2787 pq3etsec_sysctl_ic_tx_count_helper, 0, (void *)sc, 0, 2788 CTL_CREATE, CTL_EOL) != 0) 2789 goto bad; 2790 2791 return; 2792 2793 bad: 2794 aprint_error_dev(sc->sc_dev, "could not attach sysctl nodes\n"); 2795 } 2796
Indexes created Thu Oct 02 14:10:14 GMT 2025