pq3etsec.c revision 1.55
1 /* $NetBSD: pq3etsec.c,v 1.55 2021/06/16 00:21:18 riastradh Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.55 2021/06/16 00:21:18 riastradh Exp $"); 39 40 #ifdef _KERNEL_OPT 41 #include "opt_inet.h" 42 #include "opt_mpc85xx.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_net_mpsafe.h" 45 #endif 46 47 #include <sys/param.h> 48 #include <sys/cpu.h> 49 #include <sys/device.h> 50 #include <sys/mbuf.h> 51 #include <sys/ioctl.h> 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/atomic.h> 58 #include <sys/callout.h> 59 #include <sys/sysctl.h> 60 61 #include <sys/rndsource.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/bpf.h> 68 69 #include <dev/mii/miivar.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/ip.h> 75 #include <netinet/in_offload.h> 76 #endif /* INET */ 77 #ifdef INET6 78 #include <netinet6/in6.h> 79 #include <netinet/ip6.h> 80 #endif 81 #include <netinet6/in6_offload.h> 82 83 #include <powerpc/spr.h> 84 #include <powerpc/booke/spr.h> 85 #include <powerpc/booke/cpuvar.h> 86 #include <powerpc/booke/e500var.h> 87 #include <powerpc/booke/e500reg.h> 88 #include <powerpc/booke/etsecreg.h> 89 90 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 91 92 #define ETSEC_MAXTXMBUFS 30 93 #define ETSEC_NTXSEGS 30 94 #define ETSEC_MAXRXMBUFS 511 95 #define ETSEC_MINRXMBUFS 32 96 #define ETSEC_NRXSEGS 1 97 98 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 99 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx \ 100 | IFCAP_CSUM_UDPv4_Rx \ 101 | IFCAP_CSUM_TCPv6_Rx \ 102 | IFCAP_CSUM_UDPv6_Rx) 103 104 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 105 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx \ 106 | IFCAP_CSUM_UDPv4_Tx \ 107 | IFCAP_CSUM_TCPv6_Tx \ 108 | IFCAP_CSUM_UDPv6_Tx) 109 110 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN | IFCAP_RCTRL_TUCSEN \ 111 | IFCAP_TCTRL_IPCSEN | IFCAP_TCTRL_TUCSEN) 112 113 #define M_CSUM_IP (M_CSUM_CIP | M_CSUM_CTU) 114 #define M_CSUM_IP6 (M_CSUM_TCPv6 | M_CSUM_UDPv6) 115 #define M_CSUM_TUP (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6) 116 #define M_CSUM_UDP (M_CSUM_UDPv4 | M_CSUM_UDPv6) 117 #define M_CSUM_IP4 (M_CSUM_IPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4) 118 #define M_CSUM_CIP (M_CSUM_IPv4) 119 #define M_CSUM_CTU (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6) 120 121 struct pq3etsec_txqueue { 122 bus_dmamap_t txq_descmap; 123 volatile struct txbd *txq_consumer; 124 volatile struct txbd *txq_producer; 125 volatile struct txbd *txq_first; 126 volatile struct txbd *txq_last; 127 struct ifqueue txq_mbufs; 128 struct mbuf *txq_next; 129 #ifdef ETSEC_DEBUG 130 struct mbuf *txq_lmbufs[512]; 131 #endif 132 uint32_t txq_qmask; 133 uint32_t txq_free; 134 uint32_t txq_threshold; 135 uint32_t txq_lastintr; 136 bus_size_t txq_reg_tbase; 137 bus_dma_segment_t txq_descmap_seg; 138 }; 139 140 struct pq3etsec_rxqueue { 141 bus_dmamap_t rxq_descmap; 142 volatile struct rxbd *rxq_consumer; 143 volatile struct rxbd *rxq_producer; 144 volatile struct rxbd *rxq_first; 145 volatile struct rxbd *rxq_last; 146 struct mbuf *rxq_mhead; 147 struct mbuf **rxq_mtail; 148 struct mbuf *rxq_mconsumer; 149 #ifdef ETSEC_DEBUG 150 struct mbuf *rxq_mbufs[512]; 151 #endif 152 uint32_t rxq_qmask; 153 uint32_t rxq_inuse; 154 uint32_t rxq_threshold; 155 bus_size_t rxq_reg_rbase; 156 bus_size_t rxq_reg_rbptr; 157 bus_dma_segment_t rxq_descmap_seg; 158 }; 159 160 struct pq3etsec_mapcache { 161 u_int dmc_nmaps; 162 u_int dmc_maxseg; 163 u_int dmc_maxmaps; 164 u_int dmc_maxmapsize; 165 bus_dmamap_t dmc_maps[0]; 166 }; 167 168 struct pq3etsec_softc { 169 device_t sc_dev; 170 device_t sc_mdio_dev; 171 struct ethercom sc_ec; 172 #define sc_if sc_ec.ec_if 173 struct mii_data sc_mii; 174 bus_space_tag_t sc_bst; 175 bus_space_handle_t sc_bsh; 176 bus_space_handle_t sc_mdio_bsh; 177 bus_dma_tag_t sc_dmat; 178 int sc_phy_addr; 179 prop_dictionary_t sc_intrmap; 180 uint32_t sc_intrmask; 181 182 uint32_t sc_soft_flags; 183 #define SOFT_RESET 0x0001 184 #define SOFT_RXINTR 0x0010 185 #define SOFT_RXBSY 0x0020 186 #define SOFT_TXINTR 0x0100 187 #define SOFT_TXERROR 0x0200 188 189 struct pq3etsec_txqueue sc_txq; 190 struct pq3etsec_rxqueue sc_rxq; 191 uint32_t sc_txerrors; 192 uint32_t sc_rxerrors; 193 194 size_t sc_rx_adjlen; 195 196 /* 197 * Copies of various ETSEC registers. 198 */ 199 uint32_t sc_imask; 200 uint32_t sc_maccfg1; 201 uint32_t sc_maccfg2; 202 uint32_t sc_maxfrm; 203 uint32_t sc_ecntrl; 204 uint32_t sc_dmactrl; 205 uint32_t sc_macstnaddr1; 206 uint32_t sc_macstnaddr2; 207 uint32_t sc_tctrl; 208 uint32_t sc_rctrl; 209 uint32_t sc_gaddr[16]; 210 uint64_t sc_macaddrs[15]; 211 212 void *sc_tx_ih; 213 void *sc_rx_ih; 214 void *sc_error_ih; 215 void *sc_soft_ih; 216 217 kmutex_t *sc_lock; 218 kmutex_t *sc_hwlock; 219 220 struct evcnt sc_ev_tx_stall; 221 struct evcnt sc_ev_tx_intr; 222 struct evcnt sc_ev_rx_stall; 223 struct evcnt sc_ev_rx_intr; 224 struct evcnt sc_ev_error_intr; 225 struct evcnt sc_ev_soft_intr; 226 struct evcnt sc_ev_tx_pause; 227 struct evcnt sc_ev_rx_pause; 228 struct evcnt sc_ev_mii_ticks; 229 230 struct callout sc_mii_callout; 231 uint64_t sc_mii_last_tick; 232 233 struct ifqueue sc_rx_bufcache; 234 struct pq3etsec_mapcache *sc_rx_mapcache; 235 struct pq3etsec_mapcache *sc_tx_mapcache; 236 237 /* Interrupt Coalescing parameters */ 238 int sc_ic_rx_time; 239 int sc_ic_rx_count; 240 int sc_ic_tx_time; 241 int sc_ic_tx_count; 242 243 krndsource_t rnd_source; 244 }; 245 246 #define ETSEC_IC_RX_ENABLED(sc) \ 247 ((sc)->sc_ic_rx_time != 0 && (sc)->sc_ic_rx_count != 0) 248 #define ETSEC_IC_TX_ENABLED(sc) \ 249 ((sc)->sc_ic_tx_time != 0 && (sc)->sc_ic_tx_count != 0) 250 251 struct pq3mdio_softc { 252 device_t mdio_dev; 253 254 kmutex_t *mdio_lock; 255 256 bus_space_tag_t mdio_bst; 257 bus_space_handle_t mdio_bsh; 258 }; 259 260 static int pq3etsec_match(device_t, cfdata_t, void *); 261 static void pq3etsec_attach(device_t, device_t, void *); 262 263 static int pq3mdio_match(device_t, cfdata_t, void *); 264 static void pq3mdio_attach(device_t, device_t, void *); 265 266 static void pq3etsec_ifstart(struct ifnet *); 267 static void pq3etsec_ifwatchdog(struct ifnet *); 268 static int pq3etsec_ifinit(struct ifnet *); 269 static void pq3etsec_ifstop(struct ifnet *, int); 270 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 271 272 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 273 struct pq3etsec_mapcache **, size_t, size_t, size_t); 274 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 275 struct pq3etsec_mapcache *); 276 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 277 struct pq3etsec_mapcache *); 278 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 279 struct pq3etsec_mapcache *, bus_dmamap_t); 280 281 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 282 struct pq3etsec_txqueue *, u_int); 283 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 284 struct pq3etsec_txqueue *); 285 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 286 struct pq3etsec_txqueue *); 287 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 288 struct pq3etsec_txqueue *); 289 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 290 struct pq3etsec_txqueue *, struct mbuf *m); 291 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 292 struct pq3etsec_txqueue *); 293 294 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 295 struct pq3etsec_rxqueue *, u_int); 296 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 297 struct pq3etsec_rxqueue *); 298 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 299 struct pq3etsec_rxqueue *, bool); 300 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 301 struct pq3etsec_rxqueue *); 302 303 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 304 305 static void pq3etsec_mii_tick(void *); 306 static int pq3etsec_rx_intr(void *); 307 static int pq3etsec_tx_intr(void *); 308 static int pq3etsec_error_intr(void *); 309 static void pq3etsec_soft_intr(void *); 310 311 static void pq3etsec_set_ic_rx(struct pq3etsec_softc *); 312 static void pq3etsec_set_ic_tx(struct pq3etsec_softc *); 313 314 static void pq3etsec_sysctl_setup(struct sysctllog **, struct pq3etsec_softc *); 315 316 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 317 pq3etsec_match, pq3etsec_attach, NULL, NULL); 318 319 CFATTACH_DECL_NEW(pq3mdio_tsec, sizeof(struct pq3mdio_softc), 320 pq3mdio_match, pq3mdio_attach, NULL, NULL); 321 322 CFATTACH_DECL_NEW(pq3mdio_cpunode, sizeof(struct pq3mdio_softc), 323 pq3mdio_match, pq3mdio_attach, NULL, NULL); 324 325 static inline uint32_t 326 etsec_mdio_read(struct pq3mdio_softc *mdio, bus_size_t off) 327 { 328 return bus_space_read_4(mdio->mdio_bst, mdio->mdio_bsh, off); 329 } 330 331 static inline void 332 etsec_mdio_write(struct pq3mdio_softc *mdio, bus_size_t off, uint32_t data) 333 { 334 bus_space_write_4(mdio->mdio_bst, mdio->mdio_bsh, off, data); 335 } 336 337 static inline uint32_t 338 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 339 { 340 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 341 } 342 343 static int 344 pq3mdio_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 345 { 346 return strcmp(cf->cf_name, "mdio") == 0; 347 } 348 349 static int 350 pq3mdio_match(device_t parent, cfdata_t cf, void *aux) 351 { 352 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 353 const bool p1025_p = (svr == (SVR_P1025v1 >> 16) 354 || svr == (SVR_P1016v1 >> 16)); 355 356 if (device_is_a(parent, "cpunode")) { 357 if (!p1025_p 358 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 359 return 0; 360 361 return 1; 362 } 363 364 if (device_is_a(parent, "tsec")) { 365 if (p1025_p 366 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 367 return 0; 368 369 return 1; 370 } 371 372 return 0; 373 } 374 375 static void 376 pq3mdio_attach(device_t parent, device_t self, void *aux) 377 { 378 struct pq3mdio_softc * const mdio = device_private(self); 379 struct cpunode_attach_args * const cna = aux; 380 struct cpunode_locators * const cnl = &cna->cna_locs; 381 382 mdio->mdio_dev = self; 383 mdio->mdio_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 384 385 if (device_is_a(parent, "cpunode")) { 386 struct cpunode_softc * const psc = device_private(parent); 387 psc->sc_children |= cna->cna_childmask; 388 389 mdio->mdio_bst = cna->cna_memt; 390 if (bus_space_map(mdio->mdio_bst, cnl->cnl_addr, 391 cnl->cnl_size, 0, &mdio->mdio_bsh) != 0) { 392 aprint_error(": error mapping registers @ %#x\n", 393 cnl->cnl_addr); 394 return; 395 } 396 } else { 397 struct pq3etsec_softc * const sc = device_private(parent); 398 399 KASSERT(device_is_a(parent, "tsec")); 400 KASSERTMSG(cnl->cnl_addr == ETSEC1_BASE 401 || cnl->cnl_addr == ETSEC2_BASE 402 || cnl->cnl_addr == ETSEC3_BASE 403 || cnl->cnl_addr == ETSEC4_BASE, 404 "unknown tsec addr %x", cnl->cnl_addr); 405 406 mdio->mdio_bst = sc->sc_bst; 407 mdio->mdio_bsh = sc->sc_bsh; 408 } 409 410 aprint_normal("\n"); 411 } 412 413 static int 414 pq3mdio_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 415 { 416 struct pq3mdio_softc * const mdio = device_private(self); 417 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 418 419 mutex_enter(mdio->mdio_lock); 420 421 etsec_mdio_write(mdio, MIIMADD, 422 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 423 424 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 425 etsec_mdio_write(mdio, MIIMCOM, MIIMCOM_READ); 426 427 while (etsec_mdio_read(mdio, MIIMIND) != 0) { 428 delay(1); 429 } 430 *val = etsec_mdio_read(mdio, MIIMSTAT) &0xffff; 431 432 if (miimcom == MIIMCOM_SCAN) 433 etsec_mdio_write(mdio, MIIMCOM, miimcom); 434 435 #if 0 436 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 437 __func__, phy, reg, data); 438 #endif 439 mutex_exit(mdio->mdio_lock); 440 return 0; 441 } 442 443 static int 444 pq3mdio_mii_writereg(device_t self, int phy, int reg, uint16_t data) 445 { 446 struct pq3mdio_softc * const mdio = device_private(self); 447 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 448 449 #if 0 450 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 451 __func__, phy, reg, data); 452 #endif 453 454 mutex_enter(mdio->mdio_lock); 455 456 etsec_mdio_write(mdio, MIIMADD, 457 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 458 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 459 etsec_mdio_write(mdio, MIIMCON, data); 460 461 int timo = 1000; /* 1ms */ 462 while ((etsec_mdio_read(mdio, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 463 delay(1); 464 } 465 466 if (miimcom == MIIMCOM_SCAN) 467 etsec_mdio_write(mdio, MIIMCOM, miimcom); 468 469 mutex_exit(mdio->mdio_lock); 470 471 return 0; 472 } 473 474 static inline void 475 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 476 { 477 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 478 } 479 480 static void 481 pq3etsec_mii_statchg(struct ifnet *ifp) 482 { 483 struct pq3etsec_softc * const sc = ifp->if_softc; 484 struct mii_data * const mii = &sc->sc_mii; 485 486 uint32_t maccfg1 = sc->sc_maccfg1; 487 uint32_t maccfg2 = sc->sc_maccfg2; 488 uint32_t ecntrl = sc->sc_ecntrl; 489 490 maccfg1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 491 maccfg2 &= ~(MACCFG2_IFMODE | MACCFG2_FD); 492 493 if (sc->sc_mii.mii_media_active & IFM_FDX) { 494 maccfg2 |= MACCFG2_FD; 495 } 496 497 /* 498 * Now deal with the flow control bits. 499 */ 500 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 501 && (mii->mii_media_active & IFM_ETH_FMASK)) { 502 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 503 maccfg1 |= MACCFG1_RX_FLOW; 504 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 505 maccfg1 |= MACCFG1_TX_FLOW; 506 } 507 508 /* 509 * Now deal with the speed. 510 */ 511 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 512 maccfg2 |= MACCFG2_IFMODE_GMII; 513 } else { 514 maccfg2 |= MACCFG2_IFMODE_MII; 515 ecntrl &= ~ECNTRL_R100M; 516 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 517 ecntrl |= ECNTRL_R100M; 518 } 519 } 520 521 /* 522 * If things are different, re-init things. 523 */ 524 if (maccfg1 != sc->sc_maccfg1 525 || maccfg2 != sc->sc_maccfg2 526 || ecntrl != sc->sc_ecntrl) { 527 if (sc->sc_if.if_flags & IFF_RUNNING) 528 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 529 sc->sc_maccfg1 = maccfg1; 530 sc->sc_maccfg2 = maccfg2; 531 sc->sc_ecntrl = ecntrl; 532 } 533 } 534 535 #if 0 536 static void 537 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 538 { 539 struct pq3etsec_softc * const sc = ifp->if_softc; 540 541 mii_pollstat(&sc->sc_mii); 542 ether_mediastatus(ifp, ifmr); 543 ifmr->ifm_status = sc->sc_mii.mii_media_status; 544 ifmr->ifm_active = sc->sc_mii.mii_media_active; 545 } 546 547 static int 548 pq3etsec_mediachange(struct ifnet *ifp) 549 { 550 struct pq3etsec_softc * const sc = ifp->if_softc; 551 552 if ((ifp->if_flags & IFF_UP) == 0) 553 return 0; 554 555 int rv = mii_mediachg(&sc->sc_mii); 556 return (rv == ENXIO) ? 0 : rv; 557 } 558 #endif 559 560 static int 561 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 562 { 563 564 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 565 return 0; 566 567 return 1; 568 } 569 570 static void 571 pq3etsec_attach(device_t parent, device_t self, void *aux) 572 { 573 struct cpunode_softc * const psc = device_private(parent); 574 struct pq3etsec_softc * const sc = device_private(self); 575 struct mii_data * const mii = &sc->sc_mii; 576 struct cpunode_attach_args * const cna = aux; 577 struct cpunode_locators * const cnl = &cna->cna_locs; 578 cfdata_t cf = device_cfdata(self); 579 int error; 580 581 psc->sc_children |= cna->cna_childmask; 582 sc->sc_dev = self; 583 sc->sc_bst = cna->cna_memt; 584 sc->sc_dmat = &booke_bus_dma_tag; 585 586 /* 587 * Pull out the mdio bus and phy we are supposed to use. 588 */ 589 const int mdio = cf->cf_loc[CPUNODECF_MDIO]; 590 const int phy = cf->cf_loc[CPUNODECF_PHY]; 591 if (mdio != CPUNODECF_MDIO_DEFAULT) 592 aprint_normal(" mdio %d", mdio); 593 594 /* 595 * See if the phy is in the config file... 596 */ 597 if (phy != CPUNODECF_PHY_DEFAULT) { 598 sc->sc_phy_addr = phy; 599 } else { 600 unsigned char prop_name[20]; 601 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 602 cnl->cnl_instance); 603 sc->sc_phy_addr = board_info_get_number(prop_name); 604 } 605 if (sc->sc_phy_addr != MII_PHY_ANY) 606 aprint_normal(" phy %d", sc->sc_phy_addr); 607 608 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 609 &sc->sc_bsh); 610 if (error) { 611 aprint_error(": error mapping registers: %d\n", error); 612 return; 613 } 614 615 /* 616 * Assume firmware has aready set the mac address and fetch it 617 * before we reinit it. 618 */ 619 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 620 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 621 sc->sc_rctrl = RCTRL_DEFAULT; 622 sc->sc_ecntrl = etsec_read(sc, ECNTRL); 623 sc->sc_maccfg1 = etsec_read(sc, MACCFG1); 624 sc->sc_maccfg2 = etsec_read(sc, MACCFG2) | MACCFG2_DEFAULT; 625 626 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 627 size_t len; 628 const uint8_t *mac_addr = 629 board_info_get_data("tsec-mac-addr-base", &len); 630 KASSERT(len == ETHER_ADDR_LEN); 631 sc->sc_macstnaddr2 = 632 (mac_addr[1] << 24) 633 | (mac_addr[0] << 16); 634 sc->sc_macstnaddr1 = 635 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 636 | (mac_addr[4] << 16) 637 | (mac_addr[3] << 8) 638 | (mac_addr[2] << 0); 639 #if 0 640 aprint_error(": mac-address unknown\n"); 641 return; 642 #endif 643 } 644 645 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 646 sc->sc_hwlock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_VM); 647 648 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 649 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 650 651 /* Disable interrupts */ 652 etsec_write(sc, IMASK, 0); 653 654 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 655 if (error) { 656 aprint_error(": failed to init rxq: %d\n", error); 657 goto fail_1; 658 } 659 660 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 661 if (error) { 662 aprint_error(": failed to init txq: %d\n", error); 663 goto fail_2; 664 } 665 666 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 667 ETSEC_MAXRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 668 if (error) { 669 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 670 goto fail_3; 671 } 672 673 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 674 ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 675 if (error) { 676 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 677 goto fail_4; 678 } 679 680 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 681 pq3etsec_tx_intr, sc); 682 if (sc->sc_tx_ih == NULL) { 683 aprint_error(": failed to establish tx interrupt: %d\n", 684 cnl->cnl_intrs[0]); 685 goto fail_5; 686 } 687 688 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 689 pq3etsec_rx_intr, sc); 690 if (sc->sc_rx_ih == NULL) { 691 aprint_error(": failed to establish rx interrupt: %d\n", 692 cnl->cnl_intrs[1]); 693 goto fail_6; 694 } 695 696 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 697 pq3etsec_error_intr, sc); 698 if (sc->sc_error_ih == NULL) { 699 aprint_error(": failed to establish error interrupt: %d\n", 700 cnl->cnl_intrs[2]); 701 goto fail_7; 702 } 703 704 int softint_flags = SOFTINT_NET; 705 #if !defined(MULTIPROCESSOR) || defined(NET_MPSAFE) 706 softint_flags |= SOFTINT_MPSAFE; 707 #endif /* !MULTIPROCESSOR || NET_MPSAFE */ 708 sc->sc_soft_ih = softint_establish(softint_flags, 709 pq3etsec_soft_intr, sc); 710 if (sc->sc_soft_ih == NULL) { 711 aprint_error(": failed to establish soft interrupt\n"); 712 goto fail_8; 713 } 714 715 /* 716 * If there was no MDIO 717 */ 718 if (mdio == CPUNODECF_MDIO_DEFAULT) { 719 aprint_normal("\n"); 720 cfdata_t mdio_cf = config_search(self, cna, 721 CFARG_SUBMATCH, pq3mdio_find, 722 CFARG_EOL); 723 if (mdio_cf != NULL) { 724 sc->sc_mdio_dev = 725 config_attach(self, mdio_cf, cna, NULL, CFARG_EOL); 726 } 727 } else { 728 sc->sc_mdio_dev = device_find_by_driver_unit("mdio", mdio); 729 if (sc->sc_mdio_dev == NULL) { 730 aprint_error(": failed to locate mdio device\n"); 731 goto fail_9; 732 } 733 aprint_normal("\n"); 734 } 735 736 etsec_write(sc, ATTR, ATTR_DEFAULT); 737 etsec_write(sc, ATTRELI, ATTRELI_DEFAULT); 738 739 /* Enable interrupt coalesing */ 740 sc->sc_ic_rx_time = 768; 741 sc->sc_ic_rx_count = 16; 742 sc->sc_ic_tx_time = 768; 743 sc->sc_ic_tx_count = 16; 744 pq3etsec_set_ic_rx(sc); 745 pq3etsec_set_ic_tx(sc); 746 747 char enaddr[ETHER_ADDR_LEN] = { 748 [0] = sc->sc_macstnaddr2 >> 16, 749 [1] = sc->sc_macstnaddr2 >> 24, 750 [2] = sc->sc_macstnaddr1 >> 0, 751 [3] = sc->sc_macstnaddr1 >> 8, 752 [4] = sc->sc_macstnaddr1 >> 16, 753 [5] = sc->sc_macstnaddr1 >> 24, 754 }; 755 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 756 ether_sprintf(enaddr)); 757 758 const char * const xname = device_xname(sc->sc_dev); 759 struct ethercom * const ec = &sc->sc_ec; 760 struct ifnet * const ifp = &ec->ec_if; 761 762 ec->ec_mii = mii; 763 764 mii->mii_ifp = ifp; 765 mii->mii_readreg = pq3mdio_mii_readreg; 766 mii->mii_writereg = pq3mdio_mii_writereg; 767 mii->mii_statchg = pq3etsec_mii_statchg; 768 769 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 770 771 if (sc->sc_mdio_dev != NULL && sc->sc_phy_addr < 32) { 772 mii_attach(sc->sc_mdio_dev, mii, 0xffffffff, 773 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 774 775 if (LIST_FIRST(&mii->mii_phys) == NULL) { 776 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 777 0, NULL); 778 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 779 } else { 780 callout_schedule(&sc->sc_mii_callout, hz); 781 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 782 } 783 } else { 784 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 785 0, NULL); 786 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_1000_T | IFM_FDX); 787 } 788 789 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 790 | ETHERCAP_JUMBO_MTU; 791 ec->ec_capenable = ETHERCAP_VLAN_HWTAGGING; 792 793 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 794 ifp->if_softc = sc; 795 ifp->if_capabilities = IFCAP_ETSEC; 796 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 797 ifp->if_ioctl = pq3etsec_ifioctl; 798 ifp->if_start = pq3etsec_ifstart; 799 ifp->if_watchdog = pq3etsec_ifwatchdog; 800 ifp->if_init = pq3etsec_ifinit; 801 ifp->if_stop = pq3etsec_ifstop; 802 IFQ_SET_READY(&ifp->if_snd); 803 804 /* 805 * Attach the interface. 806 */ 807 if_initialize(ifp); 808 pq3etsec_sysctl_setup(NULL, sc); 809 if_attach(ifp); 810 if_deferred_start_init(ifp, NULL); 811 ether_ifattach(ifp, enaddr); 812 813 rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, 814 RND_FLAG_DEFAULT); 815 816 pq3etsec_ifstop(ifp, true); 817 818 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 819 NULL, xname, "rx stall"); 820 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 821 NULL, xname, "tx stall"); 822 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 823 NULL, xname, "tx intr"); 824 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 825 NULL, xname, "rx intr"); 826 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 827 NULL, xname, "error intr"); 828 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 829 NULL, xname, "soft intr"); 830 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 831 NULL, xname, "tx pause"); 832 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 833 NULL, xname, "rx pause"); 834 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 835 NULL, xname, "mii ticks"); 836 return; 837 838 fail_9: 839 softint_disestablish(sc->sc_soft_ih); 840 fail_8: 841 intr_disestablish(sc->sc_error_ih); 842 fail_7: 843 intr_disestablish(sc->sc_rx_ih); 844 fail_6: 845 intr_disestablish(sc->sc_tx_ih); 846 fail_5: 847 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 848 fail_4: 849 pq3etsec_mapcache_destroy(sc, sc->sc_rx_mapcache); 850 fail_3: 851 #if 0 /* notyet */ 852 pq3etsec_txq_detach(sc); 853 #endif 854 fail_2: 855 #if 0 /* notyet */ 856 pq3etsec_rxq_detach(sc); 857 #endif 858 fail_1: 859 callout_destroy(&sc->sc_mii_callout); 860 mutex_obj_free(sc->sc_lock); 861 mutex_obj_free(sc->sc_hwlock); 862 bus_space_unmap(sc->sc_bst, sc->sc_bsh, cnl->cnl_size); 863 } 864 865 static uint64_t 866 pq3etsec_macaddr_create(const uint8_t *lladdr) 867 { 868 uint64_t macaddr = 0; 869 870 lladdr += ETHER_ADDR_LEN; 871 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 872 macaddr = (macaddr << 8) | *--lladdr; 873 } 874 return macaddr << 16; 875 } 876 877 static int 878 pq3etsec_ifinit(struct ifnet *ifp) 879 { 880 struct pq3etsec_softc * const sc = ifp->if_softc; 881 int error = 0; 882 883 sc->sc_maxfrm = uimax(ifp->if_mtu + 32, MCLBYTES); 884 if (ifp->if_mtu > ETHERMTU_JUMBO) 885 return error; 886 887 KASSERT(ifp->if_flags & IFF_UP); 888 889 /* 890 * Stop the interface (steps 1 to 4 in the Soft Reset and 891 * Reconfigurating Procedure. 892 */ 893 pq3etsec_ifstop(ifp, 0); 894 895 /* 896 * If our frame size has changed (or it's our first time through) 897 * destroy the existing transmit mapcache. 898 */ 899 if (sc->sc_tx_mapcache != NULL 900 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 901 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 902 sc->sc_tx_mapcache = NULL; 903 } 904 905 if (sc->sc_tx_mapcache == NULL) { 906 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 907 ETSEC_MAXTXMBUFS, sc->sc_maxfrm, ETSEC_NTXSEGS); 908 if (error) 909 return error; 910 } 911 912 sc->sc_ev_mii_ticks.ev_count++; 913 mii_tick(&sc->sc_mii); 914 915 if (ifp->if_flags & IFF_PROMISC) { 916 sc->sc_rctrl |= RCTRL_PROM; 917 } else { 918 sc->sc_rctrl &= ~RCTRL_PROM; 919 } 920 921 uint32_t rctrl_prsdep = 0; 922 sc->sc_rctrl &= 923 ~(RCTRL_IPCSEN | RCTRL_TUCSEN | RCTRL_VLEX | RCTRL_PRSDEP); 924 if (VLAN_ATTACHED(&sc->sc_ec)) { 925 sc->sc_rctrl |= RCTRL_VLEX; 926 rctrl_prsdep = RCTRL_PRSDEP_L2; 927 } 928 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 929 sc->sc_rctrl |= RCTRL_IPCSEN; 930 rctrl_prsdep = RCTRL_PRSDEP_L3; 931 } 932 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 933 sc->sc_rctrl |= RCTRL_TUCSEN; 934 rctrl_prsdep = RCTRL_PRSDEP_L4; 935 } 936 sc->sc_rctrl |= rctrl_prsdep; 937 #if 0 938 if (sc->sc_rctrl 939 & (RCTRL_IPCSEN | RCTRL_TUCSEN | RCTRL_VLEX | RCTRL_PRSDEP)) 940 aprint_normal_dev(sc->sc_dev, 941 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 942 sc->sc_rctrl, 943 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 944 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 945 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 946 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 947 #endif 948 949 sc->sc_tctrl &= ~(TCTRL_IPCSEN | TCTRL_TUCSEN | TCTRL_VLINS); 950 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 951 sc->sc_tctrl |= TCTRL_VLINS; 952 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 953 sc->sc_tctrl |= TCTRL_IPCSEN; 954 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 955 sc->sc_tctrl |= TCTRL_TUCSEN; 956 #if 0 957 if (sc->sc_tctrl & (TCTRL_IPCSEN | TCTRL_TUCSEN | TCTRL_VLINS)) 958 aprint_normal_dev(sc->sc_dev, 959 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 960 sc->sc_tctrl, 961 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 962 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 963 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 964 #endif 965 966 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 967 968 const uint64_t macstnaddr = 969 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 970 971 sc->sc_imask = IEVENT_DPE; 972 973 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 974 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 975 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 976 977 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 978 pq3etsec_txq_reset(sc, &sc->sc_txq); 979 980 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 981 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 982 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 983 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 984 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 985 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 986 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 987 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 988 989 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 990 pq3etsec_mc_setup(sc); 991 992 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 993 etsec_write(sc, MRBLR, MCLBYTES); 994 995 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 996 sc->sc_dmactrl |= DMACTRL_DEFAULT; 997 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 998 999 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 1000 etsec_write(sc, TQUEUE, TQUEUE_EN0); 1001 sc->sc_imask |= IEVENT_TXF | IEVENT_TXE | IEVENT_TXC; 1002 1003 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 1004 1005 /* 12. Enable receive queues in RQUEUE, */ 1006 etsec_write(sc, RQUEUE, RQUEUE_EN0 | RQUEUE_EX0); 1007 sc->sc_imask |= IEVENT_RXF | IEVENT_BSY | IEVENT_RXC; 1008 1009 /* and optionally set TOE functionality in RCTRL. */ 1010 etsec_write(sc, RCTRL, sc->sc_rctrl); 1011 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 1012 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 1013 sc->sc_rx_adjlen += sizeof(struct rxfcb); 1014 1015 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 1016 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 1017 1018 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 1019 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 1020 1021 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 1022 sc->sc_dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 1023 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1024 1025 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 1026 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1027 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1028 1029 sc->sc_soft_flags = 0; 1030 1031 etsec_write(sc, IMASK, sc->sc_imask); 1032 1033 ifp->if_flags |= IFF_RUNNING; 1034 1035 return error; 1036 } 1037 1038 static void 1039 pq3etsec_ifstop(struct ifnet *ifp, int disable) 1040 { 1041 struct pq3etsec_softc * const sc = ifp->if_softc; 1042 1043 KASSERT(!cpu_intr_p()); 1044 const uint32_t imask_gsc_mask = IEVENT_GTSC | IEVENT_GRSC; 1045 /* 1046 * Clear the GTSC and GRSC from the interrupt mask until 1047 * we are ready for them. Then clear them from IEVENT, 1048 * request the graceful shutdown, and then enable the 1049 * GTSC and GRSC bits in the mask. This should cause the 1050 * error interrupt to fire which will issue a wakeup to 1051 * allow us to resume. 1052 */ 1053 1054 /* 1055 * 1. Set GRS/GTS bits in DMACTRL register 1056 */ 1057 sc->sc_dmactrl |= DMACTRL_GRS | DMACTRL_GTS; 1058 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 1059 etsec_write(sc, IEVENT, imask_gsc_mask); 1060 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1061 1062 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN | MACCFG1_RX_EN)) { 1063 /* 1064 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 1065 */ 1066 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 1067 1068 u_int timo = 1000; 1069 uint32_t ievent = etsec_read(sc, IEVENT); 1070 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 1071 if (--timo == 0) { 1072 aprint_error_dev(sc->sc_dev, 1073 "WARNING: " 1074 "request to stop failed (IEVENT=%#x)\n", 1075 ievent); 1076 break; 1077 } 1078 delay(10); 1079 ievent = etsec_read(sc, IEVENT); 1080 } 1081 } 1082 1083 /* 1084 * Now reset the controller. 1085 * 1086 * 3. Set SOFT_RESET bit in MACCFG1 register 1087 * 4. Clear SOFT_RESET bit in MACCFG1 register 1088 */ 1089 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 1090 etsec_write(sc, MACCFG1, 0); 1091 etsec_write(sc, IMASK, 0); 1092 etsec_write(sc, IEVENT, ~0); 1093 sc->sc_imask = 0; 1094 ifp->if_flags &= ~IFF_RUNNING; 1095 1096 uint32_t tbipa = etsec_read(sc, TBIPA); 1097 if (tbipa == sc->sc_phy_addr) { 1098 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 1099 etsec_write(sc, TBIPA, 0x1f); 1100 } 1101 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 1102 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 1103 etsec_write(sc, MIIMCFG, miimcfg); 1104 1105 /* 1106 * Let's consume any remaing transmitted packets. And if we are 1107 * disabling the interface, purge ourselves of any untransmitted 1108 * packets. But don't consume any received packets, just drop them. 1109 * If we aren't disabling the interface, save the mbufs in the 1110 * receive queue for reuse. 1111 */ 1112 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 1113 pq3etsec_txq_consume(sc, &sc->sc_txq); 1114 if (disable) { 1115 pq3etsec_txq_purge(sc, &sc->sc_txq); 1116 IFQ_PURGE(&ifp->if_snd); 1117 } 1118 } 1119 1120 static void 1121 pq3etsec_ifwatchdog(struct ifnet *ifp) 1122 { 1123 } 1124 1125 static void 1126 pq3etsec_mc_setup( 1127 struct pq3etsec_softc *sc) 1128 { 1129 struct ethercom * const ec = &sc->sc_ec; 1130 struct ifnet * const ifp = &sc->sc_if; 1131 struct ether_multi *enm; 1132 struct ether_multistep step; 1133 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 1134 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 1135 1136 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 1137 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1138 1139 ifp->if_flags &= ~IFF_ALLMULTI; 1140 1141 ETHER_LOCK(ec); 1142 ETHER_FIRST_MULTI(step, ec, enm); 1143 for (u_int i = 0; enm != NULL; ) { 1144 const char *addr = enm->enm_addrlo; 1145 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1146 ifp->if_flags |= IFF_ALLMULTI; 1147 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 1148 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1149 break; 1150 } 1151 if ((sc->sc_rctrl & RCTRL_EMEN) 1152 && i < __arraycount(sc->sc_macaddrs)) { 1153 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 1154 } else { 1155 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1156 #if 0 1157 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 1158 ether_sprintf(addr), crc, 1159 crc >> crc_shift, 1160 crc >> (crc_shift + 5), 1161 (crc >> crc_shift) & 31, 1162 1 << (((crc >> crc_shift) & 31) ^ 31)); 1163 #endif 1164 /* 1165 * The documentation doesn't completely follow PowerPC 1166 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 1167 * is 0x7fa32d9b. By empirical testing, the 1168 * corresponding hash bit is word 3, bit 31 (ppc bit 1169 * order). Since 3 << 31 | 31 is 0x7f, we deduce 1170 * H[0:2] selects the register while H[3:7] selects 1171 * the bit (ppc bit order). 1172 */ 1173 crc >>= crc_shift; 1174 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 1175 } 1176 ETHER_NEXT_MULTI(step, enm); 1177 } 1178 ETHER_UNLOCK(ec); 1179 for (u_int i = 0; i < 8; i++) { 1180 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 1181 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 1182 #if 0 1183 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 1184 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 1185 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 1186 i, GADDR(i), etsec_read(sc, GADDR(i))); 1187 #endif 1188 } 1189 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 1190 uint64_t macaddr = sc->sc_macaddrs[i]; 1191 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 1192 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 1193 #if 0 1194 if (macaddr) 1195 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 1196 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1197 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1198 #endif 1199 } 1200 } 1201 1202 static int 1203 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1204 { 1205 struct pq3etsec_softc *sc = ifp->if_softc; 1206 struct ifreq * const ifr = data; 1207 const int s = splnet(); 1208 int error; 1209 1210 switch (cmd) { 1211 case SIOCSIFMEDIA: 1212 /* Flow control requires full-duplex mode. */ 1213 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1214 (ifr->ifr_media & IFM_FDX) == 0) 1215 ifr->ifr_media &= ~IFM_ETH_FMASK; 1216 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1217 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1218 /* We can do both TXPAUSE and RXPAUSE. */ 1219 ifr->ifr_media |= 1220 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1221 } 1222 } 1223 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1224 break; 1225 1226 default: 1227 error = ether_ioctl(ifp, cmd, data); 1228 if (error != ENETRESET) 1229 break; 1230 1231 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1232 error = 0; 1233 if (ifp->if_flags & IFF_RUNNING) 1234 pq3etsec_mc_setup(sc); 1235 break; 1236 } 1237 error = pq3etsec_ifinit(ifp); 1238 break; 1239 } 1240 1241 splx(s); 1242 return error; 1243 } 1244 1245 static void 1246 pq3etsec_rxq_desc_presync( 1247 struct pq3etsec_softc *sc, 1248 struct pq3etsec_rxqueue *rxq, 1249 volatile struct rxbd *rxbd, 1250 size_t count) 1251 { 1252 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1253 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1254 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1255 } 1256 1257 static void 1258 pq3etsec_rxq_desc_postsync( 1259 struct pq3etsec_softc *sc, 1260 struct pq3etsec_rxqueue *rxq, 1261 volatile struct rxbd *rxbd, 1262 size_t count) 1263 { 1264 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1265 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1266 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1267 } 1268 1269 static void 1270 pq3etsec_txq_desc_presync( 1271 struct pq3etsec_softc *sc, 1272 struct pq3etsec_txqueue *txq, 1273 volatile struct txbd *txbd, 1274 size_t count) 1275 { 1276 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1277 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1278 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1279 } 1280 1281 static void 1282 pq3etsec_txq_desc_postsync( 1283 struct pq3etsec_softc *sc, 1284 struct pq3etsec_txqueue *txq, 1285 volatile struct txbd *txbd, 1286 size_t count) 1287 { 1288 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1289 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1290 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1291 } 1292 1293 static bus_dmamap_t 1294 pq3etsec_mapcache_get( 1295 struct pq3etsec_softc *sc, 1296 struct pq3etsec_mapcache *dmc) 1297 { 1298 KASSERT(dmc->dmc_nmaps > 0); 1299 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1300 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1301 } 1302 1303 static void 1304 pq3etsec_mapcache_put( 1305 struct pq3etsec_softc *sc, 1306 struct pq3etsec_mapcache *dmc, 1307 bus_dmamap_t map) 1308 { 1309 KASSERT(map != NULL); 1310 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1311 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1312 } 1313 1314 static void 1315 pq3etsec_mapcache_destroy( 1316 struct pq3etsec_softc *sc, 1317 struct pq3etsec_mapcache *dmc) 1318 { 1319 const size_t dmc_size = 1320 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1321 1322 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1323 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1324 } 1325 kmem_intr_free(dmc, dmc_size); 1326 } 1327 1328 static int 1329 pq3etsec_mapcache_create( 1330 struct pq3etsec_softc *sc, 1331 struct pq3etsec_mapcache **dmc_p, 1332 size_t maxmaps, 1333 size_t maxmapsize, 1334 size_t maxseg) 1335 { 1336 const size_t dmc_size = 1337 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1338 struct pq3etsec_mapcache * const dmc = 1339 kmem_intr_zalloc(dmc_size, KM_NOSLEEP); 1340 1341 dmc->dmc_maxmaps = maxmaps; 1342 dmc->dmc_nmaps = maxmaps; 1343 dmc->dmc_maxmapsize = maxmapsize; 1344 dmc->dmc_maxseg = maxseg; 1345 1346 for (u_int i = 0; i < maxmaps; i++) { 1347 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1348 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1349 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1350 if (error) { 1351 aprint_error_dev(sc->sc_dev, 1352 "failed to creat dma map cache " 1353 "entry %u of %zu: %d\n", 1354 i, maxmaps, error); 1355 while (i-- > 0) { 1356 bus_dmamap_destroy(sc->sc_dmat, 1357 dmc->dmc_maps[i]); 1358 } 1359 kmem_intr_free(dmc, dmc_size); 1360 return error; 1361 } 1362 KASSERT(dmc->dmc_maps[i] != NULL); 1363 } 1364 1365 *dmc_p = dmc; 1366 1367 return 0; 1368 } 1369 1370 #if 0 1371 static void 1372 pq3etsec_dmamem_free( 1373 bus_dma_tag_t dmat, 1374 size_t map_size, 1375 bus_dma_segment_t *seg, 1376 bus_dmamap_t map, 1377 void *kvap) 1378 { 1379 bus_dmamap_destroy(dmat, map); 1380 bus_dmamem_unmap(dmat, kvap, map_size); 1381 bus_dmamem_free(dmat, seg, 1); 1382 } 1383 #endif 1384 1385 static int 1386 pq3etsec_dmamem_alloc( 1387 bus_dma_tag_t dmat, 1388 size_t map_size, 1389 bus_dma_segment_t *seg, 1390 bus_dmamap_t *map, 1391 void **kvap) 1392 { 1393 int error; 1394 int nseg; 1395 1396 *kvap = NULL; 1397 *map = NULL; 1398 1399 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1400 seg, 1, &nseg, 0); 1401 if (error) 1402 return error; 1403 1404 KASSERT(nseg == 1); 1405 1406 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1407 BUS_DMA_COHERENT); 1408 if (error == 0) { 1409 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1410 map); 1411 if (error == 0) { 1412 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1413 NULL, 0); 1414 if (error == 0) 1415 return 0; 1416 bus_dmamap_destroy(dmat, *map); 1417 *map = NULL; 1418 } 1419 bus_dmamem_unmap(dmat, *kvap, map_size); 1420 *kvap = NULL; 1421 } 1422 bus_dmamem_free(dmat, seg, nseg); 1423 return 0; 1424 } 1425 1426 static struct mbuf * 1427 pq3etsec_rx_buf_alloc( 1428 struct pq3etsec_softc *sc) 1429 { 1430 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1431 if (m == NULL) { 1432 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1433 return NULL; 1434 } 1435 MCLGET(m, M_DONTWAIT); 1436 if ((m->m_flags & M_EXT) == 0) { 1437 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1438 m_freem(m); 1439 return NULL; 1440 } 1441 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1442 1443 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1444 if (map == NULL) { 1445 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1446 m_freem(m); 1447 return NULL; 1448 } 1449 M_SETCTX(m, map); 1450 m->m_len = m->m_pkthdr.len = MCLBYTES; 1451 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1452 BUS_DMA_READ | BUS_DMA_NOWAIT); 1453 if (error) { 1454 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1455 error); 1456 M_SETCTX(m, NULL); 1457 m_freem(m); 1458 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1459 return NULL; 1460 } 1461 KASSERT(map->dm_mapsize == MCLBYTES); 1462 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1463 BUS_DMASYNC_PREREAD); 1464 1465 return m; 1466 } 1467 1468 static void 1469 pq3etsec_rx_map_unload( 1470 struct pq3etsec_softc *sc, 1471 struct mbuf *m) 1472 { 1473 KASSERT(m); 1474 for (; m != NULL; m = m->m_next) { 1475 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1476 KASSERT(map); 1477 KASSERT(map->dm_mapsize == MCLBYTES); 1478 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1479 BUS_DMASYNC_POSTREAD); 1480 bus_dmamap_unload(sc->sc_dmat, map); 1481 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1482 M_SETCTX(m, NULL); 1483 } 1484 } 1485 1486 static bool 1487 pq3etsec_rxq_produce( 1488 struct pq3etsec_softc *sc, 1489 struct pq3etsec_rxqueue *rxq) 1490 { 1491 volatile struct rxbd *producer = rxq->rxq_producer; 1492 #if 0 1493 size_t inuse = rxq->rxq_inuse; 1494 #endif 1495 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1496 struct mbuf *m; 1497 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1498 if (m == NULL) { 1499 m = pq3etsec_rx_buf_alloc(sc); 1500 if (m == NULL) { 1501 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1502 break; 1503 } 1504 } 1505 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1506 KASSERT(map); 1507 1508 #ifdef ETSEC_DEBUG 1509 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1510 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1511 #endif 1512 1513 /* rxbd_len is write-only by the ETSEC */ 1514 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1515 membar_producer(); 1516 producer->rxbd_flags |= RXBD_E; 1517 if (__predict_false(rxq->rxq_mhead == NULL)) { 1518 KASSERT(producer == rxq->rxq_consumer); 1519 rxq->rxq_mconsumer = m; 1520 } 1521 *rxq->rxq_mtail = m; 1522 rxq->rxq_mtail = &m->m_next; 1523 m->m_len = MCLBYTES; 1524 m->m_next = NULL; 1525 rxq->rxq_inuse++; 1526 if (++producer == rxq->rxq_last) { 1527 membar_producer(); 1528 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1529 rxq->rxq_last - rxq->rxq_producer); 1530 producer = rxq->rxq_producer = rxq->rxq_first; 1531 } 1532 } 1533 if (producer != rxq->rxq_producer) { 1534 membar_producer(); 1535 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1536 producer - rxq->rxq_producer); 1537 rxq->rxq_producer = producer; 1538 } 1539 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1540 if (qhlt) { 1541 KASSERT(qhlt & rxq->rxq_qmask); 1542 sc->sc_ev_rx_stall.ev_count++; 1543 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1544 } 1545 #if 0 1546 aprint_normal_dev(sc->sc_dev, 1547 "%s: buffers inuse went from %zu to %zu\n", 1548 __func__, inuse, rxq->rxq_inuse); 1549 #endif 1550 return true; 1551 } 1552 1553 static bool 1554 pq3etsec_rx_offload( 1555 struct pq3etsec_softc *sc, 1556 struct mbuf *m, 1557 const struct rxfcb *fcb) 1558 { 1559 if (fcb->rxfcb_flags & RXFCB_VLN) { 1560 vlan_set_tag(m, fcb->rxfcb_vlctl); 1561 } 1562 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1563 || (fcb->rxfcb_flags & (RXFCB_CIP | RXFCB_CTU)) == 0) 1564 return true; 1565 int csum_flags = 0; 1566 if ((fcb->rxfcb_flags & (RXFCB_IP6 | RXFCB_CIP)) == RXFCB_CIP) { 1567 csum_flags |= M_CSUM_IPv4; 1568 if (fcb->rxfcb_flags & RXFCB_EIP) 1569 csum_flags |= M_CSUM_IPv4_BAD; 1570 } 1571 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1572 int ipv_flags; 1573 if (fcb->rxfcb_flags & RXFCB_IP6) 1574 ipv_flags = M_CSUM_TCPv6 | M_CSUM_UDPv6; 1575 else 1576 ipv_flags = M_CSUM_TCPv4 | M_CSUM_UDPv4; 1577 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1578 csum_flags |= (M_CSUM_TCPv4 |M_CSUM_TCPv6) & ipv_flags; 1579 } else { 1580 csum_flags |= (M_CSUM_UDPv4 |M_CSUM_UDPv6) & ipv_flags; 1581 } 1582 if (fcb->rxfcb_flags & RXFCB_ETU) 1583 csum_flags |= M_CSUM_TCP_UDP_BAD; 1584 } 1585 1586 m->m_pkthdr.csum_flags = csum_flags; 1587 return true; 1588 } 1589 1590 static void 1591 pq3etsec_rx_input( 1592 struct pq3etsec_softc *sc, 1593 struct mbuf *m, 1594 uint16_t rxbd_flags) 1595 { 1596 struct ifnet * const ifp = &sc->sc_if; 1597 1598 pq3etsec_rx_map_unload(sc, m); 1599 1600 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1601 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1602 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1603 return; 1604 } 1605 m_adj(m, sc->sc_rx_adjlen); 1606 1607 if (rxbd_flags & RXBD_M) 1608 m->m_flags |= M_PROMISC; 1609 if (rxbd_flags & RXBD_BC) 1610 m->m_flags |= M_BCAST; 1611 if (rxbd_flags & RXBD_MC) 1612 m->m_flags |= M_MCAST; 1613 m->m_flags |= M_HASFCS; 1614 m_set_rcvif(m, &sc->sc_if); 1615 1616 /* 1617 * Let's give it to the network subsystm to deal with. 1618 */ 1619 if_percpuq_enqueue(ifp->if_percpuq, m); 1620 } 1621 1622 static void 1623 pq3etsec_rxq_consume( 1624 struct pq3etsec_softc *sc, 1625 struct pq3etsec_rxqueue *rxq) 1626 { 1627 struct ifnet * const ifp = &sc->sc_if; 1628 volatile struct rxbd *consumer = rxq->rxq_consumer; 1629 size_t rxconsumed = 0; 1630 1631 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1632 1633 for (;;) { 1634 if (consumer == rxq->rxq_producer) { 1635 rxq->rxq_consumer = consumer; 1636 rxq->rxq_inuse -= rxconsumed; 1637 KASSERT(rxq->rxq_inuse == 0); 1638 break; 1639 } 1640 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1641 const uint16_t rxbd_flags = consumer->rxbd_flags; 1642 if (rxbd_flags & RXBD_E) { 1643 rxq->rxq_consumer = consumer; 1644 rxq->rxq_inuse -= rxconsumed; 1645 break; 1646 } 1647 KASSERT(rxq->rxq_mconsumer != NULL); 1648 #ifdef ETSEC_DEBUG 1649 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1650 #endif 1651 #if 0 1652 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1653 __func__, 1654 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1655 mtod(rxq->rxq_mconsumer, int *)[0], 1656 mtod(rxq->rxq_mconsumer, int *)[1], 1657 mtod(rxq->rxq_mconsumer, int *)[2], 1658 mtod(rxq->rxq_mconsumer, int *)[3]); 1659 #endif 1660 /* 1661 * We own this packet again. Clear all flags except wrap. 1662 */ 1663 rxconsumed++; 1664 consumer->rxbd_flags = rxbd_flags & (RXBD_W | RXBD_I); 1665 1666 /* 1667 * If this descriptor has the LAST bit set and no errors, 1668 * it's a valid input packet. 1669 */ 1670 if ((rxbd_flags & (RXBD_L | RXBD_ERRORS)) == RXBD_L) { 1671 size_t rxbd_len = consumer->rxbd_len; 1672 struct mbuf *m = rxq->rxq_mhead; 1673 struct mbuf *m_last = rxq->rxq_mconsumer; 1674 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1675 rxq->rxq_mtail = &rxq->rxq_mhead; 1676 rxq->rxq_mconsumer = rxq->rxq_mhead; 1677 m_last->m_next = NULL; 1678 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1679 m->m_pkthdr.len = rxbd_len; 1680 pq3etsec_rx_input(sc, m, rxbd_flags); 1681 } else if (rxbd_flags & RXBD_L) { 1682 KASSERT(rxbd_flags & RXBD_ERRORS); 1683 struct mbuf *m; 1684 /* 1685 * We encountered an error, take the mbufs and add 1686 * then to the rx bufcache so we can reuse them. 1687 */ 1688 if_statinc(ifp, if_ierrors); 1689 for (m = rxq->rxq_mhead; 1690 m != rxq->rxq_mconsumer; 1691 m = m->m_next) { 1692 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1693 } 1694 m = rxq->rxq_mconsumer; 1695 if ((rxq->rxq_mhead = m->m_next) == NULL) 1696 rxq->rxq_mtail = &rxq->rxq_mhead; 1697 rxq->rxq_mconsumer = m->m_next; 1698 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1699 } else { 1700 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1701 } 1702 #ifdef ETSEC_DEBUG 1703 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1704 #endif 1705 1706 /* 1707 * Wrap at the last entry! 1708 */ 1709 if (rxbd_flags & RXBD_W) { 1710 KASSERT(consumer + 1 == rxq->rxq_last); 1711 consumer = rxq->rxq_first; 1712 } else { 1713 consumer++; 1714 } 1715 #ifdef ETSEC_DEBUG 1716 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1717 #endif 1718 } 1719 1720 if (rxconsumed != 0) 1721 rnd_add_uint32(&sc->rnd_source, rxconsumed); 1722 } 1723 1724 static void 1725 pq3etsec_rxq_purge( 1726 struct pq3etsec_softc *sc, 1727 struct pq3etsec_rxqueue *rxq, 1728 bool discard) 1729 { 1730 struct mbuf *m; 1731 1732 if ((m = rxq->rxq_mhead) != NULL) { 1733 #ifdef ETSEC_DEBUG 1734 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1735 #endif 1736 1737 if (discard) { 1738 pq3etsec_rx_map_unload(sc, m); 1739 m_freem(m); 1740 } else { 1741 while (m != NULL) { 1742 struct mbuf *m0 = m->m_next; 1743 m->m_next = NULL; 1744 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1745 m = m0; 1746 } 1747 } 1748 } 1749 1750 rxq->rxq_mconsumer = NULL; 1751 rxq->rxq_mhead = NULL; 1752 rxq->rxq_mtail = &rxq->rxq_mhead; 1753 rxq->rxq_inuse = 0; 1754 } 1755 1756 static void 1757 pq3etsec_rxq_reset( 1758 struct pq3etsec_softc *sc, 1759 struct pq3etsec_rxqueue *rxq) 1760 { 1761 /* 1762 * sync all the descriptors 1763 */ 1764 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1765 rxq->rxq_last - rxq->rxq_first); 1766 1767 /* 1768 * Make sure we own all descriptors in the ring. 1769 */ 1770 volatile struct rxbd *rxbd; 1771 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1772 rxbd->rxbd_flags = RXBD_I; 1773 } 1774 1775 /* 1776 * Last descriptor has the wrap flag. 1777 */ 1778 rxbd->rxbd_flags = RXBD_W | RXBD_I; 1779 1780 /* 1781 * Reset the producer consumer indexes. 1782 */ 1783 rxq->rxq_consumer = rxq->rxq_first; 1784 rxq->rxq_producer = rxq->rxq_first; 1785 rxq->rxq_inuse = 0; 1786 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1787 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1788 1789 sc->sc_imask |= IEVENT_RXF | IEVENT_BSY; 1790 1791 /* 1792 * Restart the transmit at the first descriptor 1793 */ 1794 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1795 } 1796 1797 static int 1798 pq3etsec_rxq_attach( 1799 struct pq3etsec_softc *sc, 1800 struct pq3etsec_rxqueue *rxq, 1801 u_int qno) 1802 { 1803 size_t map_size = PAGE_SIZE; 1804 size_t desc_count = map_size / sizeof(struct rxbd); 1805 int error; 1806 void *descs; 1807 1808 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1809 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1810 if (error) 1811 return error; 1812 1813 memset(descs, 0, map_size); 1814 rxq->rxq_first = descs; 1815 rxq->rxq_last = rxq->rxq_first + desc_count; 1816 rxq->rxq_consumer = descs; 1817 rxq->rxq_producer = descs; 1818 1819 pq3etsec_rxq_purge(sc, rxq, true); 1820 pq3etsec_rxq_reset(sc, rxq); 1821 1822 rxq->rxq_reg_rbase = RBASEn(qno); 1823 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1824 1825 return 0; 1826 } 1827 1828 static bool 1829 pq3etsec_txq_active_p( 1830 struct pq3etsec_softc * const sc, 1831 struct pq3etsec_txqueue *txq) 1832 { 1833 return !IF_IS_EMPTY(&txq->txq_mbufs); 1834 } 1835 1836 static bool 1837 pq3etsec_txq_fillable_p( 1838 struct pq3etsec_softc * const sc, 1839 struct pq3etsec_txqueue *txq) 1840 { 1841 return txq->txq_free >= txq->txq_threshold; 1842 } 1843 1844 static int 1845 pq3etsec_txq_attach( 1846 struct pq3etsec_softc *sc, 1847 struct pq3etsec_txqueue *txq, 1848 u_int qno) 1849 { 1850 size_t map_size = PAGE_SIZE; 1851 size_t desc_count = map_size / sizeof(struct txbd); 1852 int error; 1853 void *descs; 1854 1855 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1856 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1857 if (error) 1858 return error; 1859 1860 memset(descs, 0, map_size); 1861 txq->txq_first = descs; 1862 txq->txq_last = txq->txq_first + desc_count; 1863 txq->txq_consumer = descs; 1864 txq->txq_producer = descs; 1865 1866 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1867 1868 txq->txq_reg_tbase = TBASEn(qno); 1869 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1870 1871 pq3etsec_txq_reset(sc, txq); 1872 1873 return 0; 1874 } 1875 1876 static int 1877 pq3etsec_txq_map_load( 1878 struct pq3etsec_softc *sc, 1879 struct pq3etsec_txqueue *txq, 1880 struct mbuf *m) 1881 { 1882 bus_dmamap_t map; 1883 int error; 1884 1885 map = M_GETCTX(m, bus_dmamap_t); 1886 if (map != NULL) 1887 return 0; 1888 1889 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1890 if (map == NULL) 1891 return ENOMEM; 1892 1893 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1894 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1895 if (error) 1896 return error; 1897 1898 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1899 BUS_DMASYNC_PREWRITE); 1900 M_SETCTX(m, map); 1901 return 0; 1902 } 1903 1904 static void 1905 pq3etsec_txq_map_unload( 1906 struct pq3etsec_softc *sc, 1907 struct pq3etsec_txqueue *txq, 1908 struct mbuf *m) 1909 { 1910 KASSERT(m); 1911 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1912 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1913 BUS_DMASYNC_POSTWRITE); 1914 bus_dmamap_unload(sc->sc_dmat, map); 1915 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1916 } 1917 1918 static bool 1919 pq3etsec_txq_produce( 1920 struct pq3etsec_softc *sc, 1921 struct pq3etsec_txqueue *txq, 1922 struct mbuf *m) 1923 { 1924 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1925 1926 if (map->dm_nsegs > txq->txq_free) 1927 return false; 1928 1929 /* 1930 * TCP Offload flag must be set in the first descriptor. 1931 */ 1932 volatile struct txbd *producer = txq->txq_producer; 1933 uint16_t last_flags = TXBD_L; 1934 uint16_t first_flags = TXBD_R 1935 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1936 1937 /* 1938 * If we've produced enough descriptors without consuming any 1939 * we need to ask for an interrupt to reclaim some. 1940 */ 1941 txq->txq_lastintr += map->dm_nsegs; 1942 if (ETSEC_IC_TX_ENABLED(sc) 1943 || txq->txq_lastintr >= txq->txq_threshold 1944 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1945 txq->txq_lastintr = 0; 1946 last_flags |= TXBD_I; 1947 } 1948 1949 #ifdef ETSEC_DEBUG 1950 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1951 #endif 1952 KASSERT(producer != txq->txq_last); 1953 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1954 producer->txbd_len = map->dm_segs[0].ds_len; 1955 1956 if (map->dm_nsegs > 1) { 1957 volatile struct txbd *start = producer + 1; 1958 size_t count = map->dm_nsegs - 1; 1959 for (u_int i = 1; i < map->dm_nsegs; i++) { 1960 if (__predict_false(++producer == txq->txq_last)) { 1961 producer = txq->txq_first; 1962 if (start < txq->txq_last) { 1963 pq3etsec_txq_desc_presync(sc, txq, 1964 start, txq->txq_last - start); 1965 count -= txq->txq_last - start; 1966 } 1967 start = txq->txq_first; 1968 } 1969 #ifdef ETSEC_DEBUG 1970 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1971 #endif 1972 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1973 producer->txbd_len = map->dm_segs[i].ds_len; 1974 producer->txbd_flags = TXBD_R 1975 | (producer->txbd_flags & TXBD_W) 1976 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1977 #if 0 1978 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1979 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1980 #endif 1981 } 1982 pq3etsec_txq_desc_presync(sc, txq, start, count); 1983 } else { 1984 first_flags |= last_flags; 1985 } 1986 1987 membar_producer(); 1988 txq->txq_producer->txbd_flags = 1989 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1990 #if 0 1991 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1992 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1993 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1994 #endif 1995 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1996 1997 /* 1998 * Reduce free count by the number of segments we consumed. 1999 */ 2000 txq->txq_free -= map->dm_nsegs; 2001 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 2002 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 2003 KASSERT(producer->txbd_flags & TXBD_L); 2004 #ifdef ETSEC_DEBUG 2005 txq->txq_lmbufs[producer - txq->txq_first] = m; 2006 #endif 2007 2008 #if 0 2009 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 2010 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 2011 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 2012 #endif 2013 2014 if (++producer == txq->txq_last) 2015 txq->txq_producer = txq->txq_first; 2016 else 2017 txq->txq_producer = producer; 2018 IF_ENQUEUE(&txq->txq_mbufs, m); 2019 2020 /* 2021 * Restart the transmitter. 2022 */ 2023 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 2024 2025 return true; 2026 } 2027 2028 static void 2029 pq3etsec_tx_offload( 2030 struct pq3etsec_softc *sc, 2031 struct pq3etsec_txqueue *txq, 2032 struct mbuf **mp) 2033 { 2034 struct mbuf *m = *mp; 2035 u_int csum_flags = m->m_pkthdr.csum_flags; 2036 bool have_vtag; 2037 uint16_t vtag; 2038 2039 KASSERT(m->m_flags & M_PKTHDR); 2040 2041 have_vtag = vlan_has_tag(m); 2042 vtag = (have_vtag) ? vlan_get_tag(m) : 0; 2043 2044 /* 2045 * Let see if we are doing any offload first. 2046 */ 2047 if (csum_flags == 0 && !have_vtag) { 2048 m->m_flags &= ~M_HASFCB; 2049 return; 2050 } 2051 2052 uint16_t flags = 0; 2053 if (csum_flags & M_CSUM_IP) { 2054 flags |= TXFCB_IP 2055 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 2056 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 2057 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 2058 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 2059 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 2060 } 2061 if (have_vtag) { 2062 flags |= TXFCB_VLN; 2063 } 2064 if (flags == 0) { 2065 m->m_flags &= ~M_HASFCB; 2066 return; 2067 } 2068 2069 struct txfcb fcb; 2070 fcb.txfcb_flags = flags; 2071 if (csum_flags & M_CSUM_IPv4) 2072 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2073 else 2074 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2075 fcb.txfcb_l3os = ETHER_HDR_LEN; 2076 fcb.txfcb_phcs = 0; 2077 fcb.txfcb_vlctl = vtag; 2078 2079 #if 0 2080 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 2081 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 2082 fcb.txfcb_phcs, fcb.txfcb_vlctl); 2083 #endif 2084 2085 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 2086 m->m_data -= sizeof(fcb); 2087 m->m_len += sizeof(fcb); 2088 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 2089 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 2090 m->m_data = m->m_pktdat; 2091 m->m_len += sizeof(fcb); 2092 } else { 2093 struct mbuf *mn; 2094 MGET(mn, M_DONTWAIT, m->m_type); 2095 if (mn == NULL) { 2096 if (csum_flags & M_CSUM_IP4) { 2097 #ifdef INET 2098 in_undefer_cksum(m, ETHER_HDR_LEN, 2099 csum_flags & M_CSUM_IP4); 2100 #else 2101 panic("%s: impossible M_CSUM flags %#x", 2102 device_xname(sc->sc_dev), csum_flags); 2103 #endif 2104 } else if (csum_flags & M_CSUM_IP6) { 2105 #ifdef INET6 2106 in6_undefer_cksum(m, ETHER_HDR_LEN, 2107 csum_flags & M_CSUM_IP6); 2108 #else 2109 panic("%s: impossible M_CSUM flags %#x", 2110 device_xname(sc->sc_dev), csum_flags); 2111 #endif 2112 } 2113 2114 m->m_flags &= ~M_HASFCB; 2115 return; 2116 } 2117 2118 m_move_pkthdr(mn, m); 2119 mn->m_next = m; 2120 m = mn; 2121 m_align(m, sizeof(fcb)); 2122 m->m_len = sizeof(fcb); 2123 *mp = m; 2124 } 2125 m->m_pkthdr.len += sizeof(fcb); 2126 m->m_flags |= M_HASFCB; 2127 *mtod(m, struct txfcb *) = fcb; 2128 return; 2129 } 2130 2131 static bool 2132 pq3etsec_txq_enqueue( 2133 struct pq3etsec_softc *sc, 2134 struct pq3etsec_txqueue *txq) 2135 { 2136 for (;;) { 2137 if (IF_QFULL(&txq->txq_mbufs)) 2138 return false; 2139 struct mbuf *m = txq->txq_next; 2140 if (m == NULL) { 2141 int s = splnet(); 2142 IFQ_DEQUEUE(&sc->sc_if.if_snd, m); 2143 splx(s); 2144 if (m == NULL) 2145 return true; 2146 M_SETCTX(m, NULL); 2147 pq3etsec_tx_offload(sc, txq, &m); 2148 } else { 2149 txq->txq_next = NULL; 2150 } 2151 int error = pq3etsec_txq_map_load(sc, txq, m); 2152 if (error) { 2153 aprint_error_dev(sc->sc_dev, 2154 "discarded packet due to " 2155 "dmamap load failure: %d\n", error); 2156 m_freem(m); 2157 continue; 2158 } 2159 KASSERT(txq->txq_next == NULL); 2160 if (!pq3etsec_txq_produce(sc, txq, m)) { 2161 txq->txq_next = m; 2162 return false; 2163 } 2164 KASSERT(txq->txq_next == NULL); 2165 } 2166 } 2167 2168 static bool 2169 pq3etsec_txq_consume( 2170 struct pq3etsec_softc *sc, 2171 struct pq3etsec_txqueue *txq) 2172 { 2173 struct ifnet * const ifp = &sc->sc_if; 2174 volatile struct txbd *consumer = txq->txq_consumer; 2175 size_t txfree = 0; 2176 bool ret; 2177 2178 #if 0 2179 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 2180 #endif 2181 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 2182 2183 for (;;) { 2184 if (consumer == txq->txq_producer) { 2185 txq->txq_consumer = consumer; 2186 txq->txq_free += txfree; 2187 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2188 KASSERT(txq->txq_lastintr == 0); 2189 KASSERT(txq->txq_free == 2190 txq->txq_last - txq->txq_first - 1); 2191 ret = true; 2192 break; 2193 } 2194 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2195 const uint16_t txbd_flags = consumer->txbd_flags; 2196 if (txbd_flags & TXBD_R) { 2197 txq->txq_consumer = consumer; 2198 txq->txq_free += txfree; 2199 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2200 ret = pq3etsec_txq_fillable_p(sc, txq); 2201 break; 2202 } 2203 2204 /* 2205 * If this is the last descriptor in the chain, get the 2206 * mbuf, free its dmamap, and free the mbuf chain itself. 2207 */ 2208 if (txbd_flags & TXBD_L) { 2209 struct mbuf *m; 2210 2211 IF_DEQUEUE(&txq->txq_mbufs, m); 2212 #ifdef ETSEC_DEBUG 2213 KASSERTMSG( 2214 m == txq->txq_lmbufs[consumer-txq->txq_first], 2215 "%s: %p [%u]: flags %#x m (%p) != %p (%p)", 2216 __func__, consumer, consumer - txq->txq_first, 2217 txbd_flags, m, 2218 &txq->txq_lmbufs[consumer-txq->txq_first], 2219 txq->txq_lmbufs[consumer-txq->txq_first]); 2220 #endif 2221 KASSERT(m); 2222 pq3etsec_txq_map_unload(sc, txq, m); 2223 #if 0 2224 printf("%s: mbuf %p: consumed a %u byte packet\n", 2225 __func__, m, m->m_pkthdr.len); 2226 #endif 2227 if (m->m_flags & M_HASFCB) 2228 m_adj(m, sizeof(struct txfcb)); 2229 bpf_mtap(ifp, m, BPF_D_OUT); 2230 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2231 if_statinc_ref(nsr, if_opackets); 2232 if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len); 2233 if (m->m_flags & M_MCAST) 2234 if_statinc_ref(nsr, if_omcasts); 2235 if (txbd_flags & TXBD_ERRORS) 2236 if_statinc_ref(nsr, if_oerrors); 2237 IF_STAT_PUTREF(ifp); 2238 m_freem(m); 2239 #ifdef ETSEC_DEBUG 2240 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2241 #endif 2242 } else { 2243 #ifdef ETSEC_DEBUG 2244 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2245 #endif 2246 } 2247 2248 /* 2249 * We own this packet again. Clear all flags except wrap. 2250 */ 2251 txfree++; 2252 //consumer->txbd_flags = txbd_flags & TXBD_W; 2253 2254 /* 2255 * Wrap at the last entry! 2256 */ 2257 if (txbd_flags & TXBD_W) { 2258 KASSERT(consumer + 1 == txq->txq_last); 2259 consumer = txq->txq_first; 2260 } else { 2261 consumer++; 2262 KASSERT(consumer < txq->txq_last); 2263 } 2264 } 2265 2266 if (txfree != 0) 2267 rnd_add_uint32(&sc->rnd_source, txfree); 2268 return ret; 2269 } 2270 2271 static void 2272 pq3etsec_txq_purge( 2273 struct pq3etsec_softc *sc, 2274 struct pq3etsec_txqueue *txq) 2275 { 2276 struct mbuf *m; 2277 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2278 2279 for (;;) { 2280 IF_DEQUEUE(&txq->txq_mbufs, m); 2281 if (m == NULL) 2282 break; 2283 pq3etsec_txq_map_unload(sc, txq, m); 2284 m_freem(m); 2285 } 2286 if ((m = txq->txq_next) != NULL) { 2287 txq->txq_next = NULL; 2288 pq3etsec_txq_map_unload(sc, txq, m); 2289 m_freem(m); 2290 } 2291 #ifdef ETSEC_DEBUG 2292 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2293 #endif 2294 } 2295 2296 static void 2297 pq3etsec_txq_reset( 2298 struct pq3etsec_softc *sc, 2299 struct pq3etsec_txqueue *txq) 2300 { 2301 /* 2302 * sync all the descriptors 2303 */ 2304 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2305 txq->txq_last - txq->txq_first); 2306 2307 /* 2308 * Make sure we own all descriptors in the ring. 2309 */ 2310 volatile struct txbd *txbd; 2311 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2312 txbd->txbd_flags = 0; 2313 } 2314 2315 /* 2316 * Last descriptor has the wrap flag. 2317 */ 2318 txbd->txbd_flags = TXBD_W; 2319 2320 /* 2321 * Reset the producer consumer indexes. 2322 */ 2323 txq->txq_consumer = txq->txq_first; 2324 txq->txq_producer = txq->txq_first; 2325 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2326 txq->txq_threshold = txq->txq_free / 2; 2327 txq->txq_lastintr = 0; 2328 2329 /* 2330 * What do we want to get interrupted on? 2331 */ 2332 sc->sc_imask |= IEVENT_TXF | IEVENT_TXE; 2333 2334 /* 2335 * Restart the transmit at the first descriptor 2336 */ 2337 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2338 } 2339 2340 static void 2341 pq3etsec_ifstart(struct ifnet *ifp) 2342 { 2343 struct pq3etsec_softc * const sc = ifp->if_softc; 2344 2345 if (__predict_false((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)) { 2346 return; 2347 } 2348 2349 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2350 softint_schedule(sc->sc_soft_ih); 2351 } 2352 2353 static void 2354 pq3etsec_tx_error( 2355 struct pq3etsec_softc * const sc) 2356 { 2357 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2358 2359 pq3etsec_txq_consume(sc, txq); 2360 2361 if (pq3etsec_txq_fillable_p(sc, txq)) 2362 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2363 if (sc->sc_txerrors 2364 & (IEVENT_LC | IEVENT_CRL | IEVENT_XFUN | IEVENT_BABT)) { 2365 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2366 } 2367 2368 if (pq3etsec_txq_active_p(sc, txq)) 2369 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2370 if (!pq3etsec_txq_enqueue(sc, txq)) { 2371 sc->sc_ev_tx_stall.ev_count++; 2372 sc->sc_if.if_flags |= IFF_OACTIVE; 2373 } 2374 2375 sc->sc_txerrors = 0; 2376 } 2377 2378 int 2379 pq3etsec_tx_intr(void *arg) 2380 { 2381 struct pq3etsec_softc * const sc = arg; 2382 2383 mutex_enter(sc->sc_hwlock); 2384 2385 sc->sc_ev_tx_intr.ev_count++; 2386 2387 uint32_t ievent = etsec_read(sc, IEVENT); 2388 ievent &= IEVENT_TXF | IEVENT_TXB; 2389 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2390 2391 #if 0 2392 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2393 __func__, ievent, etsec_read(sc, IMASK)); 2394 #endif 2395 2396 if (ievent == 0) { 2397 mutex_exit(sc->sc_hwlock); 2398 return 0; 2399 } 2400 2401 sc->sc_imask &= ~(IEVENT_TXF | IEVENT_TXB); 2402 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2403 etsec_write(sc, IMASK, sc->sc_imask); 2404 softint_schedule(sc->sc_soft_ih); 2405 2406 mutex_exit(sc->sc_hwlock); 2407 2408 return 1; 2409 } 2410 2411 int 2412 pq3etsec_rx_intr(void *arg) 2413 { 2414 struct pq3etsec_softc * const sc = arg; 2415 2416 mutex_enter(sc->sc_hwlock); 2417 2418 sc->sc_ev_rx_intr.ev_count++; 2419 2420 uint32_t ievent = etsec_read(sc, IEVENT); 2421 ievent &= IEVENT_RXF | IEVENT_RXB; 2422 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2423 if (ievent == 0) { 2424 mutex_exit(sc->sc_hwlock); 2425 return 0; 2426 } 2427 2428 #if 0 2429 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2430 #endif 2431 2432 sc->sc_imask &= ~(IEVENT_RXF | IEVENT_RXB); 2433 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2434 etsec_write(sc, IMASK, sc->sc_imask); 2435 softint_schedule(sc->sc_soft_ih); 2436 2437 mutex_exit(sc->sc_hwlock); 2438 2439 return 1; 2440 } 2441 2442 int 2443 pq3etsec_error_intr(void *arg) 2444 { 2445 struct pq3etsec_softc * const sc = arg; 2446 2447 mutex_enter(sc->sc_hwlock); 2448 2449 sc->sc_ev_error_intr.ev_count++; 2450 2451 for (int rv = 0, soft_flags = 0;; rv = 1) { 2452 uint32_t ievent = etsec_read(sc, IEVENT); 2453 ievent &= ~(IEVENT_RXF | IEVENT_RXB | IEVENT_TXF | IEVENT_TXB); 2454 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2455 if (ievent == 0) { 2456 if (soft_flags) { 2457 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2458 softint_schedule(sc->sc_soft_ih); 2459 } 2460 mutex_exit(sc->sc_hwlock); 2461 return rv; 2462 } 2463 #if 0 2464 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2465 __func__, ievent, etsec_read(sc, IMASK)); 2466 #endif 2467 2468 if (ievent & (IEVENT_GRSC | IEVENT_GTSC)) { 2469 sc->sc_imask &= ~(IEVENT_GRSC | IEVENT_GTSC); 2470 etsec_write(sc, IMASK, sc->sc_imask); 2471 wakeup(sc); 2472 } 2473 if (ievent & (IEVENT_MMRD | IEVENT_MMWR)) { 2474 sc->sc_imask &= ~(IEVENT_MMRD | IEVENT_MMWR); 2475 etsec_write(sc, IMASK, sc->sc_imask); 2476 wakeup(&sc->sc_mii); 2477 } 2478 if (ievent & IEVENT_BSY) { 2479 soft_flags |= SOFT_RXBSY; 2480 sc->sc_imask &= ~IEVENT_BSY; 2481 etsec_write(sc, IMASK, sc->sc_imask); 2482 } 2483 if (ievent & IEVENT_TXE) { 2484 soft_flags |= SOFT_TXERROR; 2485 sc->sc_imask &= ~IEVENT_TXE; 2486 sc->sc_txerrors |= ievent; 2487 } 2488 if (ievent & IEVENT_TXC) { 2489 sc->sc_ev_tx_pause.ev_count++; 2490 } 2491 if (ievent & IEVENT_RXC) { 2492 sc->sc_ev_rx_pause.ev_count++; 2493 } 2494 if (ievent & IEVENT_DPE) { 2495 soft_flags |= SOFT_RESET; 2496 sc->sc_imask &= ~IEVENT_DPE; 2497 etsec_write(sc, IMASK, sc->sc_imask); 2498 } 2499 } 2500 } 2501 2502 void 2503 pq3etsec_soft_intr(void *arg) 2504 { 2505 struct pq3etsec_softc * const sc = arg; 2506 struct ifnet * const ifp = &sc->sc_if; 2507 uint32_t imask = 0; 2508 2509 mutex_enter(sc->sc_lock); 2510 2511 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2512 2513 sc->sc_ev_soft_intr.ev_count++; 2514 2515 if (soft_flags & SOFT_RESET) { 2516 int s = splnet(); 2517 pq3etsec_ifinit(ifp); 2518 splx(s); 2519 soft_flags = 0; 2520 } 2521 2522 if (soft_flags & SOFT_RXBSY) { 2523 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2524 size_t threshold = 5 * rxq->rxq_threshold / 4; 2525 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2526 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2527 } else { 2528 imask |= IEVENT_BSY; 2529 } 2530 aprint_normal_dev(sc->sc_dev, 2531 "increasing receive buffers from %zu to %zu\n", 2532 rxq->rxq_threshold, threshold); 2533 rxq->rxq_threshold = threshold; 2534 } 2535 2536 if ((soft_flags & SOFT_TXINTR) 2537 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2538 /* 2539 * Let's do what we came here for. Consume transmitted 2540 * packets off the transmit ring. 2541 */ 2542 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2543 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2544 sc->sc_ev_tx_stall.ev_count++; 2545 ifp->if_flags |= IFF_OACTIVE; 2546 } else { 2547 ifp->if_flags &= ~IFF_OACTIVE; 2548 } 2549 imask |= IEVENT_TXF; 2550 } 2551 2552 if (soft_flags & (SOFT_RXINTR | SOFT_RXBSY)) { 2553 /* Let's consume */ 2554 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2555 imask |= IEVENT_RXF; 2556 } 2557 2558 if (soft_flags & SOFT_TXERROR) { 2559 pq3etsec_tx_error(sc); 2560 imask |= IEVENT_TXE; 2561 } 2562 2563 if (ifp->if_flags & IFF_RUNNING) { 2564 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2565 mutex_spin_enter(sc->sc_hwlock); 2566 sc->sc_imask |= imask; 2567 etsec_write(sc, IMASK, sc->sc_imask); 2568 mutex_spin_exit(sc->sc_hwlock); 2569 } else { 2570 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2571 } 2572 2573 mutex_exit(sc->sc_lock); 2574 } 2575 2576 static void 2577 pq3etsec_mii_tick(void *arg) 2578 { 2579 struct pq3etsec_softc * const sc = arg; 2580 mutex_enter(sc->sc_lock); 2581 callout_ack(&sc->sc_mii_callout); 2582 sc->sc_ev_mii_ticks.ev_count++; 2583 #ifdef DEBUG 2584 uint64_t now = mftb(); 2585 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2586 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2587 __func__, now - sc->sc_mii_last_tick); 2588 callout_stop(&sc->sc_mii_callout); 2589 } 2590 #endif 2591 mii_tick(&sc->sc_mii); 2592 int s = splnet(); 2593 if (sc->sc_soft_flags & SOFT_RESET) 2594 softint_schedule(sc->sc_soft_ih); 2595 splx(s); 2596 callout_schedule(&sc->sc_mii_callout, hz); 2597 #ifdef DEBUG 2598 sc->sc_mii_last_tick = now; 2599 #endif 2600 mutex_exit(sc->sc_lock); 2601 } 2602 2603 static void 2604 pq3etsec_set_ic_rx(struct pq3etsec_softc *sc) 2605 { 2606 uint32_t reg; 2607 2608 if (ETSEC_IC_RX_ENABLED(sc)) { 2609 reg = RXIC_ICEN; 2610 reg |= RXIC_ICFT_SET(sc->sc_ic_rx_count); 2611 reg |= RXIC_ICTT_SET(sc->sc_ic_rx_time); 2612 } else { 2613 /* Disable RX interrupt coalescing */ 2614 reg = 0; 2615 } 2616 2617 etsec_write(sc, RXIC, reg); 2618 } 2619 2620 static void 2621 pq3etsec_set_ic_tx(struct pq3etsec_softc *sc) 2622 { 2623 uint32_t reg; 2624 2625 if (ETSEC_IC_TX_ENABLED(sc)) { 2626 reg = TXIC_ICEN; 2627 reg |= TXIC_ICFT_SET(sc->sc_ic_tx_count); 2628 reg |= TXIC_ICTT_SET(sc->sc_ic_tx_time); 2629 } else { 2630 /* Disable TX interrupt coalescing */ 2631 reg = 0; 2632 } 2633 2634 etsec_write(sc, TXIC, reg); 2635 } 2636 2637 /* 2638 * sysctl 2639 */ 2640 static int 2641 pq3etsec_sysctl_ic_time_helper(SYSCTLFN_ARGS, int *valuep) 2642 { 2643 struct sysctlnode node = *rnode; 2644 struct pq3etsec_softc *sc = rnode->sysctl_data; 2645 int value = *valuep; 2646 int error; 2647 2648 node.sysctl_data = &value; 2649 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2650 if (error != 0 || newp == NULL) 2651 return error; 2652 2653 if (value < 0 || value > 65535) 2654 return EINVAL; 2655 2656 mutex_enter(sc->sc_lock); 2657 *valuep = value; 2658 if (valuep == &sc->sc_ic_rx_time) 2659 pq3etsec_set_ic_rx(sc); 2660 else 2661 pq3etsec_set_ic_tx(sc); 2662 mutex_exit(sc->sc_lock); 2663 2664 return 0; 2665 } 2666 2667 static int 2668 pq3etsec_sysctl_ic_count_helper(SYSCTLFN_ARGS, int *valuep) 2669 { 2670 struct sysctlnode node = *rnode; 2671 struct pq3etsec_softc *sc = rnode->sysctl_data; 2672 int value = *valuep; 2673 int error; 2674 2675 node.sysctl_data = &value; 2676 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2677 if (error != 0 || newp == NULL) 2678 return error; 2679 2680 if (value < 0 || value > 255) 2681 return EINVAL; 2682 2683 mutex_enter(sc->sc_lock); 2684 *valuep = value; 2685 if (valuep == &sc->sc_ic_rx_count) 2686 pq3etsec_set_ic_rx(sc); 2687 else 2688 pq3etsec_set_ic_tx(sc); 2689 mutex_exit(sc->sc_lock); 2690 2691 return 0; 2692 } 2693 2694 static int 2695 pq3etsec_sysctl_ic_rx_time_helper(SYSCTLFN_ARGS) 2696 { 2697 struct pq3etsec_softc *sc = rnode->sysctl_data; 2698 2699 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2700 &sc->sc_ic_rx_time); 2701 } 2702 2703 static int 2704 pq3etsec_sysctl_ic_rx_count_helper(SYSCTLFN_ARGS) 2705 { 2706 struct pq3etsec_softc *sc = rnode->sysctl_data; 2707 2708 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2709 &sc->sc_ic_rx_count); 2710 } 2711 2712 static int 2713 pq3etsec_sysctl_ic_tx_time_helper(SYSCTLFN_ARGS) 2714 { 2715 struct pq3etsec_softc *sc = rnode->sysctl_data; 2716 2717 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2718 &sc->sc_ic_tx_time); 2719 } 2720 2721 static int 2722 pq3etsec_sysctl_ic_tx_count_helper(SYSCTLFN_ARGS) 2723 { 2724 struct pq3etsec_softc *sc = rnode->sysctl_data; 2725 2726 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2727 &sc->sc_ic_tx_count); 2728 } 2729 2730 static void pq3etsec_sysctl_setup(struct sysctllog **clog, 2731 struct pq3etsec_softc *sc) 2732 { 2733 const struct sysctlnode *cnode, *rnode; 2734 2735 if (sysctl_createv(clog, 0, NULL, &rnode, 2736 CTLFLAG_PERMANENT, 2737 CTLTYPE_NODE, device_xname(sc->sc_dev), 2738 SYSCTL_DESCR("TSEC interface"), 2739 NULL, 0, NULL, 0, 2740 CTL_HW, CTL_CREATE, CTL_EOL) != 0) 2741 goto bad; 2742 2743 if (sysctl_createv(clog, 0, &rnode, &rnode, 2744 CTLFLAG_PERMANENT, 2745 CTLTYPE_NODE, "int_coal", 2746 SYSCTL_DESCR("Interrupts coalescing"), 2747 NULL, 0, NULL, 0, 2748 CTL_CREATE, CTL_EOL) != 0) 2749 goto bad; 2750 2751 if (sysctl_createv(clog, 0, &rnode, &cnode, 2752 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2753 CTLTYPE_INT, "rx_time", 2754 SYSCTL_DESCR("RX time threshold (0-65535)"), 2755 pq3etsec_sysctl_ic_rx_time_helper, 0, (void *)sc, 0, 2756 CTL_CREATE, CTL_EOL) != 0) 2757 goto bad; 2758 2759 if (sysctl_createv(clog, 0, &rnode, &cnode, 2760 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2761 CTLTYPE_INT, "rx_count", 2762 SYSCTL_DESCR("RX frame count threshold (0-255)"), 2763 pq3etsec_sysctl_ic_rx_count_helper, 0, (void *)sc, 0, 2764 CTL_CREATE, CTL_EOL) != 0) 2765 goto bad; 2766 2767 if (sysctl_createv(clog, 0, &rnode, &cnode, 2768 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2769 CTLTYPE_INT, "tx_time", 2770 SYSCTL_DESCR("TX time threshold (0-65535)"), 2771 pq3etsec_sysctl_ic_tx_time_helper, 0, (void *)sc, 0, 2772 CTL_CREATE, CTL_EOL) != 0) 2773 goto bad; 2774 2775 if (sysctl_createv(clog, 0, &rnode, &cnode, 2776 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2777 CTLTYPE_INT, "tx_count", 2778 SYSCTL_DESCR("TX frame count threshold (0-255)"), 2779 pq3etsec_sysctl_ic_tx_count_helper, 0, (void *)sc, 0, 2780 CTL_CREATE, CTL_EOL) != 0) 2781 goto bad; 2782 2783 return; 2784 2785 bad: 2786 aprint_error_dev(sc->sc_dev, "could not attach sysctl nodes\n"); 2787 } 2788
Indexes created Tue Sep 30 07:10:03 GMT 2025