pq3etsec.c revision 1.56
1 /* $NetBSD: pq3etsec.c,v 1.56 2021/08/07 16:19:02 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.56 2021/08/07 16:19:02 thorpej Exp $"); 39 40 #ifdef _KERNEL_OPT 41 #include "opt_inet.h" 42 #include "opt_mpc85xx.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_net_mpsafe.h" 45 #endif 46 47 #include <sys/param.h> 48 #include <sys/cpu.h> 49 #include <sys/device.h> 50 #include <sys/mbuf.h> 51 #include <sys/ioctl.h> 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/atomic.h> 58 #include <sys/callout.h> 59 #include <sys/sysctl.h> 60 61 #include <sys/rndsource.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/bpf.h> 68 69 #include <dev/mii/miivar.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/ip.h> 75 #include <netinet/in_offload.h> 76 #endif /* INET */ 77 #ifdef INET6 78 #include <netinet6/in6.h> 79 #include <netinet/ip6.h> 80 #endif 81 #include <netinet6/in6_offload.h> 82 83 #include <powerpc/spr.h> 84 #include <powerpc/booke/spr.h> 85 #include <powerpc/booke/cpuvar.h> 86 #include <powerpc/booke/e500var.h> 87 #include <powerpc/booke/e500reg.h> 88 #include <powerpc/booke/etsecreg.h> 89 90 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 91 92 #define ETSEC_MAXTXMBUFS 30 93 #define ETSEC_NTXSEGS 30 94 #define ETSEC_MAXRXMBUFS 511 95 #define ETSEC_MINRXMBUFS 32 96 #define ETSEC_NRXSEGS 1 97 98 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 99 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx \ 100 | IFCAP_CSUM_UDPv4_Rx \ 101 | IFCAP_CSUM_TCPv6_Rx \ 102 | IFCAP_CSUM_UDPv6_Rx) 103 104 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 105 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx \ 106 | IFCAP_CSUM_UDPv4_Tx \ 107 | IFCAP_CSUM_TCPv6_Tx \ 108 | IFCAP_CSUM_UDPv6_Tx) 109 110 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN | IFCAP_RCTRL_TUCSEN \ 111 | IFCAP_TCTRL_IPCSEN | IFCAP_TCTRL_TUCSEN) 112 113 #define M_CSUM_IP (M_CSUM_CIP | M_CSUM_CTU) 114 #define M_CSUM_IP6 (M_CSUM_TCPv6 | M_CSUM_UDPv6) 115 #define M_CSUM_TUP (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6) 116 #define M_CSUM_UDP (M_CSUM_UDPv4 | M_CSUM_UDPv6) 117 #define M_CSUM_IP4 (M_CSUM_IPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4) 118 #define M_CSUM_CIP (M_CSUM_IPv4) 119 #define M_CSUM_CTU (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6) 120 121 struct pq3etsec_txqueue { 122 bus_dmamap_t txq_descmap; 123 volatile struct txbd *txq_consumer; 124 volatile struct txbd *txq_producer; 125 volatile struct txbd *txq_first; 126 volatile struct txbd *txq_last; 127 struct ifqueue txq_mbufs; 128 struct mbuf *txq_next; 129 #ifdef ETSEC_DEBUG 130 struct mbuf *txq_lmbufs[512]; 131 #endif 132 uint32_t txq_qmask; 133 uint32_t txq_free; 134 uint32_t txq_threshold; 135 uint32_t txq_lastintr; 136 bus_size_t txq_reg_tbase; 137 bus_dma_segment_t txq_descmap_seg; 138 }; 139 140 struct pq3etsec_rxqueue { 141 bus_dmamap_t rxq_descmap; 142 volatile struct rxbd *rxq_consumer; 143 volatile struct rxbd *rxq_producer; 144 volatile struct rxbd *rxq_first; 145 volatile struct rxbd *rxq_last; 146 struct mbuf *rxq_mhead; 147 struct mbuf **rxq_mtail; 148 struct mbuf *rxq_mconsumer; 149 #ifdef ETSEC_DEBUG 150 struct mbuf *rxq_mbufs[512]; 151 #endif 152 uint32_t rxq_qmask; 153 uint32_t rxq_inuse; 154 uint32_t rxq_threshold; 155 bus_size_t rxq_reg_rbase; 156 bus_size_t rxq_reg_rbptr; 157 bus_dma_segment_t rxq_descmap_seg; 158 }; 159 160 struct pq3etsec_mapcache { 161 u_int dmc_nmaps; 162 u_int dmc_maxseg; 163 u_int dmc_maxmaps; 164 u_int dmc_maxmapsize; 165 bus_dmamap_t dmc_maps[0]; 166 }; 167 168 struct pq3etsec_softc { 169 device_t sc_dev; 170 device_t sc_mdio_dev; 171 struct ethercom sc_ec; 172 #define sc_if sc_ec.ec_if 173 struct mii_data sc_mii; 174 bus_space_tag_t sc_bst; 175 bus_space_handle_t sc_bsh; 176 bus_space_handle_t sc_mdio_bsh; 177 bus_dma_tag_t sc_dmat; 178 int sc_phy_addr; 179 prop_dictionary_t sc_intrmap; 180 uint32_t sc_intrmask; 181 182 uint32_t sc_soft_flags; 183 #define SOFT_RESET 0x0001 184 #define SOFT_RXINTR 0x0010 185 #define SOFT_RXBSY 0x0020 186 #define SOFT_TXINTR 0x0100 187 #define SOFT_TXERROR 0x0200 188 189 struct pq3etsec_txqueue sc_txq; 190 struct pq3etsec_rxqueue sc_rxq; 191 uint32_t sc_txerrors; 192 uint32_t sc_rxerrors; 193 194 size_t sc_rx_adjlen; 195 196 /* 197 * Copies of various ETSEC registers. 198 */ 199 uint32_t sc_imask; 200 uint32_t sc_maccfg1; 201 uint32_t sc_maccfg2; 202 uint32_t sc_maxfrm; 203 uint32_t sc_ecntrl; 204 uint32_t sc_dmactrl; 205 uint32_t sc_macstnaddr1; 206 uint32_t sc_macstnaddr2; 207 uint32_t sc_tctrl; 208 uint32_t sc_rctrl; 209 uint32_t sc_gaddr[16]; 210 uint64_t sc_macaddrs[15]; 211 212 void *sc_tx_ih; 213 void *sc_rx_ih; 214 void *sc_error_ih; 215 void *sc_soft_ih; 216 217 kmutex_t *sc_lock; 218 kmutex_t *sc_hwlock; 219 220 struct evcnt sc_ev_tx_stall; 221 struct evcnt sc_ev_tx_intr; 222 struct evcnt sc_ev_rx_stall; 223 struct evcnt sc_ev_rx_intr; 224 struct evcnt sc_ev_error_intr; 225 struct evcnt sc_ev_soft_intr; 226 struct evcnt sc_ev_tx_pause; 227 struct evcnt sc_ev_rx_pause; 228 struct evcnt sc_ev_mii_ticks; 229 230 struct callout sc_mii_callout; 231 uint64_t sc_mii_last_tick; 232 233 struct ifqueue sc_rx_bufcache; 234 struct pq3etsec_mapcache *sc_rx_mapcache; 235 struct pq3etsec_mapcache *sc_tx_mapcache; 236 237 /* Interrupt Coalescing parameters */ 238 int sc_ic_rx_time; 239 int sc_ic_rx_count; 240 int sc_ic_tx_time; 241 int sc_ic_tx_count; 242 243 krndsource_t rnd_source; 244 }; 245 246 #define ETSEC_IC_RX_ENABLED(sc) \ 247 ((sc)->sc_ic_rx_time != 0 && (sc)->sc_ic_rx_count != 0) 248 #define ETSEC_IC_TX_ENABLED(sc) \ 249 ((sc)->sc_ic_tx_time != 0 && (sc)->sc_ic_tx_count != 0) 250 251 struct pq3mdio_softc { 252 device_t mdio_dev; 253 254 kmutex_t *mdio_lock; 255 256 bus_space_tag_t mdio_bst; 257 bus_space_handle_t mdio_bsh; 258 }; 259 260 static int pq3etsec_match(device_t, cfdata_t, void *); 261 static void pq3etsec_attach(device_t, device_t, void *); 262 263 static int pq3mdio_match(device_t, cfdata_t, void *); 264 static void pq3mdio_attach(device_t, device_t, void *); 265 266 static void pq3etsec_ifstart(struct ifnet *); 267 static void pq3etsec_ifwatchdog(struct ifnet *); 268 static int pq3etsec_ifinit(struct ifnet *); 269 static void pq3etsec_ifstop(struct ifnet *, int); 270 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 271 272 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 273 struct pq3etsec_mapcache **, size_t, size_t, size_t); 274 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 275 struct pq3etsec_mapcache *); 276 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 277 struct pq3etsec_mapcache *); 278 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 279 struct pq3etsec_mapcache *, bus_dmamap_t); 280 281 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 282 struct pq3etsec_txqueue *, u_int); 283 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 284 struct pq3etsec_txqueue *); 285 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 286 struct pq3etsec_txqueue *); 287 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 288 struct pq3etsec_txqueue *); 289 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 290 struct pq3etsec_txqueue *, struct mbuf *m); 291 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 292 struct pq3etsec_txqueue *); 293 294 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 295 struct pq3etsec_rxqueue *, u_int); 296 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 297 struct pq3etsec_rxqueue *); 298 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 299 struct pq3etsec_rxqueue *, bool); 300 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 301 struct pq3etsec_rxqueue *); 302 303 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 304 305 static void pq3etsec_mii_tick(void *); 306 static int pq3etsec_rx_intr(void *); 307 static int pq3etsec_tx_intr(void *); 308 static int pq3etsec_error_intr(void *); 309 static void pq3etsec_soft_intr(void *); 310 311 static void pq3etsec_set_ic_rx(struct pq3etsec_softc *); 312 static void pq3etsec_set_ic_tx(struct pq3etsec_softc *); 313 314 static void pq3etsec_sysctl_setup(struct sysctllog **, struct pq3etsec_softc *); 315 316 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 317 pq3etsec_match, pq3etsec_attach, NULL, NULL); 318 319 CFATTACH_DECL_NEW(pq3mdio_tsec, sizeof(struct pq3mdio_softc), 320 pq3mdio_match, pq3mdio_attach, NULL, NULL); 321 322 CFATTACH_DECL_NEW(pq3mdio_cpunode, sizeof(struct pq3mdio_softc), 323 pq3mdio_match, pq3mdio_attach, NULL, NULL); 324 325 static inline uint32_t 326 etsec_mdio_read(struct pq3mdio_softc *mdio, bus_size_t off) 327 { 328 return bus_space_read_4(mdio->mdio_bst, mdio->mdio_bsh, off); 329 } 330 331 static inline void 332 etsec_mdio_write(struct pq3mdio_softc *mdio, bus_size_t off, uint32_t data) 333 { 334 bus_space_write_4(mdio->mdio_bst, mdio->mdio_bsh, off, data); 335 } 336 337 static inline uint32_t 338 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 339 { 340 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 341 } 342 343 static int 344 pq3mdio_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 345 { 346 return strcmp(cf->cf_name, "mdio") == 0; 347 } 348 349 static int 350 pq3mdio_match(device_t parent, cfdata_t cf, void *aux) 351 { 352 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 353 const bool p1025_p = (svr == (SVR_P1025v1 >> 16) 354 || svr == (SVR_P1016v1 >> 16)); 355 356 if (device_is_a(parent, "cpunode")) { 357 if (!p1025_p 358 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 359 return 0; 360 361 return 1; 362 } 363 364 if (device_is_a(parent, "tsec")) { 365 if (p1025_p 366 || !e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 367 return 0; 368 369 return 1; 370 } 371 372 return 0; 373 } 374 375 static void 376 pq3mdio_attach(device_t parent, device_t self, void *aux) 377 { 378 struct pq3mdio_softc * const mdio = device_private(self); 379 struct cpunode_attach_args * const cna = aux; 380 struct cpunode_locators * const cnl = &cna->cna_locs; 381 382 mdio->mdio_dev = self; 383 mdio->mdio_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 384 385 if (device_is_a(parent, "cpunode")) { 386 struct cpunode_softc * const psc = device_private(parent); 387 psc->sc_children |= cna->cna_childmask; 388 389 mdio->mdio_bst = cna->cna_memt; 390 if (bus_space_map(mdio->mdio_bst, cnl->cnl_addr, 391 cnl->cnl_size, 0, &mdio->mdio_bsh) != 0) { 392 aprint_error(": error mapping registers @ %#x\n", 393 cnl->cnl_addr); 394 return; 395 } 396 } else { 397 struct pq3etsec_softc * const sc = device_private(parent); 398 399 KASSERT(device_is_a(parent, "tsec")); 400 KASSERTMSG(cnl->cnl_addr == ETSEC1_BASE 401 || cnl->cnl_addr == ETSEC2_BASE 402 || cnl->cnl_addr == ETSEC3_BASE 403 || cnl->cnl_addr == ETSEC4_BASE, 404 "unknown tsec addr %x", cnl->cnl_addr); 405 406 mdio->mdio_bst = sc->sc_bst; 407 mdio->mdio_bsh = sc->sc_bsh; 408 } 409 410 aprint_normal("\n"); 411 } 412 413 static int 414 pq3mdio_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 415 { 416 struct pq3mdio_softc * const mdio = device_private(self); 417 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 418 419 mutex_enter(mdio->mdio_lock); 420 421 etsec_mdio_write(mdio, MIIMADD, 422 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 423 424 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 425 etsec_mdio_write(mdio, MIIMCOM, MIIMCOM_READ); 426 427 while (etsec_mdio_read(mdio, MIIMIND) != 0) { 428 delay(1); 429 } 430 *val = etsec_mdio_read(mdio, MIIMSTAT) &0xffff; 431 432 if (miimcom == MIIMCOM_SCAN) 433 etsec_mdio_write(mdio, MIIMCOM, miimcom); 434 435 #if 0 436 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 437 __func__, phy, reg, data); 438 #endif 439 mutex_exit(mdio->mdio_lock); 440 return 0; 441 } 442 443 static int 444 pq3mdio_mii_writereg(device_t self, int phy, int reg, uint16_t data) 445 { 446 struct pq3mdio_softc * const mdio = device_private(self); 447 uint32_t miimcom = etsec_mdio_read(mdio, MIIMCOM); 448 449 #if 0 450 aprint_normal_dev(mdio->mdio_dev, "%s: phy %d reg %d: %#x\n", 451 __func__, phy, reg, data); 452 #endif 453 454 mutex_enter(mdio->mdio_lock); 455 456 etsec_mdio_write(mdio, MIIMADD, 457 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 458 etsec_mdio_write(mdio, MIIMCOM, 0); /* clear any past bits */ 459 etsec_mdio_write(mdio, MIIMCON, data); 460 461 int timo = 1000; /* 1ms */ 462 while ((etsec_mdio_read(mdio, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 463 delay(1); 464 } 465 466 if (miimcom == MIIMCOM_SCAN) 467 etsec_mdio_write(mdio, MIIMCOM, miimcom); 468 469 mutex_exit(mdio->mdio_lock); 470 471 return 0; 472 } 473 474 static inline void 475 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 476 { 477 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 478 } 479 480 static void 481 pq3etsec_mii_statchg(struct ifnet *ifp) 482 { 483 struct pq3etsec_softc * const sc = ifp->if_softc; 484 struct mii_data * const mii = &sc->sc_mii; 485 486 uint32_t maccfg1 = sc->sc_maccfg1; 487 uint32_t maccfg2 = sc->sc_maccfg2; 488 uint32_t ecntrl = sc->sc_ecntrl; 489 490 maccfg1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 491 maccfg2 &= ~(MACCFG2_IFMODE | MACCFG2_FD); 492 493 if (sc->sc_mii.mii_media_active & IFM_FDX) { 494 maccfg2 |= MACCFG2_FD; 495 } 496 497 /* 498 * Now deal with the flow control bits. 499 */ 500 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 501 && (mii->mii_media_active & IFM_ETH_FMASK)) { 502 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 503 maccfg1 |= MACCFG1_RX_FLOW; 504 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 505 maccfg1 |= MACCFG1_TX_FLOW; 506 } 507 508 /* 509 * Now deal with the speed. 510 */ 511 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 512 maccfg2 |= MACCFG2_IFMODE_GMII; 513 } else { 514 maccfg2 |= MACCFG2_IFMODE_MII; 515 ecntrl &= ~ECNTRL_R100M; 516 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 517 ecntrl |= ECNTRL_R100M; 518 } 519 } 520 521 /* 522 * If things are different, re-init things. 523 */ 524 if (maccfg1 != sc->sc_maccfg1 525 || maccfg2 != sc->sc_maccfg2 526 || ecntrl != sc->sc_ecntrl) { 527 if (sc->sc_if.if_flags & IFF_RUNNING) 528 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 529 sc->sc_maccfg1 = maccfg1; 530 sc->sc_maccfg2 = maccfg2; 531 sc->sc_ecntrl = ecntrl; 532 } 533 } 534 535 #if 0 536 static void 537 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 538 { 539 struct pq3etsec_softc * const sc = ifp->if_softc; 540 541 mii_pollstat(&sc->sc_mii); 542 ether_mediastatus(ifp, ifmr); 543 ifmr->ifm_status = sc->sc_mii.mii_media_status; 544 ifmr->ifm_active = sc->sc_mii.mii_media_active; 545 } 546 547 static int 548 pq3etsec_mediachange(struct ifnet *ifp) 549 { 550 struct pq3etsec_softc * const sc = ifp->if_softc; 551 552 if ((ifp->if_flags & IFF_UP) == 0) 553 return 0; 554 555 int rv = mii_mediachg(&sc->sc_mii); 556 return (rv == ENXIO) ? 0 : rv; 557 } 558 #endif 559 560 static int 561 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 562 { 563 564 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 565 return 0; 566 567 return 1; 568 } 569 570 static void 571 pq3etsec_attach(device_t parent, device_t self, void *aux) 572 { 573 struct cpunode_softc * const psc = device_private(parent); 574 struct pq3etsec_softc * const sc = device_private(self); 575 struct mii_data * const mii = &sc->sc_mii; 576 struct cpunode_attach_args * const cna = aux; 577 struct cpunode_locators * const cnl = &cna->cna_locs; 578 cfdata_t cf = device_cfdata(self); 579 int error; 580 581 psc->sc_children |= cna->cna_childmask; 582 sc->sc_dev = self; 583 sc->sc_bst = cna->cna_memt; 584 sc->sc_dmat = &booke_bus_dma_tag; 585 586 /* 587 * Pull out the mdio bus and phy we are supposed to use. 588 */ 589 const int mdio = cf->cf_loc[CPUNODECF_MDIO]; 590 const int phy = cf->cf_loc[CPUNODECF_PHY]; 591 if (mdio != CPUNODECF_MDIO_DEFAULT) 592 aprint_normal(" mdio %d", mdio); 593 594 /* 595 * See if the phy is in the config file... 596 */ 597 if (phy != CPUNODECF_PHY_DEFAULT) { 598 sc->sc_phy_addr = phy; 599 } else { 600 unsigned char prop_name[20]; 601 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 602 cnl->cnl_instance); 603 sc->sc_phy_addr = board_info_get_number(prop_name); 604 } 605 if (sc->sc_phy_addr != MII_PHY_ANY) 606 aprint_normal(" phy %d", sc->sc_phy_addr); 607 608 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 609 &sc->sc_bsh); 610 if (error) { 611 aprint_error(": error mapping registers: %d\n", error); 612 return; 613 } 614 615 /* 616 * Assume firmware has aready set the mac address and fetch it 617 * before we reinit it. 618 */ 619 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 620 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 621 sc->sc_rctrl = RCTRL_DEFAULT; 622 sc->sc_ecntrl = etsec_read(sc, ECNTRL); 623 sc->sc_maccfg1 = etsec_read(sc, MACCFG1); 624 sc->sc_maccfg2 = etsec_read(sc, MACCFG2) | MACCFG2_DEFAULT; 625 626 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 627 size_t len; 628 const uint8_t *mac_addr = 629 board_info_get_data("tsec-mac-addr-base", &len); 630 KASSERT(len == ETHER_ADDR_LEN); 631 sc->sc_macstnaddr2 = 632 (mac_addr[1] << 24) 633 | (mac_addr[0] << 16); 634 sc->sc_macstnaddr1 = 635 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 636 | (mac_addr[4] << 16) 637 | (mac_addr[3] << 8) 638 | (mac_addr[2] << 0); 639 #if 0 640 aprint_error(": mac-address unknown\n"); 641 return; 642 #endif 643 } 644 645 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 646 sc->sc_hwlock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_VM); 647 648 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 649 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 650 651 /* Disable interrupts */ 652 etsec_write(sc, IMASK, 0); 653 654 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 655 if (error) { 656 aprint_error(": failed to init rxq: %d\n", error); 657 goto fail_1; 658 } 659 660 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 661 if (error) { 662 aprint_error(": failed to init txq: %d\n", error); 663 goto fail_2; 664 } 665 666 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 667 ETSEC_MAXRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 668 if (error) { 669 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 670 goto fail_3; 671 } 672 673 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 674 ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 675 if (error) { 676 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 677 goto fail_4; 678 } 679 680 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 681 pq3etsec_tx_intr, sc); 682 if (sc->sc_tx_ih == NULL) { 683 aprint_error(": failed to establish tx interrupt: %d\n", 684 cnl->cnl_intrs[0]); 685 goto fail_5; 686 } 687 688 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 689 pq3etsec_rx_intr, sc); 690 if (sc->sc_rx_ih == NULL) { 691 aprint_error(": failed to establish rx interrupt: %d\n", 692 cnl->cnl_intrs[1]); 693 goto fail_6; 694 } 695 696 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 697 pq3etsec_error_intr, sc); 698 if (sc->sc_error_ih == NULL) { 699 aprint_error(": failed to establish error interrupt: %d\n", 700 cnl->cnl_intrs[2]); 701 goto fail_7; 702 } 703 704 int softint_flags = SOFTINT_NET; 705 #if !defined(MULTIPROCESSOR) || defined(NET_MPSAFE) 706 softint_flags |= SOFTINT_MPSAFE; 707 #endif /* !MULTIPROCESSOR || NET_MPSAFE */ 708 sc->sc_soft_ih = softint_establish(softint_flags, 709 pq3etsec_soft_intr, sc); 710 if (sc->sc_soft_ih == NULL) { 711 aprint_error(": failed to establish soft interrupt\n"); 712 goto fail_8; 713 } 714 715 /* 716 * If there was no MDIO 717 */ 718 if (mdio == CPUNODECF_MDIO_DEFAULT) { 719 aprint_normal("\n"); 720 cfdata_t mdio_cf = config_search(self, cna, 721 CFARGS(.submatch = pq3mdio_find)); 722 if (mdio_cf != NULL) { 723 sc->sc_mdio_dev = 724 config_attach(self, mdio_cf, cna, NULL, CFARGS_NONE); 725 } 726 } else { 727 sc->sc_mdio_dev = device_find_by_driver_unit("mdio", mdio); 728 if (sc->sc_mdio_dev == NULL) { 729 aprint_error(": failed to locate mdio device\n"); 730 goto fail_9; 731 } 732 aprint_normal("\n"); 733 } 734 735 etsec_write(sc, ATTR, ATTR_DEFAULT); 736 etsec_write(sc, ATTRELI, ATTRELI_DEFAULT); 737 738 /* Enable interrupt coalesing */ 739 sc->sc_ic_rx_time = 768; 740 sc->sc_ic_rx_count = 16; 741 sc->sc_ic_tx_time = 768; 742 sc->sc_ic_tx_count = 16; 743 pq3etsec_set_ic_rx(sc); 744 pq3etsec_set_ic_tx(sc); 745 746 char enaddr[ETHER_ADDR_LEN] = { 747 [0] = sc->sc_macstnaddr2 >> 16, 748 [1] = sc->sc_macstnaddr2 >> 24, 749 [2] = sc->sc_macstnaddr1 >> 0, 750 [3] = sc->sc_macstnaddr1 >> 8, 751 [4] = sc->sc_macstnaddr1 >> 16, 752 [5] = sc->sc_macstnaddr1 >> 24, 753 }; 754 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 755 ether_sprintf(enaddr)); 756 757 const char * const xname = device_xname(sc->sc_dev); 758 struct ethercom * const ec = &sc->sc_ec; 759 struct ifnet * const ifp = &ec->ec_if; 760 761 ec->ec_mii = mii; 762 763 mii->mii_ifp = ifp; 764 mii->mii_readreg = pq3mdio_mii_readreg; 765 mii->mii_writereg = pq3mdio_mii_writereg; 766 mii->mii_statchg = pq3etsec_mii_statchg; 767 768 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 769 770 if (sc->sc_mdio_dev != NULL && sc->sc_phy_addr < 32) { 771 mii_attach(sc->sc_mdio_dev, mii, 0xffffffff, 772 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 773 774 if (LIST_FIRST(&mii->mii_phys) == NULL) { 775 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 776 0, NULL); 777 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 778 } else { 779 callout_schedule(&sc->sc_mii_callout, hz); 780 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 781 } 782 } else { 783 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 784 0, NULL); 785 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_1000_T | IFM_FDX); 786 } 787 788 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 789 | ETHERCAP_JUMBO_MTU; 790 ec->ec_capenable = ETHERCAP_VLAN_HWTAGGING; 791 792 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 793 ifp->if_softc = sc; 794 ifp->if_capabilities = IFCAP_ETSEC; 795 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 796 ifp->if_ioctl = pq3etsec_ifioctl; 797 ifp->if_start = pq3etsec_ifstart; 798 ifp->if_watchdog = pq3etsec_ifwatchdog; 799 ifp->if_init = pq3etsec_ifinit; 800 ifp->if_stop = pq3etsec_ifstop; 801 IFQ_SET_READY(&ifp->if_snd); 802 803 /* 804 * Attach the interface. 805 */ 806 if_initialize(ifp); 807 pq3etsec_sysctl_setup(NULL, sc); 808 if_attach(ifp); 809 if_deferred_start_init(ifp, NULL); 810 ether_ifattach(ifp, enaddr); 811 812 rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, 813 RND_FLAG_DEFAULT); 814 815 pq3etsec_ifstop(ifp, true); 816 817 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 818 NULL, xname, "rx stall"); 819 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 820 NULL, xname, "tx stall"); 821 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 822 NULL, xname, "tx intr"); 823 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 824 NULL, xname, "rx intr"); 825 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 826 NULL, xname, "error intr"); 827 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 828 NULL, xname, "soft intr"); 829 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 830 NULL, xname, "tx pause"); 831 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 832 NULL, xname, "rx pause"); 833 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 834 NULL, xname, "mii ticks"); 835 return; 836 837 fail_9: 838 softint_disestablish(sc->sc_soft_ih); 839 fail_8: 840 intr_disestablish(sc->sc_error_ih); 841 fail_7: 842 intr_disestablish(sc->sc_rx_ih); 843 fail_6: 844 intr_disestablish(sc->sc_tx_ih); 845 fail_5: 846 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 847 fail_4: 848 pq3etsec_mapcache_destroy(sc, sc->sc_rx_mapcache); 849 fail_3: 850 #if 0 /* notyet */ 851 pq3etsec_txq_detach(sc); 852 #endif 853 fail_2: 854 #if 0 /* notyet */ 855 pq3etsec_rxq_detach(sc); 856 #endif 857 fail_1: 858 callout_destroy(&sc->sc_mii_callout); 859 mutex_obj_free(sc->sc_lock); 860 mutex_obj_free(sc->sc_hwlock); 861 bus_space_unmap(sc->sc_bst, sc->sc_bsh, cnl->cnl_size); 862 } 863 864 static uint64_t 865 pq3etsec_macaddr_create(const uint8_t *lladdr) 866 { 867 uint64_t macaddr = 0; 868 869 lladdr += ETHER_ADDR_LEN; 870 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 871 macaddr = (macaddr << 8) | *--lladdr; 872 } 873 return macaddr << 16; 874 } 875 876 static int 877 pq3etsec_ifinit(struct ifnet *ifp) 878 { 879 struct pq3etsec_softc * const sc = ifp->if_softc; 880 int error = 0; 881 882 sc->sc_maxfrm = uimax(ifp->if_mtu + 32, MCLBYTES); 883 if (ifp->if_mtu > ETHERMTU_JUMBO) 884 return error; 885 886 KASSERT(ifp->if_flags & IFF_UP); 887 888 /* 889 * Stop the interface (steps 1 to 4 in the Soft Reset and 890 * Reconfigurating Procedure. 891 */ 892 pq3etsec_ifstop(ifp, 0); 893 894 /* 895 * If our frame size has changed (or it's our first time through) 896 * destroy the existing transmit mapcache. 897 */ 898 if (sc->sc_tx_mapcache != NULL 899 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 900 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 901 sc->sc_tx_mapcache = NULL; 902 } 903 904 if (sc->sc_tx_mapcache == NULL) { 905 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 906 ETSEC_MAXTXMBUFS, sc->sc_maxfrm, ETSEC_NTXSEGS); 907 if (error) 908 return error; 909 } 910 911 sc->sc_ev_mii_ticks.ev_count++; 912 mii_tick(&sc->sc_mii); 913 914 if (ifp->if_flags & IFF_PROMISC) { 915 sc->sc_rctrl |= RCTRL_PROM; 916 } else { 917 sc->sc_rctrl &= ~RCTRL_PROM; 918 } 919 920 uint32_t rctrl_prsdep = 0; 921 sc->sc_rctrl &= 922 ~(RCTRL_IPCSEN | RCTRL_TUCSEN | RCTRL_VLEX | RCTRL_PRSDEP); 923 if (VLAN_ATTACHED(&sc->sc_ec)) { 924 sc->sc_rctrl |= RCTRL_VLEX; 925 rctrl_prsdep = RCTRL_PRSDEP_L2; 926 } 927 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 928 sc->sc_rctrl |= RCTRL_IPCSEN; 929 rctrl_prsdep = RCTRL_PRSDEP_L3; 930 } 931 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 932 sc->sc_rctrl |= RCTRL_TUCSEN; 933 rctrl_prsdep = RCTRL_PRSDEP_L4; 934 } 935 sc->sc_rctrl |= rctrl_prsdep; 936 #if 0 937 if (sc->sc_rctrl 938 & (RCTRL_IPCSEN | RCTRL_TUCSEN | RCTRL_VLEX | RCTRL_PRSDEP)) 939 aprint_normal_dev(sc->sc_dev, 940 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 941 sc->sc_rctrl, 942 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 943 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 944 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 945 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 946 #endif 947 948 sc->sc_tctrl &= ~(TCTRL_IPCSEN | TCTRL_TUCSEN | TCTRL_VLINS); 949 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 950 sc->sc_tctrl |= TCTRL_VLINS; 951 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 952 sc->sc_tctrl |= TCTRL_IPCSEN; 953 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 954 sc->sc_tctrl |= TCTRL_TUCSEN; 955 #if 0 956 if (sc->sc_tctrl & (TCTRL_IPCSEN | TCTRL_TUCSEN | TCTRL_VLINS)) 957 aprint_normal_dev(sc->sc_dev, 958 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 959 sc->sc_tctrl, 960 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 961 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 962 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 963 #endif 964 965 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 966 967 const uint64_t macstnaddr = 968 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 969 970 sc->sc_imask = IEVENT_DPE; 971 972 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 973 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 974 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 975 976 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 977 pq3etsec_txq_reset(sc, &sc->sc_txq); 978 979 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 980 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 981 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 982 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 983 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 984 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 985 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 986 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 987 988 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 989 pq3etsec_mc_setup(sc); 990 991 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 992 etsec_write(sc, MRBLR, MCLBYTES); 993 994 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 995 sc->sc_dmactrl |= DMACTRL_DEFAULT; 996 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 997 998 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 999 etsec_write(sc, TQUEUE, TQUEUE_EN0); 1000 sc->sc_imask |= IEVENT_TXF | IEVENT_TXE | IEVENT_TXC; 1001 1002 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 1003 1004 /* 12. Enable receive queues in RQUEUE, */ 1005 etsec_write(sc, RQUEUE, RQUEUE_EN0 | RQUEUE_EX0); 1006 sc->sc_imask |= IEVENT_RXF | IEVENT_BSY | IEVENT_RXC; 1007 1008 /* and optionally set TOE functionality in RCTRL. */ 1009 etsec_write(sc, RCTRL, sc->sc_rctrl); 1010 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 1011 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 1012 sc->sc_rx_adjlen += sizeof(struct rxfcb); 1013 1014 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 1015 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 1016 1017 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 1018 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 1019 1020 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 1021 sc->sc_dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 1022 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1023 1024 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 1025 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1026 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 1027 1028 sc->sc_soft_flags = 0; 1029 1030 etsec_write(sc, IMASK, sc->sc_imask); 1031 1032 ifp->if_flags |= IFF_RUNNING; 1033 1034 return error; 1035 } 1036 1037 static void 1038 pq3etsec_ifstop(struct ifnet *ifp, int disable) 1039 { 1040 struct pq3etsec_softc * const sc = ifp->if_softc; 1041 1042 KASSERT(!cpu_intr_p()); 1043 const uint32_t imask_gsc_mask = IEVENT_GTSC | IEVENT_GRSC; 1044 /* 1045 * Clear the GTSC and GRSC from the interrupt mask until 1046 * we are ready for them. Then clear them from IEVENT, 1047 * request the graceful shutdown, and then enable the 1048 * GTSC and GRSC bits in the mask. This should cause the 1049 * error interrupt to fire which will issue a wakeup to 1050 * allow us to resume. 1051 */ 1052 1053 /* 1054 * 1. Set GRS/GTS bits in DMACTRL register 1055 */ 1056 sc->sc_dmactrl |= DMACTRL_GRS | DMACTRL_GTS; 1057 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 1058 etsec_write(sc, IEVENT, imask_gsc_mask); 1059 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 1060 1061 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN | MACCFG1_RX_EN)) { 1062 /* 1063 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 1064 */ 1065 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 1066 1067 u_int timo = 1000; 1068 uint32_t ievent = etsec_read(sc, IEVENT); 1069 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 1070 if (--timo == 0) { 1071 aprint_error_dev(sc->sc_dev, 1072 "WARNING: " 1073 "request to stop failed (IEVENT=%#x)\n", 1074 ievent); 1075 break; 1076 } 1077 delay(10); 1078 ievent = etsec_read(sc, IEVENT); 1079 } 1080 } 1081 1082 /* 1083 * Now reset the controller. 1084 * 1085 * 3. Set SOFT_RESET bit in MACCFG1 register 1086 * 4. Clear SOFT_RESET bit in MACCFG1 register 1087 */ 1088 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 1089 etsec_write(sc, MACCFG1, 0); 1090 etsec_write(sc, IMASK, 0); 1091 etsec_write(sc, IEVENT, ~0); 1092 sc->sc_imask = 0; 1093 ifp->if_flags &= ~IFF_RUNNING; 1094 1095 uint32_t tbipa = etsec_read(sc, TBIPA); 1096 if (tbipa == sc->sc_phy_addr) { 1097 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 1098 etsec_write(sc, TBIPA, 0x1f); 1099 } 1100 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 1101 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 1102 etsec_write(sc, MIIMCFG, miimcfg); 1103 1104 /* 1105 * Let's consume any remaing transmitted packets. And if we are 1106 * disabling the interface, purge ourselves of any untransmitted 1107 * packets. But don't consume any received packets, just drop them. 1108 * If we aren't disabling the interface, save the mbufs in the 1109 * receive queue for reuse. 1110 */ 1111 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 1112 pq3etsec_txq_consume(sc, &sc->sc_txq); 1113 if (disable) { 1114 pq3etsec_txq_purge(sc, &sc->sc_txq); 1115 IFQ_PURGE(&ifp->if_snd); 1116 } 1117 } 1118 1119 static void 1120 pq3etsec_ifwatchdog(struct ifnet *ifp) 1121 { 1122 } 1123 1124 static void 1125 pq3etsec_mc_setup( 1126 struct pq3etsec_softc *sc) 1127 { 1128 struct ethercom * const ec = &sc->sc_ec; 1129 struct ifnet * const ifp = &sc->sc_if; 1130 struct ether_multi *enm; 1131 struct ether_multistep step; 1132 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 1133 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 1134 1135 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 1136 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1137 1138 ifp->if_flags &= ~IFF_ALLMULTI; 1139 1140 ETHER_LOCK(ec); 1141 ETHER_FIRST_MULTI(step, ec, enm); 1142 for (u_int i = 0; enm != NULL; ) { 1143 const char *addr = enm->enm_addrlo; 1144 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1145 ifp->if_flags |= IFF_ALLMULTI; 1146 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 1147 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 1148 break; 1149 } 1150 if ((sc->sc_rctrl & RCTRL_EMEN) 1151 && i < __arraycount(sc->sc_macaddrs)) { 1152 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 1153 } else { 1154 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1155 #if 0 1156 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 1157 ether_sprintf(addr), crc, 1158 crc >> crc_shift, 1159 crc >> (crc_shift + 5), 1160 (crc >> crc_shift) & 31, 1161 1 << (((crc >> crc_shift) & 31) ^ 31)); 1162 #endif 1163 /* 1164 * The documentation doesn't completely follow PowerPC 1165 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 1166 * is 0x7fa32d9b. By empirical testing, the 1167 * corresponding hash bit is word 3, bit 31 (ppc bit 1168 * order). Since 3 << 31 | 31 is 0x7f, we deduce 1169 * H[0:2] selects the register while H[3:7] selects 1170 * the bit (ppc bit order). 1171 */ 1172 crc >>= crc_shift; 1173 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 1174 } 1175 ETHER_NEXT_MULTI(step, enm); 1176 } 1177 ETHER_UNLOCK(ec); 1178 for (u_int i = 0; i < 8; i++) { 1179 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 1180 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 1181 #if 0 1182 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 1183 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 1184 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 1185 i, GADDR(i), etsec_read(sc, GADDR(i))); 1186 #endif 1187 } 1188 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 1189 uint64_t macaddr = sc->sc_macaddrs[i]; 1190 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 1191 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 1192 #if 0 1193 if (macaddr) 1194 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 1195 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1196 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1197 #endif 1198 } 1199 } 1200 1201 static int 1202 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1203 { 1204 struct pq3etsec_softc *sc = ifp->if_softc; 1205 struct ifreq * const ifr = data; 1206 const int s = splnet(); 1207 int error; 1208 1209 switch (cmd) { 1210 case SIOCSIFMEDIA: 1211 /* Flow control requires full-duplex mode. */ 1212 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1213 (ifr->ifr_media & IFM_FDX) == 0) 1214 ifr->ifr_media &= ~IFM_ETH_FMASK; 1215 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1216 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1217 /* We can do both TXPAUSE and RXPAUSE. */ 1218 ifr->ifr_media |= 1219 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1220 } 1221 } 1222 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1223 break; 1224 1225 default: 1226 error = ether_ioctl(ifp, cmd, data); 1227 if (error != ENETRESET) 1228 break; 1229 1230 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1231 error = 0; 1232 if (ifp->if_flags & IFF_RUNNING) 1233 pq3etsec_mc_setup(sc); 1234 break; 1235 } 1236 error = pq3etsec_ifinit(ifp); 1237 break; 1238 } 1239 1240 splx(s); 1241 return error; 1242 } 1243 1244 static void 1245 pq3etsec_rxq_desc_presync( 1246 struct pq3etsec_softc *sc, 1247 struct pq3etsec_rxqueue *rxq, 1248 volatile struct rxbd *rxbd, 1249 size_t count) 1250 { 1251 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1252 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1253 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1254 } 1255 1256 static void 1257 pq3etsec_rxq_desc_postsync( 1258 struct pq3etsec_softc *sc, 1259 struct pq3etsec_rxqueue *rxq, 1260 volatile struct rxbd *rxbd, 1261 size_t count) 1262 { 1263 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1264 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1265 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1266 } 1267 1268 static void 1269 pq3etsec_txq_desc_presync( 1270 struct pq3etsec_softc *sc, 1271 struct pq3etsec_txqueue *txq, 1272 volatile struct txbd *txbd, 1273 size_t count) 1274 { 1275 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1276 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1277 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1278 } 1279 1280 static void 1281 pq3etsec_txq_desc_postsync( 1282 struct pq3etsec_softc *sc, 1283 struct pq3etsec_txqueue *txq, 1284 volatile struct txbd *txbd, 1285 size_t count) 1286 { 1287 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1288 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1289 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1290 } 1291 1292 static bus_dmamap_t 1293 pq3etsec_mapcache_get( 1294 struct pq3etsec_softc *sc, 1295 struct pq3etsec_mapcache *dmc) 1296 { 1297 KASSERT(dmc->dmc_nmaps > 0); 1298 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1299 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1300 } 1301 1302 static void 1303 pq3etsec_mapcache_put( 1304 struct pq3etsec_softc *sc, 1305 struct pq3etsec_mapcache *dmc, 1306 bus_dmamap_t map) 1307 { 1308 KASSERT(map != NULL); 1309 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1310 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1311 } 1312 1313 static void 1314 pq3etsec_mapcache_destroy( 1315 struct pq3etsec_softc *sc, 1316 struct pq3etsec_mapcache *dmc) 1317 { 1318 const size_t dmc_size = 1319 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1320 1321 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1322 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1323 } 1324 kmem_intr_free(dmc, dmc_size); 1325 } 1326 1327 static int 1328 pq3etsec_mapcache_create( 1329 struct pq3etsec_softc *sc, 1330 struct pq3etsec_mapcache **dmc_p, 1331 size_t maxmaps, 1332 size_t maxmapsize, 1333 size_t maxseg) 1334 { 1335 const size_t dmc_size = 1336 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1337 struct pq3etsec_mapcache * const dmc = 1338 kmem_intr_zalloc(dmc_size, KM_NOSLEEP); 1339 1340 dmc->dmc_maxmaps = maxmaps; 1341 dmc->dmc_nmaps = maxmaps; 1342 dmc->dmc_maxmapsize = maxmapsize; 1343 dmc->dmc_maxseg = maxseg; 1344 1345 for (u_int i = 0; i < maxmaps; i++) { 1346 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1347 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1348 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1349 if (error) { 1350 aprint_error_dev(sc->sc_dev, 1351 "failed to creat dma map cache " 1352 "entry %u of %zu: %d\n", 1353 i, maxmaps, error); 1354 while (i-- > 0) { 1355 bus_dmamap_destroy(sc->sc_dmat, 1356 dmc->dmc_maps[i]); 1357 } 1358 kmem_intr_free(dmc, dmc_size); 1359 return error; 1360 } 1361 KASSERT(dmc->dmc_maps[i] != NULL); 1362 } 1363 1364 *dmc_p = dmc; 1365 1366 return 0; 1367 } 1368 1369 #if 0 1370 static void 1371 pq3etsec_dmamem_free( 1372 bus_dma_tag_t dmat, 1373 size_t map_size, 1374 bus_dma_segment_t *seg, 1375 bus_dmamap_t map, 1376 void *kvap) 1377 { 1378 bus_dmamap_destroy(dmat, map); 1379 bus_dmamem_unmap(dmat, kvap, map_size); 1380 bus_dmamem_free(dmat, seg, 1); 1381 } 1382 #endif 1383 1384 static int 1385 pq3etsec_dmamem_alloc( 1386 bus_dma_tag_t dmat, 1387 size_t map_size, 1388 bus_dma_segment_t *seg, 1389 bus_dmamap_t *map, 1390 void **kvap) 1391 { 1392 int error; 1393 int nseg; 1394 1395 *kvap = NULL; 1396 *map = NULL; 1397 1398 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1399 seg, 1, &nseg, 0); 1400 if (error) 1401 return error; 1402 1403 KASSERT(nseg == 1); 1404 1405 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1406 BUS_DMA_COHERENT); 1407 if (error == 0) { 1408 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1409 map); 1410 if (error == 0) { 1411 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1412 NULL, 0); 1413 if (error == 0) 1414 return 0; 1415 bus_dmamap_destroy(dmat, *map); 1416 *map = NULL; 1417 } 1418 bus_dmamem_unmap(dmat, *kvap, map_size); 1419 *kvap = NULL; 1420 } 1421 bus_dmamem_free(dmat, seg, nseg); 1422 return 0; 1423 } 1424 1425 static struct mbuf * 1426 pq3etsec_rx_buf_alloc( 1427 struct pq3etsec_softc *sc) 1428 { 1429 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1430 if (m == NULL) { 1431 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1432 return NULL; 1433 } 1434 MCLGET(m, M_DONTWAIT); 1435 if ((m->m_flags & M_EXT) == 0) { 1436 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1437 m_freem(m); 1438 return NULL; 1439 } 1440 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1441 1442 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1443 if (map == NULL) { 1444 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1445 m_freem(m); 1446 return NULL; 1447 } 1448 M_SETCTX(m, map); 1449 m->m_len = m->m_pkthdr.len = MCLBYTES; 1450 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1451 BUS_DMA_READ | BUS_DMA_NOWAIT); 1452 if (error) { 1453 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1454 error); 1455 M_SETCTX(m, NULL); 1456 m_freem(m); 1457 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1458 return NULL; 1459 } 1460 KASSERT(map->dm_mapsize == MCLBYTES); 1461 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1462 BUS_DMASYNC_PREREAD); 1463 1464 return m; 1465 } 1466 1467 static void 1468 pq3etsec_rx_map_unload( 1469 struct pq3etsec_softc *sc, 1470 struct mbuf *m) 1471 { 1472 KASSERT(m); 1473 for (; m != NULL; m = m->m_next) { 1474 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1475 KASSERT(map); 1476 KASSERT(map->dm_mapsize == MCLBYTES); 1477 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1478 BUS_DMASYNC_POSTREAD); 1479 bus_dmamap_unload(sc->sc_dmat, map); 1480 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1481 M_SETCTX(m, NULL); 1482 } 1483 } 1484 1485 static bool 1486 pq3etsec_rxq_produce( 1487 struct pq3etsec_softc *sc, 1488 struct pq3etsec_rxqueue *rxq) 1489 { 1490 volatile struct rxbd *producer = rxq->rxq_producer; 1491 #if 0 1492 size_t inuse = rxq->rxq_inuse; 1493 #endif 1494 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1495 struct mbuf *m; 1496 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1497 if (m == NULL) { 1498 m = pq3etsec_rx_buf_alloc(sc); 1499 if (m == NULL) { 1500 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1501 break; 1502 } 1503 } 1504 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1505 KASSERT(map); 1506 1507 #ifdef ETSEC_DEBUG 1508 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1509 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1510 #endif 1511 1512 /* rxbd_len is write-only by the ETSEC */ 1513 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1514 membar_producer(); 1515 producer->rxbd_flags |= RXBD_E; 1516 if (__predict_false(rxq->rxq_mhead == NULL)) { 1517 KASSERT(producer == rxq->rxq_consumer); 1518 rxq->rxq_mconsumer = m; 1519 } 1520 *rxq->rxq_mtail = m; 1521 rxq->rxq_mtail = &m->m_next; 1522 m->m_len = MCLBYTES; 1523 m->m_next = NULL; 1524 rxq->rxq_inuse++; 1525 if (++producer == rxq->rxq_last) { 1526 membar_producer(); 1527 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1528 rxq->rxq_last - rxq->rxq_producer); 1529 producer = rxq->rxq_producer = rxq->rxq_first; 1530 } 1531 } 1532 if (producer != rxq->rxq_producer) { 1533 membar_producer(); 1534 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1535 producer - rxq->rxq_producer); 1536 rxq->rxq_producer = producer; 1537 } 1538 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1539 if (qhlt) { 1540 KASSERT(qhlt & rxq->rxq_qmask); 1541 sc->sc_ev_rx_stall.ev_count++; 1542 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1543 } 1544 #if 0 1545 aprint_normal_dev(sc->sc_dev, 1546 "%s: buffers inuse went from %zu to %zu\n", 1547 __func__, inuse, rxq->rxq_inuse); 1548 #endif 1549 return true; 1550 } 1551 1552 static bool 1553 pq3etsec_rx_offload( 1554 struct pq3etsec_softc *sc, 1555 struct mbuf *m, 1556 const struct rxfcb *fcb) 1557 { 1558 if (fcb->rxfcb_flags & RXFCB_VLN) { 1559 vlan_set_tag(m, fcb->rxfcb_vlctl); 1560 } 1561 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1562 || (fcb->rxfcb_flags & (RXFCB_CIP | RXFCB_CTU)) == 0) 1563 return true; 1564 int csum_flags = 0; 1565 if ((fcb->rxfcb_flags & (RXFCB_IP6 | RXFCB_CIP)) == RXFCB_CIP) { 1566 csum_flags |= M_CSUM_IPv4; 1567 if (fcb->rxfcb_flags & RXFCB_EIP) 1568 csum_flags |= M_CSUM_IPv4_BAD; 1569 } 1570 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1571 int ipv_flags; 1572 if (fcb->rxfcb_flags & RXFCB_IP6) 1573 ipv_flags = M_CSUM_TCPv6 | M_CSUM_UDPv6; 1574 else 1575 ipv_flags = M_CSUM_TCPv4 | M_CSUM_UDPv4; 1576 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1577 csum_flags |= (M_CSUM_TCPv4 |M_CSUM_TCPv6) & ipv_flags; 1578 } else { 1579 csum_flags |= (M_CSUM_UDPv4 |M_CSUM_UDPv6) & ipv_flags; 1580 } 1581 if (fcb->rxfcb_flags & RXFCB_ETU) 1582 csum_flags |= M_CSUM_TCP_UDP_BAD; 1583 } 1584 1585 m->m_pkthdr.csum_flags = csum_flags; 1586 return true; 1587 } 1588 1589 static void 1590 pq3etsec_rx_input( 1591 struct pq3etsec_softc *sc, 1592 struct mbuf *m, 1593 uint16_t rxbd_flags) 1594 { 1595 struct ifnet * const ifp = &sc->sc_if; 1596 1597 pq3etsec_rx_map_unload(sc, m); 1598 1599 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1600 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1601 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1602 return; 1603 } 1604 m_adj(m, sc->sc_rx_adjlen); 1605 1606 if (rxbd_flags & RXBD_M) 1607 m->m_flags |= M_PROMISC; 1608 if (rxbd_flags & RXBD_BC) 1609 m->m_flags |= M_BCAST; 1610 if (rxbd_flags & RXBD_MC) 1611 m->m_flags |= M_MCAST; 1612 m->m_flags |= M_HASFCS; 1613 m_set_rcvif(m, &sc->sc_if); 1614 1615 /* 1616 * Let's give it to the network subsystm to deal with. 1617 */ 1618 if_percpuq_enqueue(ifp->if_percpuq, m); 1619 } 1620 1621 static void 1622 pq3etsec_rxq_consume( 1623 struct pq3etsec_softc *sc, 1624 struct pq3etsec_rxqueue *rxq) 1625 { 1626 struct ifnet * const ifp = &sc->sc_if; 1627 volatile struct rxbd *consumer = rxq->rxq_consumer; 1628 size_t rxconsumed = 0; 1629 1630 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1631 1632 for (;;) { 1633 if (consumer == rxq->rxq_producer) { 1634 rxq->rxq_consumer = consumer; 1635 rxq->rxq_inuse -= rxconsumed; 1636 KASSERT(rxq->rxq_inuse == 0); 1637 break; 1638 } 1639 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1640 const uint16_t rxbd_flags = consumer->rxbd_flags; 1641 if (rxbd_flags & RXBD_E) { 1642 rxq->rxq_consumer = consumer; 1643 rxq->rxq_inuse -= rxconsumed; 1644 break; 1645 } 1646 KASSERT(rxq->rxq_mconsumer != NULL); 1647 #ifdef ETSEC_DEBUG 1648 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1649 #endif 1650 #if 0 1651 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1652 __func__, 1653 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1654 mtod(rxq->rxq_mconsumer, int *)[0], 1655 mtod(rxq->rxq_mconsumer, int *)[1], 1656 mtod(rxq->rxq_mconsumer, int *)[2], 1657 mtod(rxq->rxq_mconsumer, int *)[3]); 1658 #endif 1659 /* 1660 * We own this packet again. Clear all flags except wrap. 1661 */ 1662 rxconsumed++; 1663 consumer->rxbd_flags = rxbd_flags & (RXBD_W | RXBD_I); 1664 1665 /* 1666 * If this descriptor has the LAST bit set and no errors, 1667 * it's a valid input packet. 1668 */ 1669 if ((rxbd_flags & (RXBD_L | RXBD_ERRORS)) == RXBD_L) { 1670 size_t rxbd_len = consumer->rxbd_len; 1671 struct mbuf *m = rxq->rxq_mhead; 1672 struct mbuf *m_last = rxq->rxq_mconsumer; 1673 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1674 rxq->rxq_mtail = &rxq->rxq_mhead; 1675 rxq->rxq_mconsumer = rxq->rxq_mhead; 1676 m_last->m_next = NULL; 1677 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1678 m->m_pkthdr.len = rxbd_len; 1679 pq3etsec_rx_input(sc, m, rxbd_flags); 1680 } else if (rxbd_flags & RXBD_L) { 1681 KASSERT(rxbd_flags & RXBD_ERRORS); 1682 struct mbuf *m; 1683 /* 1684 * We encountered an error, take the mbufs and add 1685 * then to the rx bufcache so we can reuse them. 1686 */ 1687 if_statinc(ifp, if_ierrors); 1688 for (m = rxq->rxq_mhead; 1689 m != rxq->rxq_mconsumer; 1690 m = m->m_next) { 1691 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1692 } 1693 m = rxq->rxq_mconsumer; 1694 if ((rxq->rxq_mhead = m->m_next) == NULL) 1695 rxq->rxq_mtail = &rxq->rxq_mhead; 1696 rxq->rxq_mconsumer = m->m_next; 1697 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1698 } else { 1699 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1700 } 1701 #ifdef ETSEC_DEBUG 1702 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1703 #endif 1704 1705 /* 1706 * Wrap at the last entry! 1707 */ 1708 if (rxbd_flags & RXBD_W) { 1709 KASSERT(consumer + 1 == rxq->rxq_last); 1710 consumer = rxq->rxq_first; 1711 } else { 1712 consumer++; 1713 } 1714 #ifdef ETSEC_DEBUG 1715 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1716 #endif 1717 } 1718 1719 if (rxconsumed != 0) 1720 rnd_add_uint32(&sc->rnd_source, rxconsumed); 1721 } 1722 1723 static void 1724 pq3etsec_rxq_purge( 1725 struct pq3etsec_softc *sc, 1726 struct pq3etsec_rxqueue *rxq, 1727 bool discard) 1728 { 1729 struct mbuf *m; 1730 1731 if ((m = rxq->rxq_mhead) != NULL) { 1732 #ifdef ETSEC_DEBUG 1733 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1734 #endif 1735 1736 if (discard) { 1737 pq3etsec_rx_map_unload(sc, m); 1738 m_freem(m); 1739 } else { 1740 while (m != NULL) { 1741 struct mbuf *m0 = m->m_next; 1742 m->m_next = NULL; 1743 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1744 m = m0; 1745 } 1746 } 1747 } 1748 1749 rxq->rxq_mconsumer = NULL; 1750 rxq->rxq_mhead = NULL; 1751 rxq->rxq_mtail = &rxq->rxq_mhead; 1752 rxq->rxq_inuse = 0; 1753 } 1754 1755 static void 1756 pq3etsec_rxq_reset( 1757 struct pq3etsec_softc *sc, 1758 struct pq3etsec_rxqueue *rxq) 1759 { 1760 /* 1761 * sync all the descriptors 1762 */ 1763 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1764 rxq->rxq_last - rxq->rxq_first); 1765 1766 /* 1767 * Make sure we own all descriptors in the ring. 1768 */ 1769 volatile struct rxbd *rxbd; 1770 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1771 rxbd->rxbd_flags = RXBD_I; 1772 } 1773 1774 /* 1775 * Last descriptor has the wrap flag. 1776 */ 1777 rxbd->rxbd_flags = RXBD_W | RXBD_I; 1778 1779 /* 1780 * Reset the producer consumer indexes. 1781 */ 1782 rxq->rxq_consumer = rxq->rxq_first; 1783 rxq->rxq_producer = rxq->rxq_first; 1784 rxq->rxq_inuse = 0; 1785 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1786 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1787 1788 sc->sc_imask |= IEVENT_RXF | IEVENT_BSY; 1789 1790 /* 1791 * Restart the transmit at the first descriptor 1792 */ 1793 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1794 } 1795 1796 static int 1797 pq3etsec_rxq_attach( 1798 struct pq3etsec_softc *sc, 1799 struct pq3etsec_rxqueue *rxq, 1800 u_int qno) 1801 { 1802 size_t map_size = PAGE_SIZE; 1803 size_t desc_count = map_size / sizeof(struct rxbd); 1804 int error; 1805 void *descs; 1806 1807 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1808 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1809 if (error) 1810 return error; 1811 1812 memset(descs, 0, map_size); 1813 rxq->rxq_first = descs; 1814 rxq->rxq_last = rxq->rxq_first + desc_count; 1815 rxq->rxq_consumer = descs; 1816 rxq->rxq_producer = descs; 1817 1818 pq3etsec_rxq_purge(sc, rxq, true); 1819 pq3etsec_rxq_reset(sc, rxq); 1820 1821 rxq->rxq_reg_rbase = RBASEn(qno); 1822 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1823 1824 return 0; 1825 } 1826 1827 static bool 1828 pq3etsec_txq_active_p( 1829 struct pq3etsec_softc * const sc, 1830 struct pq3etsec_txqueue *txq) 1831 { 1832 return !IF_IS_EMPTY(&txq->txq_mbufs); 1833 } 1834 1835 static bool 1836 pq3etsec_txq_fillable_p( 1837 struct pq3etsec_softc * const sc, 1838 struct pq3etsec_txqueue *txq) 1839 { 1840 return txq->txq_free >= txq->txq_threshold; 1841 } 1842 1843 static int 1844 pq3etsec_txq_attach( 1845 struct pq3etsec_softc *sc, 1846 struct pq3etsec_txqueue *txq, 1847 u_int qno) 1848 { 1849 size_t map_size = PAGE_SIZE; 1850 size_t desc_count = map_size / sizeof(struct txbd); 1851 int error; 1852 void *descs; 1853 1854 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1855 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1856 if (error) 1857 return error; 1858 1859 memset(descs, 0, map_size); 1860 txq->txq_first = descs; 1861 txq->txq_last = txq->txq_first + desc_count; 1862 txq->txq_consumer = descs; 1863 txq->txq_producer = descs; 1864 1865 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1866 1867 txq->txq_reg_tbase = TBASEn(qno); 1868 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1869 1870 pq3etsec_txq_reset(sc, txq); 1871 1872 return 0; 1873 } 1874 1875 static int 1876 pq3etsec_txq_map_load( 1877 struct pq3etsec_softc *sc, 1878 struct pq3etsec_txqueue *txq, 1879 struct mbuf *m) 1880 { 1881 bus_dmamap_t map; 1882 int error; 1883 1884 map = M_GETCTX(m, bus_dmamap_t); 1885 if (map != NULL) 1886 return 0; 1887 1888 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1889 if (map == NULL) 1890 return ENOMEM; 1891 1892 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1893 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1894 if (error) 1895 return error; 1896 1897 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1898 BUS_DMASYNC_PREWRITE); 1899 M_SETCTX(m, map); 1900 return 0; 1901 } 1902 1903 static void 1904 pq3etsec_txq_map_unload( 1905 struct pq3etsec_softc *sc, 1906 struct pq3etsec_txqueue *txq, 1907 struct mbuf *m) 1908 { 1909 KASSERT(m); 1910 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1911 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1912 BUS_DMASYNC_POSTWRITE); 1913 bus_dmamap_unload(sc->sc_dmat, map); 1914 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1915 } 1916 1917 static bool 1918 pq3etsec_txq_produce( 1919 struct pq3etsec_softc *sc, 1920 struct pq3etsec_txqueue *txq, 1921 struct mbuf *m) 1922 { 1923 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1924 1925 if (map->dm_nsegs > txq->txq_free) 1926 return false; 1927 1928 /* 1929 * TCP Offload flag must be set in the first descriptor. 1930 */ 1931 volatile struct txbd *producer = txq->txq_producer; 1932 uint16_t last_flags = TXBD_L; 1933 uint16_t first_flags = TXBD_R 1934 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1935 1936 /* 1937 * If we've produced enough descriptors without consuming any 1938 * we need to ask for an interrupt to reclaim some. 1939 */ 1940 txq->txq_lastintr += map->dm_nsegs; 1941 if (ETSEC_IC_TX_ENABLED(sc) 1942 || txq->txq_lastintr >= txq->txq_threshold 1943 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1944 txq->txq_lastintr = 0; 1945 last_flags |= TXBD_I; 1946 } 1947 1948 #ifdef ETSEC_DEBUG 1949 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1950 #endif 1951 KASSERT(producer != txq->txq_last); 1952 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1953 producer->txbd_len = map->dm_segs[0].ds_len; 1954 1955 if (map->dm_nsegs > 1) { 1956 volatile struct txbd *start = producer + 1; 1957 size_t count = map->dm_nsegs - 1; 1958 for (u_int i = 1; i < map->dm_nsegs; i++) { 1959 if (__predict_false(++producer == txq->txq_last)) { 1960 producer = txq->txq_first; 1961 if (start < txq->txq_last) { 1962 pq3etsec_txq_desc_presync(sc, txq, 1963 start, txq->txq_last - start); 1964 count -= txq->txq_last - start; 1965 } 1966 start = txq->txq_first; 1967 } 1968 #ifdef ETSEC_DEBUG 1969 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1970 #endif 1971 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1972 producer->txbd_len = map->dm_segs[i].ds_len; 1973 producer->txbd_flags = TXBD_R 1974 | (producer->txbd_flags & TXBD_W) 1975 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1976 #if 0 1977 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1978 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1979 #endif 1980 } 1981 pq3etsec_txq_desc_presync(sc, txq, start, count); 1982 } else { 1983 first_flags |= last_flags; 1984 } 1985 1986 membar_producer(); 1987 txq->txq_producer->txbd_flags = 1988 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1989 #if 0 1990 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1991 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1992 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1993 #endif 1994 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1995 1996 /* 1997 * Reduce free count by the number of segments we consumed. 1998 */ 1999 txq->txq_free -= map->dm_nsegs; 2000 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 2001 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 2002 KASSERT(producer->txbd_flags & TXBD_L); 2003 #ifdef ETSEC_DEBUG 2004 txq->txq_lmbufs[producer - txq->txq_first] = m; 2005 #endif 2006 2007 #if 0 2008 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 2009 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 2010 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 2011 #endif 2012 2013 if (++producer == txq->txq_last) 2014 txq->txq_producer = txq->txq_first; 2015 else 2016 txq->txq_producer = producer; 2017 IF_ENQUEUE(&txq->txq_mbufs, m); 2018 2019 /* 2020 * Restart the transmitter. 2021 */ 2022 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 2023 2024 return true; 2025 } 2026 2027 static void 2028 pq3etsec_tx_offload( 2029 struct pq3etsec_softc *sc, 2030 struct pq3etsec_txqueue *txq, 2031 struct mbuf **mp) 2032 { 2033 struct mbuf *m = *mp; 2034 u_int csum_flags = m->m_pkthdr.csum_flags; 2035 bool have_vtag; 2036 uint16_t vtag; 2037 2038 KASSERT(m->m_flags & M_PKTHDR); 2039 2040 have_vtag = vlan_has_tag(m); 2041 vtag = (have_vtag) ? vlan_get_tag(m) : 0; 2042 2043 /* 2044 * Let see if we are doing any offload first. 2045 */ 2046 if (csum_flags == 0 && !have_vtag) { 2047 m->m_flags &= ~M_HASFCB; 2048 return; 2049 } 2050 2051 uint16_t flags = 0; 2052 if (csum_flags & M_CSUM_IP) { 2053 flags |= TXFCB_IP 2054 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 2055 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 2056 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 2057 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 2058 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 2059 } 2060 if (have_vtag) { 2061 flags |= TXFCB_VLN; 2062 } 2063 if (flags == 0) { 2064 m->m_flags &= ~M_HASFCB; 2065 return; 2066 } 2067 2068 struct txfcb fcb; 2069 fcb.txfcb_flags = flags; 2070 if (csum_flags & M_CSUM_IPv4) 2071 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2072 else 2073 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 2074 fcb.txfcb_l3os = ETHER_HDR_LEN; 2075 fcb.txfcb_phcs = 0; 2076 fcb.txfcb_vlctl = vtag; 2077 2078 #if 0 2079 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 2080 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 2081 fcb.txfcb_phcs, fcb.txfcb_vlctl); 2082 #endif 2083 2084 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 2085 m->m_data -= sizeof(fcb); 2086 m->m_len += sizeof(fcb); 2087 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 2088 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 2089 m->m_data = m->m_pktdat; 2090 m->m_len += sizeof(fcb); 2091 } else { 2092 struct mbuf *mn; 2093 MGET(mn, M_DONTWAIT, m->m_type); 2094 if (mn == NULL) { 2095 if (csum_flags & M_CSUM_IP4) { 2096 #ifdef INET 2097 in_undefer_cksum(m, ETHER_HDR_LEN, 2098 csum_flags & M_CSUM_IP4); 2099 #else 2100 panic("%s: impossible M_CSUM flags %#x", 2101 device_xname(sc->sc_dev), csum_flags); 2102 #endif 2103 } else if (csum_flags & M_CSUM_IP6) { 2104 #ifdef INET6 2105 in6_undefer_cksum(m, ETHER_HDR_LEN, 2106 csum_flags & M_CSUM_IP6); 2107 #else 2108 panic("%s: impossible M_CSUM flags %#x", 2109 device_xname(sc->sc_dev), csum_flags); 2110 #endif 2111 } 2112 2113 m->m_flags &= ~M_HASFCB; 2114 return; 2115 } 2116 2117 m_move_pkthdr(mn, m); 2118 mn->m_next = m; 2119 m = mn; 2120 m_align(m, sizeof(fcb)); 2121 m->m_len = sizeof(fcb); 2122 *mp = m; 2123 } 2124 m->m_pkthdr.len += sizeof(fcb); 2125 m->m_flags |= M_HASFCB; 2126 *mtod(m, struct txfcb *) = fcb; 2127 return; 2128 } 2129 2130 static bool 2131 pq3etsec_txq_enqueue( 2132 struct pq3etsec_softc *sc, 2133 struct pq3etsec_txqueue *txq) 2134 { 2135 for (;;) { 2136 if (IF_QFULL(&txq->txq_mbufs)) 2137 return false; 2138 struct mbuf *m = txq->txq_next; 2139 if (m == NULL) { 2140 int s = splnet(); 2141 IFQ_DEQUEUE(&sc->sc_if.if_snd, m); 2142 splx(s); 2143 if (m == NULL) 2144 return true; 2145 M_SETCTX(m, NULL); 2146 pq3etsec_tx_offload(sc, txq, &m); 2147 } else { 2148 txq->txq_next = NULL; 2149 } 2150 int error = pq3etsec_txq_map_load(sc, txq, m); 2151 if (error) { 2152 aprint_error_dev(sc->sc_dev, 2153 "discarded packet due to " 2154 "dmamap load failure: %d\n", error); 2155 m_freem(m); 2156 continue; 2157 } 2158 KASSERT(txq->txq_next == NULL); 2159 if (!pq3etsec_txq_produce(sc, txq, m)) { 2160 txq->txq_next = m; 2161 return false; 2162 } 2163 KASSERT(txq->txq_next == NULL); 2164 } 2165 } 2166 2167 static bool 2168 pq3etsec_txq_consume( 2169 struct pq3etsec_softc *sc, 2170 struct pq3etsec_txqueue *txq) 2171 { 2172 struct ifnet * const ifp = &sc->sc_if; 2173 volatile struct txbd *consumer = txq->txq_consumer; 2174 size_t txfree = 0; 2175 bool ret; 2176 2177 #if 0 2178 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 2179 #endif 2180 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 2181 2182 for (;;) { 2183 if (consumer == txq->txq_producer) { 2184 txq->txq_consumer = consumer; 2185 txq->txq_free += txfree; 2186 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2187 KASSERT(txq->txq_lastintr == 0); 2188 KASSERT(txq->txq_free == 2189 txq->txq_last - txq->txq_first - 1); 2190 ret = true; 2191 break; 2192 } 2193 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2194 const uint16_t txbd_flags = consumer->txbd_flags; 2195 if (txbd_flags & TXBD_R) { 2196 txq->txq_consumer = consumer; 2197 txq->txq_free += txfree; 2198 txq->txq_lastintr -= uimin(txq->txq_lastintr, txfree); 2199 ret = pq3etsec_txq_fillable_p(sc, txq); 2200 break; 2201 } 2202 2203 /* 2204 * If this is the last descriptor in the chain, get the 2205 * mbuf, free its dmamap, and free the mbuf chain itself. 2206 */ 2207 if (txbd_flags & TXBD_L) { 2208 struct mbuf *m; 2209 2210 IF_DEQUEUE(&txq->txq_mbufs, m); 2211 #ifdef ETSEC_DEBUG 2212 KASSERTMSG( 2213 m == txq->txq_lmbufs[consumer-txq->txq_first], 2214 "%s: %p [%u]: flags %#x m (%p) != %p (%p)", 2215 __func__, consumer, consumer - txq->txq_first, 2216 txbd_flags, m, 2217 &txq->txq_lmbufs[consumer-txq->txq_first], 2218 txq->txq_lmbufs[consumer-txq->txq_first]); 2219 #endif 2220 KASSERT(m); 2221 pq3etsec_txq_map_unload(sc, txq, m); 2222 #if 0 2223 printf("%s: mbuf %p: consumed a %u byte packet\n", 2224 __func__, m, m->m_pkthdr.len); 2225 #endif 2226 if (m->m_flags & M_HASFCB) 2227 m_adj(m, sizeof(struct txfcb)); 2228 bpf_mtap(ifp, m, BPF_D_OUT); 2229 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2230 if_statinc_ref(nsr, if_opackets); 2231 if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len); 2232 if (m->m_flags & M_MCAST) 2233 if_statinc_ref(nsr, if_omcasts); 2234 if (txbd_flags & TXBD_ERRORS) 2235 if_statinc_ref(nsr, if_oerrors); 2236 IF_STAT_PUTREF(ifp); 2237 m_freem(m); 2238 #ifdef ETSEC_DEBUG 2239 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2240 #endif 2241 } else { 2242 #ifdef ETSEC_DEBUG 2243 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2244 #endif 2245 } 2246 2247 /* 2248 * We own this packet again. Clear all flags except wrap. 2249 */ 2250 txfree++; 2251 //consumer->txbd_flags = txbd_flags & TXBD_W; 2252 2253 /* 2254 * Wrap at the last entry! 2255 */ 2256 if (txbd_flags & TXBD_W) { 2257 KASSERT(consumer + 1 == txq->txq_last); 2258 consumer = txq->txq_first; 2259 } else { 2260 consumer++; 2261 KASSERT(consumer < txq->txq_last); 2262 } 2263 } 2264 2265 if (txfree != 0) 2266 rnd_add_uint32(&sc->rnd_source, txfree); 2267 return ret; 2268 } 2269 2270 static void 2271 pq3etsec_txq_purge( 2272 struct pq3etsec_softc *sc, 2273 struct pq3etsec_txqueue *txq) 2274 { 2275 struct mbuf *m; 2276 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2277 2278 for (;;) { 2279 IF_DEQUEUE(&txq->txq_mbufs, m); 2280 if (m == NULL) 2281 break; 2282 pq3etsec_txq_map_unload(sc, txq, m); 2283 m_freem(m); 2284 } 2285 if ((m = txq->txq_next) != NULL) { 2286 txq->txq_next = NULL; 2287 pq3etsec_txq_map_unload(sc, txq, m); 2288 m_freem(m); 2289 } 2290 #ifdef ETSEC_DEBUG 2291 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2292 #endif 2293 } 2294 2295 static void 2296 pq3etsec_txq_reset( 2297 struct pq3etsec_softc *sc, 2298 struct pq3etsec_txqueue *txq) 2299 { 2300 /* 2301 * sync all the descriptors 2302 */ 2303 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2304 txq->txq_last - txq->txq_first); 2305 2306 /* 2307 * Make sure we own all descriptors in the ring. 2308 */ 2309 volatile struct txbd *txbd; 2310 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2311 txbd->txbd_flags = 0; 2312 } 2313 2314 /* 2315 * Last descriptor has the wrap flag. 2316 */ 2317 txbd->txbd_flags = TXBD_W; 2318 2319 /* 2320 * Reset the producer consumer indexes. 2321 */ 2322 txq->txq_consumer = txq->txq_first; 2323 txq->txq_producer = txq->txq_first; 2324 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2325 txq->txq_threshold = txq->txq_free / 2; 2326 txq->txq_lastintr = 0; 2327 2328 /* 2329 * What do we want to get interrupted on? 2330 */ 2331 sc->sc_imask |= IEVENT_TXF | IEVENT_TXE; 2332 2333 /* 2334 * Restart the transmit at the first descriptor 2335 */ 2336 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2337 } 2338 2339 static void 2340 pq3etsec_ifstart(struct ifnet *ifp) 2341 { 2342 struct pq3etsec_softc * const sc = ifp->if_softc; 2343 2344 if (__predict_false((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)) { 2345 return; 2346 } 2347 2348 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2349 softint_schedule(sc->sc_soft_ih); 2350 } 2351 2352 static void 2353 pq3etsec_tx_error( 2354 struct pq3etsec_softc * const sc) 2355 { 2356 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2357 2358 pq3etsec_txq_consume(sc, txq); 2359 2360 if (pq3etsec_txq_fillable_p(sc, txq)) 2361 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2362 if (sc->sc_txerrors 2363 & (IEVENT_LC | IEVENT_CRL | IEVENT_XFUN | IEVENT_BABT)) { 2364 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2365 } 2366 2367 if (pq3etsec_txq_active_p(sc, txq)) 2368 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2369 if (!pq3etsec_txq_enqueue(sc, txq)) { 2370 sc->sc_ev_tx_stall.ev_count++; 2371 sc->sc_if.if_flags |= IFF_OACTIVE; 2372 } 2373 2374 sc->sc_txerrors = 0; 2375 } 2376 2377 int 2378 pq3etsec_tx_intr(void *arg) 2379 { 2380 struct pq3etsec_softc * const sc = arg; 2381 2382 mutex_enter(sc->sc_hwlock); 2383 2384 sc->sc_ev_tx_intr.ev_count++; 2385 2386 uint32_t ievent = etsec_read(sc, IEVENT); 2387 ievent &= IEVENT_TXF | IEVENT_TXB; 2388 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2389 2390 #if 0 2391 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2392 __func__, ievent, etsec_read(sc, IMASK)); 2393 #endif 2394 2395 if (ievent == 0) { 2396 mutex_exit(sc->sc_hwlock); 2397 return 0; 2398 } 2399 2400 sc->sc_imask &= ~(IEVENT_TXF | IEVENT_TXB); 2401 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2402 etsec_write(sc, IMASK, sc->sc_imask); 2403 softint_schedule(sc->sc_soft_ih); 2404 2405 mutex_exit(sc->sc_hwlock); 2406 2407 return 1; 2408 } 2409 2410 int 2411 pq3etsec_rx_intr(void *arg) 2412 { 2413 struct pq3etsec_softc * const sc = arg; 2414 2415 mutex_enter(sc->sc_hwlock); 2416 2417 sc->sc_ev_rx_intr.ev_count++; 2418 2419 uint32_t ievent = etsec_read(sc, IEVENT); 2420 ievent &= IEVENT_RXF | IEVENT_RXB; 2421 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2422 if (ievent == 0) { 2423 mutex_exit(sc->sc_hwlock); 2424 return 0; 2425 } 2426 2427 #if 0 2428 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2429 #endif 2430 2431 sc->sc_imask &= ~(IEVENT_RXF | IEVENT_RXB); 2432 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2433 etsec_write(sc, IMASK, sc->sc_imask); 2434 softint_schedule(sc->sc_soft_ih); 2435 2436 mutex_exit(sc->sc_hwlock); 2437 2438 return 1; 2439 } 2440 2441 int 2442 pq3etsec_error_intr(void *arg) 2443 { 2444 struct pq3etsec_softc * const sc = arg; 2445 2446 mutex_enter(sc->sc_hwlock); 2447 2448 sc->sc_ev_error_intr.ev_count++; 2449 2450 for (int rv = 0, soft_flags = 0;; rv = 1) { 2451 uint32_t ievent = etsec_read(sc, IEVENT); 2452 ievent &= ~(IEVENT_RXF | IEVENT_RXB | IEVENT_TXF | IEVENT_TXB); 2453 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2454 if (ievent == 0) { 2455 if (soft_flags) { 2456 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2457 softint_schedule(sc->sc_soft_ih); 2458 } 2459 mutex_exit(sc->sc_hwlock); 2460 return rv; 2461 } 2462 #if 0 2463 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2464 __func__, ievent, etsec_read(sc, IMASK)); 2465 #endif 2466 2467 if (ievent & (IEVENT_GRSC | IEVENT_GTSC)) { 2468 sc->sc_imask &= ~(IEVENT_GRSC | IEVENT_GTSC); 2469 etsec_write(sc, IMASK, sc->sc_imask); 2470 wakeup(sc); 2471 } 2472 if (ievent & (IEVENT_MMRD | IEVENT_MMWR)) { 2473 sc->sc_imask &= ~(IEVENT_MMRD | IEVENT_MMWR); 2474 etsec_write(sc, IMASK, sc->sc_imask); 2475 wakeup(&sc->sc_mii); 2476 } 2477 if (ievent & IEVENT_BSY) { 2478 soft_flags |= SOFT_RXBSY; 2479 sc->sc_imask &= ~IEVENT_BSY; 2480 etsec_write(sc, IMASK, sc->sc_imask); 2481 } 2482 if (ievent & IEVENT_TXE) { 2483 soft_flags |= SOFT_TXERROR; 2484 sc->sc_imask &= ~IEVENT_TXE; 2485 sc->sc_txerrors |= ievent; 2486 } 2487 if (ievent & IEVENT_TXC) { 2488 sc->sc_ev_tx_pause.ev_count++; 2489 } 2490 if (ievent & IEVENT_RXC) { 2491 sc->sc_ev_rx_pause.ev_count++; 2492 } 2493 if (ievent & IEVENT_DPE) { 2494 soft_flags |= SOFT_RESET; 2495 sc->sc_imask &= ~IEVENT_DPE; 2496 etsec_write(sc, IMASK, sc->sc_imask); 2497 } 2498 } 2499 } 2500 2501 void 2502 pq3etsec_soft_intr(void *arg) 2503 { 2504 struct pq3etsec_softc * const sc = arg; 2505 struct ifnet * const ifp = &sc->sc_if; 2506 uint32_t imask = 0; 2507 2508 mutex_enter(sc->sc_lock); 2509 2510 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2511 2512 sc->sc_ev_soft_intr.ev_count++; 2513 2514 if (soft_flags & SOFT_RESET) { 2515 int s = splnet(); 2516 pq3etsec_ifinit(ifp); 2517 splx(s); 2518 soft_flags = 0; 2519 } 2520 2521 if (soft_flags & SOFT_RXBSY) { 2522 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2523 size_t threshold = 5 * rxq->rxq_threshold / 4; 2524 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2525 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2526 } else { 2527 imask |= IEVENT_BSY; 2528 } 2529 aprint_normal_dev(sc->sc_dev, 2530 "increasing receive buffers from %zu to %zu\n", 2531 rxq->rxq_threshold, threshold); 2532 rxq->rxq_threshold = threshold; 2533 } 2534 2535 if ((soft_flags & SOFT_TXINTR) 2536 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2537 /* 2538 * Let's do what we came here for. Consume transmitted 2539 * packets off the transmit ring. 2540 */ 2541 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2542 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2543 sc->sc_ev_tx_stall.ev_count++; 2544 ifp->if_flags |= IFF_OACTIVE; 2545 } else { 2546 ifp->if_flags &= ~IFF_OACTIVE; 2547 } 2548 imask |= IEVENT_TXF; 2549 } 2550 2551 if (soft_flags & (SOFT_RXINTR | SOFT_RXBSY)) { 2552 /* Let's consume */ 2553 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2554 imask |= IEVENT_RXF; 2555 } 2556 2557 if (soft_flags & SOFT_TXERROR) { 2558 pq3etsec_tx_error(sc); 2559 imask |= IEVENT_TXE; 2560 } 2561 2562 if (ifp->if_flags & IFF_RUNNING) { 2563 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2564 mutex_spin_enter(sc->sc_hwlock); 2565 sc->sc_imask |= imask; 2566 etsec_write(sc, IMASK, sc->sc_imask); 2567 mutex_spin_exit(sc->sc_hwlock); 2568 } else { 2569 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2570 } 2571 2572 mutex_exit(sc->sc_lock); 2573 } 2574 2575 static void 2576 pq3etsec_mii_tick(void *arg) 2577 { 2578 struct pq3etsec_softc * const sc = arg; 2579 mutex_enter(sc->sc_lock); 2580 callout_ack(&sc->sc_mii_callout); 2581 sc->sc_ev_mii_ticks.ev_count++; 2582 #ifdef DEBUG 2583 uint64_t now = mftb(); 2584 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2585 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2586 __func__, now - sc->sc_mii_last_tick); 2587 callout_stop(&sc->sc_mii_callout); 2588 } 2589 #endif 2590 mii_tick(&sc->sc_mii); 2591 int s = splnet(); 2592 if (sc->sc_soft_flags & SOFT_RESET) 2593 softint_schedule(sc->sc_soft_ih); 2594 splx(s); 2595 callout_schedule(&sc->sc_mii_callout, hz); 2596 #ifdef DEBUG 2597 sc->sc_mii_last_tick = now; 2598 #endif 2599 mutex_exit(sc->sc_lock); 2600 } 2601 2602 static void 2603 pq3etsec_set_ic_rx(struct pq3etsec_softc *sc) 2604 { 2605 uint32_t reg; 2606 2607 if (ETSEC_IC_RX_ENABLED(sc)) { 2608 reg = RXIC_ICEN; 2609 reg |= RXIC_ICFT_SET(sc->sc_ic_rx_count); 2610 reg |= RXIC_ICTT_SET(sc->sc_ic_rx_time); 2611 } else { 2612 /* Disable RX interrupt coalescing */ 2613 reg = 0; 2614 } 2615 2616 etsec_write(sc, RXIC, reg); 2617 } 2618 2619 static void 2620 pq3etsec_set_ic_tx(struct pq3etsec_softc *sc) 2621 { 2622 uint32_t reg; 2623 2624 if (ETSEC_IC_TX_ENABLED(sc)) { 2625 reg = TXIC_ICEN; 2626 reg |= TXIC_ICFT_SET(sc->sc_ic_tx_count); 2627 reg |= TXIC_ICTT_SET(sc->sc_ic_tx_time); 2628 } else { 2629 /* Disable TX interrupt coalescing */ 2630 reg = 0; 2631 } 2632 2633 etsec_write(sc, TXIC, reg); 2634 } 2635 2636 /* 2637 * sysctl 2638 */ 2639 static int 2640 pq3etsec_sysctl_ic_time_helper(SYSCTLFN_ARGS, int *valuep) 2641 { 2642 struct sysctlnode node = *rnode; 2643 struct pq3etsec_softc *sc = rnode->sysctl_data; 2644 int value = *valuep; 2645 int error; 2646 2647 node.sysctl_data = &value; 2648 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2649 if (error != 0 || newp == NULL) 2650 return error; 2651 2652 if (value < 0 || value > 65535) 2653 return EINVAL; 2654 2655 mutex_enter(sc->sc_lock); 2656 *valuep = value; 2657 if (valuep == &sc->sc_ic_rx_time) 2658 pq3etsec_set_ic_rx(sc); 2659 else 2660 pq3etsec_set_ic_tx(sc); 2661 mutex_exit(sc->sc_lock); 2662 2663 return 0; 2664 } 2665 2666 static int 2667 pq3etsec_sysctl_ic_count_helper(SYSCTLFN_ARGS, int *valuep) 2668 { 2669 struct sysctlnode node = *rnode; 2670 struct pq3etsec_softc *sc = rnode->sysctl_data; 2671 int value = *valuep; 2672 int error; 2673 2674 node.sysctl_data = &value; 2675 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2676 if (error != 0 || newp == NULL) 2677 return error; 2678 2679 if (value < 0 || value > 255) 2680 return EINVAL; 2681 2682 mutex_enter(sc->sc_lock); 2683 *valuep = value; 2684 if (valuep == &sc->sc_ic_rx_count) 2685 pq3etsec_set_ic_rx(sc); 2686 else 2687 pq3etsec_set_ic_tx(sc); 2688 mutex_exit(sc->sc_lock); 2689 2690 return 0; 2691 } 2692 2693 static int 2694 pq3etsec_sysctl_ic_rx_time_helper(SYSCTLFN_ARGS) 2695 { 2696 struct pq3etsec_softc *sc = rnode->sysctl_data; 2697 2698 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2699 &sc->sc_ic_rx_time); 2700 } 2701 2702 static int 2703 pq3etsec_sysctl_ic_rx_count_helper(SYSCTLFN_ARGS) 2704 { 2705 struct pq3etsec_softc *sc = rnode->sysctl_data; 2706 2707 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2708 &sc->sc_ic_rx_count); 2709 } 2710 2711 static int 2712 pq3etsec_sysctl_ic_tx_time_helper(SYSCTLFN_ARGS) 2713 { 2714 struct pq3etsec_softc *sc = rnode->sysctl_data; 2715 2716 return pq3etsec_sysctl_ic_time_helper(SYSCTLFN_CALL(rnode), 2717 &sc->sc_ic_tx_time); 2718 } 2719 2720 static int 2721 pq3etsec_sysctl_ic_tx_count_helper(SYSCTLFN_ARGS) 2722 { 2723 struct pq3etsec_softc *sc = rnode->sysctl_data; 2724 2725 return pq3etsec_sysctl_ic_count_helper(SYSCTLFN_CALL(rnode), 2726 &sc->sc_ic_tx_count); 2727 } 2728 2729 static void pq3etsec_sysctl_setup(struct sysctllog **clog, 2730 struct pq3etsec_softc *sc) 2731 { 2732 const struct sysctlnode *cnode, *rnode; 2733 2734 if (sysctl_createv(clog, 0, NULL, &rnode, 2735 CTLFLAG_PERMANENT, 2736 CTLTYPE_NODE, device_xname(sc->sc_dev), 2737 SYSCTL_DESCR("TSEC interface"), 2738 NULL, 0, NULL, 0, 2739 CTL_HW, CTL_CREATE, CTL_EOL) != 0) 2740 goto bad; 2741 2742 if (sysctl_createv(clog, 0, &rnode, &rnode, 2743 CTLFLAG_PERMANENT, 2744 CTLTYPE_NODE, "int_coal", 2745 SYSCTL_DESCR("Interrupts coalescing"), 2746 NULL, 0, NULL, 0, 2747 CTL_CREATE, CTL_EOL) != 0) 2748 goto bad; 2749 2750 if (sysctl_createv(clog, 0, &rnode, &cnode, 2751 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2752 CTLTYPE_INT, "rx_time", 2753 SYSCTL_DESCR("RX time threshold (0-65535)"), 2754 pq3etsec_sysctl_ic_rx_time_helper, 0, (void *)sc, 0, 2755 CTL_CREATE, CTL_EOL) != 0) 2756 goto bad; 2757 2758 if (sysctl_createv(clog, 0, &rnode, &cnode, 2759 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2760 CTLTYPE_INT, "rx_count", 2761 SYSCTL_DESCR("RX frame count threshold (0-255)"), 2762 pq3etsec_sysctl_ic_rx_count_helper, 0, (void *)sc, 0, 2763 CTL_CREATE, CTL_EOL) != 0) 2764 goto bad; 2765 2766 if (sysctl_createv(clog, 0, &rnode, &cnode, 2767 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2768 CTLTYPE_INT, "tx_time", 2769 SYSCTL_DESCR("TX time threshold (0-65535)"), 2770 pq3etsec_sysctl_ic_tx_time_helper, 0, (void *)sc, 0, 2771 CTL_CREATE, CTL_EOL) != 0) 2772 goto bad; 2773 2774 if (sysctl_createv(clog, 0, &rnode, &cnode, 2775 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2776 CTLTYPE_INT, "tx_count", 2777 SYSCTL_DESCR("TX frame count threshold (0-255)"), 2778 pq3etsec_sysctl_ic_tx_count_helper, 0, (void *)sc, 0, 2779 CTL_CREATE, CTL_EOL) != 0) 2780 goto bad; 2781 2782 return; 2783 2784 bad: 2785 aprint_error_dev(sc->sc_dev, "could not attach sysctl nodes\n"); 2786 } 2787
Indexes created Mon Sep 29 21:09:56 GMT 2025