pq3etsec.c revision 1.8
1 /* $NetBSD: pq3etsec.c,v 1.8 2011/09/27 01:02:35 jym Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_inet.h" 38 39 #include <sys/cdefs.h> 40 41 __KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.8 2011/09/27 01:02:35 jym Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/cpu.h> 45 #include <sys/device.h> 46 #include <sys/mbuf.h> 47 #include <sys/ioctl.h> 48 #include <sys/intr.h> 49 #include <sys/bus.h> 50 #include <sys/kernel.h> 51 #include <sys/kmem.h> 52 #include <sys/proc.h> 53 #include <sys/atomic.h> 54 #include <sys/callout.h> 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_ether.h> 59 #include <net/if_media.h> 60 61 #include <dev/mii/miivar.h> 62 63 #include "ioconf.h" 64 65 #include <net/bpf.h> 66 67 #ifdef INET 68 #include <netinet/in.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/ip.h> 71 #include <netinet/in_offload.h> 72 #endif /* INET */ 73 #ifdef INET6 74 #include <netinet6/in6.h> 75 #include <netinet/ip6.h> 76 #endif 77 #include <netinet6/in6_offload.h> 78 79 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500var.h> 85 #include <powerpc/booke/e500reg.h> 86 #include <powerpc/booke/etsecreg.h> 87 88 #define M_HASFCB M_LINK2 /* tx packet has FCB prepended */ 89 90 #define ETSEC_MAXTXMBUFS 30 91 #define ETSEC_NTXSEGS 30 92 #define ETSEC_MAXRXMBUFS 511 93 #define ETSEC_MINRXMBUFS 32 94 #define ETSEC_NRXSEGS 1 95 96 #define IFCAP_RCTRL_IPCSEN IFCAP_CSUM_IPv4_Rx 97 #define IFCAP_RCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Rx\ 98 |IFCAP_CSUM_UDPv4_Rx\ 99 |IFCAP_CSUM_TCPv6_Rx\ 100 |IFCAP_CSUM_UDPv6_Rx) 101 102 #define IFCAP_TCTRL_IPCSEN IFCAP_CSUM_IPv4_Tx 103 #define IFCAP_TCTRL_TUCSEN (IFCAP_CSUM_TCPv4_Tx\ 104 |IFCAP_CSUM_UDPv4_Tx\ 105 |IFCAP_CSUM_TCPv6_Tx\ 106 |IFCAP_CSUM_UDPv6_Tx) 107 108 #define IFCAP_ETSEC (IFCAP_RCTRL_IPCSEN|IFCAP_RCTRL_TUCSEN\ 109 |IFCAP_TCTRL_IPCSEN|IFCAP_TCTRL_TUCSEN) 110 111 #define M_CSUM_IP (M_CSUM_CIP|M_CSUM_CTU) 112 #define M_CSUM_IP6 (M_CSUM_TCPv6|M_CSUM_UDPv6) 113 #define M_CSUM_TUP (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 114 #define M_CSUM_UDP (M_CSUM_UDPv4|M_CSUM_UDPv6) 115 #define M_CSUM_IP4 (M_CSUM_IPv4|M_CSUM_UDPv4|M_CSUM_TCPv4) 116 #define M_CSUM_CIP (M_CSUM_IPv4) 117 #define M_CSUM_CTU (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6) 118 119 struct pq3etsec_txqueue { 120 bus_dmamap_t txq_descmap; 121 volatile struct txbd *txq_consumer; 122 volatile struct txbd *txq_producer; 123 volatile struct txbd *txq_first; 124 volatile struct txbd *txq_last; 125 struct ifqueue txq_mbufs; 126 struct mbuf *txq_next; 127 #ifdef ETSEC_DEBUG 128 struct mbuf *txq_lmbufs[512]; 129 #endif 130 uint32_t txq_qmask; 131 uint32_t txq_free; 132 uint32_t txq_threshold; 133 uint32_t txq_lastintr; 134 bus_size_t txq_reg_tbase; 135 bus_dma_segment_t txq_descmap_seg; 136 }; 137 138 struct pq3etsec_rxqueue { 139 bus_dmamap_t rxq_descmap; 140 volatile struct rxbd *rxq_consumer; 141 volatile struct rxbd *rxq_producer; 142 volatile struct rxbd *rxq_first; 143 volatile struct rxbd *rxq_last; 144 struct mbuf *rxq_mhead; 145 struct mbuf **rxq_mtail; 146 struct mbuf *rxq_mconsumer; 147 #ifdef ETSEC_DEBUG 148 struct mbuf *rxq_mbufs[512]; 149 #endif 150 uint32_t rxq_qmask; 151 uint32_t rxq_inuse; 152 uint32_t rxq_threshold; 153 bus_size_t rxq_reg_rbase; 154 bus_size_t rxq_reg_rbptr; 155 bus_dma_segment_t rxq_descmap_seg; 156 }; 157 158 struct pq3etsec_mapcache { 159 u_int dmc_nmaps; 160 u_int dmc_maxseg; 161 u_int dmc_maxmaps; 162 u_int dmc_maxmapsize; 163 bus_dmamap_t dmc_maps[0]; 164 }; 165 166 struct pq3etsec_softc { 167 device_t sc_dev; 168 struct ethercom sc_ec; 169 #define sc_if sc_ec.ec_if 170 struct mii_data sc_mii; 171 bus_space_tag_t sc_bst; 172 bus_space_handle_t sc_bsh; 173 bus_dma_tag_t sc_dmat; 174 int sc_phy_addr; 175 prop_dictionary_t sc_intrmap; 176 uint32_t sc_intrmask; 177 178 uint32_t sc_soft_flags; 179 #define SOFT_RESET 0x0001 180 #define SOFT_RXINTR 0x0010 181 #define SOFT_RXBSY 0x0020 182 #define SOFT_TXINTR 0x0100 183 #define SOFT_TXERROR 0x0200 184 185 struct pq3etsec_txqueue sc_txq; 186 struct pq3etsec_rxqueue sc_rxq; 187 uint32_t sc_txerrors; 188 uint32_t sc_rxerrors; 189 190 size_t sc_rx_adjlen; 191 192 /* 193 * Copies of various ETSEC registers. 194 */ 195 uint32_t sc_imask; 196 uint32_t sc_maccfg1; 197 uint32_t sc_maccfg2; 198 uint32_t sc_maxfrm; 199 uint32_t sc_ecntrl; 200 uint32_t sc_dmactrl; 201 uint32_t sc_macstnaddr1; 202 uint32_t sc_macstnaddr2; 203 uint32_t sc_tctrl; 204 uint32_t sc_rctrl; 205 uint32_t sc_gaddr[16]; 206 uint64_t sc_macaddrs[15]; 207 208 void *sc_tx_ih; 209 void *sc_rx_ih; 210 void *sc_error_ih; 211 void *sc_soft_ih; 212 213 kmutex_t *sc_lock; 214 215 struct evcnt sc_ev_tx_stall; 216 struct evcnt sc_ev_tx_intr; 217 struct evcnt sc_ev_rx_stall; 218 struct evcnt sc_ev_rx_intr; 219 struct evcnt sc_ev_error_intr; 220 struct evcnt sc_ev_soft_intr; 221 struct evcnt sc_ev_tx_pause; 222 struct evcnt sc_ev_rx_pause; 223 struct evcnt sc_ev_mii_ticks; 224 225 struct callout sc_mii_callout; 226 uint64_t sc_mii_last_tick; 227 228 struct ifqueue sc_rx_bufcache; 229 struct pq3etsec_mapcache *sc_rx_mapcache; 230 struct pq3etsec_mapcache *sc_tx_mapcache; 231 }; 232 233 static int pq3etsec_match(device_t, cfdata_t, void *); 234 static void pq3etsec_attach(device_t, device_t, void *); 235 236 static void pq3etsec_ifstart(struct ifnet *); 237 static void pq3etsec_ifwatchdog(struct ifnet *); 238 static int pq3etsec_ifinit(struct ifnet *); 239 static void pq3etsec_ifstop(struct ifnet *, int); 240 static int pq3etsec_ifioctl(struct ifnet *, u_long, void *); 241 242 static int pq3etsec_mapcache_create(struct pq3etsec_softc *, 243 struct pq3etsec_mapcache **, size_t, size_t, size_t, size_t); 244 static void pq3etsec_mapcache_destroy(struct pq3etsec_softc *, 245 struct pq3etsec_mapcache *); 246 static bus_dmamap_t pq3etsec_mapcache_get(struct pq3etsec_softc *, 247 struct pq3etsec_mapcache *); 248 static void pq3etsec_mapcache_put(struct pq3etsec_softc *, 249 struct pq3etsec_mapcache *, bus_dmamap_t); 250 251 static int pq3etsec_txq_attach(struct pq3etsec_softc *, 252 struct pq3etsec_txqueue *, u_int); 253 static void pq3etsec_txq_purge(struct pq3etsec_softc *, 254 struct pq3etsec_txqueue *); 255 static void pq3etsec_txq_reset(struct pq3etsec_softc *, 256 struct pq3etsec_txqueue *); 257 static bool pq3etsec_txq_consume(struct pq3etsec_softc *, 258 struct pq3etsec_txqueue *); 259 static bool pq3etsec_txq_produce(struct pq3etsec_softc *, 260 struct pq3etsec_txqueue *, struct mbuf *m); 261 static bool pq3etsec_txq_active_p(struct pq3etsec_softc *, 262 struct pq3etsec_txqueue *); 263 264 static int pq3etsec_rxq_attach(struct pq3etsec_softc *, 265 struct pq3etsec_rxqueue *, u_int); 266 static bool pq3etsec_rxq_produce(struct pq3etsec_softc *, 267 struct pq3etsec_rxqueue *); 268 static void pq3etsec_rxq_purge(struct pq3etsec_softc *, 269 struct pq3etsec_rxqueue *, bool); 270 static void pq3etsec_rxq_reset(struct pq3etsec_softc *, 271 struct pq3etsec_rxqueue *); 272 273 static void pq3etsec_mc_setup(struct pq3etsec_softc *); 274 275 static void pq3etsec_mii_tick(void *); 276 static int pq3etsec_rx_intr(void *); 277 static int pq3etsec_tx_intr(void *); 278 static int pq3etsec_error_intr(void *); 279 static void pq3etsec_soft_intr(void *); 280 281 CFATTACH_DECL_NEW(pq3etsec, sizeof(struct pq3etsec_softc), 282 pq3etsec_match, pq3etsec_attach, NULL, NULL); 283 284 static int 285 pq3etsec_match(device_t parent, cfdata_t cf, void *aux) 286 { 287 288 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 289 return 0; 290 291 return 1; 292 } 293 294 static inline uint32_t 295 etsec_read(struct pq3etsec_softc *sc, bus_size_t off) 296 { 297 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 298 } 299 300 static inline void 301 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data) 302 { 303 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, data); 304 } 305 306 static int 307 pq3etsec_mii_readreg(device_t self, int phy, int reg) 308 { 309 struct pq3etsec_softc * const sc = device_private(self); 310 uint32_t miimcom = etsec_read(sc, MIIMCOM); 311 312 // int s = splnet(); 313 314 etsec_write(sc, MIIMADD, 315 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 316 317 etsec_write(sc, IEVENT, IEVENT_MMRD); 318 etsec_write(sc, MIIMCOM, 0); /* clear any past bits */ 319 etsec_write(sc, MIIMCOM, MIIMCOM_READ); 320 #if 0 321 sc->sc_imask |= IEVENT_MMRD; 322 etsec_write(sc, IMASK, sc->sc_imask); 323 #endif 324 325 while (etsec_read(sc, MIIMIND) != 0) { 326 delay(1); 327 } 328 int data = etsec_read(sc, MIIMSTAT); 329 330 if (miimcom == MIIMCOM_SCAN) 331 etsec_write(sc, MIIMCOM, miimcom); 332 333 #if 0 334 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 335 __func__, phy, reg, data); 336 #endif 337 etsec_write(sc, IEVENT, IEVENT_MMRD); 338 // splx(s); 339 return data; 340 } 341 342 static void 343 pq3etsec_mii_writereg(device_t self, int phy, int reg, int data) 344 { 345 struct pq3etsec_softc * const sc = device_private(self); 346 uint32_t miimcom = etsec_read(sc, MIIMCOM); 347 348 #if 0 349 aprint_normal_dev(sc->sc_dev, "%s: phy %d reg %d: %#x\n", 350 __func__, phy, reg, data); 351 #endif 352 353 // int s = splnet(); 354 etsec_write(sc, IEVENT, IEVENT_MMWR); 355 etsec_write(sc, MIIMADD, 356 __SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG)); 357 etsec_write(sc, MIIMCOM, 0); /* clear any past bits */ 358 etsec_write(sc, MIIMCON, data); 359 360 #if 0 361 sc->sc_imask |= IEVENT_MMWR; 362 etsec_write(sc, IMASK, sc->sc_imask); 363 #endif 364 365 int timo = 1000; /* 1ms */ 366 while ((etsec_read(sc, MIIMIND) & MIIMIND_BUSY) && --timo > 0) { 367 delay(1); 368 } 369 370 if (miimcom == MIIMCOM_SCAN) 371 etsec_write(sc, MIIMCOM, miimcom); 372 etsec_write(sc, IEVENT, IEVENT_MMWR); 373 // splx(s); 374 } 375 376 static void 377 pq3etsec_mii_statchg(device_t self) 378 { 379 struct pq3etsec_softc * const sc = device_private(self); 380 struct mii_data * const mii = &sc->sc_mii; 381 382 uint32_t maccfg1 = sc->sc_maccfg1; 383 uint32_t maccfg2 = sc->sc_maccfg2; 384 uint32_t ecntrl = sc->sc_ecntrl; 385 386 maccfg1 &= ~(MACCFG1_TX_FLOW|MACCFG1_RX_FLOW); 387 maccfg2 &= ~(MACCFG2_IFMODE|MACCFG2_FD); 388 389 if (sc->sc_mii.mii_media_active & IFM_FDX) { 390 maccfg2 |= MACCFG2_FD; 391 } 392 393 /* 394 * Now deal with the flow control bits. 395 */ 396 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO 397 && (mii->mii_media_active & IFM_ETH_FMASK)) { 398 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 399 maccfg1 |= MACCFG1_RX_FLOW; 400 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 401 maccfg1 |= MACCFG1_TX_FLOW; 402 } 403 404 /* 405 * Now deal with the speed. 406 */ 407 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 408 maccfg2 |= MACCFG2_IFMODE_GMII; 409 } else { 410 maccfg2 |= MACCFG2_IFMODE_MII; 411 ecntrl &= ~ECNTRL_R100M; 412 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_10_T) { 413 ecntrl |= ECNTRL_R100M; 414 } 415 } 416 417 /* 418 * If things are different, re-init things. 419 */ 420 if (maccfg1 != sc->sc_maccfg1 421 || maccfg2 != sc->sc_maccfg2 422 || ecntrl != sc->sc_ecntrl) { 423 if (sc->sc_if.if_flags & IFF_RUNNING) 424 atomic_or_uint(&sc->sc_soft_flags, SOFT_RESET); 425 sc->sc_maccfg1 = maccfg1; 426 sc->sc_maccfg2 = maccfg2; 427 sc->sc_ecntrl = ecntrl; 428 } 429 } 430 431 #if 0 432 static void 433 pq3etsec_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 434 { 435 struct pq3etsec_softc * const sc = ifp->if_softc; 436 437 mii_pollstat(&sc->sc_mii); 438 ether_mediastatus(ifp, ifmr); 439 ifmr->ifm_status = sc->sc_mii.mii_media_status; 440 ifmr->ifm_active = sc->sc_mii.mii_media_active; 441 } 442 443 static int 444 pq3etsec_mediachange(struct ifnet *ifp) 445 { 446 struct pq3etsec_softc * const sc = ifp->if_softc; 447 448 if ((ifp->if_flags & IFF_UP) == 0) 449 return 0; 450 451 int rv = mii_mediachg(&sc->sc_mii); 452 return (rv == ENXIO) ? 0 : rv; 453 } 454 #endif 455 456 static void 457 pq3etsec_attach(device_t parent, device_t self, void *aux) 458 { 459 struct cpunode_softc * const psc = device_private(parent); 460 struct pq3etsec_softc * const sc = device_private(self); 461 struct cpunode_attach_args * const cna = aux; 462 struct cpunode_locators * const cnl = &cna->cna_locs; 463 cfdata_t cf = device_cfdata(self); 464 int error; 465 466 psc->sc_children |= cna->cna_childmask; 467 sc->sc_dev = self; 468 sc->sc_bst = cna->cna_memt; 469 sc->sc_dmat = &booke_bus_dma_tag; 470 471 /* 472 * If we have a common MDIO bus, if all off instance 1. 473 */ 474 device_t miiself = (cf->cf_flags & 0x100) ? tsec_cd.cd_devs[0] : self; 475 476 /* 477 * See if the phy is in the config file... 478 */ 479 if (cf->cf_flags & 0x3f) { 480 sc->sc_phy_addr = (cf->cf_flags & 0x3f) - 1; 481 } else { 482 unsigned char prop_name[20]; 483 snprintf(prop_name, sizeof(prop_name), "tsec%u-phy-addr", 484 cnl->cnl_instance); 485 sc->sc_phy_addr = board_info_get_number(prop_name); 486 } 487 aprint_normal(" phy %d", sc->sc_phy_addr); 488 489 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 490 &sc->sc_bsh); 491 if (error) { 492 aprint_error(": error mapping registers: %d\n", error); 493 return; 494 } 495 496 /* 497 * Assume firmware has aready set the mac address and fetch it 498 * before we reinit it. 499 */ 500 sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2); 501 sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1); 502 sc->sc_rctrl = RCTRL_DEFAULT; 503 sc->sc_maccfg2 = MACCFG2_DEFAULT; 504 505 if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) { 506 size_t len; 507 const uint8_t *mac_addr = 508 board_info_get_data("tsec-mac-addr-base", &len); 509 KASSERT(len == ETHER_ADDR_LEN); 510 sc->sc_macstnaddr2 = 511 (mac_addr[1] << 24) 512 | (mac_addr[0] << 16); 513 sc->sc_macstnaddr1 = 514 ((mac_addr[5] + cnl->cnl_instance - 1) << 24) 515 | (mac_addr[4] << 16) 516 | (mac_addr[3] << 8) 517 | (mac_addr[2] << 0); 518 #if 0 519 aprint_error(": mac-address unknown\n"); 520 return; 521 #endif 522 } 523 524 char enaddr[ETHER_ADDR_LEN] = { 525 [0] = sc->sc_macstnaddr2 >> 16, 526 [1] = sc->sc_macstnaddr2 >> 24, 527 [2] = sc->sc_macstnaddr1 >> 0, 528 [3] = sc->sc_macstnaddr1 >> 8, 529 [4] = sc->sc_macstnaddr1 >> 16, 530 [5] = sc->sc_macstnaddr1 >> 24, 531 }; 532 533 error = pq3etsec_rxq_attach(sc, &sc->sc_rxq, 0); 534 if (error) { 535 aprint_error(": failed to init rxq: %d\n", error); 536 return; 537 } 538 539 error = pq3etsec_txq_attach(sc, &sc->sc_txq, 0); 540 if (error) { 541 aprint_error(": failed to init txq: %d\n", error); 542 return; 543 } 544 545 error = pq3etsec_mapcache_create(sc, &sc->sc_rx_mapcache, 546 ETSEC_MAXRXMBUFS, ETSEC_MINRXMBUFS, MCLBYTES, ETSEC_NRXSEGS); 547 if (error) { 548 aprint_error(": failed to allocate rx dmamaps: %d\n", error); 549 return; 550 } 551 552 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 553 ETSEC_MAXTXMBUFS, ETSEC_MAXTXMBUFS, MCLBYTES, ETSEC_NTXSEGS); 554 if (error) { 555 aprint_error(": failed to allocate tx dmamaps: %d\n", error); 556 return; 557 } 558 559 sc->sc_tx_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 560 pq3etsec_tx_intr, sc); 561 if (sc->sc_tx_ih == NULL) { 562 aprint_error(": failed to establish tx interrupt: %d\n", 563 cnl->cnl_intrs[0]); 564 return; 565 } 566 567 sc->sc_rx_ih = intr_establish(cnl->cnl_intrs[1], IPL_VM, IST_ONCHIP, 568 pq3etsec_rx_intr, sc); 569 if (sc->sc_rx_ih == NULL) { 570 aprint_error(": failed to establish rx interrupt: %d\n", 571 cnl->cnl_intrs[1]); 572 return; 573 } 574 575 sc->sc_error_ih = intr_establish(cnl->cnl_intrs[2], IPL_VM, IST_ONCHIP, 576 pq3etsec_error_intr, sc); 577 if (sc->sc_error_ih == NULL) { 578 aprint_error(": failed to establish error interrupt: %d\n", 579 cnl->cnl_intrs[2]); 580 return; 581 } 582 583 sc->sc_soft_ih = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE, 584 pq3etsec_soft_intr, sc); 585 if (sc->sc_soft_ih == NULL) { 586 aprint_error(": failed to establish soft interrupt\n"); 587 return; 588 } 589 590 aprint_normal("\n"); 591 592 etsec_write(sc, ATTR, ATTR_DEFAULT); 593 etsec_write(sc, ATTRELI, ATTRELI_DEFAULT); 594 595 sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_SOFTNET); 596 597 callout_init(&sc->sc_mii_callout, CALLOUT_MPSAFE); 598 callout_setfunc(&sc->sc_mii_callout, pq3etsec_mii_tick, sc); 599 600 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 601 ether_sprintf(enaddr)); 602 603 const char * const xname = device_xname(sc->sc_dev); 604 struct ethercom * const ec = &sc->sc_ec; 605 struct ifnet * const ifp = &ec->ec_if; 606 607 ec->ec_mii = &sc->sc_mii; 608 609 sc->sc_mii.mii_ifp = ifp; 610 sc->sc_mii.mii_readreg = pq3etsec_mii_readreg; 611 sc->sc_mii.mii_writereg = pq3etsec_mii_writereg; 612 sc->sc_mii.mii_statchg = pq3etsec_mii_statchg; 613 614 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 615 ether_mediastatus); 616 617 if (sc->sc_phy_addr < 32) { 618 mii_attach(miiself, &sc->sc_mii, 0xffffffff, 619 sc->sc_phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 620 621 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 622 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 623 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 624 } else { 625 callout_schedule(&sc->sc_mii_callout, hz); 626 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 627 } 628 } else { 629 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 630 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX); 631 } 632 633 ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING 634 | ETHERCAP_JUMBO_MTU; 635 636 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 637 ifp->if_softc = sc; 638 ifp->if_capabilities = IFCAP_ETSEC; 639 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 640 ifp->if_ioctl = pq3etsec_ifioctl; 641 ifp->if_start = pq3etsec_ifstart; 642 ifp->if_watchdog = pq3etsec_ifwatchdog; 643 ifp->if_init = pq3etsec_ifinit; 644 ifp->if_stop = pq3etsec_ifstop; 645 IFQ_SET_READY(&ifp->if_snd); 646 647 pq3etsec_ifstop(ifp, true); 648 649 /* 650 * Attach the interface. 651 */ 652 if_attach(ifp); 653 ether_ifattach(ifp, enaddr); 654 655 evcnt_attach_dynamic(&sc->sc_ev_rx_stall, EVCNT_TYPE_MISC, 656 NULL, xname, "rx stall"); 657 evcnt_attach_dynamic(&sc->sc_ev_tx_stall, EVCNT_TYPE_MISC, 658 NULL, xname, "tx stall"); 659 evcnt_attach_dynamic(&sc->sc_ev_tx_intr, EVCNT_TYPE_INTR, 660 NULL, xname, "tx intr"); 661 evcnt_attach_dynamic(&sc->sc_ev_rx_intr, EVCNT_TYPE_INTR, 662 NULL, xname, "rx intr"); 663 evcnt_attach_dynamic(&sc->sc_ev_error_intr, EVCNT_TYPE_INTR, 664 NULL, xname, "error intr"); 665 evcnt_attach_dynamic(&sc->sc_ev_soft_intr, EVCNT_TYPE_INTR, 666 NULL, xname, "soft intr"); 667 evcnt_attach_dynamic(&sc->sc_ev_tx_pause, EVCNT_TYPE_MISC, 668 NULL, xname, "tx pause"); 669 evcnt_attach_dynamic(&sc->sc_ev_rx_pause, EVCNT_TYPE_MISC, 670 NULL, xname, "rx pause"); 671 evcnt_attach_dynamic(&sc->sc_ev_mii_ticks, EVCNT_TYPE_MISC, 672 NULL, xname, "mii ticks"); 673 } 674 675 static uint64_t 676 pq3etsec_macaddr_create(const uint8_t *lladdr) 677 { 678 uint64_t macaddr = 0; 679 680 lladdr += ETHER_ADDR_LEN; 681 for (u_int i = ETHER_ADDR_LEN; i-- > 0; ) { 682 macaddr = (macaddr << 8) | *--lladdr; 683 } 684 return macaddr << 16; 685 } 686 687 static int 688 pq3etsec_ifinit(struct ifnet *ifp) 689 { 690 struct pq3etsec_softc * const sc = ifp->if_softc; 691 int error = 0; 692 693 sc->sc_maxfrm = max(ifp->if_mtu + 32, MCLBYTES); 694 if (ifp->if_mtu > ETHERMTU_JUMBO) 695 return error; 696 697 KASSERT(ifp->if_flags & IFF_UP); 698 699 /* 700 * Stop the interface (steps 1 to 4 in the Soft Reset and 701 * Reconfigurating Procedure. 702 */ 703 pq3etsec_ifstop(ifp, 0); 704 705 /* 706 * If our frame size has changed (or it's our first time through) 707 * destroy the existing transmit mapcache. 708 */ 709 if (sc->sc_tx_mapcache != NULL 710 && sc->sc_maxfrm != sc->sc_tx_mapcache->dmc_maxmapsize) { 711 pq3etsec_mapcache_destroy(sc, sc->sc_tx_mapcache); 712 sc->sc_tx_mapcache = NULL; 713 } 714 715 if (sc->sc_tx_mapcache == NULL) { 716 error = pq3etsec_mapcache_create(sc, &sc->sc_tx_mapcache, 717 ETSEC_MAXTXMBUFS, ETSEC_MAXTXMBUFS, sc->sc_maxfrm, 718 ETSEC_NTXSEGS); 719 if (error) 720 return error; 721 } 722 723 sc->sc_ev_mii_ticks.ev_count++; 724 mii_tick(&sc->sc_mii); 725 726 if (ifp->if_flags & IFF_PROMISC) { 727 sc->sc_rctrl |= RCTRL_PROM; 728 } else { 729 sc->sc_rctrl &= ~RCTRL_PROM; 730 } 731 732 uint32_t rctrl_prsdep = 0; 733 sc->sc_rctrl &= ~(RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP); 734 if (VLAN_ATTACHED(&sc->sc_ec)) { 735 sc->sc_rctrl |= RCTRL_VLEX; 736 rctrl_prsdep = RCTRL_PRSDEP_L2; 737 } 738 if (ifp->if_capenable & IFCAP_RCTRL_IPCSEN) { 739 sc->sc_rctrl |= RCTRL_IPCSEN; 740 rctrl_prsdep = RCTRL_PRSDEP_L3; 741 } 742 if (ifp->if_capenable & IFCAP_RCTRL_TUCSEN) { 743 sc->sc_rctrl |= RCTRL_TUCSEN; 744 rctrl_prsdep = RCTRL_PRSDEP_L4; 745 } 746 sc->sc_rctrl |= rctrl_prsdep; 747 #if 0 748 if (sc->sc_rctrl & (RCTRL_IPCSEN|RCTRL_TUCSEN|RCTRL_VLEX|RCTRL_PRSDEP)) 749 aprint_normal_dev(sc->sc_dev, 750 "rctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlex=%"PRIuMAX" prsdep=%"PRIuMAX"\n", 751 sc->sc_rctrl, 752 __SHIFTOUT(sc->sc_rctrl, RCTRL_IPCSEN), 753 __SHIFTOUT(sc->sc_rctrl, RCTRL_TUCSEN), 754 __SHIFTOUT(sc->sc_rctrl, RCTRL_VLEX), 755 __SHIFTOUT(sc->sc_rctrl, RCTRL_PRSDEP)); 756 #endif 757 758 sc->sc_tctrl &= ~(TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS); 759 if (VLAN_ATTACHED(&sc->sc_ec)) /* is this really true */ 760 sc->sc_tctrl |= TCTRL_VLINS; 761 if (ifp->if_capenable & IFCAP_TCTRL_IPCSEN) 762 sc->sc_tctrl |= TCTRL_IPCSEN; 763 if (ifp->if_capenable & IFCAP_TCTRL_TUCSEN) 764 sc->sc_tctrl |= TCTRL_TUCSEN; 765 #if 0 766 if (sc->sc_tctrl & (TCTRL_IPCSEN|TCTRL_TUCSEN|TCTRL_VLINS)) 767 aprint_normal_dev(sc->sc_dev, 768 "tctrl=%#x ipcsen=%"PRIuMAX" tucsen=%"PRIuMAX" vlins=%"PRIuMAX"\n", 769 sc->sc_tctrl, 770 __SHIFTOUT(sc->sc_tctrl, TCTRL_IPCSEN), 771 __SHIFTOUT(sc->sc_tctrl, TCTRL_TUCSEN), 772 __SHIFTOUT(sc->sc_tctrl, TCTRL_VLINS)); 773 #endif 774 775 sc->sc_maccfg1 &= ~(MACCFG1_TX_EN|MACCFG1_RX_EN); 776 777 const uint64_t macstnaddr = 778 pq3etsec_macaddr_create(CLLADDR(ifp->if_sadl)); 779 780 sc->sc_imask = IEVENT_DPE; 781 782 /* 5. Load TDBPH, TBASEH, TBASE0-TBASE7 with new Tx BD pointers */ 783 pq3etsec_rxq_reset(sc, &sc->sc_rxq); 784 pq3etsec_rxq_produce(sc, &sc->sc_rxq); /* fill with rx buffers */ 785 786 /* 6. Load RDBPH, RBASEH, RBASE0-RBASE7 with new Rx BD pointers */ 787 pq3etsec_txq_reset(sc, &sc->sc_txq); 788 789 /* 7. Setup other MAC registers (MACCFG2, MAXFRM, etc.) */ 790 KASSERT(MACCFG2_PADCRC & sc->sc_maccfg2); 791 etsec_write(sc, MAXFRM, sc->sc_maxfrm); 792 etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32)); 793 etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >> 0)); 794 etsec_write(sc, MACCFG1, sc->sc_maccfg1); 795 etsec_write(sc, MACCFG2, sc->sc_maccfg2); 796 etsec_write(sc, ECNTRL, sc->sc_ecntrl); 797 798 /* 8. Setup group address hash table (GADDR0-GADDR15) */ 799 pq3etsec_mc_setup(sc); 800 801 /* 9. Setup receive frame filer table (via RQFAR, RQFCR, and RQFPR) */ 802 etsec_write(sc, MRBLR, MCLBYTES); 803 804 /* 10. Setup WWR, WOP, TOD bits in DMACTRL register */ 805 sc->sc_dmactrl |= DMACTRL_DEFAULT; 806 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 807 808 /* 11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set in TCTRL. */ 809 etsec_write(sc, TQUEUE, TQUEUE_EN0); 810 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE|IEVENT_TXC; 811 812 etsec_write(sc, TCTRL, sc->sc_tctrl); /* for TOE stuff */ 813 814 /* 12. Enable receive queues in RQUEUE, */ 815 etsec_write(sc, RQUEUE, RQUEUE_EN0|RQUEUE_EX0); 816 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY|IEVENT_RXC; 817 818 /* and optionally set TOE functionality in RCTRL. */ 819 etsec_write(sc, RCTRL, sc->sc_rctrl); 820 sc->sc_rx_adjlen = __SHIFTOUT(sc->sc_rctrl, RCTRL_PAL); 821 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) 822 sc->sc_rx_adjlen += sizeof(struct rxfcb); 823 824 /* 13. Clear THLT and TXF bits in TSTAT register by writing 1 to them */ 825 etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF); 826 827 /* 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.*/ 828 etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF); 829 830 /* 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) */ 831 sc->sc_dmactrl &= ~(DMACTRL_GRS|DMACTRL_GTS); 832 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 833 834 /* 16. Enable Tx_EN/Rx_EN in MACCFG1 register */ 835 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 836 etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN); 837 838 sc->sc_soft_flags = 0; 839 840 etsec_write(sc, IMASK, sc->sc_imask); 841 842 ifp->if_flags |= IFF_RUNNING; 843 844 return error; 845 } 846 847 static void 848 pq3etsec_ifstop(struct ifnet *ifp, int disable) 849 { 850 struct pq3etsec_softc * const sc = ifp->if_softc; 851 852 KASSERT(!cpu_intr_p()); 853 const uint32_t imask_gsc_mask = IEVENT_GTSC|IEVENT_GRSC; 854 /* 855 * Clear the GTSC and GRSC from the interrupt mask until 856 * we are ready for them. Then clear them from IEVENT, 857 * request the graceful shutdown, and then enable the 858 * GTSC and GRSC bits in the mask. This should cause the 859 * error interrupt to fire which will issue a wakeup to 860 * allow us to resume. 861 */ 862 863 /* 864 * 1. Set GRS/GTS bits in DMACTRL register 865 */ 866 sc->sc_dmactrl |= DMACTRL_GRS|DMACTRL_GTS; 867 etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask); 868 etsec_write(sc, IEVENT, imask_gsc_mask); 869 etsec_write(sc, DMACTRL, sc->sc_dmactrl); 870 871 if (etsec_read(sc, MACCFG1) & (MACCFG1_TX_EN|MACCFG1_RX_EN)) { 872 /* 873 * 2. Poll GRSC/GTSC bits in IEVENT register until both are set 874 */ 875 etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask); 876 877 u_int timo = 1000; 878 uint32_t ievent = etsec_read(sc, IEVENT); 879 while ((ievent & imask_gsc_mask) != imask_gsc_mask) { 880 if (--timo == 0) { 881 aprint_error_dev(sc->sc_dev, 882 "WARNING: " 883 "request to stop failed (IEVENT=%#x)\n", 884 ievent); 885 break; 886 } 887 delay(10); 888 ievent = etsec_read(sc, IEVENT); 889 } 890 } 891 892 /* 893 * Now reset the controller. 894 * 895 * 3. Set SOFT_RESET bit in MACCFG1 register 896 * 4. Clear SOFT_RESET bit in MACCFG1 register 897 */ 898 etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET); 899 etsec_write(sc, MACCFG1, 0); 900 etsec_write(sc, IMASK, 0); 901 etsec_write(sc, IEVENT, ~0); 902 sc->sc_imask = 0; 903 ifp->if_flags &= ~IFF_RUNNING; 904 905 uint32_t tbipa = etsec_read(sc, TBIPA); 906 if (tbipa == sc->sc_phy_addr) { 907 aprint_normal_dev(sc->sc_dev, "relocating TBI\n"); 908 etsec_write(sc, TBIPA, 0x1f); 909 } 910 uint32_t miimcfg = etsec_read(sc, MIIMCFG); 911 etsec_write(sc, MIIMCFG, MIIMCFG_RESET); 912 etsec_write(sc, MIIMCFG, miimcfg); 913 914 /* 915 * Let's consume any remaing transmitted packets. And if we are 916 * disabling the interface, purge ourselves of any untransmitted 917 * packets. But don't consume any received packets, just drop them. 918 * If we aren't disabling the interface, save the mbufs in the 919 * receive queue for reuse. 920 */ 921 pq3etsec_rxq_purge(sc, &sc->sc_rxq, disable); 922 pq3etsec_txq_consume(sc, &sc->sc_txq); 923 if (disable) { 924 pq3etsec_txq_purge(sc, &sc->sc_txq); 925 IF_PURGE(&ifp->if_snd); 926 } 927 } 928 929 static void 930 pq3etsec_ifwatchdog(struct ifnet *ifp) 931 { 932 } 933 934 static void 935 pq3etsec_mc_setup( 936 struct pq3etsec_softc *sc) 937 { 938 struct ethercom * const ec = &sc->sc_ec; 939 struct ifnet * const ifp = &sc->sc_if; 940 struct ether_multi *enm; 941 struct ether_multistep step; 942 uint32_t *gaddr = sc->sc_gaddr + ((sc->sc_rctrl & RCTRL_GHTX) ? 0 : 8); 943 const uint32_t crc_shift = 32 - ((sc->sc_rctrl & RCTRL_GHTX) ? 9 : 8); 944 945 memset(sc->sc_gaddr, 0, sizeof(sc->sc_gaddr)); 946 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 947 948 ifp->if_flags &= ~IFF_ALLMULTI; 949 950 ETHER_FIRST_MULTI(step, ec, enm); 951 for (u_int i = 0; enm != NULL; ) { 952 const char *addr = enm->enm_addrlo; 953 if (memcmp(addr, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 954 ifp->if_flags |= IFF_ALLMULTI; 955 memset(gaddr, 0xff, 32 << (crc_shift & 1)); 956 memset(sc->sc_macaddrs, 0, sizeof(sc->sc_macaddrs)); 957 break; 958 } 959 if ((sc->sc_rctrl & RCTRL_EMEN) 960 && i < __arraycount(sc->sc_macaddrs)) { 961 sc->sc_macaddrs[i++] = pq3etsec_macaddr_create(addr); 962 } else { 963 uint32_t crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 964 #if 0 965 printf("%s: %s: crc=%#x: %#x: [%u,%u]=%#x\n", __func__, 966 ether_sprintf(addr), crc, 967 crc >> crc_shift, 968 crc >> (crc_shift + 5), 969 (crc >> crc_shift) & 31, 970 1 << (((crc >> crc_shift) & 31) ^ 31)); 971 #endif 972 /* 973 * The documentation doesn't completely follow PowerPC 974 * bit order. The BE crc32 (H) for 01:00:5E:00:00:01 975 * is 0x7fa32d9b. By empirical testing, the 976 * corresponding hash bit is word 3, bit 31 (ppc bit 977 * order). Since 3 << 31 | 31 is 0x7f, we deduce 978 * H[0:2] selects the register while H[3:7] selects 979 * the bit (ppc bit order). 980 */ 981 crc >>= crc_shift; 982 gaddr[crc / 32] |= 1 << ((crc & 31) ^ 31); 983 } 984 ETHER_NEXT_MULTI(step, enm); 985 } 986 for (u_int i = 0; i < 8; i++) { 987 etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]); 988 etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]); 989 #if 0 990 if (sc->sc_gaddr[i] || sc->sc_gaddr[i+8]) 991 printf("%s: IGADDR%u(%#x)=%#x GADDR%u(%#x)=%#x\n", __func__, 992 i, IGADDR(i), etsec_read(sc, IGADDR(i)), 993 i, GADDR(i), etsec_read(sc, GADDR(i))); 994 #endif 995 } 996 for (u_int i = 0; i < __arraycount(sc->sc_macaddrs); i++) { 997 uint64_t macaddr = sc->sc_macaddrs[i]; 998 etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32)); 999 etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >> 0)); 1000 #if 0 1001 if (macaddr) 1002 printf("%s: MAC%02uADDR2(%08x)=%#x MAC%02uADDR2(%#x)=%08x\n", __func__, 1003 i+1, MACnADDR1(i), etsec_read(sc, MACnADDR1(i)), 1004 i+1, MACnADDR2(i), etsec_read(sc, MACnADDR2(i))); 1005 #endif 1006 } 1007 } 1008 1009 static int 1010 pq3etsec_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 1011 { 1012 struct pq3etsec_softc *sc = ifp->if_softc; 1013 struct ifreq * const ifr = data; 1014 const int s = splnet(); 1015 int error; 1016 1017 switch (cmd) { 1018 case SIOCSIFMEDIA: 1019 case SIOCGIFMEDIA: 1020 /* Flow control requires full-duplex mode. */ 1021 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1022 (ifr->ifr_media & IFM_FDX) == 0) 1023 ifr->ifr_media &= ~IFM_ETH_FMASK; 1024 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1025 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1026 /* We can do both TXPAUSE and RXPAUSE. */ 1027 ifr->ifr_media |= 1028 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1029 } 1030 } 1031 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1032 break; 1033 1034 default: 1035 error = ether_ioctl(ifp, cmd, data); 1036 if (error != ENETRESET) 1037 break; 1038 1039 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1040 error = 0; 1041 if (ifp->if_flags & IFF_RUNNING) 1042 pq3etsec_mc_setup(sc); 1043 break; 1044 } 1045 error = pq3etsec_ifinit(ifp); 1046 break; 1047 } 1048 1049 splx(s); 1050 return error; 1051 } 1052 1053 static void 1054 pq3etsec_rxq_desc_presync( 1055 struct pq3etsec_softc *sc, 1056 struct pq3etsec_rxqueue *rxq, 1057 volatile struct rxbd *rxbd, 1058 size_t count) 1059 { 1060 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1061 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1062 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1063 } 1064 1065 static void 1066 pq3etsec_rxq_desc_postsync( 1067 struct pq3etsec_softc *sc, 1068 struct pq3etsec_rxqueue *rxq, 1069 volatile struct rxbd *rxbd, 1070 size_t count) 1071 { 1072 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_descmap, 1073 (rxbd - rxq->rxq_first) * sizeof(*rxbd), count * sizeof(*rxbd), 1074 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1075 } 1076 1077 static void 1078 pq3etsec_txq_desc_presync( 1079 struct pq3etsec_softc *sc, 1080 struct pq3etsec_txqueue *txq, 1081 volatile struct txbd *txbd, 1082 size_t count) 1083 { 1084 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1085 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1086 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1087 } 1088 1089 static void 1090 pq3etsec_txq_desc_postsync( 1091 struct pq3etsec_softc *sc, 1092 struct pq3etsec_txqueue *txq, 1093 volatile struct txbd *txbd, 1094 size_t count) 1095 { 1096 bus_dmamap_sync(sc->sc_dmat, txq->txq_descmap, 1097 (txbd - txq->txq_first) * sizeof(*txbd), count * sizeof(*txbd), 1098 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1099 } 1100 1101 static bus_dmamap_t 1102 pq3etsec_mapcache_get( 1103 struct pq3etsec_softc *sc, 1104 struct pq3etsec_mapcache *dmc) 1105 { 1106 if (dmc->dmc_nmaps == 0) { 1107 bus_dmamap_t map; 1108 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1109 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1110 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &map); 1111 if (error) { 1112 aprint_error_dev(sc->sc_dev, 1113 "failed to allocate a %zuB map: %d\n", 1114 dmc->dmc_maxmapsize, error); 1115 return NULL; 1116 } 1117 return map; 1118 } 1119 1120 KASSERT(dmc->dmc_maps[dmc->dmc_nmaps-1] != NULL); 1121 return dmc->dmc_maps[--dmc->dmc_nmaps]; 1122 } 1123 1124 static void 1125 pq3etsec_mapcache_put( 1126 struct pq3etsec_softc *sc, 1127 struct pq3etsec_mapcache *dmc, 1128 bus_dmamap_t map) 1129 { 1130 KASSERT(map != NULL); 1131 KASSERT(dmc->dmc_nmaps < dmc->dmc_maxmaps); 1132 dmc->dmc_maps[dmc->dmc_nmaps++] = map; 1133 } 1134 1135 static void 1136 pq3etsec_mapcache_destroy( 1137 struct pq3etsec_softc *sc, 1138 struct pq3etsec_mapcache *dmc) 1139 { 1140 const size_t dmc_size = 1141 offsetof(struct pq3etsec_mapcache, dmc_maps[dmc->dmc_maxmaps]); 1142 1143 for (u_int i = 0; i < dmc->dmc_maxmaps; i++) { 1144 bus_dmamap_destroy(sc->sc_dmat, dmc->dmc_maps[i]); 1145 } 1146 kmem_free(dmc, dmc_size); 1147 } 1148 1149 static int 1150 pq3etsec_mapcache_create( 1151 struct pq3etsec_softc *sc, 1152 struct pq3etsec_mapcache **dmc_p, 1153 size_t maxmaps, 1154 size_t minmaps, 1155 size_t maxmapsize, 1156 size_t maxseg) 1157 { 1158 const size_t dmc_size = 1159 offsetof(struct pq3etsec_mapcache, dmc_maps[maxmaps]); 1160 struct pq3etsec_mapcache * const dmc = kmem_zalloc(dmc_size, KM_SLEEP); 1161 1162 dmc->dmc_maxmaps = maxmaps; 1163 dmc->dmc_nmaps = minmaps; 1164 dmc->dmc_maxmapsize = maxmapsize; 1165 dmc->dmc_maxseg = maxseg; 1166 1167 for (u_int i = 0; i < minmaps; i++) { 1168 int error = bus_dmamap_create(sc->sc_dmat, dmc->dmc_maxmapsize, 1169 dmc->dmc_maxseg, dmc->dmc_maxmapsize, 0, 1170 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &dmc->dmc_maps[i]); 1171 if (error) { 1172 aprint_error_dev(sc->sc_dev, 1173 "failed to creat dma map cache " 1174 "entry %u of %zu (max %zu): %d\n", 1175 i, minmaps, maxmaps, error); 1176 while (i-- > 0) { 1177 bus_dmamap_destroy(sc->sc_dmat, 1178 dmc->dmc_maps[i]); 1179 } 1180 kmem_free(dmc, dmc_size); 1181 return error; 1182 } 1183 KASSERT(dmc->dmc_maps[i] != NULL); 1184 } 1185 1186 *dmc_p = dmc; 1187 1188 return 0; 1189 } 1190 1191 #if 0 1192 static void 1193 pq3etsec_dmamem_free( 1194 bus_dma_tag_t dmat, 1195 size_t map_size, 1196 bus_dma_segment_t *seg, 1197 bus_dmamap_t map, 1198 void *kvap) 1199 { 1200 bus_dmamap_destroy(dmat, map); 1201 bus_dmamem_unmap(dmat, kvap, map_size); 1202 bus_dmamem_free(dmat, seg, 1); 1203 } 1204 #endif 1205 1206 static int 1207 pq3etsec_dmamem_alloc( 1208 bus_dma_tag_t dmat, 1209 size_t map_size, 1210 bus_dma_segment_t *seg, 1211 bus_dmamap_t *map, 1212 void **kvap) 1213 { 1214 int error; 1215 int nseg; 1216 1217 *kvap = NULL; 1218 *map = NULL; 1219 1220 error = bus_dmamem_alloc(dmat, map_size, PAGE_SIZE, 0, 1221 seg, 1, &nseg, 0); 1222 if (error) 1223 return error; 1224 1225 KASSERT(nseg == 1); 1226 1227 error = bus_dmamem_map(dmat, seg, nseg, map_size, (void **)kvap, 1228 BUS_DMA_COHERENT); 1229 if (error == 0) { 1230 error = bus_dmamap_create(dmat, map_size, 1, map_size, 0, 0, 1231 map); 1232 if (error == 0) { 1233 error = bus_dmamap_load(dmat, *map, *kvap, map_size, 1234 NULL, 0); 1235 if (error == 0) 1236 return 0; 1237 bus_dmamap_destroy(dmat, *map); 1238 *map = NULL; 1239 } 1240 bus_dmamem_unmap(dmat, *kvap, map_size); 1241 *kvap = NULL; 1242 } 1243 bus_dmamem_free(dmat, seg, nseg); 1244 return 0; 1245 } 1246 1247 static struct mbuf * 1248 pq3etsec_rx_buf_alloc( 1249 struct pq3etsec_softc *sc) 1250 { 1251 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 1252 if (m == NULL) { 1253 printf("%s:%d: %s\n", __func__, __LINE__, "m_gethdr"); 1254 return NULL; 1255 } 1256 MCLGET(m, M_DONTWAIT); 1257 if ((m->m_flags & M_EXT) == 0) { 1258 printf("%s:%d: %s\n", __func__, __LINE__, "MCLGET"); 1259 m_freem(m); 1260 return NULL; 1261 } 1262 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1263 1264 bus_dmamap_t map = pq3etsec_mapcache_get(sc, sc->sc_rx_mapcache); 1265 if (map == NULL) { 1266 printf("%s:%d: %s\n", __func__, __LINE__, "map get"); 1267 m_freem(m); 1268 return NULL; 1269 } 1270 M_SETCTX(m, map); 1271 m->m_len = m->m_pkthdr.len = MCLBYTES; 1272 int error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1273 BUS_DMA_READ|BUS_DMA_NOWAIT); 1274 if (error) { 1275 aprint_error_dev(sc->sc_dev, "fail to load rx dmamap: %d\n", 1276 error); 1277 M_SETCTX(m, NULL); 1278 m_freem(m); 1279 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1280 return NULL; 1281 } 1282 KASSERT(map->dm_mapsize == MCLBYTES); 1283 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1284 BUS_DMASYNC_PREREAD); 1285 1286 return m; 1287 } 1288 1289 static void 1290 pq3etsec_rx_map_unload( 1291 struct pq3etsec_softc *sc, 1292 struct mbuf *m) 1293 { 1294 KASSERT(m); 1295 for (; m != NULL; m = m->m_next) { 1296 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1297 KASSERT(map); 1298 KASSERT(map->dm_mapsize == MCLBYTES); 1299 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_len, 1300 BUS_DMASYNC_POSTREAD); 1301 bus_dmamap_unload(sc->sc_dmat, map); 1302 pq3etsec_mapcache_put(sc, sc->sc_rx_mapcache, map); 1303 M_SETCTX(m, NULL); 1304 } 1305 } 1306 1307 static bool 1308 pq3etsec_rxq_produce( 1309 struct pq3etsec_softc *sc, 1310 struct pq3etsec_rxqueue *rxq) 1311 { 1312 volatile struct rxbd *producer = rxq->rxq_producer; 1313 #if 0 1314 size_t inuse = rxq->rxq_inuse; 1315 #endif 1316 while (rxq->rxq_inuse < rxq->rxq_threshold) { 1317 struct mbuf *m; 1318 IF_DEQUEUE(&sc->sc_rx_bufcache, m); 1319 if (m == NULL) { 1320 m = pq3etsec_rx_buf_alloc(sc); 1321 if (m == NULL) { 1322 printf("%s: pq3etsec_rx_buf_alloc failed\n", __func__); 1323 break; 1324 } 1325 } 1326 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1327 KASSERT(map); 1328 1329 #ifdef ETSEC_DEBUG 1330 KASSERT(rxq->rxq_mbufs[producer-rxq->rxq_first] == NULL); 1331 rxq->rxq_mbufs[producer-rxq->rxq_first] = m; 1332 #endif 1333 1334 /* rxbd_len is write-only by the ETSEC */ 1335 producer->rxbd_bufptr = map->dm_segs[0].ds_addr; 1336 membar_producer(); 1337 producer->rxbd_flags |= RXBD_E; 1338 if (__predict_false(rxq->rxq_mhead == NULL)) { 1339 KASSERT(producer == rxq->rxq_consumer); 1340 rxq->rxq_mconsumer = m; 1341 } 1342 *rxq->rxq_mtail = m; 1343 rxq->rxq_mtail = &m->m_next; 1344 m->m_len = MCLBYTES; 1345 m->m_next = NULL; 1346 rxq->rxq_inuse++; 1347 if (++producer == rxq->rxq_last) { 1348 membar_producer(); 1349 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1350 rxq->rxq_last - rxq->rxq_producer); 1351 producer = rxq->rxq_producer = rxq->rxq_first; 1352 } 1353 } 1354 if (producer != rxq->rxq_producer) { 1355 membar_producer(); 1356 pq3etsec_rxq_desc_presync(sc, rxq, rxq->rxq_producer, 1357 producer - rxq->rxq_producer); 1358 rxq->rxq_producer = producer; 1359 } 1360 uint32_t qhlt = etsec_read(sc, RSTAT) & RSTAT_QHLT; 1361 if (qhlt) { 1362 KASSERT(qhlt & rxq->rxq_qmask); 1363 sc->sc_ev_rx_stall.ev_count++; 1364 etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask); 1365 } 1366 #if 0 1367 aprint_normal_dev(sc->sc_dev, 1368 "%s: buffers inuse went from %zu to %zu\n", 1369 __func__, inuse, rxq->rxq_inuse); 1370 #endif 1371 return true; 1372 } 1373 1374 static bool 1375 pq3etsec_rx_offload( 1376 struct pq3etsec_softc *sc, 1377 struct mbuf *m, 1378 const struct rxfcb *fcb) 1379 { 1380 if (fcb->rxfcb_flags & RXFCB_VLN) { 1381 VLAN_INPUT_TAG(&sc->sc_if, m, fcb->rxfcb_vlctl, 1382 m_freem(m); return false); 1383 } 1384 if ((fcb->rxfcb_flags & RXFCB_IP) == 0 1385 || (fcb->rxfcb_flags & (RXFCB_CIP|RXFCB_CTU)) == 0) 1386 return true; 1387 int csum_flags = 0; 1388 if ((fcb->rxfcb_flags & (RXFCB_IP6|RXFCB_CIP)) == RXFCB_CIP) { 1389 csum_flags |= M_CSUM_IPv4; 1390 if (fcb->rxfcb_flags & RXFCB_EIP) 1391 csum_flags |= M_CSUM_IPv4_BAD; 1392 } 1393 if ((fcb->rxfcb_flags & RXFCB_CTU) == RXFCB_CTU) { 1394 int ipv_flags; 1395 if (fcb->rxfcb_flags & RXFCB_IP6) 1396 ipv_flags = M_CSUM_TCPv6|M_CSUM_UDPv6; 1397 else 1398 ipv_flags = M_CSUM_TCPv4|M_CSUM_UDPv4; 1399 if (fcb->rxfcb_pro == IPPROTO_TCP) { 1400 csum_flags |= (M_CSUM_TCPv4|M_CSUM_TCPv6) & ipv_flags; 1401 } else { 1402 csum_flags |= (M_CSUM_UDPv4|M_CSUM_UDPv6) & ipv_flags; 1403 } 1404 if (fcb->rxfcb_flags & RXFCB_ETU) 1405 csum_flags |= M_CSUM_TCP_UDP_BAD; 1406 } 1407 1408 m->m_pkthdr.csum_flags = csum_flags; 1409 return true; 1410 } 1411 1412 static void 1413 pq3etsec_rx_input( 1414 struct pq3etsec_softc *sc, 1415 struct mbuf *m, 1416 uint16_t rxbd_flags) 1417 { 1418 struct ifnet * const ifp = &sc->sc_if; 1419 1420 pq3etsec_rx_map_unload(sc, m); 1421 1422 if ((sc->sc_rctrl & RCTRL_PRSDEP) != RCTRL_PRSDEP_OFF) { 1423 struct rxfcb fcb = *mtod(m, struct rxfcb *); 1424 if (!pq3etsec_rx_offload(sc, m, &fcb)) 1425 return; 1426 } 1427 m_adj(m, sc->sc_rx_adjlen); 1428 1429 if (rxbd_flags & RXBD_M) 1430 m->m_flags |= M_PROMISC; 1431 if (rxbd_flags & RXBD_BC) 1432 m->m_flags |= M_BCAST; 1433 if (rxbd_flags & RXBD_MC) 1434 m->m_flags |= M_MCAST; 1435 m->m_flags |= M_HASFCS; 1436 m->m_pkthdr.rcvif = &sc->sc_if; 1437 1438 ifp->if_ipackets++; 1439 ifp->if_ibytes += m->m_pkthdr.len; 1440 1441 /* 1442 * Let's give it to the network subsystm to deal with. 1443 */ 1444 int s = splnet(); 1445 bpf_mtap(ifp, m); 1446 (*ifp->if_input)(ifp, m); 1447 splx(s); 1448 } 1449 1450 static void 1451 pq3etsec_rxq_consume( 1452 struct pq3etsec_softc *sc, 1453 struct pq3etsec_rxqueue *rxq) 1454 { 1455 struct ifnet * const ifp = &sc->sc_if; 1456 volatile struct rxbd *consumer = rxq->rxq_consumer; 1457 size_t rxconsumed = 0; 1458 1459 etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask); 1460 1461 for (;;) { 1462 if (consumer == rxq->rxq_producer) { 1463 rxq->rxq_consumer = consumer; 1464 rxq->rxq_inuse -= rxconsumed; 1465 KASSERT(rxq->rxq_inuse == 0); 1466 return; 1467 } 1468 pq3etsec_rxq_desc_postsync(sc, rxq, consumer, 1); 1469 const uint16_t rxbd_flags = consumer->rxbd_flags; 1470 if (rxbd_flags & RXBD_E) { 1471 rxq->rxq_consumer = consumer; 1472 rxq->rxq_inuse -= rxconsumed; 1473 return; 1474 } 1475 KASSERT(rxq->rxq_mconsumer != NULL); 1476 #ifdef ETSEC_DEBUG 1477 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1478 #endif 1479 #if 0 1480 printf("%s: rxdb[%u]: flags=%#x len=%#x: %08x %08x %08x %08x\n", 1481 __func__, 1482 consumer - rxq->rxq_first, rxbd_flags, consumer->rxbd_len, 1483 mtod(rxq->rxq_mconsumer, int *)[0], 1484 mtod(rxq->rxq_mconsumer, int *)[1], 1485 mtod(rxq->rxq_mconsumer, int *)[2], 1486 mtod(rxq->rxq_mconsumer, int *)[3]); 1487 #endif 1488 /* 1489 * We own this packet again. Clear all flags except wrap. 1490 */ 1491 rxconsumed++; 1492 consumer->rxbd_flags = rxbd_flags & (RXBD_W|RXBD_I); 1493 1494 /* 1495 * If this descriptor has the LAST bit set and no errors, 1496 * it's a valid input packet. 1497 */ 1498 if ((rxbd_flags & (RXBD_L|RXBD_ERRORS)) == RXBD_L) { 1499 size_t rxbd_len = consumer->rxbd_len; 1500 struct mbuf *m = rxq->rxq_mhead; 1501 struct mbuf *m_last = rxq->rxq_mconsumer; 1502 if ((rxq->rxq_mhead = m_last->m_next) == NULL) 1503 rxq->rxq_mtail = &rxq->rxq_mhead; 1504 rxq->rxq_mconsumer = rxq->rxq_mhead; 1505 m_last->m_next = NULL; 1506 m_last->m_len = rxbd_len & (MCLBYTES - 1); 1507 m->m_pkthdr.len = rxbd_len; 1508 pq3etsec_rx_input(sc, m, rxbd_flags); 1509 } else if (rxbd_flags & RXBD_L) { 1510 KASSERT(rxbd_flags & RXBD_ERRORS); 1511 struct mbuf *m; 1512 /* 1513 * We encountered an error, take the mbufs and add 1514 * then to the rx bufcache so we can reuse them. 1515 */ 1516 ifp->if_ierrors++; 1517 for (m = rxq->rxq_mhead; 1518 m != rxq->rxq_mconsumer; 1519 m = m->m_next) { 1520 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1521 } 1522 m = rxq->rxq_mconsumer; 1523 if ((rxq->rxq_mhead = m->m_next) == NULL) 1524 rxq->rxq_mtail = &rxq->rxq_mhead; 1525 rxq->rxq_mconsumer = m->m_next; 1526 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1527 } else { 1528 rxq->rxq_mconsumer = rxq->rxq_mconsumer->m_next; 1529 } 1530 #ifdef ETSEC_DEBUG 1531 rxq->rxq_mbufs[consumer - rxq->rxq_first] = NULL; 1532 #endif 1533 1534 /* 1535 * Wrap at the last entry! 1536 */ 1537 if (rxbd_flags & RXBD_W) { 1538 KASSERT(consumer + 1 == rxq->rxq_last); 1539 consumer = rxq->rxq_first; 1540 } else { 1541 consumer++; 1542 } 1543 #ifdef ETSEC_DEBUG 1544 KASSERT(rxq->rxq_mbufs[consumer - rxq->rxq_first] == rxq->rxq_mconsumer); 1545 #endif 1546 } 1547 } 1548 1549 static void 1550 pq3etsec_rxq_purge( 1551 struct pq3etsec_softc *sc, 1552 struct pq3etsec_rxqueue *rxq, 1553 bool discard) 1554 { 1555 struct mbuf *m; 1556 1557 if ((m = rxq->rxq_mhead) != NULL) { 1558 #ifdef ETSEC_DEBUG 1559 memset(rxq->rxq_mbufs, 0, sizeof(rxq->rxq_mbufs)); 1560 #endif 1561 1562 if (discard) { 1563 pq3etsec_rx_map_unload(sc, m); 1564 m_freem(m); 1565 } else { 1566 while (m != NULL) { 1567 struct mbuf *m0 = m->m_next; 1568 m->m_next = NULL; 1569 IF_ENQUEUE(&sc->sc_rx_bufcache, m); 1570 m = m0; 1571 } 1572 } 1573 1574 } 1575 1576 rxq->rxq_mconsumer = NULL; 1577 rxq->rxq_mhead = NULL; 1578 rxq->rxq_mtail = &rxq->rxq_mhead; 1579 rxq->rxq_inuse = 0; 1580 } 1581 1582 static void 1583 pq3etsec_rxq_reset( 1584 struct pq3etsec_softc *sc, 1585 struct pq3etsec_rxqueue *rxq) 1586 { 1587 /* 1588 * sync all the descriptors 1589 */ 1590 pq3etsec_rxq_desc_postsync(sc, rxq, rxq->rxq_first, 1591 rxq->rxq_last - rxq->rxq_first); 1592 1593 /* 1594 * Make sure we own all descriptors in the ring. 1595 */ 1596 volatile struct rxbd *rxbd; 1597 for (rxbd = rxq->rxq_first; rxbd < rxq->rxq_last - 1; rxbd++) { 1598 rxbd->rxbd_flags = RXBD_I; 1599 } 1600 1601 /* 1602 * Last descriptor has the wrap flag. 1603 */ 1604 rxbd->rxbd_flags = RXBD_W|RXBD_I; 1605 1606 /* 1607 * Reset the producer consumer indexes. 1608 */ 1609 rxq->rxq_consumer = rxq->rxq_first; 1610 rxq->rxq_producer = rxq->rxq_first; 1611 rxq->rxq_inuse = 0; 1612 if (rxq->rxq_threshold < ETSEC_MINRXMBUFS) 1613 rxq->rxq_threshold = ETSEC_MINRXMBUFS; 1614 1615 sc->sc_imask |= IEVENT_RXF|IEVENT_BSY; 1616 1617 /* 1618 * Restart the transmit at the first descriptor 1619 */ 1620 etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr); 1621 } 1622 1623 static int 1624 pq3etsec_rxq_attach( 1625 struct pq3etsec_softc *sc, 1626 struct pq3etsec_rxqueue *rxq, 1627 u_int qno) 1628 { 1629 size_t map_size = PAGE_SIZE; 1630 size_t desc_count = map_size / sizeof(struct rxbd); 1631 int error; 1632 void *descs; 1633 1634 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1635 &rxq->rxq_descmap_seg, &rxq->rxq_descmap, &descs); 1636 if (error) 1637 return error; 1638 1639 memset(descs, 0, map_size); 1640 rxq->rxq_first = descs; 1641 rxq->rxq_last = rxq->rxq_first + desc_count; 1642 rxq->rxq_consumer = descs; 1643 rxq->rxq_producer = descs; 1644 1645 pq3etsec_rxq_purge(sc, rxq, true); 1646 pq3etsec_rxq_reset(sc, rxq); 1647 1648 rxq->rxq_reg_rbase = RBASEn(qno); 1649 rxq->rxq_qmask = RSTAT_QHLTn(qno) | RSTAT_RXFn(qno); 1650 1651 return 0; 1652 } 1653 1654 static bool 1655 pq3etsec_txq_active_p( 1656 struct pq3etsec_softc * const sc, 1657 struct pq3etsec_txqueue *txq) 1658 { 1659 return !IF_IS_EMPTY(&txq->txq_mbufs); 1660 } 1661 1662 static bool 1663 pq3etsec_txq_fillable_p( 1664 struct pq3etsec_softc * const sc, 1665 struct pq3etsec_txqueue *txq) 1666 { 1667 return txq->txq_free >= txq->txq_threshold; 1668 } 1669 1670 static int 1671 pq3etsec_txq_attach( 1672 struct pq3etsec_softc *sc, 1673 struct pq3etsec_txqueue *txq, 1674 u_int qno) 1675 { 1676 size_t map_size = PAGE_SIZE; 1677 size_t desc_count = map_size / sizeof(struct txbd); 1678 int error; 1679 void *descs; 1680 1681 error = pq3etsec_dmamem_alloc(sc->sc_dmat, map_size, 1682 &txq->txq_descmap_seg, &txq->txq_descmap, &descs); 1683 if (error) 1684 return error; 1685 1686 memset(descs, 0, map_size); 1687 txq->txq_first = descs; 1688 txq->txq_last = txq->txq_first + desc_count; 1689 txq->txq_consumer = descs; 1690 txq->txq_producer = descs; 1691 1692 IFQ_SET_MAXLEN(&txq->txq_mbufs, ETSEC_MAXTXMBUFS); 1693 1694 txq->txq_reg_tbase = TBASEn(qno); 1695 txq->txq_qmask = TSTAT_THLTn(qno) | TSTAT_TXFn(qno); 1696 1697 pq3etsec_txq_reset(sc, txq); 1698 1699 return 0; 1700 } 1701 1702 static int 1703 pq3etsec_txq_map_load( 1704 struct pq3etsec_softc *sc, 1705 struct pq3etsec_txqueue *txq, 1706 struct mbuf *m) 1707 { 1708 bus_dmamap_t map; 1709 int error; 1710 1711 map = M_GETCTX(m, bus_dmamap_t); 1712 if (map != NULL) 1713 return 0; 1714 1715 map = pq3etsec_mapcache_get(sc, sc->sc_tx_mapcache); 1716 if (map == NULL) 1717 return ENOMEM; 1718 1719 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1720 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1721 if (error) 1722 return error; 1723 1724 bus_dmamap_sync(sc->sc_dmat, map, 0, m->m_pkthdr.len, 1725 BUS_DMASYNC_PREWRITE); 1726 M_SETCTX(m, map); 1727 return 0; 1728 } 1729 1730 static void 1731 pq3etsec_txq_map_unload( 1732 struct pq3etsec_softc *sc, 1733 struct pq3etsec_txqueue *txq, 1734 struct mbuf *m) 1735 { 1736 KASSERT(m); 1737 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1738 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1739 BUS_DMASYNC_POSTWRITE); 1740 bus_dmamap_unload(sc->sc_dmat, map); 1741 pq3etsec_mapcache_put(sc, sc->sc_tx_mapcache, map); 1742 } 1743 1744 static bool 1745 pq3etsec_txq_produce( 1746 struct pq3etsec_softc *sc, 1747 struct pq3etsec_txqueue *txq, 1748 struct mbuf *m) 1749 { 1750 bus_dmamap_t map = M_GETCTX(m, bus_dmamap_t); 1751 1752 if (map->dm_nsegs > txq->txq_free) 1753 return false; 1754 1755 /* 1756 * TCP Offload flag must be set in the first descriptor. 1757 */ 1758 volatile struct txbd *producer = txq->txq_producer; 1759 uint16_t last_flags = TXBD_L; 1760 uint16_t first_flags = TXBD_R 1761 | ((m->m_flags & M_HASFCB) ? TXBD_TOE : 0); 1762 1763 /* 1764 * If we've produced enough descriptors without consuming any 1765 * we need to ask for an interrupt to reclaim some. 1766 */ 1767 txq->txq_lastintr += map->dm_nsegs; 1768 if (txq->txq_lastintr >= txq->txq_threshold 1769 || txq->txq_mbufs.ifq_len + 1 == txq->txq_mbufs.ifq_maxlen) { 1770 txq->txq_lastintr = 0; 1771 last_flags |= TXBD_I; 1772 } 1773 1774 #ifdef ETSEC_DEBUG 1775 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1776 #endif 1777 KASSERT(producer != txq->txq_last); 1778 producer->txbd_bufptr = map->dm_segs[0].ds_addr; 1779 producer->txbd_len = map->dm_segs[0].ds_len; 1780 1781 if (map->dm_nsegs > 1) { 1782 volatile struct txbd *start = producer + 1; 1783 size_t count = map->dm_nsegs - 1; 1784 for (u_int i = 1; i < map->dm_nsegs; i++) { 1785 if (__predict_false(++producer == txq->txq_last)) { 1786 producer = txq->txq_first; 1787 if (start < txq->txq_last) { 1788 pq3etsec_txq_desc_presync(sc, txq, 1789 start, txq->txq_last - start); 1790 count -= txq->txq_last - start; 1791 } 1792 start = txq->txq_first; 1793 } 1794 #ifdef ETSEC_DEBUG 1795 KASSERT(txq->txq_lmbufs[producer - txq->txq_first] == NULL); 1796 #endif 1797 producer->txbd_bufptr = map->dm_segs[i].ds_addr; 1798 producer->txbd_len = map->dm_segs[i].ds_len; 1799 producer->txbd_flags = TXBD_R 1800 | (producer->txbd_flags & TXBD_W) 1801 | (i == map->dm_nsegs - 1 ? last_flags : 0); 1802 #if 0 1803 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, producer - txq->txq_first, 1804 producer->txbd_flags, producer->txbd_len, producer->txbd_bufptr); 1805 #endif 1806 } 1807 pq3etsec_txq_desc_presync(sc, txq, start, count); 1808 } else { 1809 first_flags |= last_flags; 1810 } 1811 1812 membar_producer(); 1813 txq->txq_producer->txbd_flags = 1814 first_flags | (txq->txq_producer->txbd_flags & TXBD_W); 1815 #if 0 1816 printf("%s: txbd[%u]=%#x/%u/%#x\n", __func__, 1817 txq->txq_producer - txq->txq_first, txq->txq_producer->txbd_flags, 1818 txq->txq_producer->txbd_len, txq->txq_producer->txbd_bufptr); 1819 #endif 1820 pq3etsec_txq_desc_presync(sc, txq, txq->txq_producer, 1); 1821 1822 /* 1823 * Reduce free count by the number of segments we consumed. 1824 */ 1825 txq->txq_free -= map->dm_nsegs; 1826 KASSERT(map->dm_nsegs == 1 || txq->txq_producer != producer); 1827 KASSERT(map->dm_nsegs == 1 || (txq->txq_producer->txbd_flags & TXBD_L) == 0); 1828 KASSERT(producer->txbd_flags & TXBD_L); 1829 #ifdef ETSEC_DEBUG 1830 txq->txq_lmbufs[producer - txq->txq_first] = m; 1831 #endif 1832 1833 #if 0 1834 printf("%s: mbuf %p: produced a %u byte packet in %u segments (%u..%u)\n", 1835 __func__, m, m->m_pkthdr.len, map->dm_nsegs, 1836 txq->txq_producer - txq->txq_first, producer - txq->txq_first); 1837 #endif 1838 1839 if (++producer == txq->txq_last) 1840 txq->txq_producer = txq->txq_first; 1841 else 1842 txq->txq_producer = producer; 1843 IF_ENQUEUE(&txq->txq_mbufs, m); 1844 1845 /* 1846 * Restart the transmitter. 1847 */ 1848 etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT); /* W1C */ 1849 1850 return true; 1851 } 1852 1853 static void 1854 pq3etsec_tx_offload( 1855 struct pq3etsec_softc *sc, 1856 struct pq3etsec_txqueue *txq, 1857 struct mbuf **mp) 1858 { 1859 struct mbuf *m = *mp; 1860 u_int csum_flags = m->m_pkthdr.csum_flags; 1861 struct m_tag *vtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m); 1862 1863 KASSERT(m->m_flags & M_PKTHDR); 1864 1865 /* 1866 * Let see if we are doing any offload first. 1867 */ 1868 if (csum_flags == 0 && vtag == 0) { 1869 m->m_flags &= ~M_HASFCB; 1870 return; 1871 } 1872 1873 uint16_t flags = 0; 1874 if (csum_flags & M_CSUM_IP) { 1875 flags |= TXFCB_IP 1876 | ((csum_flags & M_CSUM_IP6) ? TXFCB_IP6 : 0) 1877 | ((csum_flags & M_CSUM_TUP) ? TXFCB_TUP : 0) 1878 | ((csum_flags & M_CSUM_UDP) ? TXFCB_UDP : 0) 1879 | ((csum_flags & M_CSUM_CIP) ? TXFCB_CIP : 0) 1880 | ((csum_flags & M_CSUM_CTU) ? TXFCB_CTU : 0); 1881 } 1882 if (vtag) { 1883 flags |= TXFCB_VLN; 1884 } 1885 if (flags == 0) { 1886 m->m_flags &= ~M_HASFCB; 1887 return; 1888 } 1889 1890 struct txfcb fcb; 1891 fcb.txfcb_flags = flags; 1892 if (csum_flags & M_CSUM_IPv4) 1893 fcb.txfcb_l4os = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 1894 else 1895 fcb.txfcb_l4os = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 1896 fcb.txfcb_l3os = ETHER_HDR_LEN; 1897 fcb.txfcb_phcs = 0; 1898 fcb.txfcb_vlctl = vtag ? VLAN_TAG_VALUE(vtag) & 0xffff : 0; 1899 1900 #if 0 1901 printf("%s: csum_flags=%#x: txfcb flags=%#x lsos=%u l4os=%u phcs=%u vlctl=%#x\n", 1902 __func__, csum_flags, fcb.txfcb_flags, fcb.txfcb_l3os, fcb.txfcb_l4os, 1903 fcb.txfcb_phcs, fcb.txfcb_vlctl); 1904 #endif 1905 1906 if (M_LEADINGSPACE(m) >= sizeof(fcb)) { 1907 m->m_data -= sizeof(fcb); 1908 m->m_len += sizeof(fcb); 1909 } else if (!(m->m_flags & M_EXT) && MHLEN - m->m_len >= sizeof(fcb)) { 1910 memmove(m->m_pktdat + sizeof(fcb), m->m_data, m->m_len); 1911 m->m_data = m->m_pktdat; 1912 m->m_len += sizeof(fcb); 1913 } else { 1914 struct mbuf *mn; 1915 MGET(mn, M_DONTWAIT, m->m_type); 1916 if (mn == NULL) { 1917 if (csum_flags & M_CSUM_IP4) { 1918 #ifdef INET 1919 ip_undefer_csum(m, ETHER_HDR_LEN, 1920 csum_flags & M_CSUM_IP4); 1921 #else 1922 panic("%s: impossible M_CSUM flags %#x", 1923 device_xname(sc->sc_dev), csum_flags); 1924 #endif 1925 } else if (csum_flags & M_CSUM_IP6) { 1926 #ifdef INET6 1927 ip6_undefer_csum(m, ETHER_HDR_LEN, 1928 csum_flags & M_CSUM_IP6); 1929 #else 1930 panic("%s: impossible M_CSUM flags %#x", 1931 device_xname(sc->sc_dev), csum_flags); 1932 #endif 1933 } else if (vtag) { 1934 } 1935 1936 m->m_flags &= ~M_HASFCB; 1937 return; 1938 } 1939 1940 M_MOVE_PKTHDR(mn, m); 1941 mn->m_next = m; 1942 m = mn; 1943 MH_ALIGN(m, sizeof(fcb)); 1944 m->m_len = sizeof(fcb); 1945 *mp = m; 1946 } 1947 m->m_pkthdr.len += sizeof(fcb); 1948 m->m_flags |= M_HASFCB; 1949 *mtod(m, struct txfcb *) = fcb; 1950 return; 1951 } 1952 1953 static bool 1954 pq3etsec_txq_enqueue( 1955 struct pq3etsec_softc *sc, 1956 struct pq3etsec_txqueue *txq) 1957 { 1958 for (;;) { 1959 if (IF_QFULL(&txq->txq_mbufs)) 1960 return false; 1961 struct mbuf *m = txq->txq_next; 1962 if (m == NULL) { 1963 int s = splnet(); 1964 IF_DEQUEUE(&sc->sc_if.if_snd, m); 1965 splx(s); 1966 if (m == NULL) 1967 return true; 1968 M_SETCTX(m, NULL); 1969 pq3etsec_tx_offload(sc, txq, &m); 1970 } else { 1971 txq->txq_next = NULL; 1972 } 1973 int error = pq3etsec_txq_map_load(sc, txq, m); 1974 if (error) { 1975 aprint_error_dev(sc->sc_dev, 1976 "discarded packet due to " 1977 "dmamap load failure: %d\n", error); 1978 m_freem(m); 1979 continue; 1980 } 1981 KASSERT(txq->txq_next == NULL); 1982 if (!pq3etsec_txq_produce(sc, txq, m)) { 1983 txq->txq_next = m; 1984 return false; 1985 } 1986 KASSERT(txq->txq_next == NULL); 1987 } 1988 } 1989 1990 static bool 1991 pq3etsec_txq_consume( 1992 struct pq3etsec_softc *sc, 1993 struct pq3etsec_txqueue *txq) 1994 { 1995 struct ifnet * const ifp = &sc->sc_if; 1996 volatile struct txbd *consumer = txq->txq_consumer; 1997 size_t txfree = 0; 1998 1999 #if 0 2000 printf("%s: entry: free=%zu\n", __func__, txq->txq_free); 2001 #endif 2002 etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask); 2003 2004 for (;;) { 2005 if (consumer == txq->txq_producer) { 2006 txq->txq_consumer = consumer; 2007 txq->txq_free += txfree; 2008 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2009 #if 0 2010 printf("%s: empty: freed %zu descriptors going form %zu to %zu\n", 2011 __func__, txfree, txq->txq_free - txfree, txq->txq_free); 2012 #endif 2013 KASSERT(txq->txq_lastintr == 0); 2014 KASSERT(txq->txq_free == txq->txq_last - txq->txq_first - 1); 2015 return true; 2016 } 2017 pq3etsec_txq_desc_postsync(sc, txq, consumer, 1); 2018 const uint16_t txbd_flags = consumer->txbd_flags; 2019 if (txbd_flags & TXBD_R) { 2020 txq->txq_consumer = consumer; 2021 txq->txq_free += txfree; 2022 txq->txq_lastintr -= min(txq->txq_lastintr, txfree); 2023 #if 0 2024 printf("%s: freed %zu descriptors\n", 2025 __func__, txfree); 2026 #endif 2027 return pq3etsec_txq_fillable_p(sc, txq); 2028 } 2029 2030 /* 2031 * If this is the last descriptor in the chain, get the 2032 * mbuf, free its dmamap, and free the mbuf chain itself. 2033 */ 2034 if (txbd_flags & TXBD_L) { 2035 struct mbuf *m; 2036 2037 IF_DEQUEUE(&txq->txq_mbufs, m); 2038 #ifdef ETSEC_DEBUG 2039 KASSERTMSG( 2040 m == txq->txq_lmbufs[consumer-txq->txq_first], 2041 "%s: %p [%u]: flags %#x m (%p) != %p (%p)", 2042 __func__, consumer, consumer - txq->txq_first, 2043 txbd_flags, m, 2044 &txq->txq_lmbufs[consumer-txq->txq_first], 2045 txq->txq_lmbufs[consumer-txq->txq_first]); 2046 #endif 2047 KASSERT(m); 2048 pq3etsec_txq_map_unload(sc, txq, m); 2049 #if 0 2050 printf("%s: mbuf %p: consumed a %u byte packet\n", 2051 __func__, m, m->m_pkthdr.len); 2052 #endif 2053 if (m->m_flags & M_HASFCB) 2054 m_adj(m, sizeof(struct txfcb)); 2055 ifp->if_opackets++; 2056 ifp->if_obytes += m->m_pkthdr.len; 2057 if (m->m_flags & M_MCAST) 2058 ifp->if_omcasts++; 2059 if (txbd_flags & TXBD_ERRORS) 2060 ifp->if_oerrors++; 2061 m_freem(m); 2062 #ifdef ETSEC_DEBUG 2063 txq->txq_lmbufs[consumer - txq->txq_first] = NULL; 2064 #endif 2065 } else { 2066 #ifdef ETSEC_DEBUG 2067 KASSERT(txq->txq_lmbufs[consumer-txq->txq_first] == NULL); 2068 #endif 2069 } 2070 2071 /* 2072 * We own this packet again. Clear all flags except wrap. 2073 */ 2074 txfree++; 2075 //consumer->txbd_flags = txbd_flags & TXBD_W; 2076 2077 /* 2078 * Wrap at the last entry! 2079 */ 2080 if (txbd_flags & TXBD_W) { 2081 KASSERT(consumer + 1 == txq->txq_last); 2082 consumer = txq->txq_first; 2083 } else { 2084 consumer++; 2085 KASSERT(consumer < txq->txq_last); 2086 } 2087 } 2088 } 2089 2090 static void 2091 pq3etsec_txq_purge( 2092 struct pq3etsec_softc *sc, 2093 struct pq3etsec_txqueue *txq) 2094 { 2095 struct mbuf *m; 2096 KASSERT((etsec_read(sc, MACCFG1) & MACCFG1_TX_EN) == 0); 2097 2098 for (;;) { 2099 IF_DEQUEUE(&txq->txq_mbufs, m); 2100 if (m == NULL) 2101 break; 2102 pq3etsec_txq_map_unload(sc, txq, m); 2103 m_freem(m); 2104 } 2105 if ((m = txq->txq_next) != NULL) { 2106 txq->txq_next = NULL; 2107 pq3etsec_txq_map_unload(sc, txq, m); 2108 m_freem(m); 2109 } 2110 #ifdef ETSEC_DEBUG 2111 memset(txq->txq_lmbufs, 0, sizeof(txq->txq_lmbufs)); 2112 #endif 2113 } 2114 2115 static void 2116 pq3etsec_txq_reset( 2117 struct pq3etsec_softc *sc, 2118 struct pq3etsec_txqueue *txq) 2119 { 2120 /* 2121 * sync all the descriptors 2122 */ 2123 pq3etsec_txq_desc_postsync(sc, txq, txq->txq_first, 2124 txq->txq_last - txq->txq_first); 2125 2126 /* 2127 * Make sure we own all descriptors in the ring. 2128 */ 2129 volatile struct txbd *txbd; 2130 for (txbd = txq->txq_first; txbd < txq->txq_last - 1; txbd++) { 2131 txbd->txbd_flags = 0; 2132 } 2133 2134 /* 2135 * Last descriptor has the wrap flag. 2136 */ 2137 txbd->txbd_flags = TXBD_W; 2138 2139 /* 2140 * Reset the producer consumer indexes. 2141 */ 2142 txq->txq_consumer = txq->txq_first; 2143 txq->txq_producer = txq->txq_first; 2144 txq->txq_free = txq->txq_last - txq->txq_first - 1; 2145 txq->txq_threshold = txq->txq_free / 2; 2146 txq->txq_lastintr = 0; 2147 2148 /* 2149 * What do we want to get interrupted on? 2150 */ 2151 sc->sc_imask |= IEVENT_TXF|IEVENT_TXE; 2152 2153 /* 2154 * Restart the transmit at the first descriptor 2155 */ 2156 etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr); 2157 } 2158 2159 static void 2160 pq3etsec_ifstart(struct ifnet *ifp) 2161 { 2162 struct pq3etsec_softc * const sc = ifp->if_softc; 2163 2164 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2165 softint_schedule(sc->sc_soft_ih); 2166 } 2167 2168 static void 2169 pq3etsec_tx_error( 2170 struct pq3etsec_softc * const sc) 2171 { 2172 struct pq3etsec_txqueue * const txq = &sc->sc_txq; 2173 2174 pq3etsec_txq_consume(sc, txq); 2175 2176 if (pq3etsec_txq_fillable_p(sc, txq)) 2177 sc->sc_if.if_flags &= ~IFF_OACTIVE; 2178 if (sc->sc_txerrors & (IEVENT_LC|IEVENT_CRL|IEVENT_XFUN|IEVENT_BABT)) { 2179 } else if (sc->sc_txerrors & IEVENT_EBERR) { 2180 } 2181 2182 if (pq3etsec_txq_active_p(sc, txq)) 2183 etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask); 2184 if (!pq3etsec_txq_enqueue(sc, txq)) { 2185 sc->sc_ev_tx_stall.ev_count++; 2186 sc->sc_if.if_flags |= IFF_OACTIVE; 2187 } 2188 2189 sc->sc_txerrors = 0; 2190 } 2191 2192 int 2193 pq3etsec_tx_intr(void *arg) 2194 { 2195 struct pq3etsec_softc * const sc = arg; 2196 2197 sc->sc_ev_tx_intr.ev_count++; 2198 2199 uint32_t ievent = etsec_read(sc, IEVENT); 2200 ievent &= IEVENT_TXF|IEVENT_TXB; 2201 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2202 2203 #if 0 2204 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2205 __func__, ievent, etsec_read(sc, IMASK)); 2206 #endif 2207 2208 if (ievent == 0) 2209 return 0; 2210 2211 sc->sc_imask &= ~(IEVENT_TXF|IEVENT_TXB); 2212 atomic_or_uint(&sc->sc_soft_flags, SOFT_TXINTR); 2213 etsec_write(sc, IMASK, sc->sc_imask); 2214 softint_schedule(sc->sc_soft_ih); 2215 return 1; 2216 } 2217 2218 int 2219 pq3etsec_rx_intr(void *arg) 2220 { 2221 struct pq3etsec_softc * const sc = arg; 2222 2223 sc->sc_ev_rx_intr.ev_count++; 2224 2225 uint32_t ievent = etsec_read(sc, IEVENT); 2226 ievent &= IEVENT_RXF|IEVENT_RXB; 2227 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2228 if (ievent == 0) 2229 return 0; 2230 2231 #if 0 2232 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x\n", __func__, ievent); 2233 #endif 2234 2235 sc->sc_imask &= ~(IEVENT_RXF|IEVENT_RXB); 2236 atomic_or_uint(&sc->sc_soft_flags, SOFT_RXINTR); 2237 etsec_write(sc, IMASK, sc->sc_imask); 2238 softint_schedule(sc->sc_soft_ih); 2239 return 1; 2240 } 2241 2242 int 2243 pq3etsec_error_intr(void *arg) 2244 { 2245 struct pq3etsec_softc * const sc = arg; 2246 2247 sc->sc_ev_error_intr.ev_count++; 2248 2249 for (int rv = 0, soft_flags = 0;; rv = 1) { 2250 uint32_t ievent = etsec_read(sc, IEVENT); 2251 ievent &= ~(IEVENT_RXF|IEVENT_RXB|IEVENT_TXF|IEVENT_TXB); 2252 etsec_write(sc, IEVENT, ievent); /* write 1 to clear */ 2253 if (ievent == 0) { 2254 if (soft_flags) { 2255 atomic_or_uint(&sc->sc_soft_flags, soft_flags); 2256 softint_schedule(sc->sc_soft_ih); 2257 } 2258 return rv; 2259 } 2260 #if 0 2261 aprint_normal_dev(sc->sc_dev, "%s: ievent=%#x imask=%#x\n", 2262 __func__, ievent, etsec_read(sc, IMASK)); 2263 #endif 2264 2265 if (ievent & (IEVENT_GRSC|IEVENT_GTSC)) { 2266 sc->sc_imask &= ~(IEVENT_GRSC|IEVENT_GTSC); 2267 etsec_write(sc, IMASK, sc->sc_imask); 2268 wakeup(sc); 2269 } 2270 if (ievent & (IEVENT_MMRD|IEVENT_MMWR)) { 2271 sc->sc_imask &= ~(IEVENT_MMRD|IEVENT_MMWR); 2272 etsec_write(sc, IMASK, sc->sc_imask); 2273 wakeup(&sc->sc_mii); 2274 } 2275 if (ievent & IEVENT_BSY) { 2276 soft_flags |= SOFT_RXBSY; 2277 sc->sc_imask &= ~IEVENT_BSY; 2278 etsec_write(sc, IMASK, sc->sc_imask); 2279 } 2280 if (ievent & IEVENT_TXE) { 2281 soft_flags |= SOFT_TXERROR; 2282 sc->sc_imask &= ~IEVENT_TXE; 2283 sc->sc_txerrors |= ievent; 2284 } 2285 if (ievent & IEVENT_TXC) { 2286 sc->sc_ev_tx_pause.ev_count++; 2287 } 2288 if (ievent & IEVENT_RXC) { 2289 sc->sc_ev_rx_pause.ev_count++; 2290 } 2291 if (ievent & IEVENT_DPE) { 2292 soft_flags |= SOFT_RESET; 2293 sc->sc_imask &= ~IEVENT_DPE; 2294 etsec_write(sc, IMASK, sc->sc_imask); 2295 } 2296 } 2297 } 2298 2299 void 2300 pq3etsec_soft_intr(void *arg) 2301 { 2302 struct pq3etsec_softc * const sc = arg; 2303 struct ifnet * const ifp = &sc->sc_if; 2304 2305 mutex_enter(sc->sc_lock); 2306 2307 u_int soft_flags = atomic_swap_uint(&sc->sc_soft_flags, 0); 2308 2309 sc->sc_ev_soft_intr.ev_count++; 2310 2311 if (soft_flags & SOFT_RESET) { 2312 int s = splnet(); 2313 pq3etsec_ifinit(ifp); 2314 splx(s); 2315 soft_flags = 0; 2316 } 2317 2318 if (soft_flags & SOFT_RXBSY) { 2319 struct pq3etsec_rxqueue * const rxq = &sc->sc_rxq; 2320 size_t threshold = 5 * rxq->rxq_threshold / 4; 2321 if (threshold >= rxq->rxq_last - rxq->rxq_first) { 2322 threshold = rxq->rxq_last - rxq->rxq_first - 1; 2323 } else { 2324 sc->sc_imask |= IEVENT_BSY; 2325 } 2326 aprint_normal_dev(sc->sc_dev, 2327 "increasing receive buffers from %zu to %zu\n", 2328 rxq->rxq_threshold, threshold); 2329 rxq->rxq_threshold = threshold; 2330 } 2331 2332 if ((soft_flags & SOFT_TXINTR) 2333 || pq3etsec_txq_active_p(sc, &sc->sc_txq)) { 2334 /* 2335 * Let's do what we came here for. Consume transmitted 2336 * packets off the the transmit ring. 2337 */ 2338 if (!pq3etsec_txq_consume(sc, &sc->sc_txq) 2339 || !pq3etsec_txq_enqueue(sc, &sc->sc_txq)) { 2340 sc->sc_ev_tx_stall.ev_count++; 2341 ifp->if_flags |= IFF_OACTIVE; 2342 } else { 2343 ifp->if_flags &= ~IFF_OACTIVE; 2344 } 2345 sc->sc_imask |= IEVENT_TXF; 2346 } 2347 2348 if (soft_flags & (SOFT_RXINTR|SOFT_RXBSY)) { 2349 /* 2350 * Let's consume 2351 */ 2352 pq3etsec_rxq_consume(sc, &sc->sc_rxq); 2353 sc->sc_imask |= IEVENT_RXF; 2354 } 2355 2356 if (soft_flags & SOFT_TXERROR) { 2357 pq3etsec_tx_error(sc); 2358 sc->sc_imask |= IEVENT_TXE; 2359 } 2360 2361 if (ifp->if_flags & IFF_RUNNING) { 2362 pq3etsec_rxq_produce(sc, &sc->sc_rxq); 2363 etsec_write(sc, IMASK, sc->sc_imask); 2364 } else { 2365 KASSERT((soft_flags & SOFT_RXBSY) == 0); 2366 } 2367 2368 mutex_exit(sc->sc_lock); 2369 } 2370 2371 static void 2372 pq3etsec_mii_tick(void *arg) 2373 { 2374 struct pq3etsec_softc * const sc = arg; 2375 mutex_enter(sc->sc_lock); 2376 callout_ack(&sc->sc_mii_callout); 2377 sc->sc_ev_mii_ticks.ev_count++; 2378 #ifdef DEBUG 2379 uint64_t now = mftb(); 2380 if (now - sc->sc_mii_last_tick < cpu_timebase - 5000) { 2381 aprint_debug_dev(sc->sc_dev, "%s: diff=%"PRIu64"\n", 2382 __func__, now - sc->sc_mii_last_tick); 2383 callout_stop(&sc->sc_mii_callout); 2384 } 2385 #endif 2386 mii_tick(&sc->sc_mii); 2387 int s = splnet(); 2388 if (sc->sc_soft_flags & SOFT_RESET) 2389 softint_schedule(sc->sc_soft_ih); 2390 splx(s); 2391 callout_schedule(&sc->sc_mii_callout, hz); 2392 #ifdef DEBUG 2393 sc->sc_mii_last_tick = now; 2394 #endif 2395 mutex_exit(sc->sc_lock); 2396 } 2397
Indexes created Mon Sep 29 21:09:56 GMT 2025