pq3gpio.c revision 1.4.2.2
1 /* $NetBSD: pq3gpio.c,v 1.4.2.2 2012/05/23 10:07:46 yamt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #define GLOBAL_PRIVATE 38 #define GPIO_PRIVATE 39 40 #include "opt_mpc85xx.h" 41 42 #include <sys/cdefs.h> 43 44 __KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.4.2.2 2012/05/23 10:07:46 yamt Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/cpu.h> 48 #include <sys/device.h> 49 #include <sys/tty.h> 50 #include <sys/kmem.h> 51 #include <sys/gpio.h> 52 #include <sys/bitops.h> 53 54 #include "ioconf.h" 55 56 #include <sys/intr.h> 57 #include <sys/bus.h> 58 59 #include <dev/gpio/gpiovar.h> 60 61 #include <powerpc/booke/cpuvar.h> 62 #include <powerpc/booke/spr.h> 63 #include <powerpc/booke/e500var.h> 64 #include <powerpc/booke/e500reg.h> 65 66 struct pq3gpio_group { 67 struct gpio_chipset_tag gc_tag; 68 gpio_pin_t gc_pins[32]; 69 bus_space_tag_t gc_bst; 70 bus_space_handle_t gc_bsh; 71 bus_size_t gc_reg; 72 }; 73 74 struct pq3gpio_softc { 75 device_t sc_dev; 76 bus_space_tag_t sc_bst; 77 bus_space_handle_t sc_bsh; 78 SIMPLEQ_HEAD(,pq3gpio_group) sc_gpios; 79 }; 80 81 static int 82 pq3gpio_pin_read(void *v, int num) 83 { 84 struct pq3gpio_group * const gc = v; 85 86 uint32_t data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg); 87 88 return (data >> (gc->gc_pins[num].pin_num ^ 31)) & 1; 89 } 90 91 static void 92 pq3gpio_pin_write(void *v, int num, int val) 93 { 94 struct pq3gpio_group * const gc = v; 95 const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31); 96 97 val = val ? mask : 0; 98 u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg); 99 if ((data & mask) != val) { 100 data = (data & ~mask) | val; 101 bus_space_write_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg, data); 102 } 103 } 104 105 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8544) 106 static void 107 pq3gpio_null_pin_ctl(void *v, int num, int ctl) 108 { 109 } 110 #endif 111 112 #if defined(MPC8536) || defined(P2020) 113 /* 114 * MPC8536 / P20x0 have controllable input/output pins 115 */ 116 static void 117 pq3gpio_pin_ctl(void *v, int num, int ctl) 118 { 119 struct pq3gpio_group * const gc = v; 120 const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31); 121 122 uint32_t old_dir = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPDIR); 123 uint32_t new_dir = old_dir; 124 switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 125 case GPIO_PIN_OUTPUT: new_dir |= mask; break; 126 case GPIO_PIN_INPUT: new_dir &= ~mask; break; 127 default: return; 128 } 129 if (old_dir != new_dir) 130 bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPDIR, new_dir); 131 132 /* 133 * Now handle opendrain 134 */ 135 uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPODR); 136 uint32_t new_odr = old_odr; 137 138 if (ctl & GPIO_PIN_OPENDRAIN) { 139 new_odr |= mask; 140 } else { 141 new_odr &= ~mask; 142 } 143 144 if (old_odr != new_odr) 145 bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPODR, new_odr); 146 } 147 #endif 148 149 static void 150 pq3gpio_group_create(device_t self, bus_space_tag_t bst, bus_space_handle_t bsh, 151 bus_size_t reg, uint32_t pinmask, int pincaps, 152 void (*pin_ctl)(void *, int, int)) 153 { 154 struct pq3gpio_group * const gc = kmem_zalloc(sizeof(*gc), KM_SLEEP); 155 156 gc->gc_bst = bst; 157 gc->gc_bsh = bsh; 158 gc->gc_reg = reg; 159 gc->gc_tag.gp_cookie = gc; 160 #if 0 161 gc->gc_tag.gp_gc_open = pq3gpio_gc_open; 162 gc->gc_tag.gp_gc_close = pq3gpio_gc_close; 163 #endif 164 gc->gc_tag.gp_pin_read = pq3gpio_pin_read; 165 gc->gc_tag.gp_pin_write = pq3gpio_pin_write; 166 gc->gc_tag.gp_pin_ctl = pin_ctl; 167 168 u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, reg); 169 u_int mask = __BIT(31); 170 gpio_pin_t *pin = gc->gc_pins; 171 for (u_int i = 0; mask != 0; i++, mask >>= 1) { 172 if (mask & pinmask) { 173 pin->pin_num = i; 174 pin->pin_caps = pincaps; 175 pin->pin_flags = pincaps; 176 pin->pin_state = (data & mask) != 0; 177 pin++; 178 } 179 } 180 181 struct gpiobus_attach_args gba = { 182 .gba_gc = &gc->gc_tag, 183 .gba_pins = gc->gc_pins, 184 .gba_npins = pin - gc->gc_pins, 185 }; 186 187 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 188 } 189 190 #ifdef MPC8536 191 static void 192 pq3gpio_mpc8536_attach(device_t self, bus_space_tag_t bst, 193 bus_space_handle_t bsh, u_int svr) 194 { 195 static const uint8_t gpio2pmuxcr_map[] = { 196 [0] = ilog2(PMUXCR_PCI_REQGNT3), 197 [1] = ilog2(PMUXCR_PCI_REQGNT4), 198 [2] = ilog2(PMUXCR_PCI_REQGNT3), 199 [3] = ilog2(PMUXCR_PCI_REQGNT4), 200 [4] = ilog2(PMUXCR_SDHC_CD), 201 [5] = ilog2(PMUXCR_SDHC_WP), 202 [6] = ilog2(PMUXCR_USB1), 203 [7] = ilog2(PMUXCR_USB1), 204 [8] = ilog2(PMUXCR_USB2), 205 [9] = ilog2(PMUXCR_USB2), 206 [10] = ilog2(PMUXCR_DMA0), 207 [11] = ilog2(PMUXCR_DMA1), 208 [12] = ilog2(PMUXCR_DMA0), 209 [13] = ilog2(PMUXCR_DMA1), 210 [14] = ilog2(PMUXCR_DMA0), 211 [15] = ilog2(PMUXCR_DMA1), 212 }; 213 214 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */ 215 uint32_t gpiomask = __BIT(31); 216 size_t pincnt = 16; 217 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR); 218 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); 219 i++, gpiomask >>= 1) { 220 if (pmuxcr & __BIT(gpio2pmuxcr_map[i])) { 221 pinmask &= ~gpiomask; 222 pincnt--; 223 } 224 } 225 226 /* 227 * Create GPIO pin groups 228 */ 229 aprint_normal_dev(self, "%zu input/output/opendrain pins\n", 230 pincnt); 231 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask, 232 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN, 233 pq3gpio_pin_ctl); 234 } 235 #endif /* MPC8536 */ 236 237 #ifdef MPC8544 238 static void 239 pq3gpio_mpc8544_attach(device_t self, bus_space_tag_t bst, 240 bus_space_handle_t bsh, u_int svr) 241 { 242 /* 243 * Enable GPOUT 244 */ 245 uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR); 246 gpiocr |= GPIOCR_GPOUT; 247 bus_space_write_4(bst, bsh, GPIOCR, gpiocr); 248 249 aprint_normal_dev(self, "8 input pins, 8 output pins\n"); 250 251 /* 252 * Create GPIO pin groups 253 */ 254 pq3gpio_group_create(self, bst, bsh, GPINDR, 0xff000000, 255 GPIO_PIN_INPUT, pq3gpio_null_pin_ctl); 256 pq3gpio_group_create(self, bst, bsh, GPOUTDR, 0xff000000, 257 GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl); 258 } 259 #endif /* MPC8544 */ 260 261 #if defined(MPC8548) || defined(MPC8555) 262 static void 263 pq3gpio_mpc8548_attach(device_t self, bus_space_tag_t bst, 264 bus_space_handle_t bsh, u_int svr) 265 { 266 const uint32_t pordevsr = bus_space_read_4(bst, bsh, PORDEVSR); 267 const uint32_t devdisr = bus_space_read_4(bst, bsh, DEVDISR); 268 uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR); 269 270 uint32_t inmask = 0; 271 uint32_t outmask = 0; 272 273 size_t ipins = 0; 274 size_t opins = 0; 275 276 aprint_normal_dev(self, "GPIOCR %#x, DEVDISR %#x, PORDEVSR %#x\n", 277 gpiocr, devdisr, pordevsr); 278 aprint_normal_dev(self, "GPINDR %#x, GPOUTDR %#x, GPPORCR %#x\n", 279 bus_space_read_4(bst, bsh, GPINDR), 280 bus_space_read_4(bst, bsh, GPOUTDR), 281 bus_space_read_4(bst, bsh, GPPORCR)); 282 283 /* 284 * Use PCI2 AD[15:0] as GPIO if PCI2 is disabled and 285 * PCI1 is either disabled or not 64bits wide. 286 */ 287 if ((devdisr & DEVDISR_PCI2) && 288 ((devdisr & DEVDISR_PCI1) || (pordevsr & PORDEVSR_PCI32))) { 289 gpiocr |= GPIOCR_PCIOUT; 290 gpiocr |= GPIOCR_PCIIN; 291 outmask |= 0x00ff0000; 292 inmask |= 0x00ff0000; 293 opins += 8; 294 ipins += 8; 295 } 296 if (devdisr & DEVDISR_TSEC2) { 297 gpiocr |= GPIOCR_TX2; 298 gpiocr |= GPIOCR_RX2; 299 outmask |= 0xff000000; 300 inmask |= 0xff000000; 301 opins += 8; 302 ipins += 8; 303 } 304 if (svr != (SVR_MPC8555v1 >> 16)) { 305 gpiocr |= GPIOCR_GPOUT; 306 outmask |= 0x000000ff; 307 opins += 8; 308 } 309 #if 1 310 aprint_normal_dev(self, "GPIOCR: %#x\n", gpiocr); 311 #else 312 bus_space_write_4(bst, bsh, GPIOCR, gpiocr); 313 #endif 314 315 /* 316 * Create GPIO pin groups 317 */ 318 aprint_normal_dev(self, "%zu input pins, %zu output pins\n", 319 ipins, opins); 320 321 if (inmask) 322 pq3gpio_group_create(self, bst, bsh, GPINDR, inmask, 323 GPIO_PIN_INPUT, pq3gpio_null_pin_ctl); 324 if (outmask) 325 pq3gpio_group_create(self, bst, bsh, GPOUTDR, outmask, 326 GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl); 327 } 328 #endif /* MPC8548 */ 329 330 #ifdef P2020 331 static void 332 pq3gpio_p20x0_attach(device_t self, bus_space_tag_t bst, 333 bus_space_handle_t bsh, u_int svr) 334 { 335 static const uint32_t gpio2pmuxcr_map[][2] = { 336 { __BIT(8), PMUXCR_SDHC_CD }, 337 { __BIT(9), PMUXCR_SDHC_WP }, 338 /* 339 * These are really two bits but the low bit MBZ so we ignore 340 * it. 341 */ 342 { __BIT(10), PMUXCR_TSEC3_TS }, 343 { __BIT(11), PMUXCR_TSEC3_TS }, 344 }; 345 346 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */ 347 size_t pincnt = 16; 348 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR); 349 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) { 350 if (pmuxcr & gpio2pmuxcr_map[i][1]) { 351 pinmask &= ~gpio2pmuxcr_map[i][0]; 352 pincnt--; 353 } 354 } 355 356 /* 357 * Create GPIO pin groups 358 */ 359 aprint_normal_dev(self, "%zu input/output/opendrain pins\n", 360 pincnt); 361 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask, 362 GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN, 363 pq3gpio_pin_ctl); 364 } 365 #endif /* P2020 */ 366 367 static const struct pq3gpio_svr_info { 368 uint16_t si_svr; 369 void (*si_attach)(device_t, bus_space_tag_t, bus_space_handle_t, u_int); 370 bus_addr_t si_base; 371 bus_size_t si_size; 372 } pq3gpio_svrs[] = { 373 #ifdef MPC8548 374 { SVR_MPC8548v2 >> 16, pq3gpio_mpc8548_attach, 375 GLOBAL_BASE, GLOBAL_SIZE }, 376 #endif 377 #ifdef MPC8555 378 { SVR_MPC8555v1 >> 16, pq3gpio_mpc8548_attach, 379 GLOBAL_BASE, GLOBAL_SIZE }, 380 #endif 381 #ifdef MPC8544 382 { SVR_MPC8544v1 >> 16, pq3gpio_mpc8544_attach, 383 GLOBAL_BASE, GLOBAL_SIZE }, 384 #endif 385 #ifdef MPC8536 386 { SVR_MPC8536v1 >> 16, pq3gpio_mpc8536_attach, 387 GPIO_BASE, GPIO_SIZE }, 388 #endif 389 #ifdef P2020 390 { SVR_P2020v2 >> 16, pq3gpio_p20x0_attach, 391 GPIO_BASE, GPIO_SIZE }, 392 #endif 393 }; 394 395 void 396 pq3gpio_attach(device_t parent, device_t self, void *aux) 397 { 398 struct mainbus_attach_args * const ma = aux; 399 bus_space_tag_t bst = ma->ma_memt; 400 bus_space_handle_t bsh; 401 402 const uint16_t svr = e500_get_svr(); 403 for (u_int i = 0; i < __arraycount(pq3gpio_svrs); i++) { 404 const struct pq3gpio_svr_info * const si = &pq3gpio_svrs[i]; 405 if (si->si_svr == svr) { 406 int error = bus_space_map(bst, si->si_base, 407 si->si_size, 0, &bsh); 408 if (error) { 409 aprint_error_dev(self, 410 "can't map global registers for gpio: %d\n", 411 error); 412 return; 413 } 414 (*si->si_attach)(self, bst, bsh, svr); 415 return; 416 } 417 } 418 aprint_normal_dev(self, 419 "0 input groups, 0 output groups (unknown svr %#x)\n", 420 svr); 421 } 422
Indexes created Wed Oct 01 15:09:59 GMT 2025