pq3gpio.c revision 1.8
1 /* $NetBSD: pq3gpio.c,v 1.8 2012/07/15 08:44:56 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #define GLOBAL_PRIVATE 38 #define GPIO_PRIVATE 39 40 #include "opt_mpc85xx.h" 41 42 #include <sys/cdefs.h> 43 44 __KERNEL_RCSID(0, "$NetBSD: pq3gpio.c,v 1.8 2012/07/15 08:44:56 matt Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/cpu.h> 48 #include <sys/device.h> 49 #include <sys/tty.h> 50 #include <sys/kmem.h> 51 #include <sys/gpio.h> 52 #include <sys/bitops.h> 53 54 #include "ioconf.h" 55 56 #include <sys/intr.h> 57 #include <sys/bus.h> 58 59 #include <dev/gpio/gpiovar.h> 60 61 #include <powerpc/booke/cpuvar.h> 62 #include <powerpc/booke/spr.h> 63 #include <powerpc/booke/e500var.h> 64 #include <powerpc/booke/e500reg.h> 65 66 struct pq3gpio_group { 67 struct gpio_chipset_tag gc_tag; 68 gpio_pin_t gc_pins[32]; 69 bus_space_tag_t gc_bst; 70 bus_space_handle_t gc_bsh; 71 bus_size_t gc_reg; 72 }; 73 74 struct pq3gpio_softc { 75 device_t sc_dev; 76 bus_space_tag_t sc_bst; 77 bus_space_handle_t sc_bsh; 78 SIMPLEQ_HEAD(,pq3gpio_group) sc_gpios; 79 }; 80 81 static int 82 pq3gpio_pin_read(void *v, int num) 83 { 84 struct pq3gpio_group * const gc = v; 85 86 uint32_t data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg); 87 88 return (data >> (gc->gc_pins[num].pin_num ^ 31)) & 1; 89 } 90 91 static void 92 pq3gpio_pin_write(void *v, int num, int val) 93 { 94 struct pq3gpio_group * const gc = v; 95 const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31); 96 97 val = val ? mask : 0; 98 u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg); 99 if ((data & mask) != val) { 100 data = (data & ~mask) | val; 101 bus_space_write_4(gc->gc_bst, gc->gc_bsh, gc->gc_reg, data); 102 } 103 } 104 105 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8544) 106 static void 107 pq3gpio_null_pin_ctl(void *v, int num, int ctl) 108 { 109 } 110 #endif 111 112 #if defined(P1025) 113 /* 114 * P1025 has controllable input/output pins 115 */ 116 static void 117 pq3gpio_pin_ctl(void *v, int num, int ctl) 118 { 119 struct pq3gpio_group * const gc = v; 120 const size_t shift = gc->gc_pins[num].pin_num ^ 31; 121 122 uint64_t old_dir = 123 ((uint64_t)bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR1) << 32) 124 | (bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPDIR2) << 0); 125 126 uint32_t dir = 0; 127 switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 128 case GPIO_PIN_INPUT|GPIO_PIN_OUTPUT: dir = CPDIR_INOUT; break; 129 case GPIO_PIN_OUTPUT: dir = CPDIR_OUT; break; 130 case GPIO_PIN_INPUT: dir = CPDIR_INOUT; break; 131 case 0: dir = CPDIR_DIS; break; 132 } 133 134 uint64_t new_dir = (old_dir & (3ULL << (2 * shift))) 135 | ((uint64_t)dir << (2 * shift)); 136 137 if ((uint32_t)old_dir != (uint32_t)new_dir) 138 bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR2, 139 (uint32_t)new_dir); 140 new_dir >>= 32; 141 old_dir >>= 32; 142 if ((uint32_t)old_dir != (uint32_t)new_dir) 143 bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPDIR1, 144 (uint32_t)new_dir); 145 146 /* 147 * Now handle opendrain 148 */ 149 uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, CPODR); 150 uint32_t new_odr = old_odr; 151 uint32_t odr_mask = 1UL << shift; 152 153 if (ctl & GPIO_PIN_OPENDRAIN) { 154 new_odr |= odr_mask; 155 } else { 156 new_odr &= ~odr_mask; 157 } 158 159 if (old_odr != new_odr) 160 bus_space_write_4(gc->gc_bst, gc->gc_bsh, CPODR, new_odr); 161 } 162 #endif 163 164 #if defined(MPC8536) || defined(P2020) 165 /* 166 * MPC8536 / P20x0 have controllable input/output pins 167 */ 168 static void 169 pq3gpio_pin_ctl(void *v, int num, int ctl) 170 { 171 struct pq3gpio_group * const gc = v; 172 const u_int mask = 1 << (gc->gc_pins[num].pin_num ^ 31); 173 174 uint32_t old_dir = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPDIR); 175 uint32_t new_dir = old_dir; 176 switch (ctl & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 177 case GPIO_PIN_OUTPUT: new_dir |= mask; break; 178 case GPIO_PIN_INPUT: new_dir &= ~mask; break; 179 default: return; 180 } 181 if (old_dir != new_dir) 182 bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPDIR, new_dir); 183 184 /* 185 * Now handle opendrain 186 */ 187 uint32_t old_odr = bus_space_read_4(gc->gc_bst, gc->gc_bsh, GPODR); 188 uint32_t new_odr = old_odr; 189 190 if (ctl & GPIO_PIN_OPENDRAIN) { 191 new_odr |= mask; 192 } else { 193 new_odr &= ~mask; 194 } 195 196 if (old_odr != new_odr) 197 bus_space_write_4(gc->gc_bst, gc->gc_bsh, GPODR, new_odr); 198 } 199 #endif 200 201 static void 202 pq3gpio_group_create(device_t self, bus_space_tag_t bst, bus_space_handle_t bsh, 203 bus_size_t reg, uint32_t pinmask, int pincaps, 204 void (*pin_ctl)(void *, int, int)) 205 { 206 struct pq3gpio_group * const gc = kmem_zalloc(sizeof(*gc), KM_SLEEP); 207 208 gc->gc_bst = bst; 209 gc->gc_bsh = bsh; 210 gc->gc_reg = reg; 211 gc->gc_tag.gp_cookie = gc; 212 #if 0 213 gc->gc_tag.gp_gc_open = pq3gpio_gc_open; 214 gc->gc_tag.gp_gc_close = pq3gpio_gc_close; 215 #endif 216 gc->gc_tag.gp_pin_read = pq3gpio_pin_read; 217 gc->gc_tag.gp_pin_write = pq3gpio_pin_write; 218 gc->gc_tag.gp_pin_ctl = pin_ctl; 219 220 u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, reg); 221 u_int mask = __BIT(31); 222 gpio_pin_t *pin = gc->gc_pins; 223 for (u_int i = 0; mask != 0; i++, mask >>= 1) { 224 if (mask & pinmask) { 225 pin->pin_num = i; 226 pin->pin_caps = pincaps; 227 pin->pin_flags = pincaps; 228 pin->pin_state = (data & mask) != 0; 229 pin++; 230 } 231 } 232 233 struct gpiobus_attach_args gba = { 234 .gba_gc = &gc->gc_tag, 235 .gba_pins = gc->gc_pins, 236 .gba_npins = pin - gc->gc_pins, 237 }; 238 239 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 240 } 241 242 #ifdef MPC8536 243 static void 244 pq3gpio_mpc8536_attach(device_t self, bus_space_tag_t bst, 245 bus_space_handle_t bsh, u_int svr) 246 { 247 static const uint8_t gpio2pmuxcr_map[] = { 248 [0] = ilog2(PMUXCR_PCI_REQGNT3), 249 [1] = ilog2(PMUXCR_PCI_REQGNT4), 250 [2] = ilog2(PMUXCR_PCI_REQGNT3), 251 [3] = ilog2(PMUXCR_PCI_REQGNT4), 252 [4] = ilog2(PMUXCR_SDHC_CD), 253 [5] = ilog2(PMUXCR_SDHC_WP), 254 [6] = ilog2(PMUXCR_USB1), 255 [7] = ilog2(PMUXCR_USB1), 256 [8] = ilog2(PMUXCR_USB2), 257 [9] = ilog2(PMUXCR_USB2), 258 [10] = ilog2(PMUXCR_DMA0), 259 [11] = ilog2(PMUXCR_DMA1), 260 [12] = ilog2(PMUXCR_DMA0), 261 [13] = ilog2(PMUXCR_DMA1), 262 [14] = ilog2(PMUXCR_DMA0), 263 [15] = ilog2(PMUXCR_DMA1), 264 }; 265 266 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */ 267 uint32_t gpiomask = __BIT(31); 268 size_t pincnt = 16; 269 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR); 270 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); 271 i++, gpiomask >>= 1) { 272 if (pmuxcr & __BIT(gpio2pmuxcr_map[i])) { 273 pinmask &= ~gpiomask; 274 pincnt--; 275 } 276 } 277 278 /* 279 * Create GPIO pin groups 280 */ 281 aprint_normal_dev(self, "%zu input/output/opendrain pins\n", 282 pincnt); 283 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask, 284 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN, 285 pq3gpio_pin_ctl); 286 } 287 #endif /* MPC8536 */ 288 289 #ifdef MPC8544 290 static void 291 pq3gpio_mpc8544_attach(device_t self, bus_space_tag_t bst, 292 bus_space_handle_t bsh, u_int svr) 293 { 294 /* 295 * Enable GPOUT 296 */ 297 uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR); 298 gpiocr |= GPIOCR_GPOUT; 299 bus_space_write_4(bst, bsh, GPIOCR, gpiocr); 300 301 aprint_normal_dev(self, "8 input pins, 8 output pins\n"); 302 303 /* 304 * Create GPIO pin groups 305 */ 306 pq3gpio_group_create(self, bst, bsh, GPINDR, 0xff000000, 307 GPIO_PIN_INPUT, pq3gpio_null_pin_ctl); 308 pq3gpio_group_create(self, bst, bsh, GPOUTDR, 0xff000000, 309 GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl); 310 } 311 #endif /* MPC8544 */ 312 313 #if defined(MPC8548) || defined(MPC8555) 314 static void 315 pq3gpio_mpc8548_attach(device_t self, bus_space_tag_t bst, 316 bus_space_handle_t bsh, u_int svr) 317 { 318 const uint32_t pordevsr = bus_space_read_4(bst, bsh, PORDEVSR); 319 const uint32_t devdisr = bus_space_read_4(bst, bsh, DEVDISR); 320 uint32_t gpiocr = bus_space_read_4(bst, bsh, GPIOCR); 321 322 uint32_t inmask = 0; 323 uint32_t outmask = 0; 324 325 size_t ipins = 0; 326 size_t opins = 0; 327 328 aprint_normal_dev(self, "GPIOCR %#x, DEVDISR %#x, PORDEVSR %#x\n", 329 gpiocr, devdisr, pordevsr); 330 aprint_normal_dev(self, "GPINDR %#x, GPOUTDR %#x, GPPORCR %#x\n", 331 bus_space_read_4(bst, bsh, GPINDR), 332 bus_space_read_4(bst, bsh, GPOUTDR), 333 bus_space_read_4(bst, bsh, GPPORCR)); 334 335 /* 336 * Use PCI2 AD[15:0] as GPIO if PCI2 is disabled and 337 * PCI1 is either disabled or not 64bits wide. 338 */ 339 if ((devdisr & DEVDISR_PCI2) && 340 ((devdisr & DEVDISR_PCI1) || (pordevsr & PORDEVSR_PCI32))) { 341 gpiocr |= GPIOCR_PCIOUT; 342 gpiocr |= GPIOCR_PCIIN; 343 outmask |= 0x00ff0000; 344 inmask |= 0x00ff0000; 345 opins += 8; 346 ipins += 8; 347 } 348 if (devdisr & DEVDISR_TSEC2) { 349 gpiocr |= GPIOCR_TX2; 350 gpiocr |= GPIOCR_RX2; 351 outmask |= 0xff000000; 352 inmask |= 0xff000000; 353 opins += 8; 354 ipins += 8; 355 } 356 if (svr != (SVR_MPC8555v1 >> 16)) { 357 gpiocr |= GPIOCR_GPOUT; 358 outmask |= 0x000000ff; 359 opins += 8; 360 } 361 #if 1 362 aprint_normal_dev(self, "GPIOCR: %#x\n", gpiocr); 363 #else 364 bus_space_write_4(bst, bsh, GPIOCR, gpiocr); 365 #endif 366 367 /* 368 * Create GPIO pin groups 369 */ 370 aprint_normal_dev(self, "%zu input pins, %zu output pins\n", 371 ipins, opins); 372 373 if (inmask) 374 pq3gpio_group_create(self, bst, bsh, GPINDR, inmask, 375 GPIO_PIN_INPUT, pq3gpio_null_pin_ctl); 376 if (outmask) 377 pq3gpio_group_create(self, bst, bsh, GPOUTDR, outmask, 378 GPIO_PIN_OUTPUT, pq3gpio_null_pin_ctl); 379 } 380 #endif /* MPC8548 */ 381 382 #ifdef P1025 383 static void 384 pq3gpio_p1025_attach(device_t self, bus_space_tag_t bst, 385 bus_space_handle_t bsh, u_int svr) 386 { 387 static const uint32_t gpio2pmuxcr_map[][4] = { 388 { 0, __BIT(12), 0, PMUXCR_SDHC_WP }, 389 { __BIT(15), __BIT(8), 0, PMUXCR_USB1 }, 390 { __BITS(14,4)|__BIT(16)|__BITS(27,17)|__BIT(30), 391 __BIT(1)|__BITS(3,2), 0, PMUXCR_QE0 }, 392 { __BITS(3,1), 0, 0, PMUXCR_QE3 }, 393 { 0, __BITS(17,14), 0, PMUXCR_QE8 }, 394 { __BIT(29), __BITS(19,18), 0, PMUXCR_QE9 }, 395 { 0, __BITS(22,21), 0, PMUXCR_QE10 }, 396 { 0, __BITS(28,23), 0, PMUXCR_QE11 }, 397 { 0, __BIT(20), 0, PMUXCR_QE12 }, 398 }; 399 400 uint32_t pinmask[3] = { 401 0xffffffff, 0xffffffff, 0xffffffff 402 }; /* assume all bits are valid */ 403 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR); 404 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) { 405 if (pmuxcr & gpio2pmuxcr_map[i][3]) { 406 pinmask[0] &= ~gpio2pmuxcr_map[i][0]; 407 pinmask[1] &= ~gpio2pmuxcr_map[i][1]; 408 pinmask[2] &= ~gpio2pmuxcr_map[i][2]; 409 } 410 } 411 412 /* 413 * Create GPIO pin groups 414 */ 415 for (size_t i = 0; i < 3; i++) { 416 if (pinmask[i]) { 417 bus_space_handle_t bsh2; 418 aprint_normal_dev(self, 419 "gpio[%c]: %zu input/output/opendrain pins\n", 420 "abc"[i], popcount32(pinmask[i])); 421 bus_space_subregion(bst, bsh, CPBASE(i), 0x20, &bsh2); 422 pq3gpio_group_create(self, bst, bsh2, CPDAT, 423 pinmask[0], 424 GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN, 425 pq3gpio_pin_ctl); 426 } 427 } 428 } 429 #endif /* P1025 */ 430 431 #ifdef P2020 432 static void 433 pq3gpio_p20x0_attach(device_t self, bus_space_tag_t bst, 434 bus_space_handle_t bsh, u_int svr) 435 { 436 static const uint32_t gpio2pmuxcr_map[][2] = { 437 { __BIT(8), PMUXCR_SDHC_CD }, 438 { __BIT(9), PMUXCR_SDHC_WP }, 439 /* 440 * These are really two bits but the low bit MBZ so we ignore 441 * it. 442 */ 443 { __BIT(10), PMUXCR_TSEC3_TS }, 444 { __BIT(11), PMUXCR_TSEC3_TS }, 445 }; 446 447 uint32_t pinmask = 0xffff0000; /* assume all bits are valid */ 448 size_t pincnt = 16; 449 const uint32_t pmuxcr = cpu_read_4(GLOBAL_BASE + PMUXCR); 450 for (size_t i = 0; i < __arraycount(gpio2pmuxcr_map); i++) { 451 if (pmuxcr & gpio2pmuxcr_map[i][1]) { 452 pinmask &= ~gpio2pmuxcr_map[i][0]; 453 pincnt--; 454 } 455 } 456 457 /* 458 * Create GPIO pin groups 459 */ 460 aprint_normal_dev(self, "%zu input/output/opendrain pins\n", 461 pincnt); 462 pq3gpio_group_create(self, bst, bsh, GPDAT, pinmask, 463 GPIO_PIN_INPUT|GPIO_PIN_OUTPUT|GPIO_PIN_OPENDRAIN, 464 pq3gpio_pin_ctl); 465 } 466 #endif /* P2020 */ 467 468 static const struct pq3gpio_svr_info { 469 uint16_t si_svr; 470 void (*si_attach)(device_t, bus_space_tag_t, bus_space_handle_t, u_int); 471 bus_addr_t si_base; 472 bus_size_t si_size; 473 } pq3gpio_svrs[] = { 474 #ifdef MPC8548 475 { SVR_MPC8548v2 >> 16, pq3gpio_mpc8548_attach, 476 GLOBAL_BASE, GLOBAL_SIZE }, 477 #endif 478 #ifdef MPC8555 479 { SVR_MPC8555v1 >> 16, pq3gpio_mpc8548_attach, 480 GLOBAL_BASE, GLOBAL_SIZE }, 481 #endif 482 #ifdef MPC8544 483 { SVR_MPC8544v1 >> 16, pq3gpio_mpc8544_attach, 484 GLOBAL_BASE, GLOBAL_SIZE }, 485 #endif 486 #ifdef MPC8536 487 { SVR_MPC8536v1 >> 16, pq3gpio_mpc8536_attach, 488 GPIO_BASE, GPIO_SIZE }, 489 #endif 490 #ifdef P1025 491 { SVR_P1025v1 >> 16, pq3gpio_p1025_attach, 492 GLOBAL_BASE, GLOBAL_SIZE }, 493 #endif 494 #ifdef P2020 495 { SVR_P2020v2 >> 16, pq3gpio_p20x0_attach, 496 GPIO_BASE, GPIO_SIZE }, 497 #endif 498 }; 499 500 void 501 pq3gpio_attach(device_t parent, device_t self, void *aux) 502 { 503 struct mainbus_attach_args * const ma = aux; 504 bus_space_tag_t bst = ma->ma_memt; 505 bus_space_handle_t bsh; 506 507 const uint16_t svr = e500_get_svr(); 508 for (u_int i = 0; i < __arraycount(pq3gpio_svrs); i++) { 509 const struct pq3gpio_svr_info * const si = &pq3gpio_svrs[i]; 510 if (si->si_svr == svr) { 511 int error = bus_space_map(bst, si->si_base, 512 si->si_size, 0, &bsh); 513 if (error) { 514 aprint_error_dev(self, 515 "can't map global registers for gpio: %d\n", 516 error); 517 return; 518 } 519 (*si->si_attach)(self, bst, bsh, svr); 520 return; 521 } 522 } 523 aprint_normal_dev(self, 524 "0 input groups, 0 output groups (unknown svr %#x)\n", 525 svr); 526 } 527
Indexes created Sun Sep 28 16:09:52 GMT 2025