e500_intr.c revision 1.21
1 /* $NetBSD: e500_intr.c,v 1.21 2012/08/01 21:30:22 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_mpc85xx.h" 38 39 #define __INTR_PRIVATE 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.21 2012/08/01 21:30:22 matt Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/proc.h> 46 #include <sys/intr.h> 47 #include <sys/cpu.h> 48 #include <sys/kmem.h> 49 #include <sys/atomic.h> 50 #include <sys/bus.h> 51 #include <sys/xcall.h> 52 #include <sys/bitops.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #ifdef __HAVE_FAST_SOFTINTS 57 #include <powerpc/softint.h> 58 #endif 59 60 #include <powerpc/spr.h> 61 #include <powerpc/booke/spr.h> 62 63 #include <powerpc/booke/cpuvar.h> 64 #include <powerpc/booke/e500reg.h> 65 #include <powerpc/booke/e500var.h> 66 #include <powerpc/booke/openpicreg.h> 67 68 #define IPL2CTPR(ipl) ((ipl) + 15 - IPL_HIGH) 69 #define CTPR2IPL(ctpr) ((ctpr) - (15 - IPL_HIGH)) 70 71 #define IST_PERCPU_P(ist) ((ist) >= IST_TIMER) 72 73 struct e500_intr_irq_info { 74 bus_addr_t irq_vpr; 75 bus_addr_t irq_dr; 76 u_int irq_vector; 77 }; 78 79 struct intr_source { 80 int (*is_func)(void *); 81 void *is_arg; 82 int8_t is_ipl; 83 uint8_t is_ist; 84 uint8_t is_irq; 85 bus_size_t is_vpr; 86 bus_size_t is_dr; 87 }; 88 89 #define INTR_SOURCE_INITIALIZER \ 90 { .is_func = e500_intr_spurious, .is_arg = NULL, \ 91 .is_irq = -1, .is_ipl = IPL_NONE, .is_ist = IST_NONE, } 92 93 struct e500_intr_name { 94 uint8_t in_irq; 95 const char in_name[15]; 96 }; 97 98 static const struct e500_intr_name e500_onchip_intr_names[] = { 99 { ISOURCE_L2, "l2" }, 100 { ISOURCE_ECM, "ecm" }, 101 { ISOURCE_DDR, "ddr" }, 102 { ISOURCE_LBC, "lbc" }, 103 { ISOURCE_DMA_CHAN1, "dma-chan1" }, 104 { ISOURCE_DMA_CHAN2, "dma-chan2" }, 105 { ISOURCE_DMA_CHAN3, "dma-chan3" }, 106 { ISOURCE_DMA_CHAN4, "dma-chan4" }, 107 { ISOURCE_PCI1, "pci1" }, 108 { ISOURCE_PCIEX2, "pcie2" }, 109 { ISOURCE_PCIEX , "pcie1" }, 110 { ISOURCE_PCIEX3, "pcie3" }, 111 { ISOURCE_USB1, "usb1" }, 112 { ISOURCE_ETSEC1_TX, "etsec1-tx" }, 113 { ISOURCE_ETSEC1_RX, "etsec1-rx" }, 114 { ISOURCE_ETSEC3_TX, "etsec3-tx" }, 115 { ISOURCE_ETSEC3_RX, "etsec3-rx" }, 116 { ISOURCE_ETSEC3_ERR, "etsec3-err" }, 117 { ISOURCE_ETSEC1_ERR, "etsec1-err" }, 118 { ISOURCE_ETSEC2_TX, "etsec2-tx" }, 119 { ISOURCE_ETSEC2_RX, "etsec2-rx" }, 120 { ISOURCE_ETSEC4_TX, "etsec4-tx" }, 121 { ISOURCE_ETSEC4_RX, "etsec4-rx" }, 122 { ISOURCE_ETSEC4_ERR, "etsec4-err" }, 123 { ISOURCE_ETSEC2_ERR, "etsec2-err" }, 124 { ISOURCE_DUART, "duart" }, 125 { ISOURCE_I2C, "i2c" }, 126 { ISOURCE_PERFMON, "perfmon" }, 127 { ISOURCE_SECURITY1, "sec1" }, 128 { ISOURCE_GPIO, "gpio" }, 129 { ISOURCE_SRIO_EWPU, "srio-ewpu" }, 130 { ISOURCE_SRIO_ODBELL, "srio-odbell" }, 131 { ISOURCE_SRIO_IDBELL, "srio-idbell" }, 132 { ISOURCE_SRIO_OMU1, "srio-omu1" }, 133 { ISOURCE_SRIO_IMU1, "srio-imu1" }, 134 { ISOURCE_SRIO_OMU2, "srio-omu2" }, 135 { ISOURCE_SRIO_IMU2, "srio-imu2" }, 136 { ISOURCE_SECURITY2, "sec2" }, 137 { ISOURCE_SPI, "spi" }, 138 { ISOURCE_ETSEC1_PTP, "etsec1-ptp" }, 139 { ISOURCE_ETSEC2_PTP, "etsec2-ptp" }, 140 { ISOURCE_ETSEC3_PTP, "etsec3-ptp" }, 141 { ISOURCE_ETSEC4_PTP, "etsec4-ptp" }, 142 { ISOURCE_ESDHC, "esdhc" }, 143 { 0, "" }, 144 }; 145 146 const struct e500_intr_name default_external_intr_names[] = { 147 { 0, "" }, 148 }; 149 150 static const struct e500_intr_name e500_msigroup_intr_names[] = { 151 { 0, "msigroup0" }, 152 { 1, "msigroup1" }, 153 { 2, "msigroup2" }, 154 { 3, "msigroup3" }, 155 { 4, "msigroup4" }, 156 { 5, "msigroup5" }, 157 { 6, "msigroup6" }, 158 { 7, "msigroup7" }, 159 { 0, "" }, 160 }; 161 162 static const struct e500_intr_name e500_timer_intr_names[] = { 163 { 0, "timer0" }, 164 { 1, "timer1" }, 165 { 2, "timer2" }, 166 { 3, "timer3" }, 167 { 0, "" }, 168 }; 169 170 static const struct e500_intr_name e500_ipi_intr_names[] = { 171 { 0, "ipi0" }, 172 { 1, "ipi1" }, 173 { 2, "ipi2" }, 174 { 3, "ipi3" }, 175 { 0, "" }, 176 }; 177 178 static const struct e500_intr_name e500_mi_intr_names[] = { 179 { 0, "mi0" }, 180 { 1, "mi1" }, 181 { 2, "mi2" }, 182 { 3, "mi3" }, 183 { 0, "" }, 184 }; 185 186 struct e500_intr_info { 187 u_int ii_external_sources; 188 uint32_t ii_onchip_bitmap[2]; 189 u_int ii_onchip_sources; 190 u_int ii_msigroup_sources; 191 u_int ii_ipi_sources; /* per-cpu */ 192 u_int ii_timer_sources; /* per-cpu */ 193 u_int ii_mi_sources; /* per-cpu */ 194 u_int ii_percpu_sources; 195 const struct e500_intr_name *ii_external_intr_names; 196 const struct e500_intr_name *ii_onchip_intr_names; 197 u_int8_t ii_ist_vectors[IST_MAX+1]; 198 }; 199 200 static kmutex_t e500_intr_lock __cacheline_aligned; 201 static struct e500_intr_info e500_intr_info; 202 203 #define INTR_INFO_DECL(lc_chip, UC_CHIP) \ 204 static const struct e500_intr_info lc_chip##_intr_info = { \ 205 .ii_external_sources = UC_CHIP ## _EXTERNALSOURCES, \ 206 .ii_onchip_bitmap = UC_CHIP ## _ONCHIPBITMAP, \ 207 .ii_onchip_sources = UC_CHIP ## _ONCHIPSOURCES, \ 208 .ii_msigroup_sources = UC_CHIP ## _MSIGROUPSOURCES, \ 209 .ii_timer_sources = UC_CHIP ## _TIMERSOURCES, \ 210 .ii_ipi_sources = UC_CHIP ## _IPISOURCES, \ 211 .ii_mi_sources = UC_CHIP ## _MISOURCES, \ 212 .ii_percpu_sources = UC_CHIP ## _TIMERSOURCES \ 213 + UC_CHIP ## _IPISOURCES + UC_CHIP ## _MISOURCES, \ 214 .ii_external_intr_names = lc_chip ## _external_intr_names, \ 215 .ii_onchip_intr_names = lc_chip ## _onchip_intr_names, \ 216 .ii_ist_vectors = { \ 217 [IST_NONE] = ~0, \ 218 [IST_EDGE] = 0, \ 219 [IST_LEVEL_LOW] = 0, \ 220 [IST_LEVEL_HIGH] = 0, \ 221 [IST_PULSE] = 0, \ 222 [IST_ONCHIP] = UC_CHIP ## _EXTERNALSOURCES, \ 223 [IST_MSIGROUP] = UC_CHIP ## _EXTERNALSOURCES \ 224 + UC_CHIP ## _ONCHIPSOURCES, \ 225 [IST_TIMER] = UC_CHIP ## _EXTERNALSOURCES \ 226 + UC_CHIP ## _ONCHIPSOURCES \ 227 + UC_CHIP ## _MSIGROUPSOURCES, \ 228 [IST_IPI] = UC_CHIP ## _EXTERNALSOURCES \ 229 + UC_CHIP ## _ONCHIPSOURCES \ 230 + UC_CHIP ## _MSIGROUPSOURCES \ 231 + UC_CHIP ## _TIMERSOURCES, \ 232 [IST_MI] = UC_CHIP ## _EXTERNALSOURCES \ 233 + UC_CHIP ## _ONCHIPSOURCES \ 234 + UC_CHIP ## _MSIGROUPSOURCES \ 235 + UC_CHIP ## _TIMERSOURCES \ 236 + UC_CHIP ## _IPISOURCES, \ 237 [IST_MAX] = UC_CHIP ## _EXTERNALSOURCES \ 238 + UC_CHIP ## _ONCHIPSOURCES \ 239 + UC_CHIP ## _MSIGROUPSOURCES \ 240 + UC_CHIP ## _TIMERSOURCES \ 241 + UC_CHIP ## _IPISOURCES \ 242 + UC_CHIP ## _MISOURCES, \ 243 }, \ 244 } 245 246 #ifdef MPC8536 247 #define mpc8536_external_intr_names default_external_intr_names 248 const struct e500_intr_name mpc8536_onchip_intr_names[] = { 249 { ISOURCE_SATA2, "sata2" }, 250 { ISOURCE_USB2, "usb2" }, 251 { ISOURCE_USB3, "usb3" }, 252 { ISOURCE_SATA1, "sata1" }, 253 { 0, "" }, 254 }; 255 256 INTR_INFO_DECL(mpc8536, MPC8536); 257 #endif 258 259 #ifdef MPC8544 260 #define mpc8544_external_intr_names default_external_intr_names 261 const struct e500_intr_name mpc8544_onchip_intr_names[] = { 262 { 0, "" }, 263 }; 264 265 INTR_INFO_DECL(mpc8544, MPC8544); 266 #endif 267 #ifdef MPC8548 268 #define mpc8548_external_intr_names default_external_intr_names 269 const struct e500_intr_name mpc8548_onchip_intr_names[] = { 270 { ISOURCE_PCI1, "pci1" }, 271 { ISOURCE_PCI2, "pci2" }, 272 { 0, "" }, 273 }; 274 275 INTR_INFO_DECL(mpc8548, MPC8548); 276 #endif 277 #ifdef MPC8555 278 #define mpc8555_external_intr_names default_external_intr_names 279 const struct e500_intr_name mpc8555_onchip_intr_names[] = { 280 { ISOURCE_PCI2, "pci2" }, 281 { ISOURCE_CPM, "CPM" }, 282 { 0, "" }, 283 }; 284 285 INTR_INFO_DECL(mpc8555, MPC8555); 286 #endif 287 #ifdef MPC8568 288 #define mpc8568_external_intr_names default_external_intr_names 289 const struct e500_intr_name mpc8568_onchip_intr_names[] = { 290 { ISOURCE_QEB_LOW, "QEB low" }, 291 { ISOURCE_QEB_PORT, "QEB port" }, 292 { ISOURCE_QEB_IECC, "QEB iram ecc" }, 293 { ISOURCE_QEB_MUECC, "QEB ram ecc" }, 294 { ISOURCE_TLU1, "tlu1" }, 295 { ISOURCE_QEB_HIGH, "QEB high" }, 296 { 0, "" }, 297 }; 298 299 INTR_INFO_DECL(mpc8568, MPC8568); 300 #endif 301 #ifdef MPC8572 302 #define mpc8572_external_intr_names default_external_intr_names 303 const struct e500_intr_name mpc8572_onchip_intr_names[] = { 304 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 305 { ISOURCE_FEC, "fec" }, 306 { ISOURCE_PME_GENERAL, "pme" }, 307 { ISOURCE_TLU1, "tlu1" }, 308 { ISOURCE_TLU2, "tlu2" }, 309 { ISOURCE_PME_CHAN1, "pme-chan1" }, 310 { ISOURCE_PME_CHAN2, "pme-chan2" }, 311 { ISOURCE_PME_CHAN3, "pme-chan3" }, 312 { ISOURCE_PME_CHAN4, "pme-chan4" }, 313 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 314 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 315 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 316 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 317 { 0, "" }, 318 }; 319 320 INTR_INFO_DECL(mpc8572, MPC8572); 321 #endif 322 323 #ifdef P1025 324 #define p1025_external_intr_names default_external_intr_names 325 const struct e500_intr_name p1025_onchip_intr_names[] = { 326 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 327 { ISOURCE_ETSEC1_G1_TX, "etsec1-g1-tx" }, 328 { ISOURCE_ETSEC1_G1_RX, "etsec1-g1-rx" }, 329 { ISOURCE_ETSEC1_G1_ERR, "etsec1-g1-error" }, 330 { ISOURCE_ETSEC2_G1_TX, "etsec2-g1-tx" }, 331 { ISOURCE_ETSEC2_G1_RX, "etsec2-g1-rx" }, 332 { ISOURCE_ETSEC2_G1_ERR, "etsec2-g1-error" }, 333 { ISOURCE_ETSEC3_G1_TX, "etsec3-g1-tx" }, 334 { ISOURCE_ETSEC3_G1_RX, "etsec3-g1-rx" }, 335 { ISOURCE_ETSEC3_G1_ERR, "etsec3-g1-error" }, 336 { ISOURCE_QEB_MUECC, "qeb-low" }, 337 { ISOURCE_QEB_HIGH, "qeb-crit" }, 338 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 339 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 340 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 341 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 342 { 0, "" }, 343 }; 344 345 INTR_INFO_DECL(p1025, P1025); 346 #endif 347 348 #ifdef P2020 349 #define p20x0_external_intr_names default_external_intr_names 350 const struct e500_intr_name p20x0_onchip_intr_names[] = { 351 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 352 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 353 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 354 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 355 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 356 { 0, "" }, 357 }; 358 359 INTR_INFO_DECL(p20x0, P20x0); 360 #endif 361 362 static const char ist_names[][12] = { 363 [IST_NONE] = "none", 364 [IST_EDGE] = "edge", 365 [IST_LEVEL_LOW] = "level-", 366 [IST_LEVEL_HIGH] = "level+", 367 [IST_PULSE] = "pulse", 368 [IST_MSI] = "msi", 369 [IST_ONCHIP] = "onchip", 370 [IST_MSIGROUP] = "msigroup", 371 [IST_TIMER] = "timer", 372 [IST_IPI] = "ipi", 373 [IST_MI] = "msgint", 374 }; 375 376 static struct intr_source *e500_intr_sources; 377 static const struct intr_source *e500_intr_last_source; 378 379 static void *e500_intr_establish(int, int, int, int (*)(void *), void *); 380 static void e500_intr_disestablish(void *); 381 static void e500_intr_cpu_attach(struct cpu_info *ci); 382 static void e500_intr_cpu_hatch(struct cpu_info *ci); 383 static void e500_intr_cpu_send_ipi(cpuid_t, uintptr_t); 384 static void e500_intr_init(void); 385 static const char *e500_intr_string(int, int); 386 static const char *e500_intr_typename(int); 387 static void e500_critintr(struct trapframe *tf); 388 static void e500_decrintr(struct trapframe *tf); 389 static void e500_extintr(struct trapframe *tf); 390 static void e500_fitintr(struct trapframe *tf); 391 static void e500_wdogintr(struct trapframe *tf); 392 static void e500_spl0(void); 393 static int e500_splraise(int); 394 static void e500_splx(int); 395 396 const struct intrsw e500_intrsw = { 397 .intrsw_establish = e500_intr_establish, 398 .intrsw_disestablish = e500_intr_disestablish, 399 .intrsw_init = e500_intr_init, 400 .intrsw_cpu_attach = e500_intr_cpu_attach, 401 .intrsw_cpu_hatch = e500_intr_cpu_hatch, 402 .intrsw_cpu_send_ipi = e500_intr_cpu_send_ipi, 403 .intrsw_string = e500_intr_string, 404 .intrsw_typename = e500_intr_typename, 405 406 .intrsw_critintr = e500_critintr, 407 .intrsw_decrintr = e500_decrintr, 408 .intrsw_extintr = e500_extintr, 409 .intrsw_fitintr = e500_fitintr, 410 .intrsw_wdogintr = e500_wdogintr, 411 412 .intrsw_splraise = e500_splraise, 413 .intrsw_splx = e500_splx, 414 .intrsw_spl0 = e500_spl0, 415 416 #ifdef __HAVE_FAST_SOFTINTS 417 .intrsw_softint_init_md = powerpc_softint_init_md, 418 .intrsw_softint_trigger = powerpc_softint_trigger, 419 #endif 420 }; 421 422 static bool wdog_barked; 423 424 static inline uint32_t 425 openpic_read(struct cpu_softc *cpu, bus_size_t offset) 426 { 427 428 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, 429 OPENPIC_BASE + offset); 430 } 431 432 static inline void 433 openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val) 434 { 435 436 return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, 437 OPENPIC_BASE + offset, val); 438 } 439 440 static const char * 441 e500_intr_external_name_lookup(int irq) 442 { 443 prop_array_t extirqs = board_info_get_object("external-irqs"); 444 prop_string_t irqname = prop_array_get(extirqs, irq); 445 KASSERT(irqname != NULL); 446 KASSERT(prop_object_type(irqname) == PROP_TYPE_STRING); 447 448 return prop_string_cstring_nocopy(irqname); 449 } 450 451 static const char * 452 e500_intr_name_lookup(const struct e500_intr_name *names, int irq) 453 { 454 for (; names->in_name[0] != '\0'; names++) { 455 if (names->in_irq == irq) 456 return names->in_name; 457 } 458 459 return NULL; 460 } 461 462 static const char * 463 e500_intr_onchip_name_lookup(int irq) 464 { 465 const char *name; 466 467 name = e500_intr_name_lookup(e500_intr_info.ii_onchip_intr_names, irq); 468 if (name == NULL) 469 name = e500_intr_name_lookup(e500_onchip_intr_names, irq); 470 471 return name; 472 } 473 474 static inline void 475 e500_splset(struct cpu_info *ci, int ipl) 476 { 477 struct cpu_softc * const cpu = ci->ci_softc; 478 479 KASSERT((curlwp->l_pflag & LP_INTR) == 0 || ipl != IPL_NONE); 480 const u_int ctpr = IPL2CTPR(ipl); 481 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == IPL2CTPR(ci->ci_cpl)); 482 openpic_write(cpu, OPENPIC_CTPR, ctpr); 483 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ctpr); 484 #ifdef DIAGNOSTIC 485 cpu->cpu_spl_tb[ipl][ci->ci_cpl] = mftb(); 486 #endif 487 ci->ci_cpl = ipl; 488 } 489 490 static void 491 e500_spl0(void) 492 { 493 wrtee(0); 494 495 struct cpu_info * const ci = curcpu(); 496 497 #ifdef __HAVE_FAST_SOFTINTS 498 if (__predict_false(ci->ci_data.cpu_softints != 0)) { 499 e500_splset(ci, IPL_HIGH); 500 wrtee(PSL_EE); 501 powerpc_softint(ci, IPL_NONE, 502 (vaddr_t)__builtin_return_address(0)); 503 wrtee(0); 504 } 505 #endif /* __HAVE_FAST_SOFTINTS */ 506 e500_splset(ci, IPL_NONE); 507 508 wrtee(PSL_EE); 509 } 510 511 static void 512 e500_splx(int ipl) 513 { 514 struct cpu_info * const ci = curcpu(); 515 const int old_ipl = ci->ci_cpl; 516 517 /* if we paniced because of watchdog, PSL_CE will be clear. */ 518 KASSERT(wdog_barked || (mfmsr() & PSL_CE)); 519 520 if (ipl == old_ipl) 521 return; 522 523 if (__predict_false(ipl > old_ipl)) { 524 printf("%s: %p: cpl=%u: ignoring splx(%u) to raise ipl\n", 525 __func__, __builtin_return_address(0), old_ipl, ipl); 526 if (old_ipl == IPL_NONE) 527 Debugger(); 528 } 529 530 // const 531 register_t msr = wrtee(0); 532 #ifdef __HAVE_FAST_SOFTINTS 533 const u_int softints = ci->ci_data.cpu_softints & (IPL_SOFTMASK << ipl); 534 if (__predict_false(softints != 0)) { 535 e500_splset(ci, IPL_HIGH); 536 wrtee(msr); 537 powerpc_softint(ci, ipl, 538 (vaddr_t)__builtin_return_address(0)); 539 wrtee(0); 540 } 541 #endif /* __HAVE_FAST_SOFTINTS */ 542 e500_splset(ci, ipl); 543 #if 1 544 if (ipl < IPL_VM && old_ipl >= IPL_VM) 545 msr = PSL_EE; 546 #endif 547 wrtee(msr); 548 } 549 550 static int 551 e500_splraise(int ipl) 552 { 553 struct cpu_info * const ci = curcpu(); 554 const int old_ipl = ci->ci_cpl; 555 556 /* if we paniced because of watchdog, PSL_CE will be clear. */ 557 KASSERT(wdog_barked || (mfmsr() & PSL_CE)); 558 559 if (old_ipl < ipl) { 560 //const 561 register_t msr = wrtee(0); 562 e500_splset(ci, ipl); 563 #if 0 564 if (old_ipl < IPL_VM && ipl >= IPL_VM) 565 msr = 0; 566 #endif 567 wrtee(msr); 568 } else if (ipl == IPL_NONE) { 569 panic("%s: %p: cpl=%u: attempt to splraise(IPL_NONE)", 570 __func__, __builtin_return_address(0), old_ipl); 571 #if 0 572 } else if (old_ipl > ipl) { 573 printf("%s: %p: cpl=%u: ignoring splraise(%u) to lower ipl\n", 574 __func__, __builtin_return_address(0), old_ipl, ipl); 575 #endif 576 } 577 578 return old_ipl; 579 } 580 581 static int 582 e500_intr_spurious(void *arg) 583 { 584 return 0; 585 } 586 587 static bool 588 e500_intr_irq_info_get(struct cpu_info *ci, u_int irq, int ipl, int ist, 589 struct e500_intr_irq_info *ii) 590 { 591 const struct e500_intr_info * const info = &e500_intr_info; 592 bool ok; 593 594 #if DEBUG > 2 595 printf("%s(%p,irq=%u,ipl=%u,ist=%u,%p)\n", __func__, ci, irq, ipl, ist, ii); 596 #endif 597 598 if (ipl < IPL_VM || ipl > IPL_HIGH) { 599 #if DEBUG > 2 600 printf("%s:%d ipl=%u\n", __func__, __LINE__, ipl); 601 #endif 602 return false; 603 } 604 605 if (ist <= IST_NONE || ist >= IST_MAX) { 606 #if DEBUG > 2 607 printf("%s:%d ist=%u\n", __func__, __LINE__, ist); 608 #endif 609 return false; 610 } 611 612 ii->irq_vector = irq + info->ii_ist_vectors[ist]; 613 if (IST_PERCPU_P(ist) && ist != IST_IPI) 614 ii->irq_vector += ci->ci_cpuid * info->ii_percpu_sources; 615 616 switch (ist) { 617 default: 618 ii->irq_vpr = OPENPIC_EIVPR(irq); 619 ii->irq_dr = OPENPIC_EIDR(irq); 620 ok = irq < info->ii_external_sources 621 && (ist == IST_EDGE 622 || ist == IST_LEVEL_LOW 623 || ist == IST_LEVEL_HIGH); 624 break; 625 case IST_PULSE: 626 ok = false; 627 break; 628 case IST_ONCHIP: 629 ii->irq_vpr = OPENPIC_IIVPR(irq); 630 ii->irq_dr = OPENPIC_IIDR(irq); 631 ok = irq < 32 * __arraycount(info->ii_onchip_bitmap); 632 #if DEBUG > 2 633 printf("%s: irq=%u: ok=%u\n", __func__, irq, ok); 634 #endif 635 ok = ok && (info->ii_onchip_bitmap[irq/32] & (1 << (irq & 31))); 636 #if DEBUG > 2 637 printf("%s: %08x%08x -> %08x%08x: ok=%u\n", __func__, 638 irq < 32 ? 0 : (1 << irq), irq < 32 ? (1 << irq) : 0, 639 info->ii_onchip_bitmap[1], info->ii_onchip_bitmap[0], 640 ok); 641 #endif 642 break; 643 case IST_MSIGROUP: 644 ii->irq_vpr = OPENPIC_MSIVPR(irq); 645 ii->irq_dr = OPENPIC_MSIDR(irq); 646 ok = irq < info->ii_msigroup_sources 647 && ipl == IPL_VM; 648 break; 649 case IST_TIMER: 650 ii->irq_vpr = OPENPIC_GTVPR(ci->ci_cpuid, irq); 651 ii->irq_dr = OPENPIC_GTDR(ci->ci_cpuid, irq); 652 ok = irq < info->ii_timer_sources; 653 #if DEBUG > 2 654 printf("%s: IST_TIMER irq=%u: ok=%u\n", __func__, irq, ok); 655 #endif 656 break; 657 case IST_IPI: 658 ii->irq_vpr = OPENPIC_IPIVPR(irq); 659 ii->irq_dr = OPENPIC_IPIDR(irq); 660 ok = irq < info->ii_ipi_sources; 661 break; 662 case IST_MI: 663 ii->irq_vpr = OPENPIC_MIVPR(irq); 664 ii->irq_dr = OPENPIC_MIDR(irq); 665 ok = irq < info->ii_mi_sources; 666 break; 667 } 668 669 return ok; 670 } 671 672 static const char * 673 e500_intr_string(int irq, int ist) 674 { 675 struct cpu_info * const ci = curcpu(); 676 struct cpu_softc * const cpu = ci->ci_softc; 677 struct e500_intr_irq_info ii; 678 679 if (!e500_intr_irq_info_get(ci, irq, IPL_VM, ist, &ii)) 680 return NULL; 681 682 return cpu->cpu_evcnt_intrs[ii.irq_vector].ev_name; 683 } 684 685 __CTASSERT(__arraycount(ist_names) == IST_MAX); 686 687 static const char * 688 e500_intr_typename(int ist) 689 { 690 if (IST_NONE <= ist && ist < IST_MAX) 691 return ist_names[ist]; 692 693 return NULL; 694 } 695 696 static void * 697 e500_intr_cpu_establish(struct cpu_info *ci, int irq, int ipl, int ist, 698 int (*handler)(void *), void *arg) 699 { 700 struct cpu_softc * const cpu = ci->ci_softc; 701 struct e500_intr_irq_info ii; 702 703 KASSERT(ipl >= IPL_VM && ipl <= IPL_HIGH); 704 KASSERT(ist > IST_NONE && ist < IST_MAX && ist != IST_MSI); 705 706 if (!e500_intr_irq_info_get(ci, irq, ipl, ist, &ii)) { 707 printf("%s: e500_intr_irq_info_get(%p,%u,%u,%u,%p) failed\n", 708 __func__, ci, irq, ipl, ist, &ii); 709 return NULL; 710 } 711 712 struct intr_source * const is = &e500_intr_sources[ii.irq_vector]; 713 mutex_enter(&e500_intr_lock); 714 if (is->is_ipl != IPL_NONE) 715 return NULL; 716 717 is->is_func = handler; 718 is->is_arg = arg; 719 is->is_ipl = ipl; 720 is->is_ist = ist; 721 is->is_irq = irq; 722 is->is_vpr = ii.irq_vpr; 723 is->is_dr = ii.irq_dr; 724 725 uint32_t vpr = VPR_PRIORITY_MAKE(IPL2CTPR(ipl)) 726 | VPR_VECTOR_MAKE(((ii.irq_vector + 1) << 4) | ipl) 727 | (ist == IST_LEVEL_LOW 728 ? VPR_LEVEL_LOW 729 : (ist == IST_LEVEL_HIGH 730 ? VPR_LEVEL_HIGH 731 : (ist == IST_ONCHIP 732 ? VPR_P_HIGH 733 : 0))); 734 735 /* 736 * All interrupts go to the primary except per-cpu interrupts which get 737 * routed to the appropriate cpu. 738 */ 739 uint32_t dr = openpic_read(cpu, ii.irq_dr); 740 741 dr |= 1 << (IST_PERCPU_P(ist) ? ci->ci_cpuid : 0); 742 743 /* 744 * Update the vector/priority and destination registers keeping the 745 * interrupt masked. 746 */ 747 const register_t msr = wrtee(0); /* disable interrupts */ 748 openpic_write(cpu, ii.irq_vpr, vpr | VPR_MSK); 749 openpic_write(cpu, ii.irq_dr, dr); 750 751 /* 752 * Now unmask the interrupt. 753 */ 754 openpic_write(cpu, ii.irq_vpr, vpr); 755 756 wrtee(msr); /* re-enable interrupts */ 757 758 mutex_exit(&e500_intr_lock); 759 760 return is; 761 } 762 763 static void * 764 e500_intr_establish(int irq, int ipl, int ist, 765 int (*handler)(void *), void *arg) 766 { 767 return e500_intr_cpu_establish(curcpu(), irq, ipl, ist, handler, arg); 768 } 769 770 static void 771 e500_intr_disestablish(void *vis) 772 { 773 struct cpu_softc * const cpu = curcpu()->ci_softc; 774 struct intr_source * const is = vis; 775 struct e500_intr_irq_info ii; 776 777 KASSERT(e500_intr_sources <= is); 778 KASSERT(is < e500_intr_last_source); 779 KASSERT(!cpu_intr_p()); 780 781 bool ok = e500_intr_irq_info_get(curcpu(), is->is_irq, is->is_ipl, 782 is->is_ist, &ii); 783 (void)ok; /* appease gcc */ 784 KASSERT(ok); 785 KASSERT(is - e500_intr_sources == ii.irq_vector); 786 787 mutex_enter(&e500_intr_lock); 788 /* 789 * Mask the source using the mask (MSK) bit in the vector/priority reg. 790 */ 791 uint32_t vpr = openpic_read(cpu, ii.irq_vpr); 792 openpic_write(cpu, ii.irq_vpr, VPR_MSK | vpr); 793 794 /* 795 * Wait for the Activity (A) bit for the source to be cleared. 796 */ 797 while (openpic_read(cpu, ii.irq_vpr) & VPR_A) 798 ; 799 800 /* 801 * Now the source can be modified. 802 */ 803 openpic_write(cpu, ii.irq_dr, 0); /* stop delivery */ 804 openpic_write(cpu, ii.irq_vpr, VPR_MSK); /* mask/reset it */ 805 806 *is = (struct intr_source)INTR_SOURCE_INITIALIZER; 807 808 mutex_exit(&e500_intr_lock); 809 } 810 811 static void 812 e500_critintr(struct trapframe *tf) 813 { 814 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 815 } 816 817 static void 818 e500_decrintr(struct trapframe *tf) 819 { 820 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 821 } 822 823 static void 824 e500_fitintr(struct trapframe *tf) 825 { 826 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 827 } 828 829 static void 830 e500_wdogintr(struct trapframe *tf) 831 { 832 struct cpu_info * const ci = curcpu(); 833 mtspr(SPR_TSR, TSR_ENW|TSR_WIS); 834 wdog_barked = true; 835 dump_splhist(ci, NULL); 836 dump_trapframe(tf, NULL); 837 panic("%s: tf=%p tb=%"PRId64" srr0/srr1=%#lx/%#lx" 838 " cpl=%d idepth=%d, mtxcount=%d", 839 __func__, tf, mftb(), tf->tf_srr0, tf->tf_srr1, 840 ci->ci_cpl, ci->ci_idepth, ci->ci_mtx_count); 841 } 842 843 static void 844 e500_extintr(struct trapframe *tf) 845 { 846 struct cpu_info * const ci = curcpu(); 847 struct cpu_softc * const cpu = ci->ci_softc; 848 const int old_ipl = ci->ci_cpl; 849 850 /* if we paniced because of watchdog, PSL_CE will be clear. */ 851 KASSERT(wdog_barked || (mfmsr() & PSL_CE)); 852 853 #if 0 854 // printf("%s(%p): idepth=%d enter\n", __func__, tf, ci->ci_idepth); 855 if ((register_t)tf >= (register_t)curlwp->l_addr + USPACE 856 || (register_t)tf < (register_t)curlwp->l_addr + NBPG) { 857 printf("%s(entry): pid %d.%d (%s): srr0/srr1=%#lx/%#lx: invalid tf addr %p\n", 858 __func__, curlwp->l_proc->p_pid, curlwp->l_lid, 859 curlwp->l_proc->p_comm, tf->tf_srr0, tf->tf_srr1, tf); 860 } 861 #endif 862 863 864 ci->ci_data.cpu_nintr++; 865 tf->tf_cf.cf_idepth = ci->ci_idepth++; 866 cpu->cpu_pcpls[ci->ci_idepth] = old_ipl; 867 #if 1 868 if (mfmsr() & PSL_EE) 869 panic("%s(%p): MSR[EE] is on (%#lx)!", __func__, tf, mfmsr()); 870 if (old_ipl == IPL_HIGH 871 || IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 872 panic("%s(%p): old_ipl(%u) == IPL_HIGH(%u) " 873 "|| old_ipl + %u != OPENPIC_CTPR (%u)", 874 __func__, tf, old_ipl, IPL_HIGH, 875 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 876 #else 877 if (old_ipl >= IPL_VM) 878 panic("%s(%p): old_ipl(%u) >= IPL_VM(%u) CTPR=%u", 879 __func__, tf, old_ipl, IPL_VM, openpic_read(cpu, OPENPIC_CTPR)); 880 #endif 881 882 for (;;) { 883 /* 884 * Find out the pending interrupt. 885 */ 886 KASSERTMSG((mfmsr() & PSL_EE) == 0, 887 "%s(%p): MSR[EE] left on (%#lx)!", __func__, tf, mfmsr()); 888 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 889 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 890 __func__, tf, __LINE__, old_ipl, 891 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 892 const uint32_t iack = openpic_read(cpu, OPENPIC_IACK); 893 #ifdef DIAGNOSTIC 894 const int ipl = iack & 0xf; 895 #endif 896 const int irq = (iack >> 4) - 1; 897 #if 0 898 printf("%s: iack=%d ipl=%d irq=%d <%s>\n", 899 __func__, iack, ipl, irq, 900 (iack != IRQ_SPURIOUS ? 901 cpu->cpu_evcnt_intrs[irq].ev_name : "spurious")); 902 #endif 903 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 904 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 905 __func__, tf, __LINE__, old_ipl, 906 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 907 if (iack == IRQ_SPURIOUS) 908 break; 909 910 struct intr_source * const is = &e500_intr_sources[irq]; 911 if (__predict_true(is < e500_intr_last_source)) { 912 /* 913 * Timer interrupts get their argument overriden with 914 * the pointer to the trapframe. 915 */ 916 KASSERT(is->is_ipl == ipl); 917 void *arg = (is->is_ist == IST_TIMER ? tf : is->is_arg); 918 if (is->is_ipl <= old_ipl) 919 panic("%s(%p): %s (%u): is->is_ipl (%u) <= old_ipl (%u)\n", 920 __func__, tf, 921 cpu->cpu_evcnt_intrs[irq].ev_name, irq, 922 is->is_ipl, old_ipl); 923 KASSERT(is->is_ipl > old_ipl); 924 e500_splset(ci, is->is_ipl); /* change IPL */ 925 if (__predict_false(is->is_func == NULL)) { 926 aprint_error_dev(ci->ci_dev, 927 "interrupt from unestablished irq %d\n", 928 irq); 929 } else { 930 int (*func)(void *) = is->is_func; 931 wrtee(PSL_EE); 932 int rv = (*func)(arg); 933 wrtee(0); 934 #if DEBUG > 2 935 printf("%s: %s handler %p(%p) returned %d\n", 936 __func__, 937 cpu->cpu_evcnt_intrs[irq].ev_name, 938 func, arg, rv); 939 #endif 940 if (rv == 0) 941 cpu->cpu_evcnt_spurious_intr.ev_count++; 942 } 943 e500_splset(ci, old_ipl); /* restore IPL */ 944 cpu->cpu_evcnt_intrs[irq].ev_count++; 945 } else { 946 aprint_error_dev(ci->ci_dev, 947 "interrupt from illegal irq %d\n", irq); 948 cpu->cpu_evcnt_spurious_intr.ev_count++; 949 } 950 /* 951 * If this is a nested interrupt, simply ack it and exit 952 * because the loop we interrupted will complete looking 953 * for interrupts. 954 */ 955 KASSERTMSG((mfmsr() & PSL_EE) == 0, 956 "%s(%p): MSR[EE] left on (%#lx)!", __func__, tf, mfmsr()); 957 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 958 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 959 __func__, tf, __LINE__, old_ipl, 960 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 961 962 openpic_write(cpu, OPENPIC_EOI, 0); 963 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 964 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 965 __func__, tf, __LINE__, old_ipl, 966 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 967 if (ci->ci_idepth > 0) 968 break; 969 } 970 971 ci->ci_idepth--; 972 973 #ifdef __HAVE_FAST_SOFTINTS 974 /* 975 * Before exiting, deal with any softints that need to be dealt with. 976 */ 977 const u_int softints = ci->ci_data.cpu_softints & (IPL_SOFTMASK << old_ipl); 978 if (__predict_false(softints != 0)) { 979 KASSERT(old_ipl < IPL_VM); 980 e500_splset(ci, IPL_HIGH); /* pop to high */ 981 wrtee(PSL_EE); /* reenable interrupts */ 982 powerpc_softint(ci, old_ipl, /* deal with them */ 983 tf->tf_srr0); 984 wrtee(0); /* disable interrupts */ 985 e500_splset(ci, old_ipl); /* and drop back */ 986 } 987 #endif /* __HAVE_FAST_SOFTINTS */ 988 KASSERT(ci->ci_cpl == old_ipl); 989 990 /* 991 * If we interrupted while power-saving and we need to exit idle, 992 * we need to clear PSL_POW so we won't go back into power-saving. 993 */ 994 if (__predict_false(tf->tf_srr1 & PSL_POW) && ci->ci_want_resched) 995 tf->tf_srr1 &= ~PSL_POW; 996 997 // printf("%s(%p): idepth=%d exit\n", __func__, tf, ci->ci_idepth); 998 } 999 1000 static void 1001 e500_intr_init(void) 1002 { 1003 struct cpu_info * const ci = curcpu(); 1004 struct cpu_softc * const cpu = ci->ci_softc; 1005 const uint32_t frr = openpic_read(cpu, OPENPIC_FRR); 1006 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1007 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1008 struct intr_source *is; 1009 struct e500_intr_info * const ii = &e500_intr_info; 1010 1011 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 1012 switch (svr) { 1013 #ifdef MPC8536 1014 case SVR_MPC8536v1 >> 16: 1015 *ii = mpc8536_intr_info; 1016 break; 1017 #endif 1018 #ifdef MPC8544 1019 case SVR_MPC8544v1 >> 16: 1020 *ii = mpc8544_intr_info; 1021 break; 1022 #endif 1023 #ifdef MPC8548 1024 case SVR_MPC8543v1 >> 16: 1025 case SVR_MPC8548v1 >> 16: 1026 *ii = mpc8548_intr_info; 1027 break; 1028 #endif 1029 #ifdef MPC8555 1030 case SVR_MPC8541v1 >> 16: 1031 case SVR_MPC8555v1 >> 16: 1032 *ii = mpc8555_intr_info; 1033 break; 1034 #endif 1035 #ifdef MPC8568 1036 case SVR_MPC8568v1 >> 16: 1037 *ii = mpc8568_intr_info; 1038 break; 1039 #endif 1040 #ifdef MPC8572 1041 case SVR_MPC8572v1 >> 16: 1042 *ii = mpc8572_intr_info; 1043 break; 1044 #endif 1045 #ifdef P1025 1046 case SVR_P1016v1 >> 16: 1047 case SVR_P1025v1 >> 16: 1048 *ii = p1025_intr_info; 1049 break; 1050 #endif 1051 #ifdef P2020 1052 case SVR_P2010v2 >> 16: 1053 case SVR_P2020v2 >> 16: 1054 *ii = p20x0_intr_info; 1055 break; 1056 #endif 1057 default: 1058 panic("%s: don't know how to deal with SVR %#lx", 1059 __func__, mfspr(SPR_SVR)); 1060 } 1061 1062 /* 1063 * We need to be in mixed mode. 1064 */ 1065 openpic_write(cpu, OPENPIC_GCR, GCR_M); 1066 1067 /* 1068 * Make we and the openpic both agree about the current SPL level. 1069 */ 1070 e500_splset(ci, ci->ci_cpl); 1071 1072 /* 1073 * Allow the required number of interrupt sources. 1074 */ 1075 is = kmem_zalloc(nirq * sizeof(*is), KM_SLEEP); 1076 KASSERT(is); 1077 e500_intr_sources = is; 1078 e500_intr_last_source = is + nirq; 1079 1080 /* 1081 * Initialize all the external interrupts as active low. 1082 */ 1083 for (u_int irq = 0; irq < e500_intr_info.ii_external_sources; irq++) { 1084 openpic_write(cpu, OPENPIC_EIVPR(irq), 1085 VPR_VECTOR_MAKE(irq) | VPR_LEVEL_LOW); 1086 } 1087 } 1088 1089 static void 1090 e500_idlespin(void) 1091 { 1092 KASSERTMSG(curcpu()->ci_cpl == IPL_NONE, 1093 "%s: cpu%u: ci_cpl (%d) != 0", __func__, cpu_number(), 1094 curcpu()->ci_cpl); 1095 KASSERTMSG(CTPR2IPL(openpic_read(curcpu()->ci_softc, OPENPIC_CTPR)) == IPL_NONE, 1096 "%s: cpu%u: CTPR (%d) != IPL_NONE", __func__, cpu_number(), 1097 CTPR2IPL(openpic_read(curcpu()->ci_softc, OPENPIC_CTPR))); 1098 KASSERT(mfmsr() & PSL_EE); 1099 1100 if (powersave > 0) 1101 mtmsr(mfmsr() | PSL_POW); 1102 } 1103 1104 static void 1105 e500_intr_cpu_attach(struct cpu_info *ci) 1106 { 1107 struct cpu_softc * const cpu = ci->ci_softc; 1108 const char * const xname = device_xname(ci->ci_dev); 1109 1110 const u_int32_t frr = openpic_read(cpu, OPENPIC_FRR); 1111 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1112 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1113 1114 const struct e500_intr_info * const info = &e500_intr_info; 1115 1116 cpu->cpu_clock_gtbcr = OPENPIC_GTBCR(ci->ci_cpuid, E500_CLOCK_TIMER); 1117 1118 cpu->cpu_evcnt_intrs = 1119 kmem_zalloc(nirq * sizeof(cpu->cpu_evcnt_intrs[0]), KM_SLEEP); 1120 KASSERT(cpu->cpu_evcnt_intrs); 1121 1122 struct evcnt *evcnt = cpu->cpu_evcnt_intrs; 1123 for (size_t j = 0; j < info->ii_external_sources; j++, evcnt++) { 1124 const char *name = e500_intr_external_name_lookup(j); 1125 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, NULL, xname, name); 1126 } 1127 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_ONCHIP]); 1128 for (size_t j = 0; j < info->ii_onchip_sources; j++, evcnt++) { 1129 if (info->ii_onchip_bitmap[j / 32] & __BIT(j & 31)) { 1130 const char *name = e500_intr_onchip_name_lookup(j); 1131 if (name != NULL) { 1132 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1133 NULL, xname, name); 1134 #ifdef DIAGNOSTIC 1135 } else { 1136 printf("%s: missing evcnt for onchip irq %zu\n", 1137 __func__, j); 1138 #endif 1139 } 1140 } 1141 } 1142 1143 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_MSIGROUP]); 1144 for (size_t j = 0; j < info->ii_msigroup_sources; j++, evcnt++) { 1145 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1146 NULL, xname, e500_msigroup_intr_names[j].in_name); 1147 } 1148 1149 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_TIMER]); 1150 evcnt += ci->ci_cpuid * info->ii_percpu_sources; 1151 for (size_t j = 0; j < info->ii_timer_sources; j++, evcnt++) { 1152 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1153 NULL, xname, e500_timer_intr_names[j].in_name); 1154 } 1155 1156 for (size_t j = 0; j < info->ii_ipi_sources; j++, evcnt++) { 1157 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1158 NULL, xname, e500_ipi_intr_names[j].in_name); 1159 } 1160 1161 for (size_t j = 0; j < info->ii_mi_sources; j++, evcnt++) { 1162 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1163 NULL, xname, e500_mi_intr_names[j].in_name); 1164 } 1165 1166 ci->ci_idlespin = e500_idlespin; 1167 } 1168 1169 static void 1170 e500_intr_cpu_send_ipi(cpuid_t target, uint32_t ipimsg) 1171 { 1172 struct cpu_info * const ci = curcpu(); 1173 struct cpu_softc * const cpu = ci->ci_softc; 1174 uint32_t dstmask; 1175 1176 if (target >= CPU_MAXNUM) { 1177 CPU_INFO_ITERATOR cii; 1178 struct cpu_info *dst_ci; 1179 1180 KASSERT(target == IPI_DST_NOTME || target == IPI_DST_ALL); 1181 1182 dstmask = 0; 1183 for (CPU_INFO_FOREACH(cii, dst_ci)) { 1184 if (target == IPI_DST_ALL || ci != dst_ci) { 1185 dstmask |= 1 << cpu_index(ci); 1186 if (ipimsg) 1187 atomic_or_32(&dst_ci->ci_pending_ipis, 1188 ipimsg); 1189 } 1190 } 1191 } else { 1192 struct cpu_info * const dst_ci = cpu_lookup(target); 1193 KASSERT(dst_ci != NULL); 1194 KASSERTMSG(target == cpu_index(dst_ci), 1195 "%s: target (%lu) != cpu_index(cpu%u)", 1196 __func__, target, cpu_index(dst_ci)); 1197 dstmask = (1 << target); 1198 if (ipimsg) 1199 atomic_or_32(&dst_ci->ci_pending_ipis, ipimsg); 1200 } 1201 1202 openpic_write(cpu, OPENPIC_IPIDR(0), dstmask); 1203 } 1204 1205 typedef void (*ipifunc_t)(void); 1206 1207 #ifdef __HAVE_PREEEMPTION 1208 static void 1209 e500_ipi_kpreempt(void) 1210 { 1211 poowerpc_softint_trigger(1 << IPL_NONE); 1212 } 1213 #endif 1214 1215 static const ipifunc_t e500_ipifuncs[] = { 1216 [ilog2(IPI_XCALL)] = xc_ipi_handler, 1217 [ilog2(IPI_HALT)] = e500_ipi_halt, 1218 #ifdef __HAVE_PREEMPTION 1219 [ilog2(IPI_KPREEMPT)] = e500_ipi_kpreempt, 1220 #endif 1221 [ilog2(IPI_TLB1SYNC)] = e500_tlb1_sync, 1222 }; 1223 1224 static int 1225 e500_ipi_intr(void *v) 1226 { 1227 struct cpu_info * const ci = curcpu(); 1228 1229 ci->ci_ev_ipi.ev_count++; 1230 1231 uint32_t pending_ipis = atomic_swap_32(&ci->ci_pending_ipis, 0); 1232 for (u_int ipi = 31; pending_ipis != 0; ipi--, pending_ipis <<= 1) { 1233 const u_int bits = __builtin_clz(pending_ipis); 1234 ipi -= bits; 1235 pending_ipis <<= bits; 1236 KASSERT(e500_ipifuncs[ipi] != NULL); 1237 (*e500_ipifuncs[ipi])(); 1238 } 1239 1240 return 1; 1241 } 1242 1243 static void 1244 e500_intr_cpu_hatch(struct cpu_info *ci) 1245 { 1246 /* 1247 * Establish clock interrupt for this CPU. 1248 */ 1249 if (e500_intr_cpu_establish(ci, E500_CLOCK_TIMER, IPL_CLOCK, IST_TIMER, 1250 e500_clock_intr, NULL) == NULL) 1251 panic("%s: failed to establish clock interrupt!", __func__); 1252 1253 /* 1254 * Establish the IPI interrupts for this CPU. 1255 */ 1256 if (e500_intr_cpu_establish(ci, 0, IPL_VM, IST_IPI, e500_ipi_intr, 1257 NULL) == NULL) 1258 panic("%s: failed to establish ipi interrupt!", __func__); 1259 1260 /* 1261 * Enable watchdog interrupts. 1262 */ 1263 uint32_t tcr = mfspr(SPR_TCR); 1264 tcr |= TCR_WIE; 1265 mtspr(SPR_TCR, tcr); 1266 } 1267
Indexes created Mon Sep 29 21:09:56 GMT 2025