e500_intr.c revision 1.28
1 /* $NetBSD: e500_intr.c,v 1.28 2014/12/27 16:19:33 nonaka Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_mpc85xx.h" 38 39 #define __INTR_PRIVATE 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: e500_intr.c,v 1.28 2014/12/27 16:19:33 nonaka Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/proc.h> 46 #include <sys/intr.h> 47 #include <sys/cpu.h> 48 #include <sys/kmem.h> 49 #include <sys/atomic.h> 50 #include <sys/bus.h> 51 #include <sys/xcall.h> 52 #include <sys/ipi.h> 53 #include <sys/bitops.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #ifdef __HAVE_FAST_SOFTINTS 58 #include <powerpc/softint.h> 59 #endif 60 61 #include <powerpc/spr.h> 62 #include <powerpc/booke/spr.h> 63 64 #include <powerpc/booke/cpuvar.h> 65 #include <powerpc/booke/e500reg.h> 66 #include <powerpc/booke/e500var.h> 67 #include <powerpc/booke/openpicreg.h> 68 69 #define IPL2CTPR(ipl) ((ipl) + 15 - IPL_HIGH) 70 #define CTPR2IPL(ctpr) ((ctpr) - (15 - IPL_HIGH)) 71 72 #define IST_PERCPU_P(ist) ((ist) >= IST_TIMER) 73 74 struct e500_intr_irq_info { 75 bus_addr_t irq_vpr; 76 bus_addr_t irq_dr; 77 u_int irq_vector; 78 }; 79 80 struct intr_source { 81 int (*is_func)(void *); 82 void *is_arg; 83 int8_t is_ipl; 84 uint8_t is_ist; 85 uint8_t is_irq; 86 bus_size_t is_vpr; 87 bus_size_t is_dr; 88 }; 89 90 #define INTR_SOURCE_INITIALIZER \ 91 { .is_func = e500_intr_spurious, .is_arg = NULL, \ 92 .is_irq = -1, .is_ipl = IPL_NONE, .is_ist = IST_NONE, } 93 94 struct e500_intr_name { 95 uint8_t in_irq; 96 const char in_name[15]; 97 }; 98 99 static const struct e500_intr_name e500_onchip_intr_names[] = { 100 { ISOURCE_L2, "l2" }, 101 { ISOURCE_ECM, "ecm" }, 102 { ISOURCE_DDR, "ddr" }, 103 { ISOURCE_LBC, "lbc" }, 104 { ISOURCE_DMA_CHAN1, "dma-chan1" }, 105 { ISOURCE_DMA_CHAN2, "dma-chan2" }, 106 { ISOURCE_DMA_CHAN3, "dma-chan3" }, 107 { ISOURCE_DMA_CHAN4, "dma-chan4" }, 108 { ISOURCE_PCI1, "pci1" }, 109 { ISOURCE_PCIEX2, "pcie2" }, 110 { ISOURCE_PCIEX , "pcie1" }, 111 { ISOURCE_PCIEX3, "pcie3" }, 112 { ISOURCE_USB1, "usb1" }, 113 { ISOURCE_ETSEC1_TX, "etsec1-tx" }, 114 { ISOURCE_ETSEC1_RX, "etsec1-rx" }, 115 { ISOURCE_ETSEC3_TX, "etsec3-tx" }, 116 { ISOURCE_ETSEC3_RX, "etsec3-rx" }, 117 { ISOURCE_ETSEC3_ERR, "etsec3-err" }, 118 { ISOURCE_ETSEC1_ERR, "etsec1-err" }, 119 { ISOURCE_ETSEC2_TX, "etsec2-tx" }, 120 { ISOURCE_ETSEC2_RX, "etsec2-rx" }, 121 { ISOURCE_ETSEC4_TX, "etsec4-tx" }, 122 { ISOURCE_ETSEC4_RX, "etsec4-rx" }, 123 { ISOURCE_ETSEC4_ERR, "etsec4-err" }, 124 { ISOURCE_ETSEC2_ERR, "etsec2-err" }, 125 { ISOURCE_DUART, "duart" }, 126 { ISOURCE_I2C, "i2c" }, 127 { ISOURCE_PERFMON, "perfmon" }, 128 { ISOURCE_SECURITY1, "sec1" }, 129 { ISOURCE_GPIO, "gpio" }, 130 { ISOURCE_SRIO_EWPU, "srio-ewpu" }, 131 { ISOURCE_SRIO_ODBELL, "srio-odbell" }, 132 { ISOURCE_SRIO_IDBELL, "srio-idbell" }, 133 { ISOURCE_SRIO_OMU1, "srio-omu1" }, 134 { ISOURCE_SRIO_IMU1, "srio-imu1" }, 135 { ISOURCE_SRIO_OMU2, "srio-omu2" }, 136 { ISOURCE_SRIO_IMU2, "srio-imu2" }, 137 { ISOURCE_SECURITY2, "sec2" }, 138 { ISOURCE_SPI, "spi" }, 139 { ISOURCE_ETSEC1_PTP, "etsec1-ptp" }, 140 { ISOURCE_ETSEC2_PTP, "etsec2-ptp" }, 141 { ISOURCE_ETSEC3_PTP, "etsec3-ptp" }, 142 { ISOURCE_ETSEC4_PTP, "etsec4-ptp" }, 143 { ISOURCE_ESDHC, "esdhc" }, 144 { 0, "" }, 145 }; 146 147 const struct e500_intr_name default_external_intr_names[] = { 148 { 0, "" }, 149 }; 150 151 static const struct e500_intr_name e500_msigroup_intr_names[] = { 152 { 0, "msigroup0" }, 153 { 1, "msigroup1" }, 154 { 2, "msigroup2" }, 155 { 3, "msigroup3" }, 156 { 4, "msigroup4" }, 157 { 5, "msigroup5" }, 158 { 6, "msigroup6" }, 159 { 7, "msigroup7" }, 160 { 0, "" }, 161 }; 162 163 static const struct e500_intr_name e500_timer_intr_names[] = { 164 { 0, "timer0" }, 165 { 1, "timer1" }, 166 { 2, "timer2" }, 167 { 3, "timer3" }, 168 { 0, "" }, 169 }; 170 171 static const struct e500_intr_name e500_ipi_intr_names[] = { 172 { 0, "ipi0" }, 173 { 1, "ipi1" }, 174 { 2, "ipi2" }, 175 { 3, "ipi3" }, 176 { 0, "" }, 177 }; 178 179 static const struct e500_intr_name e500_mi_intr_names[] = { 180 { 0, "mi0" }, 181 { 1, "mi1" }, 182 { 2, "mi2" }, 183 { 3, "mi3" }, 184 { 0, "" }, 185 }; 186 187 struct e500_intr_info { 188 u_int ii_external_sources; 189 uint32_t ii_onchip_bitmap[2]; 190 u_int ii_onchip_sources; 191 u_int ii_msigroup_sources; 192 u_int ii_ipi_sources; /* per-cpu */ 193 u_int ii_timer_sources; /* per-cpu */ 194 u_int ii_mi_sources; /* per-cpu */ 195 u_int ii_percpu_sources; 196 const struct e500_intr_name *ii_external_intr_names; 197 const struct e500_intr_name *ii_onchip_intr_names; 198 u_int8_t ii_ist_vectors[IST_MAX+1]; 199 }; 200 201 static kmutex_t e500_intr_lock __cacheline_aligned; 202 static struct e500_intr_info e500_intr_info; 203 204 #define INTR_INFO_DECL(lc_chip, UC_CHIP) \ 205 static const struct e500_intr_info lc_chip##_intr_info = { \ 206 .ii_external_sources = UC_CHIP ## _EXTERNALSOURCES, \ 207 .ii_onchip_bitmap = UC_CHIP ## _ONCHIPBITMAP, \ 208 .ii_onchip_sources = UC_CHIP ## _ONCHIPSOURCES, \ 209 .ii_msigroup_sources = UC_CHIP ## _MSIGROUPSOURCES, \ 210 .ii_timer_sources = UC_CHIP ## _TIMERSOURCES, \ 211 .ii_ipi_sources = UC_CHIP ## _IPISOURCES, \ 212 .ii_mi_sources = UC_CHIP ## _MISOURCES, \ 213 .ii_percpu_sources = UC_CHIP ## _TIMERSOURCES \ 214 + UC_CHIP ## _IPISOURCES + UC_CHIP ## _MISOURCES, \ 215 .ii_external_intr_names = lc_chip ## _external_intr_names, \ 216 .ii_onchip_intr_names = lc_chip ## _onchip_intr_names, \ 217 .ii_ist_vectors = { \ 218 [IST_NONE] = ~0, \ 219 [IST_EDGE] = 0, \ 220 [IST_LEVEL_LOW] = 0, \ 221 [IST_LEVEL_HIGH] = 0, \ 222 [IST_PULSE] = 0, \ 223 [IST_ONCHIP] = UC_CHIP ## _EXTERNALSOURCES, \ 224 [IST_MSIGROUP] = UC_CHIP ## _EXTERNALSOURCES \ 225 + UC_CHIP ## _ONCHIPSOURCES, \ 226 [IST_TIMER] = UC_CHIP ## _EXTERNALSOURCES \ 227 + UC_CHIP ## _ONCHIPSOURCES \ 228 + UC_CHIP ## _MSIGROUPSOURCES, \ 229 [IST_IPI] = UC_CHIP ## _EXTERNALSOURCES \ 230 + UC_CHIP ## _ONCHIPSOURCES \ 231 + UC_CHIP ## _MSIGROUPSOURCES \ 232 + UC_CHIP ## _TIMERSOURCES, \ 233 [IST_MI] = UC_CHIP ## _EXTERNALSOURCES \ 234 + UC_CHIP ## _ONCHIPSOURCES \ 235 + UC_CHIP ## _MSIGROUPSOURCES \ 236 + UC_CHIP ## _TIMERSOURCES \ 237 + UC_CHIP ## _IPISOURCES, \ 238 [IST_MAX] = UC_CHIP ## _EXTERNALSOURCES \ 239 + UC_CHIP ## _ONCHIPSOURCES \ 240 + UC_CHIP ## _MSIGROUPSOURCES \ 241 + UC_CHIP ## _TIMERSOURCES \ 242 + UC_CHIP ## _IPISOURCES \ 243 + UC_CHIP ## _MISOURCES, \ 244 }, \ 245 } 246 247 #ifdef MPC8536 248 #define mpc8536_external_intr_names default_external_intr_names 249 const struct e500_intr_name mpc8536_onchip_intr_names[] = { 250 { ISOURCE_SATA2, "sata2" }, 251 { ISOURCE_USB2, "usb2" }, 252 { ISOURCE_USB3, "usb3" }, 253 { ISOURCE_SATA1, "sata1" }, 254 { 0, "" }, 255 }; 256 257 INTR_INFO_DECL(mpc8536, MPC8536); 258 #endif 259 260 #ifdef MPC8544 261 #define mpc8544_external_intr_names default_external_intr_names 262 const struct e500_intr_name mpc8544_onchip_intr_names[] = { 263 { 0, "" }, 264 }; 265 266 INTR_INFO_DECL(mpc8544, MPC8544); 267 #endif 268 #ifdef MPC8548 269 #define mpc8548_external_intr_names default_external_intr_names 270 const struct e500_intr_name mpc8548_onchip_intr_names[] = { 271 { ISOURCE_PCI1, "pci1" }, 272 { ISOURCE_PCI2, "pci2" }, 273 { 0, "" }, 274 }; 275 276 INTR_INFO_DECL(mpc8548, MPC8548); 277 #endif 278 #ifdef MPC8555 279 #define mpc8555_external_intr_names default_external_intr_names 280 const struct e500_intr_name mpc8555_onchip_intr_names[] = { 281 { ISOURCE_PCI2, "pci2" }, 282 { ISOURCE_CPM, "CPM" }, 283 { 0, "" }, 284 }; 285 286 INTR_INFO_DECL(mpc8555, MPC8555); 287 #endif 288 #ifdef MPC8568 289 #define mpc8568_external_intr_names default_external_intr_names 290 const struct e500_intr_name mpc8568_onchip_intr_names[] = { 291 { ISOURCE_QEB_LOW, "QEB low" }, 292 { ISOURCE_QEB_PORT, "QEB port" }, 293 { ISOURCE_QEB_IECC, "QEB iram ecc" }, 294 { ISOURCE_QEB_MUECC, "QEB ram ecc" }, 295 { ISOURCE_TLU1, "tlu1" }, 296 { ISOURCE_QEB_HIGH, "QEB high" }, 297 { 0, "" }, 298 }; 299 300 INTR_INFO_DECL(mpc8568, MPC8568); 301 #endif 302 #ifdef MPC8572 303 #define mpc8572_external_intr_names default_external_intr_names 304 const struct e500_intr_name mpc8572_onchip_intr_names[] = { 305 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 306 { ISOURCE_FEC, "fec" }, 307 { ISOURCE_PME_GENERAL, "pme" }, 308 { ISOURCE_TLU1, "tlu1" }, 309 { ISOURCE_TLU2, "tlu2" }, 310 { ISOURCE_PME_CHAN1, "pme-chan1" }, 311 { ISOURCE_PME_CHAN2, "pme-chan2" }, 312 { ISOURCE_PME_CHAN3, "pme-chan3" }, 313 { ISOURCE_PME_CHAN4, "pme-chan4" }, 314 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 315 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 316 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 317 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 318 { 0, "" }, 319 }; 320 321 INTR_INFO_DECL(mpc8572, MPC8572); 322 #endif 323 324 #ifdef P1025 325 #define p1025_external_intr_names default_external_intr_names 326 const struct e500_intr_name p1025_onchip_intr_names[] = { 327 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 328 { ISOURCE_ETSEC1_G1_TX, "etsec1-g1-tx" }, 329 { ISOURCE_ETSEC1_G1_RX, "etsec1-g1-rx" }, 330 { ISOURCE_ETSEC1_G1_ERR, "etsec1-g1-error" }, 331 { ISOURCE_ETSEC2_G1_TX, "etsec2-g1-tx" }, 332 { ISOURCE_ETSEC2_G1_RX, "etsec2-g1-rx" }, 333 { ISOURCE_ETSEC2_G1_ERR, "etsec2-g1-error" }, 334 { ISOURCE_ETSEC3_G1_TX, "etsec3-g1-tx" }, 335 { ISOURCE_ETSEC3_G1_RX, "etsec3-g1-rx" }, 336 { ISOURCE_ETSEC3_G1_ERR, "etsec3-g1-error" }, 337 { ISOURCE_QEB_MUECC, "qeb-low" }, 338 { ISOURCE_QEB_HIGH, "qeb-crit" }, 339 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 340 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 341 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 342 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 343 { 0, "" }, 344 }; 345 346 INTR_INFO_DECL(p1025, P1025); 347 #endif 348 349 #ifdef P2020 350 #define p20x0_external_intr_names default_external_intr_names 351 const struct e500_intr_name p20x0_onchip_intr_names[] = { 352 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 353 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 354 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 355 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 356 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 357 { 0, "" }, 358 }; 359 360 INTR_INFO_DECL(p20x0, P20x0); 361 #endif 362 363 #ifdef P1023 364 #define p1023_external_intr_names default_external_intr_names 365 const struct e500_intr_name p1023_onchip_intr_names[] = { 366 { ISOURCE_FMAN, "fman" }, 367 { ISOURCE_MDIO, "mdio" }, 368 { ISOURCE_QMAN0, "qman0" }, 369 { ISOURCE_BMAN0, "bman0" }, 370 { ISOURCE_QMAN1, "qman1" }, 371 { ISOURCE_BMAN1, "bman1" }, 372 { ISOURCE_QMAN2, "qman2" }, 373 { ISOURCE_BMAN2, "bman2" }, 374 { ISOURCE_SECURITY2_P1023, "sec2" }, 375 { ISOURCE_SEC_GENERAL, "sec-general" }, 376 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 377 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 378 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 379 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 380 { 0, "" }, 381 }; 382 383 INTR_INFO_DECL(p1023, P1023); 384 #endif 385 386 static const char ist_names[][12] = { 387 [IST_NONE] = "none", 388 [IST_EDGE] = "edge", 389 [IST_LEVEL_LOW] = "level-", 390 [IST_LEVEL_HIGH] = "level+", 391 [IST_PULSE] = "pulse", 392 [IST_MSI] = "msi", 393 [IST_ONCHIP] = "onchip", 394 [IST_MSIGROUP] = "msigroup", 395 [IST_TIMER] = "timer", 396 [IST_IPI] = "ipi", 397 [IST_MI] = "msgint", 398 }; 399 400 static struct intr_source *e500_intr_sources; 401 static const struct intr_source *e500_intr_last_source; 402 403 static void *e500_intr_establish(int, int, int, int (*)(void *), void *); 404 static void e500_intr_disestablish(void *); 405 static void e500_intr_cpu_attach(struct cpu_info *ci); 406 static void e500_intr_cpu_hatch(struct cpu_info *ci); 407 static void e500_intr_cpu_send_ipi(cpuid_t, uintptr_t); 408 static void e500_intr_init(void); 409 static const char *e500_intr_string(int, int, char *, size_t); 410 static const char *e500_intr_typename(int); 411 static void e500_critintr(struct trapframe *tf); 412 static void e500_decrintr(struct trapframe *tf); 413 static void e500_extintr(struct trapframe *tf); 414 static void e500_fitintr(struct trapframe *tf); 415 static void e500_wdogintr(struct trapframe *tf); 416 static void e500_spl0(void); 417 static int e500_splraise(int); 418 static void e500_splx(int); 419 420 const struct intrsw e500_intrsw = { 421 .intrsw_establish = e500_intr_establish, 422 .intrsw_disestablish = e500_intr_disestablish, 423 .intrsw_init = e500_intr_init, 424 .intrsw_cpu_attach = e500_intr_cpu_attach, 425 .intrsw_cpu_hatch = e500_intr_cpu_hatch, 426 .intrsw_cpu_send_ipi = e500_intr_cpu_send_ipi, 427 .intrsw_string = e500_intr_string, 428 .intrsw_typename = e500_intr_typename, 429 430 .intrsw_critintr = e500_critintr, 431 .intrsw_decrintr = e500_decrintr, 432 .intrsw_extintr = e500_extintr, 433 .intrsw_fitintr = e500_fitintr, 434 .intrsw_wdogintr = e500_wdogintr, 435 436 .intrsw_splraise = e500_splraise, 437 .intrsw_splx = e500_splx, 438 .intrsw_spl0 = e500_spl0, 439 440 #ifdef __HAVE_FAST_SOFTINTS 441 .intrsw_softint_init_md = powerpc_softint_init_md, 442 .intrsw_softint_trigger = powerpc_softint_trigger, 443 #endif 444 }; 445 446 static bool wdog_barked; 447 448 static inline uint32_t 449 openpic_read(struct cpu_softc *cpu, bus_size_t offset) 450 { 451 452 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, 453 OPENPIC_BASE + offset); 454 } 455 456 static inline void 457 openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val) 458 { 459 460 return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, 461 OPENPIC_BASE + offset, val); 462 } 463 464 static const char * 465 e500_intr_external_name_lookup(int irq) 466 { 467 prop_array_t extirqs = board_info_get_object("external-irqs"); 468 prop_string_t irqname = prop_array_get(extirqs, irq); 469 KASSERT(irqname != NULL); 470 KASSERT(prop_object_type(irqname) == PROP_TYPE_STRING); 471 472 return prop_string_cstring_nocopy(irqname); 473 } 474 475 static const char * 476 e500_intr_name_lookup(const struct e500_intr_name *names, int irq) 477 { 478 for (; names->in_name[0] != '\0'; names++) { 479 if (names->in_irq == irq) 480 return names->in_name; 481 } 482 483 return NULL; 484 } 485 486 static const char * 487 e500_intr_onchip_name_lookup(int irq) 488 { 489 const char *name; 490 491 name = e500_intr_name_lookup(e500_intr_info.ii_onchip_intr_names, irq); 492 if (name == NULL) 493 name = e500_intr_name_lookup(e500_onchip_intr_names, irq); 494 495 return name; 496 } 497 498 static inline void 499 e500_splset(struct cpu_info *ci, int ipl) 500 { 501 struct cpu_softc * const cpu = ci->ci_softc; 502 503 KASSERT((curlwp->l_pflag & LP_INTR) == 0 || ipl != IPL_NONE); 504 const u_int ctpr = IPL2CTPR(ipl); 505 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == IPL2CTPR(ci->ci_cpl)); 506 openpic_write(cpu, OPENPIC_CTPR, ctpr); 507 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ctpr); 508 #ifdef DIAGNOSTIC 509 cpu->cpu_spl_tb[ipl][ci->ci_cpl] = mftb(); 510 #endif 511 ci->ci_cpl = ipl; 512 } 513 514 static void 515 e500_spl0(void) 516 { 517 wrtee(0); 518 519 struct cpu_info * const ci = curcpu(); 520 521 #ifdef __HAVE_FAST_SOFTINTS 522 if (__predict_false(ci->ci_data.cpu_softints != 0)) { 523 e500_splset(ci, IPL_HIGH); 524 wrtee(PSL_EE); 525 powerpc_softint(ci, IPL_NONE, 526 (vaddr_t)__builtin_return_address(0)); 527 wrtee(0); 528 } 529 #endif /* __HAVE_FAST_SOFTINTS */ 530 e500_splset(ci, IPL_NONE); 531 532 wrtee(PSL_EE); 533 } 534 535 static void 536 e500_splx(int ipl) 537 { 538 struct cpu_info * const ci = curcpu(); 539 const int old_ipl = ci->ci_cpl; 540 541 /* if we paniced because of watchdog, PSL_CE will be clear. */ 542 KASSERT(wdog_barked || (mfmsr() & PSL_CE)); 543 544 if (ipl == old_ipl) 545 return; 546 547 if (__predict_false(ipl > old_ipl)) { 548 printf("%s: %p: cpl=%u: ignoring splx(%u) to raise ipl\n", 549 __func__, __builtin_return_address(0), old_ipl, ipl); 550 if (old_ipl == IPL_NONE) 551 Debugger(); 552 } 553 554 // const 555 register_t msr = wrtee(0); 556 #ifdef __HAVE_FAST_SOFTINTS 557 const u_int softints = ci->ci_data.cpu_softints & (IPL_SOFTMASK << ipl); 558 if (__predict_false(softints != 0)) { 559 e500_splset(ci, IPL_HIGH); 560 wrtee(msr); 561 powerpc_softint(ci, ipl, 562 (vaddr_t)__builtin_return_address(0)); 563 wrtee(0); 564 } 565 #endif /* __HAVE_FAST_SOFTINTS */ 566 e500_splset(ci, ipl); 567 #if 1 568 if (ipl < IPL_VM && old_ipl >= IPL_VM) 569 msr = PSL_EE; 570 #endif 571 wrtee(msr); 572 } 573 574 static int 575 e500_splraise(int ipl) 576 { 577 struct cpu_info * const ci = curcpu(); 578 const int old_ipl = ci->ci_cpl; 579 580 /* if we paniced because of watchdog, PSL_CE will be clear. */ 581 KASSERT(wdog_barked || (mfmsr() & PSL_CE)); 582 583 if (old_ipl < ipl) { 584 //const 585 register_t msr = wrtee(0); 586 e500_splset(ci, ipl); 587 #if 0 588 if (old_ipl < IPL_VM && ipl >= IPL_VM) 589 msr = 0; 590 #endif 591 wrtee(msr); 592 } else if (ipl == IPL_NONE) { 593 panic("%s: %p: cpl=%u: attempt to splraise(IPL_NONE)", 594 __func__, __builtin_return_address(0), old_ipl); 595 #if 0 596 } else if (old_ipl > ipl) { 597 printf("%s: %p: cpl=%u: ignoring splraise(%u) to lower ipl\n", 598 __func__, __builtin_return_address(0), old_ipl, ipl); 599 #endif 600 } 601 602 return old_ipl; 603 } 604 605 static int 606 e500_intr_spurious(void *arg) 607 { 608 return 0; 609 } 610 611 static bool 612 e500_intr_irq_info_get(struct cpu_info *ci, u_int irq, int ipl, int ist, 613 struct e500_intr_irq_info *ii) 614 { 615 const struct e500_intr_info * const info = &e500_intr_info; 616 bool ok; 617 618 #if DEBUG > 2 619 printf("%s(%p,irq=%u,ipl=%u,ist=%u,%p)\n", __func__, ci, irq, ipl, ist, ii); 620 #endif 621 622 if (ipl < IPL_VM || ipl > IPL_HIGH) { 623 #if DEBUG > 2 624 printf("%s:%d ipl=%u\n", __func__, __LINE__, ipl); 625 #endif 626 return false; 627 } 628 629 if (ist <= IST_NONE || ist >= IST_MAX) { 630 #if DEBUG > 2 631 printf("%s:%d ist=%u\n", __func__, __LINE__, ist); 632 #endif 633 return false; 634 } 635 636 ii->irq_vector = irq + info->ii_ist_vectors[ist]; 637 if (IST_PERCPU_P(ist) && ist != IST_IPI) 638 ii->irq_vector += ci->ci_cpuid * info->ii_percpu_sources; 639 640 switch (ist) { 641 default: 642 ii->irq_vpr = OPENPIC_EIVPR(irq); 643 ii->irq_dr = OPENPIC_EIDR(irq); 644 ok = irq < info->ii_external_sources 645 && (ist == IST_EDGE 646 || ist == IST_LEVEL_LOW 647 || ist == IST_LEVEL_HIGH); 648 break; 649 case IST_PULSE: 650 ok = false; 651 break; 652 case IST_ONCHIP: 653 ii->irq_vpr = OPENPIC_IIVPR(irq); 654 ii->irq_dr = OPENPIC_IIDR(irq); 655 ok = irq < 32 * __arraycount(info->ii_onchip_bitmap); 656 #if DEBUG > 2 657 printf("%s: irq=%u: ok=%u\n", __func__, irq, ok); 658 #endif 659 ok = ok && (info->ii_onchip_bitmap[irq/32] & (1 << (irq & 31))); 660 #if DEBUG > 2 661 printf("%s: %08x%08x -> %08x%08x: ok=%u\n", __func__, 662 irq < 32 ? 0 : (1 << irq), irq < 32 ? (1 << irq) : 0, 663 info->ii_onchip_bitmap[1], info->ii_onchip_bitmap[0], 664 ok); 665 #endif 666 break; 667 case IST_MSIGROUP: 668 ii->irq_vpr = OPENPIC_MSIVPR(irq); 669 ii->irq_dr = OPENPIC_MSIDR(irq); 670 ok = irq < info->ii_msigroup_sources 671 && ipl == IPL_VM; 672 break; 673 case IST_TIMER: 674 ii->irq_vpr = OPENPIC_GTVPR(ci->ci_cpuid, irq); 675 ii->irq_dr = OPENPIC_GTDR(ci->ci_cpuid, irq); 676 ok = irq < info->ii_timer_sources; 677 #if DEBUG > 2 678 printf("%s: IST_TIMER irq=%u: ok=%u\n", __func__, irq, ok); 679 #endif 680 break; 681 case IST_IPI: 682 ii->irq_vpr = OPENPIC_IPIVPR(irq); 683 ii->irq_dr = OPENPIC_IPIDR(irq); 684 ok = irq < info->ii_ipi_sources; 685 break; 686 case IST_MI: 687 ii->irq_vpr = OPENPIC_MIVPR(irq); 688 ii->irq_dr = OPENPIC_MIDR(irq); 689 ok = irq < info->ii_mi_sources; 690 break; 691 } 692 693 return ok; 694 } 695 696 static const char * 697 e500_intr_string(int irq, int ist, char *buf, size_t len) 698 { 699 struct cpu_info * const ci = curcpu(); 700 struct cpu_softc * const cpu = ci->ci_softc; 701 struct e500_intr_irq_info ii; 702 703 if (!e500_intr_irq_info_get(ci, irq, IPL_VM, ist, &ii)) 704 return NULL; 705 706 strlcpy(buf, cpu->cpu_evcnt_intrs[ii.irq_vector].ev_name, len); 707 return buf; 708 } 709 710 __CTASSERT(__arraycount(ist_names) == IST_MAX); 711 712 static const char * 713 e500_intr_typename(int ist) 714 { 715 if (IST_NONE <= ist && ist < IST_MAX) 716 return ist_names[ist]; 717 718 return NULL; 719 } 720 721 static void * 722 e500_intr_cpu_establish(struct cpu_info *ci, int irq, int ipl, int ist, 723 int (*handler)(void *), void *arg) 724 { 725 struct cpu_softc * const cpu = ci->ci_softc; 726 struct e500_intr_irq_info ii; 727 728 KASSERT(ipl >= IPL_VM && ipl <= IPL_HIGH); 729 KASSERT(ist > IST_NONE && ist < IST_MAX && ist != IST_MSI); 730 731 if (!e500_intr_irq_info_get(ci, irq, ipl, ist, &ii)) { 732 printf("%s: e500_intr_irq_info_get(%p,%u,%u,%u,%p) failed\n", 733 __func__, ci, irq, ipl, ist, &ii); 734 return NULL; 735 } 736 737 struct intr_source * const is = &e500_intr_sources[ii.irq_vector]; 738 mutex_enter(&e500_intr_lock); 739 if (is->is_ipl != IPL_NONE) { 740 mutex_exit(&e500_intr_lock); 741 return NULL; 742 } 743 744 is->is_func = handler; 745 is->is_arg = arg; 746 is->is_ipl = ipl; 747 is->is_ist = ist; 748 is->is_irq = irq; 749 is->is_vpr = ii.irq_vpr; 750 is->is_dr = ii.irq_dr; 751 752 uint32_t vpr = VPR_PRIORITY_MAKE(IPL2CTPR(ipl)) 753 | VPR_VECTOR_MAKE(((ii.irq_vector + 1) << 4) | ipl) 754 | (ist == IST_LEVEL_LOW 755 ? VPR_LEVEL_LOW 756 : (ist == IST_LEVEL_HIGH 757 ? VPR_LEVEL_HIGH 758 : (ist == IST_ONCHIP 759 ? VPR_P_HIGH 760 : 0))); 761 762 /* 763 * All interrupts go to the primary except per-cpu interrupts which get 764 * routed to the appropriate cpu. 765 */ 766 uint32_t dr = openpic_read(cpu, ii.irq_dr); 767 768 dr |= 1 << (IST_PERCPU_P(ist) ? ci->ci_cpuid : 0); 769 770 /* 771 * Update the vector/priority and destination registers keeping the 772 * interrupt masked. 773 */ 774 const register_t msr = wrtee(0); /* disable interrupts */ 775 openpic_write(cpu, ii.irq_vpr, vpr | VPR_MSK); 776 openpic_write(cpu, ii.irq_dr, dr); 777 778 /* 779 * Now unmask the interrupt. 780 */ 781 openpic_write(cpu, ii.irq_vpr, vpr); 782 783 wrtee(msr); /* re-enable interrupts */ 784 785 mutex_exit(&e500_intr_lock); 786 787 return is; 788 } 789 790 static void * 791 e500_intr_establish(int irq, int ipl, int ist, 792 int (*handler)(void *), void *arg) 793 { 794 return e500_intr_cpu_establish(curcpu(), irq, ipl, ist, handler, arg); 795 } 796 797 static void 798 e500_intr_disestablish(void *vis) 799 { 800 struct cpu_softc * const cpu = curcpu()->ci_softc; 801 struct intr_source * const is = vis; 802 struct e500_intr_irq_info ii; 803 804 KASSERT(e500_intr_sources <= is); 805 KASSERT(is < e500_intr_last_source); 806 KASSERT(!cpu_intr_p()); 807 808 bool ok = e500_intr_irq_info_get(curcpu(), is->is_irq, is->is_ipl, 809 is->is_ist, &ii); 810 (void)ok; /* appease gcc */ 811 KASSERT(ok); 812 KASSERT(is - e500_intr_sources == ii.irq_vector); 813 814 mutex_enter(&e500_intr_lock); 815 /* 816 * Mask the source using the mask (MSK) bit in the vector/priority reg. 817 */ 818 uint32_t vpr = openpic_read(cpu, ii.irq_vpr); 819 openpic_write(cpu, ii.irq_vpr, VPR_MSK | vpr); 820 821 /* 822 * Wait for the Activity (A) bit for the source to be cleared. 823 */ 824 while (openpic_read(cpu, ii.irq_vpr) & VPR_A) 825 ; 826 827 /* 828 * Now the source can be modified. 829 */ 830 openpic_write(cpu, ii.irq_dr, 0); /* stop delivery */ 831 openpic_write(cpu, ii.irq_vpr, VPR_MSK); /* mask/reset it */ 832 833 *is = (struct intr_source)INTR_SOURCE_INITIALIZER; 834 835 mutex_exit(&e500_intr_lock); 836 } 837 838 static void 839 e500_critintr(struct trapframe *tf) 840 { 841 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 842 } 843 844 static void 845 e500_decrintr(struct trapframe *tf) 846 { 847 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 848 } 849 850 static void 851 e500_fitintr(struct trapframe *tf) 852 { 853 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 854 } 855 856 static void 857 e500_wdogintr(struct trapframe *tf) 858 { 859 struct cpu_info * const ci = curcpu(); 860 mtspr(SPR_TSR, TSR_ENW|TSR_WIS); 861 wdog_barked = true; 862 dump_splhist(ci, NULL); 863 dump_trapframe(tf, NULL); 864 panic("%s: tf=%p tb=%"PRId64" srr0/srr1=%#lx/%#lx" 865 " cpl=%d idepth=%d, mtxcount=%d", 866 __func__, tf, mftb(), tf->tf_srr0, tf->tf_srr1, 867 ci->ci_cpl, ci->ci_idepth, ci->ci_mtx_count); 868 } 869 870 static void 871 e500_extintr(struct trapframe *tf) 872 { 873 struct cpu_info * const ci = curcpu(); 874 struct cpu_softc * const cpu = ci->ci_softc; 875 const int old_ipl = ci->ci_cpl; 876 877 /* if we paniced because of watchdog, PSL_CE will be clear. */ 878 KASSERT(wdog_barked || (mfmsr() & PSL_CE)); 879 880 #if 0 881 // printf("%s(%p): idepth=%d enter\n", __func__, tf, ci->ci_idepth); 882 if ((register_t)tf >= (register_t)curlwp->l_addr + USPACE 883 || (register_t)tf < (register_t)curlwp->l_addr + NBPG) { 884 printf("%s(entry): pid %d.%d (%s): srr0/srr1=%#lx/%#lx: invalid tf addr %p\n", 885 __func__, curlwp->l_proc->p_pid, curlwp->l_lid, 886 curlwp->l_proc->p_comm, tf->tf_srr0, tf->tf_srr1, tf); 887 } 888 #endif 889 890 891 ci->ci_data.cpu_nintr++; 892 tf->tf_cf.cf_idepth = ci->ci_idepth++; 893 cpu->cpu_pcpls[ci->ci_idepth] = old_ipl; 894 #if 1 895 if (mfmsr() & PSL_EE) 896 panic("%s(%p): MSR[EE] is on (%#lx)!", __func__, tf, mfmsr()); 897 if (old_ipl == IPL_HIGH 898 || IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 899 panic("%s(%p): old_ipl(%u) == IPL_HIGH(%u) " 900 "|| old_ipl + %u != OPENPIC_CTPR (%u)", 901 __func__, tf, old_ipl, IPL_HIGH, 902 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 903 #else 904 if (old_ipl >= IPL_VM) 905 panic("%s(%p): old_ipl(%u) >= IPL_VM(%u) CTPR=%u", 906 __func__, tf, old_ipl, IPL_VM, openpic_read(cpu, OPENPIC_CTPR)); 907 #endif 908 909 for (;;) { 910 /* 911 * Find out the pending interrupt. 912 */ 913 KASSERTMSG((mfmsr() & PSL_EE) == 0, 914 "%s(%p): MSR[EE] left on (%#lx)!", __func__, tf, mfmsr()); 915 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 916 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 917 __func__, tf, __LINE__, old_ipl, 918 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 919 const uint32_t iack = openpic_read(cpu, OPENPIC_IACK); 920 #ifdef DIAGNOSTIC 921 const int ipl = iack & 0xf; 922 #endif 923 const int irq = (iack >> 4) - 1; 924 #if 0 925 printf("%s: iack=%d ipl=%d irq=%d <%s>\n", 926 __func__, iack, ipl, irq, 927 (iack != IRQ_SPURIOUS ? 928 cpu->cpu_evcnt_intrs[irq].ev_name : "spurious")); 929 #endif 930 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 931 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 932 __func__, tf, __LINE__, old_ipl, 933 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 934 if (iack == IRQ_SPURIOUS) 935 break; 936 937 struct intr_source * const is = &e500_intr_sources[irq]; 938 if (__predict_true(is < e500_intr_last_source)) { 939 /* 940 * Timer interrupts get their argument overriden with 941 * the pointer to the trapframe. 942 */ 943 KASSERTMSG(is->is_ipl == ipl, 944 "iack %#x: is %p: irq %d ipl %d != iack ipl %d", 945 iack, is, irq, is->is_ipl, ipl); 946 void *arg = (is->is_ist == IST_TIMER ? tf : is->is_arg); 947 if (is->is_ipl <= old_ipl) 948 panic("%s(%p): %s (%u): is->is_ipl (%u) <= old_ipl (%u)\n", 949 __func__, tf, 950 cpu->cpu_evcnt_intrs[irq].ev_name, irq, 951 is->is_ipl, old_ipl); 952 KASSERT(is->is_ipl > old_ipl); 953 e500_splset(ci, is->is_ipl); /* change IPL */ 954 if (__predict_false(is->is_func == NULL)) { 955 aprint_error_dev(ci->ci_dev, 956 "interrupt from unestablished irq %d\n", 957 irq); 958 } else { 959 int (*func)(void *) = is->is_func; 960 wrtee(PSL_EE); 961 int rv = (*func)(arg); 962 wrtee(0); 963 #if DEBUG > 2 964 printf("%s: %s handler %p(%p) returned %d\n", 965 __func__, 966 cpu->cpu_evcnt_intrs[irq].ev_name, 967 func, arg, rv); 968 #endif 969 if (rv == 0) 970 cpu->cpu_evcnt_spurious_intr.ev_count++; 971 } 972 e500_splset(ci, old_ipl); /* restore IPL */ 973 cpu->cpu_evcnt_intrs[irq].ev_count++; 974 } else { 975 aprint_error_dev(ci->ci_dev, 976 "interrupt from illegal irq %d\n", irq); 977 cpu->cpu_evcnt_spurious_intr.ev_count++; 978 } 979 /* 980 * If this is a nested interrupt, simply ack it and exit 981 * because the loop we interrupted will complete looking 982 * for interrupts. 983 */ 984 KASSERTMSG((mfmsr() & PSL_EE) == 0, 985 "%s(%p): MSR[EE] left on (%#lx)!", __func__, tf, mfmsr()); 986 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 987 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 988 __func__, tf, __LINE__, old_ipl, 989 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 990 991 openpic_write(cpu, OPENPIC_EOI, 0); 992 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 993 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 994 __func__, tf, __LINE__, old_ipl, 995 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 996 if (ci->ci_idepth > 0) 997 break; 998 } 999 1000 ci->ci_idepth--; 1001 1002 #ifdef __HAVE_FAST_SOFTINTS 1003 /* 1004 * Before exiting, deal with any softints that need to be dealt with. 1005 */ 1006 const u_int softints = ci->ci_data.cpu_softints & (IPL_SOFTMASK << old_ipl); 1007 if (__predict_false(softints != 0)) { 1008 KASSERT(old_ipl < IPL_VM); 1009 e500_splset(ci, IPL_HIGH); /* pop to high */ 1010 wrtee(PSL_EE); /* reenable interrupts */ 1011 powerpc_softint(ci, old_ipl, /* deal with them */ 1012 tf->tf_srr0); 1013 wrtee(0); /* disable interrupts */ 1014 e500_splset(ci, old_ipl); /* and drop back */ 1015 } 1016 #endif /* __HAVE_FAST_SOFTINTS */ 1017 KASSERT(ci->ci_cpl == old_ipl); 1018 1019 /* 1020 * If we interrupted while power-saving and we need to exit idle, 1021 * we need to clear PSL_POW so we won't go back into power-saving. 1022 */ 1023 if (__predict_false(tf->tf_srr1 & PSL_POW) && ci->ci_want_resched) 1024 tf->tf_srr1 &= ~PSL_POW; 1025 1026 // printf("%s(%p): idepth=%d exit\n", __func__, tf, ci->ci_idepth); 1027 } 1028 1029 static void 1030 e500_intr_init(void) 1031 { 1032 struct cpu_info * const ci = curcpu(); 1033 struct cpu_softc * const cpu = ci->ci_softc; 1034 const uint32_t frr = openpic_read(cpu, OPENPIC_FRR); 1035 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1036 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1037 struct intr_source *is; 1038 struct e500_intr_info * const ii = &e500_intr_info; 1039 1040 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 1041 switch (svr) { 1042 #ifdef MPC8536 1043 case SVR_MPC8536v1 >> 16: 1044 *ii = mpc8536_intr_info; 1045 break; 1046 #endif 1047 #ifdef MPC8544 1048 case SVR_MPC8544v1 >> 16: 1049 *ii = mpc8544_intr_info; 1050 break; 1051 #endif 1052 #ifdef MPC8548 1053 case SVR_MPC8543v1 >> 16: 1054 case SVR_MPC8548v1 >> 16: 1055 *ii = mpc8548_intr_info; 1056 break; 1057 #endif 1058 #ifdef MPC8555 1059 case SVR_MPC8541v1 >> 16: 1060 case SVR_MPC8555v1 >> 16: 1061 *ii = mpc8555_intr_info; 1062 break; 1063 #endif 1064 #ifdef MPC8568 1065 case SVR_MPC8568v1 >> 16: 1066 *ii = mpc8568_intr_info; 1067 break; 1068 #endif 1069 #ifdef MPC8572 1070 case SVR_MPC8572v1 >> 16: 1071 *ii = mpc8572_intr_info; 1072 break; 1073 #endif 1074 #ifdef P1023 1075 case SVR_P1017v1 >> 16: 1076 case SVR_P1023v1 >> 16: 1077 *ii = p1023_intr_info; 1078 break; 1079 #endif 1080 #ifdef P1025 1081 case SVR_P1016v1 >> 16: 1082 case SVR_P1025v1 >> 16: 1083 *ii = p1025_intr_info; 1084 break; 1085 #endif 1086 #ifdef P2020 1087 case SVR_P2010v2 >> 16: 1088 case SVR_P2020v2 >> 16: 1089 *ii = p20x0_intr_info; 1090 break; 1091 #endif 1092 default: 1093 panic("%s: don't know how to deal with SVR %#lx", 1094 __func__, mfspr(SPR_SVR)); 1095 } 1096 1097 /* 1098 * We need to be in mixed mode. 1099 */ 1100 openpic_write(cpu, OPENPIC_GCR, GCR_M); 1101 1102 /* 1103 * Make we and the openpic both agree about the current SPL level. 1104 */ 1105 e500_splset(ci, ci->ci_cpl); 1106 1107 /* 1108 * Allow the required number of interrupt sources. 1109 */ 1110 is = kmem_zalloc(nirq * sizeof(*is), KM_SLEEP); 1111 KASSERT(is); 1112 e500_intr_sources = is; 1113 e500_intr_last_source = is + nirq; 1114 1115 /* 1116 * Initialize all the external interrupts as active low. 1117 */ 1118 for (u_int irq = 0; irq < e500_intr_info.ii_external_sources; irq++) { 1119 openpic_write(cpu, OPENPIC_EIVPR(irq), 1120 VPR_VECTOR_MAKE(irq) | VPR_LEVEL_LOW); 1121 } 1122 } 1123 1124 static void 1125 e500_idlespin(void) 1126 { 1127 KASSERTMSG(curcpu()->ci_cpl == IPL_NONE, 1128 "%s: cpu%u: ci_cpl (%d) != 0", __func__, cpu_number(), 1129 curcpu()->ci_cpl); 1130 KASSERTMSG(CTPR2IPL(openpic_read(curcpu()->ci_softc, OPENPIC_CTPR)) == IPL_NONE, 1131 "%s: cpu%u: CTPR (%d) != IPL_NONE", __func__, cpu_number(), 1132 CTPR2IPL(openpic_read(curcpu()->ci_softc, OPENPIC_CTPR))); 1133 KASSERT(mfmsr() & PSL_EE); 1134 1135 if (powersave > 0) 1136 mtmsr(mfmsr() | PSL_POW); 1137 } 1138 1139 static void 1140 e500_intr_cpu_attach(struct cpu_info *ci) 1141 { 1142 struct cpu_softc * const cpu = ci->ci_softc; 1143 const char * const xname = device_xname(ci->ci_dev); 1144 1145 const u_int32_t frr = openpic_read(cpu, OPENPIC_FRR); 1146 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1147 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1148 1149 const struct e500_intr_info * const info = &e500_intr_info; 1150 1151 cpu->cpu_clock_gtbcr = OPENPIC_GTBCR(ci->ci_cpuid, E500_CLOCK_TIMER); 1152 1153 cpu->cpu_evcnt_intrs = 1154 kmem_zalloc(nirq * sizeof(cpu->cpu_evcnt_intrs[0]), KM_SLEEP); 1155 KASSERT(cpu->cpu_evcnt_intrs); 1156 1157 struct evcnt *evcnt = cpu->cpu_evcnt_intrs; 1158 for (size_t j = 0; j < info->ii_external_sources; j++, evcnt++) { 1159 const char *name = e500_intr_external_name_lookup(j); 1160 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, NULL, xname, name); 1161 } 1162 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_ONCHIP]); 1163 for (size_t j = 0; j < info->ii_onchip_sources; j++, evcnt++) { 1164 if (info->ii_onchip_bitmap[j / 32] & __BIT(j & 31)) { 1165 const char *name = e500_intr_onchip_name_lookup(j); 1166 if (name != NULL) { 1167 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1168 NULL, xname, name); 1169 #ifdef DIAGNOSTIC 1170 } else { 1171 printf("%s: missing evcnt for onchip irq %zu\n", 1172 __func__, j); 1173 #endif 1174 } 1175 } 1176 } 1177 1178 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_MSIGROUP]); 1179 for (size_t j = 0; j < info->ii_msigroup_sources; j++, evcnt++) { 1180 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1181 NULL, xname, e500_msigroup_intr_names[j].in_name); 1182 } 1183 1184 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_TIMER]); 1185 evcnt += ci->ci_cpuid * info->ii_percpu_sources; 1186 for (size_t j = 0; j < info->ii_timer_sources; j++, evcnt++) { 1187 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1188 NULL, xname, e500_timer_intr_names[j].in_name); 1189 } 1190 1191 for (size_t j = 0; j < info->ii_ipi_sources; j++, evcnt++) { 1192 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1193 NULL, xname, e500_ipi_intr_names[j].in_name); 1194 } 1195 1196 for (size_t j = 0; j < info->ii_mi_sources; j++, evcnt++) { 1197 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1198 NULL, xname, e500_mi_intr_names[j].in_name); 1199 } 1200 1201 ci->ci_idlespin = e500_idlespin; 1202 } 1203 1204 static void 1205 e500_intr_cpu_send_ipi(cpuid_t target, uint32_t ipimsg) 1206 { 1207 struct cpu_info * const ci = curcpu(); 1208 struct cpu_softc * const cpu = ci->ci_softc; 1209 uint32_t dstmask; 1210 1211 if (target >= CPU_MAXNUM) { 1212 CPU_INFO_ITERATOR cii; 1213 struct cpu_info *dst_ci; 1214 1215 KASSERT(target == IPI_DST_NOTME || target == IPI_DST_ALL); 1216 1217 dstmask = 0; 1218 for (CPU_INFO_FOREACH(cii, dst_ci)) { 1219 if (target == IPI_DST_ALL || ci != dst_ci) { 1220 dstmask |= 1 << cpu_index(ci); 1221 if (ipimsg) 1222 atomic_or_32(&dst_ci->ci_pending_ipis, 1223 ipimsg); 1224 } 1225 } 1226 } else { 1227 struct cpu_info * const dst_ci = cpu_lookup(target); 1228 KASSERT(dst_ci != NULL); 1229 KASSERTMSG(target == cpu_index(dst_ci), 1230 "%s: target (%lu) != cpu_index(cpu%u)", 1231 __func__, target, cpu_index(dst_ci)); 1232 dstmask = (1 << target); 1233 if (ipimsg) 1234 atomic_or_32(&dst_ci->ci_pending_ipis, ipimsg); 1235 } 1236 1237 openpic_write(cpu, OPENPIC_IPIDR(0), dstmask); 1238 } 1239 1240 typedef void (*ipifunc_t)(void); 1241 1242 #ifdef __HAVE_PREEEMPTION 1243 static void 1244 e500_ipi_kpreempt(void) 1245 { 1246 poowerpc_softint_trigger(1 << IPL_NONE); 1247 } 1248 #endif 1249 1250 static const ipifunc_t e500_ipifuncs[] = { 1251 [ilog2(IPI_XCALL)] = xc_ipi_handler, 1252 [ilog2(IPI_GENERIC)] = ipi_cpu_handler, 1253 [ilog2(IPI_HALT)] = e500_ipi_halt, 1254 #ifdef __HAVE_PREEMPTION 1255 [ilog2(IPI_KPREEMPT)] = e500_ipi_kpreempt, 1256 #endif 1257 [ilog2(IPI_TLB1SYNC)] = e500_tlb1_sync, 1258 }; 1259 1260 static int 1261 e500_ipi_intr(void *v) 1262 { 1263 struct cpu_info * const ci = curcpu(); 1264 1265 ci->ci_ev_ipi.ev_count++; 1266 1267 uint32_t pending_ipis = atomic_swap_32(&ci->ci_pending_ipis, 0); 1268 for (u_int ipi = 31; pending_ipis != 0; ipi--, pending_ipis <<= 1) { 1269 const u_int bits = __builtin_clz(pending_ipis); 1270 ipi -= bits; 1271 pending_ipis <<= bits; 1272 KASSERT(e500_ipifuncs[ipi] != NULL); 1273 (*e500_ipifuncs[ipi])(); 1274 } 1275 1276 return 1; 1277 } 1278 1279 static void 1280 e500_intr_cpu_hatch(struct cpu_info *ci) 1281 { 1282 /* 1283 * Establish clock interrupt for this CPU. 1284 */ 1285 if (e500_intr_cpu_establish(ci, E500_CLOCK_TIMER, IPL_CLOCK, IST_TIMER, 1286 e500_clock_intr, NULL) == NULL) 1287 panic("%s: failed to establish clock interrupt!", __func__); 1288 1289 /* 1290 * Establish the IPI interrupts for this CPU. 1291 */ 1292 if (e500_intr_cpu_establish(ci, 0, IPL_VM, IST_IPI, e500_ipi_intr, 1293 NULL) == NULL) 1294 panic("%s: failed to establish ipi interrupt!", __func__); 1295 1296 /* 1297 * Enable watchdog interrupts. 1298 */ 1299 uint32_t tcr = mfspr(SPR_TCR); 1300 tcr |= TCR_WIE; 1301 mtspr(SPR_TCR, tcr); 1302 } 1303
Indexes created Mon Sep 29 21:09:56 GMT 2025