e500_intr.c revision 1.6
1 /* $NetBSD: e500_intr.c,v 1.6 2011/05/17 17:42:46 dyoung Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_mpc85xx.h" 38 39 #define __INTR_PRIVATE 40 41 #include <sys/param.h> 42 #include <sys/proc.h> 43 #include <sys/intr.h> 44 #include <sys/cpu.h> 45 #include <sys/kmem.h> 46 #include <sys/atomic.h> 47 #include <sys/bus.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/spr.h> 52 #include <powerpc/booke/spr.h> 53 54 #include <powerpc/booke/cpuvar.h> 55 #include <powerpc/booke/e500reg.h> 56 #include <powerpc/booke/e500var.h> 57 #include <powerpc/booke/openpicreg.h> 58 59 #define IPL2CTPR(ipl) ((ipl) + 15 - IPL_HIGH) 60 #define CTPR2IPL(ctpr) ((ctpr) - (15 - IPL_HIGH)) 61 62 #define IST_PERCPU_P(ist) ((ist) >= IST_TIMER) 63 64 #define IPL_SOFTMASK \ 65 ((1 << IPL_SOFTSERIAL) | (1 << IPL_SOFTNET ) \ 66 |(1 << IPL_SOFTBIO ) | (1 << IPL_SOFTCLOCK )) 67 68 #define SOFTINT2IPL_MAP \ 69 ((IPL_SOFTSERIAL << (4*SOFTINT_SERIAL)) \ 70 |(IPL_SOFTNET << (4*SOFTINT_NET )) \ 71 |(IPL_SOFTBIO << (4*SOFTINT_BIO )) \ 72 |(IPL_SOFTCLOCK << (4*SOFTINT_CLOCK ))) 73 #define SOFTINT2IPL(si_level) ((SOFTINT2IPL_MAP >> (4 * si_level)) & 0x0f) 74 75 struct e500_intr_irq_info { 76 bus_addr_t irq_vpr; 77 bus_addr_t irq_dr; 78 u_int irq_vector; 79 }; 80 81 struct intr_source { 82 int (*is_func)(void *); 83 void *is_arg; 84 int8_t is_ipl; 85 uint8_t is_ist; 86 uint8_t is_irq; 87 bus_size_t is_vpr; 88 bus_size_t is_dr; 89 }; 90 91 #define INTR_SOURCE_INITIALIZER \ 92 { .is_func = e500_intr_spurious, .is_arg = NULL, \ 93 .is_irq = -1, .is_ipl = IPL_NONE, .is_ist = IST_NONE, } 94 95 struct e500_intr_name { 96 uint8_t in_irq; 97 const char in_name[15]; 98 }; 99 100 static const struct e500_intr_name e500_onchip_intr_names[] = { 101 { ISOURCE_L2, "l2" }, 102 { ISOURCE_ECM, "ecm" }, 103 { ISOURCE_DDR, "ddr" }, 104 { ISOURCE_LBC, "lbc" }, 105 { ISOURCE_DMA_CHAN1, "dma-chan1" }, 106 { ISOURCE_DMA_CHAN2, "dma-chan2" }, 107 { ISOURCE_DMA_CHAN3, "dma-chan3" }, 108 { ISOURCE_DMA_CHAN4, "dma-chan4" }, 109 { ISOURCE_PCI1, "pci1" }, 110 { ISOURCE_PCIEX2, "pcie2" }, 111 { ISOURCE_PCIEX , "pcie1" }, 112 { ISOURCE_PCIEX3, "pcie3" }, 113 { ISOURCE_USB1, "usb1" }, 114 { ISOURCE_ETSEC1_TX, "etsec1-tx" }, 115 { ISOURCE_ETSEC1_RX, "etsec1-rx" }, 116 { ISOURCE_ETSEC3_TX, "etsec3-tx" }, 117 { ISOURCE_ETSEC3_RX, "etsec3-rx" }, 118 { ISOURCE_ETSEC3_ERR, "etsec3-err" }, 119 { ISOURCE_ETSEC1_ERR, "etsec1-err" }, 120 { ISOURCE_ETSEC2_TX, "etsec2-tx" }, 121 { ISOURCE_ETSEC2_RX, "etsec2-rx" }, 122 { ISOURCE_ETSEC4_TX, "etsec4-tx" }, 123 { ISOURCE_ETSEC4_RX, "etsec4-rx" }, 124 { ISOURCE_ETSEC4_ERR, "etsec4-err" }, 125 { ISOURCE_ETSEC2_ERR, "etsec2-err" }, 126 { ISOURCE_DUART, "duart" }, 127 { ISOURCE_I2C, "i2c" }, 128 { ISOURCE_PERFMON, "perfmon" }, 129 { ISOURCE_SECURITY1, "sec1" }, 130 { ISOURCE_GPIO, "gpio" }, 131 { ISOURCE_SRIO_EWPU, "srio-ewpu" }, 132 { ISOURCE_SRIO_ODBELL, "srio-odbell" }, 133 { ISOURCE_SRIO_IDBELL, "srio-idbell" }, 134 { ISOURCE_SRIO_OMU1, "srio-omu1" }, 135 { ISOURCE_SRIO_IMU1, "srio-imu1" }, 136 { ISOURCE_SRIO_OMU2, "srio-omu2" }, 137 { ISOURCE_SECURITY2, "sec2" }, 138 { ISOURCE_SPI, "spi" }, 139 { ISOURCE_ETSEC1_PTP, "etsec1-ptp" }, 140 { ISOURCE_ETSEC2_PTP, "etsec2-ptp" }, 141 { ISOURCE_ETSEC3_PTP, "etsec3-ptp" }, 142 { ISOURCE_ETSEC4_PTP, "etsec4-ptp" }, 143 { ISOURCE_ESDHC, "esdhc" }, 144 { 0, "" }, 145 }; 146 147 const struct e500_intr_name default_external_intr_names[] = { 148 { 0, "" }, 149 }; 150 151 static const struct e500_intr_name e500_msigroup_intr_names[] = { 152 { 0, "msigroup0" }, 153 { 1, "msigroup1" }, 154 { 2, "msigroup2" }, 155 { 3, "msigroup3" }, 156 { 4, "msigroup4" }, 157 { 5, "msigroup5" }, 158 { 6, "msigroup6" }, 159 { 7, "msigroup7" }, 160 { 0, "" }, 161 }; 162 163 static const struct e500_intr_name e500_timer_intr_names[] = { 164 { 0, "timer0" }, 165 { 1, "timer1" }, 166 { 2, "timer2" }, 167 { 3, "timer3" }, 168 { 0, "" }, 169 }; 170 171 static const struct e500_intr_name e500_ipi_intr_names[] = { 172 { 0, "ipi0" }, 173 { 1, "ipi1" }, 174 { 2, "ipi2" }, 175 { 3, "ipi3" }, 176 { 0, "" }, 177 }; 178 179 static const struct e500_intr_name e500_mi_intr_names[] = { 180 { 0, "mi0" }, 181 { 1, "mi1" }, 182 { 2, "mi2" }, 183 { 3, "mi3" }, 184 { 0, "" }, 185 }; 186 187 struct e500_intr_info { 188 u_int ii_external_sources; 189 uint32_t ii_onchip_bitmap[2]; 190 u_int ii_onchip_sources; 191 u_int ii_msigroup_sources; 192 u_int ii_ipi_sources; /* per-cpu */ 193 u_int ii_timer_sources; /* per-cpu */ 194 u_int ii_mi_sources; /* per-cpu */ 195 u_int ii_percpu_sources; 196 const struct e500_intr_name *ii_external_intr_names; 197 const struct e500_intr_name *ii_onchip_intr_names; 198 u_int8_t ii_ist_vectors[IST_MAX+1]; 199 }; 200 201 static kmutex_t e500_intr_lock __cacheline_aligned; 202 static struct e500_intr_info e500_intr_info; 203 204 #define INTR_INFO_DECL(lc_chip, UC_CHIP) \ 205 static const struct e500_intr_info lc_chip##_intr_info = { \ 206 .ii_external_sources = UC_CHIP ## _EXTERNALSOURCES, \ 207 .ii_onchip_bitmap = UC_CHIP ## _ONCHIPBITMAP, \ 208 .ii_onchip_sources = UC_CHIP ## _ONCHIPSOURCES, \ 209 .ii_msigroup_sources = UC_CHIP ## _MSIGROUPSOURCES, \ 210 .ii_timer_sources = UC_CHIP ## _TIMERSOURCES, \ 211 .ii_ipi_sources = UC_CHIP ## _IPISOURCES, \ 212 .ii_mi_sources = UC_CHIP ## _MISOURCES, \ 213 .ii_percpu_sources = UC_CHIP ## _TIMERSOURCES \ 214 + UC_CHIP ## _IPISOURCES + UC_CHIP ## _MISOURCES, \ 215 .ii_external_intr_names = lc_chip ## _external_intr_names, \ 216 .ii_onchip_intr_names = lc_chip ## _onchip_intr_names, \ 217 .ii_ist_vectors = { \ 218 [IST_NONE] = ~0, \ 219 [IST_EDGE] = 0, \ 220 [IST_LEVEL_LOW] = 0, \ 221 [IST_LEVEL_HIGH] = 0, \ 222 [IST_ONCHIP] = UC_CHIP ## _EXTERNALSOURCES, \ 223 [IST_MSIGROUP] = UC_CHIP ## _EXTERNALSOURCES \ 224 + UC_CHIP ## _ONCHIPSOURCES, \ 225 [IST_TIMER] = UC_CHIP ## _EXTERNALSOURCES \ 226 + UC_CHIP ## _ONCHIPSOURCES \ 227 + UC_CHIP ## _MSIGROUPSOURCES, \ 228 [IST_IPI] = UC_CHIP ## _EXTERNALSOURCES \ 229 + UC_CHIP ## _ONCHIPSOURCES \ 230 + UC_CHIP ## _MSIGROUPSOURCES \ 231 + UC_CHIP ## _TIMERSOURCES, \ 232 [IST_MI] = UC_CHIP ## _EXTERNALSOURCES \ 233 + UC_CHIP ## _ONCHIPSOURCES \ 234 + UC_CHIP ## _MSIGROUPSOURCES \ 235 + UC_CHIP ## _TIMERSOURCES \ 236 + UC_CHIP ## _IPISOURCES, \ 237 [IST_MAX] = UC_CHIP ## _EXTERNALSOURCES \ 238 + UC_CHIP ## _ONCHIPSOURCES \ 239 + UC_CHIP ## _MSIGROUPSOURCES \ 240 + UC_CHIP ## _TIMERSOURCES \ 241 + UC_CHIP ## _IPISOURCES \ 242 + UC_CHIP ## _MISOURCES, \ 243 }, \ 244 } 245 246 #ifdef MPC8536 247 #define mpc8536_external_intr_names default_external_intr_names 248 const struct e500_intr_name mpc8536_onchip_intr_names[] = { 249 { ISOURCE_SATA2, "sata2" }, 250 { ISOURCE_USB2, "usb2" }, 251 { ISOURCE_USB3, "usb3" }, 252 { ISOURCE_SATA1, "sata1" }, 253 { 0, "" }, 254 }; 255 256 INTR_INFO_DECL(mpc8536, MPC8536); 257 #endif 258 259 #ifdef MPC8544 260 #define mpc8544_external_intr_names default_external_intr_names 261 const struct e500_intr_name mpc8544_onchip_intr_names[] = { 262 { 0, "" }, 263 }; 264 265 INTR_INFO_DECL(mpc8544, MPC8544); 266 #endif 267 #ifdef MPC8548 268 #define mpc8548_external_intr_names default_external_intr_names 269 const struct e500_intr_name mpc8548_onchip_intr_names[] = { 270 { ISOURCE_PCI1, "pci1" }, 271 { ISOURCE_PCI2, "pci2" }, 272 { 0, "" }, 273 }; 274 275 INTR_INFO_DECL(mpc8548, MPC8548); 276 #endif 277 #ifdef MPC8555 278 #define mpc8555_external_intr_names default_external_intr_names 279 const struct e500_intr_name mpc8555_onchip_intr_names[] = { 280 { ISOURCE_PCI2, "pci2" }, 281 { ISOURCE_CPM, "CPM" }, 282 { 0, "" }, 283 }; 284 285 INTR_INFO_DECL(mpc8555, MPC8555); 286 #endif 287 #ifdef MPC8568 288 #define mpc8568_external_intr_names default_external_intr_names 289 const struct e500_intr_name mpc8568_onchip_intr_names[] = { 290 { ISOURCE_QEB_LOW, "QEB low" }, 291 { ISOURCE_QEB_PORT, "QEB port" }, 292 { ISOURCE_QEB_IECC, "QEB iram ecc" }, 293 { ISOURCE_QEB_MUECC, "QEB ram ecc" }, 294 { ISOURCE_TLU1, "tlu1" }, 295 { ISOURCE_QEB_HIGH, "QEB high" }, 296 { 0, "" }, 297 }; 298 299 INTR_INFO_DECL(mpc8568, MPC8568); 300 #endif 301 #ifdef MPC8572 302 #define mpc8572_external_intr_names default_external_intr_names 303 const struct e500_intr_name mpc8572_onchip_intr_names[] = { 304 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 305 { ISOURCE_FEC, "fec" }, 306 { ISOURCE_PME_GENERAL, "pme" }, 307 { ISOURCE_TLU1, "tlu1" }, 308 { ISOURCE_TLU2, "tlu2" }, 309 { ISOURCE_PME_CHAN1, "pme-chan1" }, 310 { ISOURCE_PME_CHAN2, "pme-chan2" }, 311 { ISOURCE_PME_CHAN3, "pme-chan3" }, 312 { ISOURCE_PME_CHAN4, "pme-chan4" }, 313 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 314 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 315 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 316 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 317 { 0, "" }, 318 }; 319 320 INTR_INFO_DECL(mpc8572, MPC8572); 321 #endif 322 #ifdef P2020 323 #define p20x0_external_intr_names default_external_intr_names 324 const struct e500_intr_name p20x0_onchip_intr_names[] = { 325 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 326 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 327 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 328 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 329 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 330 { 0, "" }, 331 }; 332 333 INTR_INFO_DECL(p20x0, P20x0); 334 #endif 335 336 static const char ist_names[][12] = { 337 [IST_NONE] = "none", 338 [IST_EDGE] = "edge", 339 [IST_LEVEL_LOW] = "level-", 340 [IST_LEVEL_HIGH] = "level+", 341 [IST_MSI] = "msi", 342 [IST_ONCHIP] = "onchip", 343 [IST_MSIGROUP] = "msigroup", 344 [IST_TIMER] = "timer", 345 [IST_IPI] = "ipi", 346 [IST_MI] = "msgint", 347 }; 348 349 static struct intr_source *e500_intr_sources; 350 static const struct intr_source *e500_intr_last_source; 351 352 static void *e500_intr_establish(int, int, int, int (*)(void *), void *); 353 static void e500_intr_disestablish(void *); 354 static void e500_intr_cpu_init(struct cpu_info *ci); 355 static void e500_intr_init(void); 356 static const char *e500_intr_string(int, int); 357 static void e500_critintr(struct trapframe *tf); 358 static void e500_decrintr(struct trapframe *tf); 359 static void e500_extintr(struct trapframe *tf); 360 static void e500_fitintr(struct trapframe *tf); 361 static void e500_wdogintr(struct trapframe *tf); 362 static void e500_spl0(void); 363 static int e500_splraise(int); 364 static void e500_splx(int); 365 #ifdef __HAVE_FAST_SOFTINTS 366 static void e500_softint_init_md(lwp_t *l, u_int si_level, uintptr_t *machdep_p); 367 static void e500_softint_trigger(uintptr_t machdep); 368 #endif 369 370 const struct intrsw e500_intrsw = { 371 .intrsw_establish = e500_intr_establish, 372 .intrsw_disestablish = e500_intr_disestablish, 373 .intrsw_init = e500_intr_init, 374 .intrsw_cpu_init = e500_intr_cpu_init, 375 .intrsw_string = e500_intr_string, 376 377 .intrsw_critintr = e500_critintr, 378 .intrsw_decrintr = e500_decrintr, 379 .intrsw_extintr = e500_extintr, 380 .intrsw_fitintr = e500_fitintr, 381 .intrsw_wdogintr = e500_wdogintr, 382 383 .intrsw_splraise = e500_splraise, 384 .intrsw_splx = e500_splx, 385 .intrsw_spl0 = e500_spl0, 386 387 #ifdef __HAVE_FAST_SOFTINTS 388 .intrsw_softint_init_md = e500_softint_init_md, 389 .intrsw_softint_trigger = e500_softint_trigger, 390 #endif 391 }; 392 393 static inline uint32_t 394 openpic_read(struct cpu_softc *cpu, bus_size_t offset) 395 { 396 397 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, 398 OPENPIC_BASE + offset); 399 } 400 401 static inline void 402 openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val) 403 { 404 405 return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, 406 OPENPIC_BASE + offset, val); 407 } 408 409 static const char * 410 e500_intr_external_name_lookup(int irq) 411 { 412 prop_array_t extirqs = board_info_get_object("external-irqs"); 413 prop_string_t irqname = prop_array_get(extirqs, irq); 414 KASSERT(irqname != NULL); 415 KASSERT(prop_object_type(irqname) == PROP_TYPE_STRING); 416 417 return prop_string_cstring_nocopy(irqname); 418 } 419 420 static const char * 421 e500_intr_name_lookup(const struct e500_intr_name *names, int irq) 422 { 423 for (; names->in_name[0] != '\0'; names++) { 424 if (names->in_irq == irq) 425 return names->in_name; 426 } 427 428 return NULL; 429 } 430 431 static const char * 432 e500_intr_onchip_name_lookup(int irq) 433 { 434 const char *name; 435 436 name = e500_intr_name_lookup(e500_intr_info.ii_onchip_intr_names, irq); 437 if (name == NULL) 438 name = e500_intr_name_lookup(e500_onchip_intr_names, irq); 439 440 return name; 441 } 442 443 #ifdef __HAVE_FAST_SOFTINTS 444 static inline void 445 e500_softint_deliver(struct cpu_info *ci, struct cpu_softc *cpu, 446 int ipl, int si_level) 447 { 448 KASSERT(ci->ci_data.cpu_softints & (1 << ipl)); 449 ci->ci_data.cpu_softints ^= 1 << ipl; 450 softint_fast_dispatch(cpu->cpu_softlwps[si_level], ipl); 451 KASSERT(cpu->cpu_softlwps[si_level]->l_ctxswtch == 0); 452 KASSERTMSG(ci->ci_cpl == IPL_HIGH, 453 ("%s: cpl (%d) != HIGH", __func__, ci->ci_cpl)); 454 } 455 456 static inline void 457 e500_softint(struct cpu_info *ci, struct cpu_softc *cpu, int old_ipl) 458 { 459 const u_int softint_mask = (IPL_SOFTMASK << old_ipl) & IPL_SOFTMASK; 460 u_int softints; 461 462 KASSERT(ci->ci_mtx_count == 0); 463 KASSERT(ci->ci_cpl == IPL_HIGH); 464 while ((softints = (ci->ci_data.cpu_softints & softint_mask)) != 0) { 465 KASSERT(old_ipl < IPL_SOFTSERIAL); 466 if (softints & (1 << IPL_SOFTSERIAL)) { 467 e500_softint_deliver(ci, cpu, IPL_SOFTSERIAL, 468 SOFTINT_SERIAL); 469 continue; 470 } 471 KASSERT(old_ipl < IPL_SOFTNET); 472 if (softints & (1 << IPL_SOFTNET)) { 473 e500_softint_deliver(ci, cpu, IPL_SOFTNET, 474 SOFTINT_NET); 475 continue; 476 } 477 KASSERT(old_ipl < IPL_SOFTBIO); 478 if (softints & (1 << IPL_SOFTBIO)) { 479 e500_softint_deliver(ci, cpu, IPL_SOFTBIO, 480 SOFTINT_BIO); 481 continue; 482 } 483 KASSERT(old_ipl < IPL_SOFTCLOCK); 484 if (softints & (1 << IPL_SOFTCLOCK)) { 485 e500_softint_deliver(ci, cpu, IPL_SOFTCLOCK, 486 SOFTINT_CLOCK); 487 continue; 488 } 489 } 490 } 491 #endif /* __HAVE_FAST_SOFTINTS */ 492 493 static inline void 494 e500_splset(struct cpu_info *ci, int ipl) 495 { 496 struct cpu_softc * const cpu = ci->ci_softc; 497 //KASSERT(!cpu_intr_p() || ipl >= IPL_VM); 498 KASSERT((curlwp->l_pflag & LP_INTR) == 0 || ipl != IPL_NONE); 499 #if 0 500 u_int ctpr = ipl; 501 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ci->ci_cpl); 502 #elif 0 503 u_int old_ctpr = (ci->ci_cpl >= IPL_VM ? 15 : ci->ci_cpl); 504 u_int ctpr = (ipl >= IPL_VM ? 15 : ipl); 505 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == old_ctpr); 506 #else 507 #ifdef DIAGNOSTIC 508 u_int old_ctpr = IPL2CTPR(ci->ci_cpl); 509 #endif 510 u_int ctpr = IPL2CTPR(ipl); 511 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == old_ctpr); 512 #endif 513 openpic_write(cpu, OPENPIC_CTPR, ctpr); 514 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ctpr); 515 ci->ci_cpl = ipl; 516 } 517 518 static void 519 e500_spl0(void) 520 { 521 struct cpu_info * const ci = curcpu(); 522 523 wrtee(0); 524 525 #ifdef __HAVE_FAST_SOFTINTS 526 if (__predict_false(ci->ci_data.cpu_softints != 0)) { 527 e500_splset(ci, IPL_HIGH); 528 e500_softint(ci, ci->ci_softc, IPL_NONE); 529 } 530 #endif /* __HAVE_FAST_SOFTINTS */ 531 e500_splset(ci, IPL_NONE); 532 533 wrtee(PSL_EE); 534 } 535 536 static void 537 e500_splx(int ipl) 538 { 539 struct cpu_info * const ci = curcpu(); 540 const int old_ipl = ci->ci_cpl; 541 542 KASSERT(mfmsr() & PSL_CE); 543 544 if (ipl == old_ipl) 545 return; 546 547 if (__predict_false(ipl > old_ipl)) { 548 printf("%s: %p: cpl=%u: ignoring splx(%u) to raise ipl\n", 549 __func__, __builtin_return_address(0), old_ipl, ipl); 550 if (old_ipl == IPL_NONE) 551 Debugger(); 552 } 553 554 // const 555 register_t msr = wrtee(0); 556 #ifdef __HAVE_FAST_SOFTINTS 557 const u_int softints = (ci->ci_data.cpu_softints << ipl) & IPL_SOFTMASK; 558 if (__predict_false(softints != 0)) { 559 e500_splset(ci, IPL_HIGH); 560 e500_softint(ci, ci->ci_softc, ipl); 561 } 562 #endif /* __HAVE_FAST_SOFTINTS */ 563 e500_splset(ci, ipl); 564 #if 1 565 if (ipl < IPL_VM && old_ipl >= IPL_VM) 566 msr = PSL_EE; 567 #endif 568 wrtee(msr); 569 } 570 571 static int 572 e500_splraise(int ipl) 573 { 574 struct cpu_info * const ci = curcpu(); 575 const int old_ipl = ci->ci_cpl; 576 577 KASSERT(mfmsr() & PSL_CE); 578 579 if (old_ipl < ipl) { 580 //const 581 register_t msr = wrtee(0); 582 e500_splset(ci, ipl); 583 #if 1 584 if (old_ipl < IPL_VM && ipl >= IPL_VM) 585 msr = 0; 586 #endif 587 wrtee(msr); 588 } else if (ipl == IPL_NONE) { 589 panic("%s: %p: cpl=%u: attempt to splraise(IPL_NONE)", 590 __func__, __builtin_return_address(0), old_ipl); 591 #if 0 592 } else if (old_ipl > ipl) { 593 printf("%s: %p: cpl=%u: ignoring splraise(%u) to lower ipl\n", 594 __func__, __builtin_return_address(0), old_ipl, ipl); 595 #endif 596 } 597 598 return old_ipl; 599 } 600 601 #ifdef __HAVE_FAST_SOFTINTS 602 static void 603 e500_softint_init_md(lwp_t *l, u_int si_level, uintptr_t *machdep_p) 604 { 605 struct cpu_info * const ci = l->l_cpu; 606 struct cpu_softc * const cpu = ci->ci_softc; 607 608 *machdep_p = 1 << SOFTINT2IPL(si_level); 609 KASSERT(*machdep_p & IPL_SOFTMASK); 610 cpu->cpu_softlwps[si_level] = l; 611 } 612 613 static void 614 e500_softint_trigger(uintptr_t machdep) 615 { 616 struct cpu_info * const ci = curcpu(); 617 618 atomic_or_uint(&ci->ci_data.cpu_softints, machdep); 619 if (machdep == (1 << IPL_SOFTBIO)) 620 printf("%s(%u): cpl=%u\n", __func__, machdep, ci->ci_cpl); 621 } 622 #endif /* __HAVE_FAST_SOFTINTS */ 623 624 static int 625 e500_intr_spurious(void *arg) 626 { 627 return 0; 628 } 629 630 static bool 631 e500_intr_irq_info_get(struct cpu_info *ci, u_int irq, int ipl, int ist, 632 struct e500_intr_irq_info *ii) 633 { 634 const struct e500_intr_info * const info = &e500_intr_info; 635 bool ok; 636 637 #if DEBUG > 2 638 printf("%s(%p,irq=%u,ipl=%u,ist=%u,%p)\n", __func__, ci, irq, ipl, ist, ii); 639 #endif 640 641 if (ipl < IPL_VM || ipl > IPL_HIGH) { 642 #if DEBUG > 2 643 printf("%s:%d ipl=%u\n", __func__, __LINE__, ipl); 644 #endif 645 return false; 646 } 647 648 if (ist <= IST_NONE || ist >= IST_MAX) { 649 #if DEBUG > 2 650 printf("%s:%d ist=%u\n", __func__, __LINE__, ist); 651 #endif 652 return false; 653 } 654 655 ii->irq_vector = irq + info->ii_ist_vectors[ist]; 656 if (IST_PERCPU_P(ist)) 657 ii->irq_vector += ci->ci_cpuid * info->ii_percpu_sources; 658 659 switch (ist) { 660 default: 661 ii->irq_vpr = OPENPIC_EIVPR(irq); 662 ii->irq_dr = OPENPIC_EIDR(irq); 663 ok = irq < info->ii_external_sources 664 && (ist == IST_EDGE 665 || ist == IST_LEVEL_LOW 666 || ist == IST_LEVEL_HIGH); 667 break; 668 case IST_ONCHIP: 669 ii->irq_vpr = OPENPIC_IIVPR(irq); 670 ii->irq_dr = OPENPIC_IIDR(irq); 671 ok = irq < 32 * __arraycount(info->ii_onchip_bitmap); 672 #if DEBUG > 2 673 printf("%s: irq=%u: ok=%u\n", __func__, irq, ok); 674 #endif 675 ok = ok && (info->ii_onchip_bitmap[irq/32] & (1 << (irq & 31))); 676 #if DEBUG > 2 677 printf("%s: %08x%08x -> %08x%08x: ok=%u\n", __func__, 678 irq < 32 ? 0 : (1 << irq), irq < 32 ? (1 << irq) : 0, 679 info->ii_onchip_bitmap[1], info->ii_onchip_bitmap[0], 680 ok); 681 #endif 682 break; 683 case IST_MSIGROUP: 684 ii->irq_vpr = OPENPIC_MSIVPR(irq); 685 ii->irq_dr = OPENPIC_MSIDR(irq); 686 ok = irq < info->ii_msigroup_sources 687 && ipl == IPL_VM; 688 break; 689 case IST_TIMER: 690 ii->irq_vpr = OPENPIC_GTVPR(ci->ci_cpuid, irq); 691 ii->irq_dr = OPENPIC_GTDR(ci->ci_cpuid, irq); 692 ok = irq < info->ii_timer_sources; 693 #if DEBUG > 2 694 printf("%s: IST_TIMER irq=%u: ok=%u\n", __func__, irq, ok); 695 #endif 696 break; 697 case IST_IPI: 698 ii->irq_vpr = OPENPIC_IPIVPR(irq); 699 ii->irq_dr = OPENPIC_IPIDR(irq); 700 ok = irq < info->ii_ipi_sources; 701 break; 702 case IST_MI: 703 ii->irq_vpr = OPENPIC_MIVPR(irq); 704 ii->irq_dr = OPENPIC_MIDR(irq); 705 ok = irq < info->ii_mi_sources; 706 break; 707 } 708 709 return ok; 710 } 711 712 static const char * 713 e500_intr_string(int irq, int ist) 714 { 715 struct cpu_info * const ci = curcpu(); 716 struct cpu_softc * const cpu = ci->ci_softc; 717 struct e500_intr_irq_info ii; 718 719 if (!e500_intr_irq_info_get(ci, irq, IPL_VM, ist, &ii)) 720 return NULL; 721 722 return cpu->cpu_evcnt_intrs[ii.irq_vector].ev_name; 723 } 724 725 static void * 726 e500_intr_cpu_establish(struct cpu_info *ci, int irq, int ipl, int ist, 727 int (*handler)(void *), void *arg) 728 { 729 struct cpu_softc * const cpu = ci->ci_softc; 730 struct e500_intr_irq_info ii; 731 732 KASSERT(ipl >= IPL_VM && ipl <= IPL_HIGH); 733 KASSERT(ist > IST_NONE && ist < IST_MAX && ist != IST_MSI); 734 735 if (!e500_intr_irq_info_get(ci, irq, ipl, ist, &ii)) { 736 printf("%s: e500_intr_irq_info_get(%p,%u,%u,%u,%p) failed\n", 737 __func__, ci, irq, ipl, ist, &ii); 738 return NULL; 739 } 740 741 struct intr_source * const is = &e500_intr_sources[ii.irq_vector]; 742 mutex_enter(&e500_intr_lock); 743 if (is->is_ipl != IPL_NONE) 744 return NULL; 745 746 is->is_func = handler; 747 is->is_arg = arg; 748 is->is_ipl = ipl; 749 is->is_ist = ist; 750 is->is_irq = irq; 751 is->is_vpr = ii.irq_vpr; 752 is->is_dr = ii.irq_dr; 753 754 uint32_t vpr = VPR_PRIORITY_MAKE(IPL2CTPR(ipl)) 755 | VPR_VECTOR_MAKE(((ii.irq_vector + 1) << 4) | ipl) 756 | (ist == IST_LEVEL_LOW 757 ? VPR_LEVEL_LOW 758 : (ist == IST_LEVEL_HIGH 759 ? VPR_LEVEL_HIGH 760 : (ist == IST_ONCHIP 761 ? VPR_P_HIGH 762 : 0))); 763 764 /* 765 * All interrupts go to the primary except per-cpu interrupts which get 766 * routed to the appropriate cpu. 767 */ 768 uint32_t dr = IST_PERCPU_P(ist) ? 1 << ci->ci_cpuid : 1; 769 770 /* 771 * Update the vector/priority and destination registers keeping the 772 * interrupt masked. 773 */ 774 const register_t msr = wrtee(0); /* disable interrupts */ 775 openpic_write(cpu, ii.irq_vpr, vpr | VPR_MSK); 776 openpic_write(cpu, ii.irq_dr, dr); 777 778 /* 779 * Now unmask the interrupt. 780 */ 781 openpic_write(cpu, ii.irq_vpr, vpr); 782 783 wrtee(msr); /* re-enable interrupts */ 784 785 mutex_exit(&e500_intr_lock); 786 787 return is; 788 } 789 790 static void * 791 e500_intr_establish(int irq, int ipl, int ist, 792 int (*handler)(void *), void *arg) 793 { 794 return e500_intr_cpu_establish(curcpu(), irq, ipl, ist, handler, arg); 795 } 796 797 static void 798 e500_intr_disestablish(void *vis) 799 { 800 struct cpu_softc * const cpu = curcpu()->ci_softc; 801 struct intr_source * const is = vis; 802 struct e500_intr_irq_info ii; 803 804 KASSERT(e500_intr_sources <= is); 805 KASSERT(is < e500_intr_last_source); 806 KASSERT(!cpu_intr_p()); 807 808 bool ok = e500_intr_irq_info_get(curcpu(), is->is_irq, is->is_ipl, 809 is->is_ist, &ii); 810 (void)ok; /* appease gcc */ 811 KASSERT(ok); 812 KASSERT(is - e500_intr_sources == ii.irq_vector); 813 814 mutex_enter(&e500_intr_lock); 815 /* 816 * Mask the source using the mask (MSK) bit in the vector/priority reg. 817 */ 818 uint32_t vpr = openpic_read(cpu, ii.irq_vpr); 819 openpic_write(cpu, ii.irq_vpr, VPR_MSK | vpr); 820 821 /* 822 * Wait for the Activity (A) bit for the source to be cleared. 823 */ 824 while (openpic_read(cpu, ii.irq_vpr) & VPR_A) 825 ; 826 827 /* 828 * Now the source can be modified. 829 */ 830 openpic_write(cpu, ii.irq_dr, 0); /* stop delivery */ 831 openpic_write(cpu, ii.irq_vpr, VPR_MSK); /* mask/reset it */ 832 833 *is = (struct intr_source)INTR_SOURCE_INITIALIZER; 834 835 mutex_exit(&e500_intr_lock); 836 } 837 838 static void 839 e500_critintr(struct trapframe *tf) 840 { 841 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 842 } 843 844 static void 845 e500_decrintr(struct trapframe *tf) 846 { 847 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 848 } 849 850 static void 851 e500_fitintr(struct trapframe *tf) 852 { 853 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 854 } 855 856 static void 857 e500_wdogintr(struct trapframe *tf) 858 { 859 mtspr(SPR_TSR, TSR_ENW|TSR_WIS); 860 panic("%s: tf=%p tb=%"PRId64" srr0/srr1=%#lx/%#lx", __func__, tf, 861 mftb(), tf->tf_srr0, tf->tf_srr1); 862 } 863 864 static void 865 e500_extintr(struct trapframe *tf) 866 { 867 struct cpu_info * const ci = curcpu(); 868 struct cpu_softc * const cpu = ci->ci_softc; 869 const int old_ipl = ci->ci_cpl; 870 871 KASSERT(mfmsr() & PSL_CE); 872 873 #if 0 874 // printf("%s(%p): idepth=%d enter\n", __func__, tf, ci->ci_idepth); 875 if ((register_t)tf >= (register_t)curlwp->l_addr + USPACE 876 || (register_t)tf < (register_t)curlwp->l_addr + NBPG) { 877 printf("%s(entry): pid %d.%d (%s): srr0/srr1=%#lx/%#lx: invalid tf addr %p\n", 878 __func__, curlwp->l_proc->p_pid, curlwp->l_lid, 879 curlwp->l_proc->p_comm, tf->tf_srr0, tf->tf_srr1, tf); 880 } 881 #endif 882 883 884 ci->ci_data.cpu_nintr++; 885 tf->tf_cf.cf_idepth = ci->ci_idepth++; 886 cpu->cpu_pcpls[ci->ci_idepth] = old_ipl; 887 #if 1 888 if (mfmsr() & PSL_EE) 889 panic("%s(%p): MSR[EE] is on (%#lx)!", __func__, tf, mfmsr()); 890 if (old_ipl == IPL_HIGH 891 || IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 892 panic("%s(%p): old_ipl(%u) == IPL_HIGH(%u) " 893 "|| old_ipl + %u != OPENPIC_CTPR (%u)", 894 __func__, tf, old_ipl, IPL_HIGH, 895 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 896 #else 897 if (old_ipl >= IPL_VM) 898 panic("%s(%p): old_ipl(%u) >= IPL_VM(%u) CTPR=%u", 899 __func__, tf, old_ipl, IPL_VM, openpic_read(cpu, OPENPIC_CTPR)); 900 #endif 901 902 for (;;) { 903 /* 904 * Find out the pending interrupt. 905 */ 906 if (mfmsr() & PSL_EE) 907 panic("%s(%p): MSR[EE] turned on (%#lx)!", __func__, tf, mfmsr()); 908 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 909 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 910 __func__, tf, __LINE__, old_ipl, 911 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 912 const uint32_t iack = openpic_read(cpu, OPENPIC_IACK); 913 #ifdef DIAGNOSTIC 914 const int ipl = iack & 0xf; 915 #endif 916 const int irq = (iack >> 4) - 1; 917 #if 0 918 printf("%s: iack=%d ipl=%d irq=%d <%s>\n", 919 __func__, iack, ipl, irq, 920 (iack != IRQ_SPURIOUS ? 921 cpu->cpu_evcnt_intrs[irq].ev_name : "spurious")); 922 #endif 923 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 924 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 925 __func__, tf, __LINE__, old_ipl, 926 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 927 if (iack == IRQ_SPURIOUS) 928 break; 929 930 struct intr_source * const is = &e500_intr_sources[irq]; 931 if (__predict_true(is < e500_intr_last_source)) { 932 /* 933 * Timer interrupts get their argument overriden with 934 * the pointer to the trapframe. 935 */ 936 KASSERT(is->is_ipl == ipl); 937 void *arg = (is->is_ist == IST_TIMER ? tf : is->is_arg); 938 if (is->is_ipl <= old_ipl) 939 panic("%s(%p): %s (%u): is->is_ipl (%u) <= old_ipl (%u)\n", 940 __func__, tf, 941 cpu->cpu_evcnt_intrs[irq].ev_name, irq, 942 is->is_ipl, old_ipl); 943 KASSERT(is->is_ipl > old_ipl); 944 e500_splset(ci, is->is_ipl); /* change IPL */ 945 if (__predict_false(is->is_func == NULL)) { 946 aprint_error_dev(ci->ci_dev, 947 "interrupt from unestablished irq %d\n", 948 irq); 949 } else { 950 int (*func)(void *) = is->is_func; 951 wrtee(PSL_EE); 952 int rv = (*func)(arg); 953 wrtee(0); 954 #if DEBUG > 2 955 printf("%s: %s handler %p(%p) returned %d\n", 956 __func__, 957 cpu->cpu_evcnt_intrs[irq].ev_name, 958 func, arg, rv); 959 #endif 960 if (rv == 0) 961 cpu->cpu_evcnt_spurious_intr.ev_count++; 962 } 963 e500_splset(ci, old_ipl); /* restore IPL */ 964 cpu->cpu_evcnt_intrs[irq].ev_count++; 965 } else { 966 aprint_error_dev(ci->ci_dev, 967 "interrupt from illegal irq %d\n", irq); 968 cpu->cpu_evcnt_spurious_intr.ev_count++; 969 } 970 /* 971 * If this is a nested interrupt, simply ack it and exit 972 * because the loop we interrupted will complete looking 973 * for interrupts. 974 */ 975 if (mfmsr() & PSL_EE) 976 panic("%s(%p): MSR[EE] left on (%#lx)!", __func__, tf, mfmsr()); 977 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 978 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 979 __func__, tf, __LINE__, old_ipl, 980 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 981 982 openpic_write(cpu, OPENPIC_EOI, 0); 983 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 984 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 985 __func__, tf, __LINE__, old_ipl, 986 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 987 if (ci->ci_idepth > 0) 988 break; 989 } 990 991 ci->ci_idepth--; 992 993 #ifdef __HAVE_FAST_SOFTINTS 994 /* 995 * Before exiting, deal with any softints that need to be dealt with. 996 */ 997 const u_int softints = (ci->ci_data.cpu_softints << old_ipl) & IPL_SOFTMASK; 998 if (__predict_false(softints != 0)) { 999 KASSERT(old_ipl < IPL_VM); 1000 e500_splset(ci, IPL_HIGH); /* pop to high */ 1001 e500_softint(ci, cpu, old_ipl); /* deal with them */ 1002 e500_splset(ci, old_ipl); /* and drop back */ 1003 } 1004 #endif /* __HAVE_FAST_SOFTINTS */ 1005 #if 1 1006 KASSERT(ci->ci_cpl == old_ipl); 1007 #else 1008 e500_splset(ci, old_ipl); /* and drop back */ 1009 #endif 1010 1011 // printf("%s(%p): idepth=%d exit\n", __func__, tf, ci->ci_idepth); 1012 } 1013 1014 static void 1015 e500_intr_init(void) 1016 { 1017 struct cpu_info * const ci = curcpu(); 1018 struct cpu_softc * const cpu = ci->ci_softc; 1019 const uint32_t frr = openpic_read(cpu, OPENPIC_FRR); 1020 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1021 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1022 struct intr_source *is; 1023 struct e500_intr_info * const ii = &e500_intr_info; 1024 1025 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 1026 switch (svr) { 1027 #ifdef MPC8536 1028 case SVR_MPC8536v1 >> 16: 1029 *ii = mpc8536_intr_info; 1030 break; 1031 #endif 1032 #ifdef MPC8544 1033 case SVR_MPC8544v1 >> 16: 1034 *ii = mpc8544_intr_info; 1035 break; 1036 #endif 1037 #ifdef MPC8548 1038 case SVR_MPC8543v1 >> 16: 1039 case SVR_MPC8548v1 >> 16: 1040 *ii = mpc8548_intr_info; 1041 break; 1042 #endif 1043 #ifdef MPC8555 1044 case SVR_MPC8541v1 >> 16: 1045 case SVR_MPC8555v1 >> 16: 1046 *ii = mpc8555_intr_info; 1047 break; 1048 #endif 1049 #ifdef MPC8568 1050 case SVR_MPC8568v1 >> 16: 1051 *ii = mpc8568_intr_info; 1052 break; 1053 #endif 1054 #ifdef MPC8572 1055 case SVR_MPC8572v1 >> 16: 1056 *ii = mpc8572_intr_info; 1057 break; 1058 #endif 1059 #ifdef P2020 1060 case SVR_P2010v2 >> 16: 1061 case SVR_P2020v2 >> 16: 1062 *ii = p20x0_intr_info; 1063 break; 1064 #endif 1065 default: 1066 panic("%s: don't know how to deal with SVR %#lx", 1067 __func__, mfspr(SPR_SVR)); 1068 } 1069 1070 /* 1071 * We need to be in mixed mode. 1072 */ 1073 openpic_write(cpu, OPENPIC_GCR, GCR_M); 1074 1075 /* 1076 * Make we and the openpic both agree about the current SPL level. 1077 */ 1078 e500_splset(ci, ci->ci_cpl); 1079 1080 /* 1081 * Allow the required number of interrupt sources. 1082 */ 1083 is = kmem_zalloc(nirq * sizeof(*is), KM_SLEEP); 1084 KASSERT(is); 1085 e500_intr_sources = is; 1086 e500_intr_last_source = is + nirq; 1087 1088 /* 1089 * Initialize all the external interrupts as active low. 1090 */ 1091 for (u_int irq = 0; irq < e500_intr_info.ii_external_sources; irq++) { 1092 openpic_write(cpu, OPENPIC_EIVPR(irq), 1093 VPR_VECTOR_MAKE(irq) | VPR_LEVEL_LOW); 1094 } 1095 } 1096 1097 static void 1098 e500_intr_cpu_init(struct cpu_info *ci) 1099 { 1100 struct cpu_softc * const cpu = ci->ci_softc; 1101 const char * const xname = device_xname(ci->ci_dev); 1102 1103 const u_int32_t frr = openpic_read(cpu, OPENPIC_FRR); 1104 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1105 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1106 1107 const struct e500_intr_info * const info = &e500_intr_info; 1108 1109 cpu->cpu_clock_gtbcr = OPENPIC_GTBCR(ci->ci_cpuid, E500_CLOCK_TIMER); 1110 1111 cpu->cpu_evcnt_intrs = 1112 kmem_zalloc(nirq * sizeof(cpu->cpu_evcnt_intrs[0]), KM_SLEEP); 1113 KASSERT(cpu->cpu_evcnt_intrs); 1114 1115 struct evcnt *evcnt = cpu->cpu_evcnt_intrs; 1116 for (size_t j = 0; j < info->ii_external_sources; j++, evcnt++) { 1117 const char *name = e500_intr_external_name_lookup(j); 1118 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, NULL, xname, name); 1119 } 1120 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_ONCHIP]); 1121 for (size_t j = 0; j < info->ii_onchip_sources; j++, evcnt++) { 1122 if (info->ii_onchip_bitmap[j / 32] & __BIT(j & 31)) { 1123 const char *name = e500_intr_onchip_name_lookup(j); 1124 if (name != NULL) { 1125 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1126 NULL, xname, name); 1127 #ifdef DIAGNOSTIC 1128 } else { 1129 printf("%s: missing evcnt for onchip irq %zu\n", 1130 __func__, j); 1131 #endif 1132 } 1133 } 1134 } 1135 1136 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_MSIGROUP]); 1137 for (size_t j = 0; j < info->ii_msigroup_sources; j++, evcnt++) { 1138 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1139 NULL, xname, e500_msigroup_intr_names[j].in_name); 1140 } 1141 1142 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_TIMER]); 1143 evcnt += ci->ci_cpuid * info->ii_percpu_sources; 1144 for (size_t j = 0; j < info->ii_timer_sources; j++, evcnt++) { 1145 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1146 NULL, xname, e500_timer_intr_names[j].in_name); 1147 } 1148 1149 for (size_t j = 0; j < info->ii_ipi_sources; j++, evcnt++) { 1150 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1151 NULL, xname, e500_ipi_intr_names[j].in_name); 1152 } 1153 1154 for (size_t j = 0; j < info->ii_mi_sources; j++, evcnt++) { 1155 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1156 NULL, xname, e500_mi_intr_names[j].in_name); 1157 } 1158 1159 /* 1160 * Establish interrupt for this CPU. 1161 */ 1162 if (e500_intr_cpu_establish(ci, E500_CLOCK_TIMER, IPL_CLOCK, IST_TIMER, 1163 e500_clock_intr, NULL) == NULL) 1164 panic("%s: failed to establish clock interrupt!", __func__); 1165 1166 /* 1167 * Enable watchdog interrupts. 1168 */ 1169 uint32_t tcr = mfspr(SPR_TCR); 1170 tcr |= TCR_WIE; 1171 mtspr(SPR_TCR, tcr); 1172 } 1173
Indexes created Mon Sep 29 21:09:56 GMT 2025