e500_intr.c revision 1.7
1 /* $NetBSD: e500_intr.c,v 1.7 2011/05/27 15:19:43 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_mpc85xx.h" 38 39 #define __INTR_PRIVATE 40 41 #include <sys/param.h> 42 #include <sys/proc.h> 43 #include <sys/intr.h> 44 #include <sys/cpu.h> 45 #include <sys/kmem.h> 46 #include <sys/atomic.h> 47 #include <sys/bus.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/spr.h> 52 #include <powerpc/booke/spr.h> 53 54 #include <powerpc/booke/cpuvar.h> 55 #include <powerpc/booke/e500reg.h> 56 #include <powerpc/booke/e500var.h> 57 #include <powerpc/booke/openpicreg.h> 58 59 #define IPL2CTPR(ipl) ((ipl) + 15 - IPL_HIGH) 60 #define CTPR2IPL(ctpr) ((ctpr) - (15 - IPL_HIGH)) 61 62 #define IST_PERCPU_P(ist) ((ist) >= IST_TIMER) 63 64 #define IPL_SOFTMASK \ 65 ((1 << IPL_SOFTSERIAL) | (1 << IPL_SOFTNET ) \ 66 |(1 << IPL_SOFTBIO ) | (1 << IPL_SOFTCLOCK )) 67 68 #define SOFTINT2IPL_MAP \ 69 ((IPL_SOFTSERIAL << (4*SOFTINT_SERIAL)) \ 70 |(IPL_SOFTNET << (4*SOFTINT_NET )) \ 71 |(IPL_SOFTBIO << (4*SOFTINT_BIO )) \ 72 |(IPL_SOFTCLOCK << (4*SOFTINT_CLOCK ))) 73 #define SOFTINT2IPL(si_level) ((SOFTINT2IPL_MAP >> (4 * si_level)) & 0x0f) 74 75 struct e500_intr_irq_info { 76 bus_addr_t irq_vpr; 77 bus_addr_t irq_dr; 78 u_int irq_vector; 79 }; 80 81 struct intr_source { 82 int (*is_func)(void *); 83 void *is_arg; 84 int8_t is_ipl; 85 uint8_t is_ist; 86 uint8_t is_irq; 87 bus_size_t is_vpr; 88 bus_size_t is_dr; 89 }; 90 91 #define INTR_SOURCE_INITIALIZER \ 92 { .is_func = e500_intr_spurious, .is_arg = NULL, \ 93 .is_irq = -1, .is_ipl = IPL_NONE, .is_ist = IST_NONE, } 94 95 struct e500_intr_name { 96 uint8_t in_irq; 97 const char in_name[15]; 98 }; 99 100 static const struct e500_intr_name e500_onchip_intr_names[] = { 101 { ISOURCE_L2, "l2" }, 102 { ISOURCE_ECM, "ecm" }, 103 { ISOURCE_DDR, "ddr" }, 104 { ISOURCE_LBC, "lbc" }, 105 { ISOURCE_DMA_CHAN1, "dma-chan1" }, 106 { ISOURCE_DMA_CHAN2, "dma-chan2" }, 107 { ISOURCE_DMA_CHAN3, "dma-chan3" }, 108 { ISOURCE_DMA_CHAN4, "dma-chan4" }, 109 { ISOURCE_PCI1, "pci1" }, 110 { ISOURCE_PCIEX2, "pcie2" }, 111 { ISOURCE_PCIEX , "pcie1" }, 112 { ISOURCE_PCIEX3, "pcie3" }, 113 { ISOURCE_USB1, "usb1" }, 114 { ISOURCE_ETSEC1_TX, "etsec1-tx" }, 115 { ISOURCE_ETSEC1_RX, "etsec1-rx" }, 116 { ISOURCE_ETSEC3_TX, "etsec3-tx" }, 117 { ISOURCE_ETSEC3_RX, "etsec3-rx" }, 118 { ISOURCE_ETSEC3_ERR, "etsec3-err" }, 119 { ISOURCE_ETSEC1_ERR, "etsec1-err" }, 120 { ISOURCE_ETSEC2_TX, "etsec2-tx" }, 121 { ISOURCE_ETSEC2_RX, "etsec2-rx" }, 122 { ISOURCE_ETSEC4_TX, "etsec4-tx" }, 123 { ISOURCE_ETSEC4_RX, "etsec4-rx" }, 124 { ISOURCE_ETSEC4_ERR, "etsec4-err" }, 125 { ISOURCE_ETSEC2_ERR, "etsec2-err" }, 126 { ISOURCE_DUART, "duart" }, 127 { ISOURCE_I2C, "i2c" }, 128 { ISOURCE_PERFMON, "perfmon" }, 129 { ISOURCE_SECURITY1, "sec1" }, 130 { ISOURCE_GPIO, "gpio" }, 131 { ISOURCE_SRIO_EWPU, "srio-ewpu" }, 132 { ISOURCE_SRIO_ODBELL, "srio-odbell" }, 133 { ISOURCE_SRIO_IDBELL, "srio-idbell" }, 134 { ISOURCE_SRIO_OMU1, "srio-omu1" }, 135 { ISOURCE_SRIO_IMU1, "srio-imu1" }, 136 { ISOURCE_SRIO_OMU2, "srio-omu2" }, 137 { ISOURCE_SRIO_IMU2, "srio-imu2" }, 138 { ISOURCE_SECURITY2, "sec2" }, 139 { ISOURCE_SPI, "spi" }, 140 { ISOURCE_ETSEC1_PTP, "etsec1-ptp" }, 141 { ISOURCE_ETSEC2_PTP, "etsec2-ptp" }, 142 { ISOURCE_ETSEC3_PTP, "etsec3-ptp" }, 143 { ISOURCE_ETSEC4_PTP, "etsec4-ptp" }, 144 { ISOURCE_ESDHC, "esdhc" }, 145 { 0, "" }, 146 }; 147 148 const struct e500_intr_name default_external_intr_names[] = { 149 { 0, "" }, 150 }; 151 152 static const struct e500_intr_name e500_msigroup_intr_names[] = { 153 { 0, "msigroup0" }, 154 { 1, "msigroup1" }, 155 { 2, "msigroup2" }, 156 { 3, "msigroup3" }, 157 { 4, "msigroup4" }, 158 { 5, "msigroup5" }, 159 { 6, "msigroup6" }, 160 { 7, "msigroup7" }, 161 { 0, "" }, 162 }; 163 164 static const struct e500_intr_name e500_timer_intr_names[] = { 165 { 0, "timer0" }, 166 { 1, "timer1" }, 167 { 2, "timer2" }, 168 { 3, "timer3" }, 169 { 0, "" }, 170 }; 171 172 static const struct e500_intr_name e500_ipi_intr_names[] = { 173 { 0, "ipi0" }, 174 { 1, "ipi1" }, 175 { 2, "ipi2" }, 176 { 3, "ipi3" }, 177 { 0, "" }, 178 }; 179 180 static const struct e500_intr_name e500_mi_intr_names[] = { 181 { 0, "mi0" }, 182 { 1, "mi1" }, 183 { 2, "mi2" }, 184 { 3, "mi3" }, 185 { 0, "" }, 186 }; 187 188 struct e500_intr_info { 189 u_int ii_external_sources; 190 uint32_t ii_onchip_bitmap[2]; 191 u_int ii_onchip_sources; 192 u_int ii_msigroup_sources; 193 u_int ii_ipi_sources; /* per-cpu */ 194 u_int ii_timer_sources; /* per-cpu */ 195 u_int ii_mi_sources; /* per-cpu */ 196 u_int ii_percpu_sources; 197 const struct e500_intr_name *ii_external_intr_names; 198 const struct e500_intr_name *ii_onchip_intr_names; 199 u_int8_t ii_ist_vectors[IST_MAX+1]; 200 }; 201 202 static kmutex_t e500_intr_lock __cacheline_aligned; 203 static struct e500_intr_info e500_intr_info; 204 205 #define INTR_INFO_DECL(lc_chip, UC_CHIP) \ 206 static const struct e500_intr_info lc_chip##_intr_info = { \ 207 .ii_external_sources = UC_CHIP ## _EXTERNALSOURCES, \ 208 .ii_onchip_bitmap = UC_CHIP ## _ONCHIPBITMAP, \ 209 .ii_onchip_sources = UC_CHIP ## _ONCHIPSOURCES, \ 210 .ii_msigroup_sources = UC_CHIP ## _MSIGROUPSOURCES, \ 211 .ii_timer_sources = UC_CHIP ## _TIMERSOURCES, \ 212 .ii_ipi_sources = UC_CHIP ## _IPISOURCES, \ 213 .ii_mi_sources = UC_CHIP ## _MISOURCES, \ 214 .ii_percpu_sources = UC_CHIP ## _TIMERSOURCES \ 215 + UC_CHIP ## _IPISOURCES + UC_CHIP ## _MISOURCES, \ 216 .ii_external_intr_names = lc_chip ## _external_intr_names, \ 217 .ii_onchip_intr_names = lc_chip ## _onchip_intr_names, \ 218 .ii_ist_vectors = { \ 219 [IST_NONE] = ~0, \ 220 [IST_EDGE] = 0, \ 221 [IST_LEVEL_LOW] = 0, \ 222 [IST_LEVEL_HIGH] = 0, \ 223 [IST_ONCHIP] = UC_CHIP ## _EXTERNALSOURCES, \ 224 [IST_MSIGROUP] = UC_CHIP ## _EXTERNALSOURCES \ 225 + UC_CHIP ## _ONCHIPSOURCES, \ 226 [IST_TIMER] = UC_CHIP ## _EXTERNALSOURCES \ 227 + UC_CHIP ## _ONCHIPSOURCES \ 228 + UC_CHIP ## _MSIGROUPSOURCES, \ 229 [IST_IPI] = UC_CHIP ## _EXTERNALSOURCES \ 230 + UC_CHIP ## _ONCHIPSOURCES \ 231 + UC_CHIP ## _MSIGROUPSOURCES \ 232 + UC_CHIP ## _TIMERSOURCES, \ 233 [IST_MI] = UC_CHIP ## _EXTERNALSOURCES \ 234 + UC_CHIP ## _ONCHIPSOURCES \ 235 + UC_CHIP ## _MSIGROUPSOURCES \ 236 + UC_CHIP ## _TIMERSOURCES \ 237 + UC_CHIP ## _IPISOURCES, \ 238 [IST_MAX] = UC_CHIP ## _EXTERNALSOURCES \ 239 + UC_CHIP ## _ONCHIPSOURCES \ 240 + UC_CHIP ## _MSIGROUPSOURCES \ 241 + UC_CHIP ## _TIMERSOURCES \ 242 + UC_CHIP ## _IPISOURCES \ 243 + UC_CHIP ## _MISOURCES, \ 244 }, \ 245 } 246 247 #ifdef MPC8536 248 #define mpc8536_external_intr_names default_external_intr_names 249 const struct e500_intr_name mpc8536_onchip_intr_names[] = { 250 { ISOURCE_SATA2, "sata2" }, 251 { ISOURCE_USB2, "usb2" }, 252 { ISOURCE_USB3, "usb3" }, 253 { ISOURCE_SATA1, "sata1" }, 254 { 0, "" }, 255 }; 256 257 INTR_INFO_DECL(mpc8536, MPC8536); 258 #endif 259 260 #ifdef MPC8544 261 #define mpc8544_external_intr_names default_external_intr_names 262 const struct e500_intr_name mpc8544_onchip_intr_names[] = { 263 { 0, "" }, 264 }; 265 266 INTR_INFO_DECL(mpc8544, MPC8544); 267 #endif 268 #ifdef MPC8548 269 #define mpc8548_external_intr_names default_external_intr_names 270 const struct e500_intr_name mpc8548_onchip_intr_names[] = { 271 { ISOURCE_PCI1, "pci1" }, 272 { ISOURCE_PCI2, "pci2" }, 273 { 0, "" }, 274 }; 275 276 INTR_INFO_DECL(mpc8548, MPC8548); 277 #endif 278 #ifdef MPC8555 279 #define mpc8555_external_intr_names default_external_intr_names 280 const struct e500_intr_name mpc8555_onchip_intr_names[] = { 281 { ISOURCE_PCI2, "pci2" }, 282 { ISOURCE_CPM, "CPM" }, 283 { 0, "" }, 284 }; 285 286 INTR_INFO_DECL(mpc8555, MPC8555); 287 #endif 288 #ifdef MPC8568 289 #define mpc8568_external_intr_names default_external_intr_names 290 const struct e500_intr_name mpc8568_onchip_intr_names[] = { 291 { ISOURCE_QEB_LOW, "QEB low" }, 292 { ISOURCE_QEB_PORT, "QEB port" }, 293 { ISOURCE_QEB_IECC, "QEB iram ecc" }, 294 { ISOURCE_QEB_MUECC, "QEB ram ecc" }, 295 { ISOURCE_TLU1, "tlu1" }, 296 { ISOURCE_QEB_HIGH, "QEB high" }, 297 { 0, "" }, 298 }; 299 300 INTR_INFO_DECL(mpc8568, MPC8568); 301 #endif 302 #ifdef MPC8572 303 #define mpc8572_external_intr_names default_external_intr_names 304 const struct e500_intr_name mpc8572_onchip_intr_names[] = { 305 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 306 { ISOURCE_FEC, "fec" }, 307 { ISOURCE_PME_GENERAL, "pme" }, 308 { ISOURCE_TLU1, "tlu1" }, 309 { ISOURCE_TLU2, "tlu2" }, 310 { ISOURCE_PME_CHAN1, "pme-chan1" }, 311 { ISOURCE_PME_CHAN2, "pme-chan2" }, 312 { ISOURCE_PME_CHAN3, "pme-chan3" }, 313 { ISOURCE_PME_CHAN4, "pme-chan4" }, 314 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 315 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 316 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 317 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 318 { 0, "" }, 319 }; 320 321 INTR_INFO_DECL(mpc8572, MPC8572); 322 #endif 323 #ifdef P2020 324 #define p20x0_external_intr_names default_external_intr_names 325 const struct e500_intr_name p20x0_onchip_intr_names[] = { 326 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 327 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 328 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 329 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 330 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 331 { 0, "" }, 332 }; 333 334 INTR_INFO_DECL(p20x0, P20x0); 335 #endif 336 337 static const char ist_names[][12] = { 338 [IST_NONE] = "none", 339 [IST_EDGE] = "edge", 340 [IST_LEVEL_LOW] = "level-", 341 [IST_LEVEL_HIGH] = "level+", 342 [IST_MSI] = "msi", 343 [IST_ONCHIP] = "onchip", 344 [IST_MSIGROUP] = "msigroup", 345 [IST_TIMER] = "timer", 346 [IST_IPI] = "ipi", 347 [IST_MI] = "msgint", 348 }; 349 350 static struct intr_source *e500_intr_sources; 351 static const struct intr_source *e500_intr_last_source; 352 353 static void *e500_intr_establish(int, int, int, int (*)(void *), void *); 354 static void e500_intr_disestablish(void *); 355 static void e500_intr_cpu_init(struct cpu_info *ci); 356 static void e500_intr_init(void); 357 static const char *e500_intr_string(int, int); 358 static void e500_critintr(struct trapframe *tf); 359 static void e500_decrintr(struct trapframe *tf); 360 static void e500_extintr(struct trapframe *tf); 361 static void e500_fitintr(struct trapframe *tf); 362 static void e500_wdogintr(struct trapframe *tf); 363 static void e500_spl0(void); 364 static int e500_splraise(int); 365 static void e500_splx(int); 366 #ifdef __HAVE_FAST_SOFTINTS 367 static void e500_softint_init_md(lwp_t *l, u_int si_level, uintptr_t *machdep_p); 368 static void e500_softint_trigger(uintptr_t machdep); 369 #endif 370 371 const struct intrsw e500_intrsw = { 372 .intrsw_establish = e500_intr_establish, 373 .intrsw_disestablish = e500_intr_disestablish, 374 .intrsw_init = e500_intr_init, 375 .intrsw_cpu_init = e500_intr_cpu_init, 376 .intrsw_string = e500_intr_string, 377 378 .intrsw_critintr = e500_critintr, 379 .intrsw_decrintr = e500_decrintr, 380 .intrsw_extintr = e500_extintr, 381 .intrsw_fitintr = e500_fitintr, 382 .intrsw_wdogintr = e500_wdogintr, 383 384 .intrsw_splraise = e500_splraise, 385 .intrsw_splx = e500_splx, 386 .intrsw_spl0 = e500_spl0, 387 388 #ifdef __HAVE_FAST_SOFTINTS 389 .intrsw_softint_init_md = e500_softint_init_md, 390 .intrsw_softint_trigger = e500_softint_trigger, 391 #endif 392 }; 393 394 static inline uint32_t 395 openpic_read(struct cpu_softc *cpu, bus_size_t offset) 396 { 397 398 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, 399 OPENPIC_BASE + offset); 400 } 401 402 static inline void 403 openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val) 404 { 405 406 return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, 407 OPENPIC_BASE + offset, val); 408 } 409 410 static const char * 411 e500_intr_external_name_lookup(int irq) 412 { 413 prop_array_t extirqs = board_info_get_object("external-irqs"); 414 prop_string_t irqname = prop_array_get(extirqs, irq); 415 KASSERT(irqname != NULL); 416 KASSERT(prop_object_type(irqname) == PROP_TYPE_STRING); 417 418 return prop_string_cstring_nocopy(irqname); 419 } 420 421 static const char * 422 e500_intr_name_lookup(const struct e500_intr_name *names, int irq) 423 { 424 for (; names->in_name[0] != '\0'; names++) { 425 if (names->in_irq == irq) 426 return names->in_name; 427 } 428 429 return NULL; 430 } 431 432 static const char * 433 e500_intr_onchip_name_lookup(int irq) 434 { 435 const char *name; 436 437 name = e500_intr_name_lookup(e500_intr_info.ii_onchip_intr_names, irq); 438 if (name == NULL) 439 name = e500_intr_name_lookup(e500_onchip_intr_names, irq); 440 441 return name; 442 } 443 444 #ifdef __HAVE_FAST_SOFTINTS 445 static inline void 446 e500_softint_deliver(struct cpu_info *ci, struct cpu_softc *cpu, 447 int ipl, int si_level) 448 { 449 KASSERT(ci->ci_data.cpu_softints & (1 << ipl)); 450 ci->ci_data.cpu_softints ^= 1 << ipl; 451 softint_fast_dispatch(cpu->cpu_softlwps[si_level], ipl); 452 KASSERT(cpu->cpu_softlwps[si_level]->l_ctxswtch == 0); 453 KASSERTMSG(ci->ci_cpl == IPL_HIGH, 454 ("%s: cpl (%d) != HIGH", __func__, ci->ci_cpl)); 455 } 456 457 static inline void 458 e500_softint(struct cpu_info *ci, struct cpu_softc *cpu, int old_ipl) 459 { 460 const u_int softint_mask = (IPL_SOFTMASK << old_ipl) & IPL_SOFTMASK; 461 u_int softints; 462 463 KASSERT(ci->ci_mtx_count == 0); 464 KASSERT(ci->ci_cpl == IPL_HIGH); 465 while ((softints = (ci->ci_data.cpu_softints & softint_mask)) != 0) { 466 KASSERT(old_ipl < IPL_SOFTSERIAL); 467 if (softints & (1 << IPL_SOFTSERIAL)) { 468 e500_softint_deliver(ci, cpu, IPL_SOFTSERIAL, 469 SOFTINT_SERIAL); 470 continue; 471 } 472 KASSERT(old_ipl < IPL_SOFTNET); 473 if (softints & (1 << IPL_SOFTNET)) { 474 e500_softint_deliver(ci, cpu, IPL_SOFTNET, 475 SOFTINT_NET); 476 continue; 477 } 478 KASSERT(old_ipl < IPL_SOFTBIO); 479 if (softints & (1 << IPL_SOFTBIO)) { 480 e500_softint_deliver(ci, cpu, IPL_SOFTBIO, 481 SOFTINT_BIO); 482 continue; 483 } 484 KASSERT(old_ipl < IPL_SOFTCLOCK); 485 if (softints & (1 << IPL_SOFTCLOCK)) { 486 e500_softint_deliver(ci, cpu, IPL_SOFTCLOCK, 487 SOFTINT_CLOCK); 488 continue; 489 } 490 } 491 } 492 #endif /* __HAVE_FAST_SOFTINTS */ 493 494 static inline void 495 e500_splset(struct cpu_info *ci, int ipl) 496 { 497 struct cpu_softc * const cpu = ci->ci_softc; 498 //KASSERT(!cpu_intr_p() || ipl >= IPL_VM); 499 KASSERT((curlwp->l_pflag & LP_INTR) == 0 || ipl != IPL_NONE); 500 #if 0 501 u_int ctpr = ipl; 502 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ci->ci_cpl); 503 #elif 0 504 u_int old_ctpr = (ci->ci_cpl >= IPL_VM ? 15 : ci->ci_cpl); 505 u_int ctpr = (ipl >= IPL_VM ? 15 : ipl); 506 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == old_ctpr); 507 #else 508 #ifdef DIAGNOSTIC 509 u_int old_ctpr = IPL2CTPR(ci->ci_cpl); 510 #endif 511 u_int ctpr = IPL2CTPR(ipl); 512 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == old_ctpr); 513 #endif 514 openpic_write(cpu, OPENPIC_CTPR, ctpr); 515 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ctpr); 516 ci->ci_cpl = ipl; 517 } 518 519 static void 520 e500_spl0(void) 521 { 522 struct cpu_info * const ci = curcpu(); 523 524 wrtee(0); 525 526 #ifdef __HAVE_FAST_SOFTINTS 527 if (__predict_false(ci->ci_data.cpu_softints != 0)) { 528 e500_splset(ci, IPL_HIGH); 529 e500_softint(ci, ci->ci_softc, IPL_NONE); 530 } 531 #endif /* __HAVE_FAST_SOFTINTS */ 532 e500_splset(ci, IPL_NONE); 533 534 wrtee(PSL_EE); 535 } 536 537 static void 538 e500_splx(int ipl) 539 { 540 struct cpu_info * const ci = curcpu(); 541 const int old_ipl = ci->ci_cpl; 542 543 KASSERT(mfmsr() & PSL_CE); 544 545 if (ipl == old_ipl) 546 return; 547 548 if (__predict_false(ipl > old_ipl)) { 549 printf("%s: %p: cpl=%u: ignoring splx(%u) to raise ipl\n", 550 __func__, __builtin_return_address(0), old_ipl, ipl); 551 if (old_ipl == IPL_NONE) 552 Debugger(); 553 } 554 555 // const 556 register_t msr = wrtee(0); 557 #ifdef __HAVE_FAST_SOFTINTS 558 const u_int softints = (ci->ci_data.cpu_softints << ipl) & IPL_SOFTMASK; 559 if (__predict_false(softints != 0)) { 560 e500_splset(ci, IPL_HIGH); 561 e500_softint(ci, ci->ci_softc, ipl); 562 } 563 #endif /* __HAVE_FAST_SOFTINTS */ 564 e500_splset(ci, ipl); 565 #if 1 566 if (ipl < IPL_VM && old_ipl >= IPL_VM) 567 msr = PSL_EE; 568 #endif 569 wrtee(msr); 570 } 571 572 static int 573 e500_splraise(int ipl) 574 { 575 struct cpu_info * const ci = curcpu(); 576 const int old_ipl = ci->ci_cpl; 577 578 KASSERT(mfmsr() & PSL_CE); 579 580 if (old_ipl < ipl) { 581 //const 582 register_t msr = wrtee(0); 583 e500_splset(ci, ipl); 584 #if 1 585 if (old_ipl < IPL_VM && ipl >= IPL_VM) 586 msr = 0; 587 #endif 588 wrtee(msr); 589 } else if (ipl == IPL_NONE) { 590 panic("%s: %p: cpl=%u: attempt to splraise(IPL_NONE)", 591 __func__, __builtin_return_address(0), old_ipl); 592 #if 0 593 } else if (old_ipl > ipl) { 594 printf("%s: %p: cpl=%u: ignoring splraise(%u) to lower ipl\n", 595 __func__, __builtin_return_address(0), old_ipl, ipl); 596 #endif 597 } 598 599 return old_ipl; 600 } 601 602 #ifdef __HAVE_FAST_SOFTINTS 603 static void 604 e500_softint_init_md(lwp_t *l, u_int si_level, uintptr_t *machdep_p) 605 { 606 struct cpu_info * const ci = l->l_cpu; 607 struct cpu_softc * const cpu = ci->ci_softc; 608 609 *machdep_p = 1 << SOFTINT2IPL(si_level); 610 KASSERT(*machdep_p & IPL_SOFTMASK); 611 cpu->cpu_softlwps[si_level] = l; 612 } 613 614 static void 615 e500_softint_trigger(uintptr_t machdep) 616 { 617 struct cpu_info * const ci = curcpu(); 618 619 atomic_or_uint(&ci->ci_data.cpu_softints, machdep); 620 } 621 #endif /* __HAVE_FAST_SOFTINTS */ 622 623 static int 624 e500_intr_spurious(void *arg) 625 { 626 return 0; 627 } 628 629 static bool 630 e500_intr_irq_info_get(struct cpu_info *ci, u_int irq, int ipl, int ist, 631 struct e500_intr_irq_info *ii) 632 { 633 const struct e500_intr_info * const info = &e500_intr_info; 634 bool ok; 635 636 #if DEBUG > 2 637 printf("%s(%p,irq=%u,ipl=%u,ist=%u,%p)\n", __func__, ci, irq, ipl, ist, ii); 638 #endif 639 640 if (ipl < IPL_VM || ipl > IPL_HIGH) { 641 #if DEBUG > 2 642 printf("%s:%d ipl=%u\n", __func__, __LINE__, ipl); 643 #endif 644 return false; 645 } 646 647 if (ist <= IST_NONE || ist >= IST_MAX) { 648 #if DEBUG > 2 649 printf("%s:%d ist=%u\n", __func__, __LINE__, ist); 650 #endif 651 return false; 652 } 653 654 ii->irq_vector = irq + info->ii_ist_vectors[ist]; 655 if (IST_PERCPU_P(ist)) 656 ii->irq_vector += ci->ci_cpuid * info->ii_percpu_sources; 657 658 switch (ist) { 659 default: 660 ii->irq_vpr = OPENPIC_EIVPR(irq); 661 ii->irq_dr = OPENPIC_EIDR(irq); 662 ok = irq < info->ii_external_sources 663 && (ist == IST_EDGE 664 || ist == IST_LEVEL_LOW 665 || ist == IST_LEVEL_HIGH); 666 break; 667 case IST_ONCHIP: 668 ii->irq_vpr = OPENPIC_IIVPR(irq); 669 ii->irq_dr = OPENPIC_IIDR(irq); 670 ok = irq < 32 * __arraycount(info->ii_onchip_bitmap); 671 #if DEBUG > 2 672 printf("%s: irq=%u: ok=%u\n", __func__, irq, ok); 673 #endif 674 ok = ok && (info->ii_onchip_bitmap[irq/32] & (1 << (irq & 31))); 675 #if DEBUG > 2 676 printf("%s: %08x%08x -> %08x%08x: ok=%u\n", __func__, 677 irq < 32 ? 0 : (1 << irq), irq < 32 ? (1 << irq) : 0, 678 info->ii_onchip_bitmap[1], info->ii_onchip_bitmap[0], 679 ok); 680 #endif 681 break; 682 case IST_MSIGROUP: 683 ii->irq_vpr = OPENPIC_MSIVPR(irq); 684 ii->irq_dr = OPENPIC_MSIDR(irq); 685 ok = irq < info->ii_msigroup_sources 686 && ipl == IPL_VM; 687 break; 688 case IST_TIMER: 689 ii->irq_vpr = OPENPIC_GTVPR(ci->ci_cpuid, irq); 690 ii->irq_dr = OPENPIC_GTDR(ci->ci_cpuid, irq); 691 ok = irq < info->ii_timer_sources; 692 #if DEBUG > 2 693 printf("%s: IST_TIMER irq=%u: ok=%u\n", __func__, irq, ok); 694 #endif 695 break; 696 case IST_IPI: 697 ii->irq_vpr = OPENPIC_IPIVPR(irq); 698 ii->irq_dr = OPENPIC_IPIDR(irq); 699 ok = irq < info->ii_ipi_sources; 700 break; 701 case IST_MI: 702 ii->irq_vpr = OPENPIC_MIVPR(irq); 703 ii->irq_dr = OPENPIC_MIDR(irq); 704 ok = irq < info->ii_mi_sources; 705 break; 706 } 707 708 return ok; 709 } 710 711 static const char * 712 e500_intr_string(int irq, int ist) 713 { 714 struct cpu_info * const ci = curcpu(); 715 struct cpu_softc * const cpu = ci->ci_softc; 716 struct e500_intr_irq_info ii; 717 718 if (!e500_intr_irq_info_get(ci, irq, IPL_VM, ist, &ii)) 719 return NULL; 720 721 return cpu->cpu_evcnt_intrs[ii.irq_vector].ev_name; 722 } 723 724 static void * 725 e500_intr_cpu_establish(struct cpu_info *ci, int irq, int ipl, int ist, 726 int (*handler)(void *), void *arg) 727 { 728 struct cpu_softc * const cpu = ci->ci_softc; 729 struct e500_intr_irq_info ii; 730 731 KASSERT(ipl >= IPL_VM && ipl <= IPL_HIGH); 732 KASSERT(ist > IST_NONE && ist < IST_MAX && ist != IST_MSI); 733 734 if (!e500_intr_irq_info_get(ci, irq, ipl, ist, &ii)) { 735 printf("%s: e500_intr_irq_info_get(%p,%u,%u,%u,%p) failed\n", 736 __func__, ci, irq, ipl, ist, &ii); 737 return NULL; 738 } 739 740 struct intr_source * const is = &e500_intr_sources[ii.irq_vector]; 741 mutex_enter(&e500_intr_lock); 742 if (is->is_ipl != IPL_NONE) 743 return NULL; 744 745 is->is_func = handler; 746 is->is_arg = arg; 747 is->is_ipl = ipl; 748 is->is_ist = ist; 749 is->is_irq = irq; 750 is->is_vpr = ii.irq_vpr; 751 is->is_dr = ii.irq_dr; 752 753 uint32_t vpr = VPR_PRIORITY_MAKE(IPL2CTPR(ipl)) 754 | VPR_VECTOR_MAKE(((ii.irq_vector + 1) << 4) | ipl) 755 | (ist == IST_LEVEL_LOW 756 ? VPR_LEVEL_LOW 757 : (ist == IST_LEVEL_HIGH 758 ? VPR_LEVEL_HIGH 759 : (ist == IST_ONCHIP 760 ? VPR_P_HIGH 761 : 0))); 762 763 /* 764 * All interrupts go to the primary except per-cpu interrupts which get 765 * routed to the appropriate cpu. 766 */ 767 uint32_t dr = IST_PERCPU_P(ist) ? 1 << ci->ci_cpuid : 1; 768 769 /* 770 * Update the vector/priority and destination registers keeping the 771 * interrupt masked. 772 */ 773 const register_t msr = wrtee(0); /* disable interrupts */ 774 openpic_write(cpu, ii.irq_vpr, vpr | VPR_MSK); 775 openpic_write(cpu, ii.irq_dr, dr); 776 777 /* 778 * Now unmask the interrupt. 779 */ 780 openpic_write(cpu, ii.irq_vpr, vpr); 781 782 wrtee(msr); /* re-enable interrupts */ 783 784 mutex_exit(&e500_intr_lock); 785 786 return is; 787 } 788 789 static void * 790 e500_intr_establish(int irq, int ipl, int ist, 791 int (*handler)(void *), void *arg) 792 { 793 return e500_intr_cpu_establish(curcpu(), irq, ipl, ist, handler, arg); 794 } 795 796 static void 797 e500_intr_disestablish(void *vis) 798 { 799 struct cpu_softc * const cpu = curcpu()->ci_softc; 800 struct intr_source * const is = vis; 801 struct e500_intr_irq_info ii; 802 803 KASSERT(e500_intr_sources <= is); 804 KASSERT(is < e500_intr_last_source); 805 KASSERT(!cpu_intr_p()); 806 807 bool ok = e500_intr_irq_info_get(curcpu(), is->is_irq, is->is_ipl, 808 is->is_ist, &ii); 809 (void)ok; /* appease gcc */ 810 KASSERT(ok); 811 KASSERT(is - e500_intr_sources == ii.irq_vector); 812 813 mutex_enter(&e500_intr_lock); 814 /* 815 * Mask the source using the mask (MSK) bit in the vector/priority reg. 816 */ 817 uint32_t vpr = openpic_read(cpu, ii.irq_vpr); 818 openpic_write(cpu, ii.irq_vpr, VPR_MSK | vpr); 819 820 /* 821 * Wait for the Activity (A) bit for the source to be cleared. 822 */ 823 while (openpic_read(cpu, ii.irq_vpr) & VPR_A) 824 ; 825 826 /* 827 * Now the source can be modified. 828 */ 829 openpic_write(cpu, ii.irq_dr, 0); /* stop delivery */ 830 openpic_write(cpu, ii.irq_vpr, VPR_MSK); /* mask/reset it */ 831 832 *is = (struct intr_source)INTR_SOURCE_INITIALIZER; 833 834 mutex_exit(&e500_intr_lock); 835 } 836 837 static void 838 e500_critintr(struct trapframe *tf) 839 { 840 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 841 } 842 843 static void 844 e500_decrintr(struct trapframe *tf) 845 { 846 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 847 } 848 849 static void 850 e500_fitintr(struct trapframe *tf) 851 { 852 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 853 } 854 855 static void 856 e500_wdogintr(struct trapframe *tf) 857 { 858 mtspr(SPR_TSR, TSR_ENW|TSR_WIS); 859 panic("%s: tf=%p tb=%"PRId64" srr0/srr1=%#lx/%#lx", __func__, tf, 860 mftb(), tf->tf_srr0, tf->tf_srr1); 861 } 862 863 static void 864 e500_extintr(struct trapframe *tf) 865 { 866 struct cpu_info * const ci = curcpu(); 867 struct cpu_softc * const cpu = ci->ci_softc; 868 const int old_ipl = ci->ci_cpl; 869 870 KASSERT(mfmsr() & PSL_CE); 871 872 #if 0 873 // printf("%s(%p): idepth=%d enter\n", __func__, tf, ci->ci_idepth); 874 if ((register_t)tf >= (register_t)curlwp->l_addr + USPACE 875 || (register_t)tf < (register_t)curlwp->l_addr + NBPG) { 876 printf("%s(entry): pid %d.%d (%s): srr0/srr1=%#lx/%#lx: invalid tf addr %p\n", 877 __func__, curlwp->l_proc->p_pid, curlwp->l_lid, 878 curlwp->l_proc->p_comm, tf->tf_srr0, tf->tf_srr1, tf); 879 } 880 #endif 881 882 883 ci->ci_data.cpu_nintr++; 884 tf->tf_cf.cf_idepth = ci->ci_idepth++; 885 cpu->cpu_pcpls[ci->ci_idepth] = old_ipl; 886 #if 1 887 if (mfmsr() & PSL_EE) 888 panic("%s(%p): MSR[EE] is on (%#lx)!", __func__, tf, mfmsr()); 889 if (old_ipl == IPL_HIGH 890 || IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 891 panic("%s(%p): old_ipl(%u) == IPL_HIGH(%u) " 892 "|| old_ipl + %u != OPENPIC_CTPR (%u)", 893 __func__, tf, old_ipl, IPL_HIGH, 894 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 895 #else 896 if (old_ipl >= IPL_VM) 897 panic("%s(%p): old_ipl(%u) >= IPL_VM(%u) CTPR=%u", 898 __func__, tf, old_ipl, IPL_VM, openpic_read(cpu, OPENPIC_CTPR)); 899 #endif 900 901 for (;;) { 902 /* 903 * Find out the pending interrupt. 904 */ 905 if (mfmsr() & PSL_EE) 906 panic("%s(%p): MSR[EE] turned on (%#lx)!", __func__, tf, mfmsr()); 907 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 908 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 909 __func__, tf, __LINE__, old_ipl, 910 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 911 const uint32_t iack = openpic_read(cpu, OPENPIC_IACK); 912 #ifdef DIAGNOSTIC 913 const int ipl = iack & 0xf; 914 #endif 915 const int irq = (iack >> 4) - 1; 916 #if 0 917 printf("%s: iack=%d ipl=%d irq=%d <%s>\n", 918 __func__, iack, ipl, irq, 919 (iack != IRQ_SPURIOUS ? 920 cpu->cpu_evcnt_intrs[irq].ev_name : "spurious")); 921 #endif 922 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 923 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 924 __func__, tf, __LINE__, old_ipl, 925 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 926 if (iack == IRQ_SPURIOUS) 927 break; 928 929 struct intr_source * const is = &e500_intr_sources[irq]; 930 if (__predict_true(is < e500_intr_last_source)) { 931 /* 932 * Timer interrupts get their argument overriden with 933 * the pointer to the trapframe. 934 */ 935 KASSERT(is->is_ipl == ipl); 936 void *arg = (is->is_ist == IST_TIMER ? tf : is->is_arg); 937 if (is->is_ipl <= old_ipl) 938 panic("%s(%p): %s (%u): is->is_ipl (%u) <= old_ipl (%u)\n", 939 __func__, tf, 940 cpu->cpu_evcnt_intrs[irq].ev_name, irq, 941 is->is_ipl, old_ipl); 942 KASSERT(is->is_ipl > old_ipl); 943 e500_splset(ci, is->is_ipl); /* change IPL */ 944 if (__predict_false(is->is_func == NULL)) { 945 aprint_error_dev(ci->ci_dev, 946 "interrupt from unestablished irq %d\n", 947 irq); 948 } else { 949 int (*func)(void *) = is->is_func; 950 wrtee(PSL_EE); 951 int rv = (*func)(arg); 952 wrtee(0); 953 #if DEBUG > 2 954 printf("%s: %s handler %p(%p) returned %d\n", 955 __func__, 956 cpu->cpu_evcnt_intrs[irq].ev_name, 957 func, arg, rv); 958 #endif 959 if (rv == 0) 960 cpu->cpu_evcnt_spurious_intr.ev_count++; 961 } 962 e500_splset(ci, old_ipl); /* restore IPL */ 963 cpu->cpu_evcnt_intrs[irq].ev_count++; 964 } else { 965 aprint_error_dev(ci->ci_dev, 966 "interrupt from illegal irq %d\n", irq); 967 cpu->cpu_evcnt_spurious_intr.ev_count++; 968 } 969 /* 970 * If this is a nested interrupt, simply ack it and exit 971 * because the loop we interrupted will complete looking 972 * for interrupts. 973 */ 974 if (mfmsr() & PSL_EE) 975 panic("%s(%p): MSR[EE] left on (%#lx)!", __func__, tf, mfmsr()); 976 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 977 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 978 __func__, tf, __LINE__, old_ipl, 979 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 980 981 openpic_write(cpu, OPENPIC_EOI, 0); 982 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 983 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 984 __func__, tf, __LINE__, old_ipl, 985 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 986 if (ci->ci_idepth > 0) 987 break; 988 } 989 990 ci->ci_idepth--; 991 992 #ifdef __HAVE_FAST_SOFTINTS 993 /* 994 * Before exiting, deal with any softints that need to be dealt with. 995 */ 996 const u_int softints = (ci->ci_data.cpu_softints << old_ipl) & IPL_SOFTMASK; 997 if (__predict_false(softints != 0)) { 998 KASSERT(old_ipl < IPL_VM); 999 e500_splset(ci, IPL_HIGH); /* pop to high */ 1000 e500_softint(ci, cpu, old_ipl); /* deal with them */ 1001 e500_splset(ci, old_ipl); /* and drop back */ 1002 } 1003 #endif /* __HAVE_FAST_SOFTINTS */ 1004 #if 1 1005 KASSERT(ci->ci_cpl == old_ipl); 1006 #else 1007 e500_splset(ci, old_ipl); /* and drop back */ 1008 #endif 1009 1010 // printf("%s(%p): idepth=%d exit\n", __func__, tf, ci->ci_idepth); 1011 } 1012 1013 static void 1014 e500_intr_init(void) 1015 { 1016 struct cpu_info * const ci = curcpu(); 1017 struct cpu_softc * const cpu = ci->ci_softc; 1018 const uint32_t frr = openpic_read(cpu, OPENPIC_FRR); 1019 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1020 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1021 struct intr_source *is; 1022 struct e500_intr_info * const ii = &e500_intr_info; 1023 1024 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 1025 switch (svr) { 1026 #ifdef MPC8536 1027 case SVR_MPC8536v1 >> 16: 1028 *ii = mpc8536_intr_info; 1029 break; 1030 #endif 1031 #ifdef MPC8544 1032 case SVR_MPC8544v1 >> 16: 1033 *ii = mpc8544_intr_info; 1034 break; 1035 #endif 1036 #ifdef MPC8548 1037 case SVR_MPC8543v1 >> 16: 1038 case SVR_MPC8548v1 >> 16: 1039 *ii = mpc8548_intr_info; 1040 break; 1041 #endif 1042 #ifdef MPC8555 1043 case SVR_MPC8541v1 >> 16: 1044 case SVR_MPC8555v1 >> 16: 1045 *ii = mpc8555_intr_info; 1046 break; 1047 #endif 1048 #ifdef MPC8568 1049 case SVR_MPC8568v1 >> 16: 1050 *ii = mpc8568_intr_info; 1051 break; 1052 #endif 1053 #ifdef MPC8572 1054 case SVR_MPC8572v1 >> 16: 1055 *ii = mpc8572_intr_info; 1056 break; 1057 #endif 1058 #ifdef P2020 1059 case SVR_P2010v2 >> 16: 1060 case SVR_P2020v2 >> 16: 1061 *ii = p20x0_intr_info; 1062 break; 1063 #endif 1064 default: 1065 panic("%s: don't know how to deal with SVR %#lx", 1066 __func__, mfspr(SPR_SVR)); 1067 } 1068 1069 /* 1070 * We need to be in mixed mode. 1071 */ 1072 openpic_write(cpu, OPENPIC_GCR, GCR_M); 1073 1074 /* 1075 * Make we and the openpic both agree about the current SPL level. 1076 */ 1077 e500_splset(ci, ci->ci_cpl); 1078 1079 /* 1080 * Allow the required number of interrupt sources. 1081 */ 1082 is = kmem_zalloc(nirq * sizeof(*is), KM_SLEEP); 1083 KASSERT(is); 1084 e500_intr_sources = is; 1085 e500_intr_last_source = is + nirq; 1086 1087 /* 1088 * Initialize all the external interrupts as active low. 1089 */ 1090 for (u_int irq = 0; irq < e500_intr_info.ii_external_sources; irq++) { 1091 openpic_write(cpu, OPENPIC_EIVPR(irq), 1092 VPR_VECTOR_MAKE(irq) | VPR_LEVEL_LOW); 1093 } 1094 } 1095 1096 static void 1097 e500_intr_cpu_init(struct cpu_info *ci) 1098 { 1099 struct cpu_softc * const cpu = ci->ci_softc; 1100 const char * const xname = device_xname(ci->ci_dev); 1101 1102 const u_int32_t frr = openpic_read(cpu, OPENPIC_FRR); 1103 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1104 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1105 1106 const struct e500_intr_info * const info = &e500_intr_info; 1107 1108 cpu->cpu_clock_gtbcr = OPENPIC_GTBCR(ci->ci_cpuid, E500_CLOCK_TIMER); 1109 1110 cpu->cpu_evcnt_intrs = 1111 kmem_zalloc(nirq * sizeof(cpu->cpu_evcnt_intrs[0]), KM_SLEEP); 1112 KASSERT(cpu->cpu_evcnt_intrs); 1113 1114 struct evcnt *evcnt = cpu->cpu_evcnt_intrs; 1115 for (size_t j = 0; j < info->ii_external_sources; j++, evcnt++) { 1116 const char *name = e500_intr_external_name_lookup(j); 1117 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, NULL, xname, name); 1118 } 1119 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_ONCHIP]); 1120 for (size_t j = 0; j < info->ii_onchip_sources; j++, evcnt++) { 1121 if (info->ii_onchip_bitmap[j / 32] & __BIT(j & 31)) { 1122 const char *name = e500_intr_onchip_name_lookup(j); 1123 if (name != NULL) { 1124 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1125 NULL, xname, name); 1126 #ifdef DIAGNOSTIC 1127 } else { 1128 printf("%s: missing evcnt for onchip irq %zu\n", 1129 __func__, j); 1130 #endif 1131 } 1132 } 1133 } 1134 1135 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_MSIGROUP]); 1136 for (size_t j = 0; j < info->ii_msigroup_sources; j++, evcnt++) { 1137 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1138 NULL, xname, e500_msigroup_intr_names[j].in_name); 1139 } 1140 1141 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_TIMER]); 1142 evcnt += ci->ci_cpuid * info->ii_percpu_sources; 1143 for (size_t j = 0; j < info->ii_timer_sources; j++, evcnt++) { 1144 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1145 NULL, xname, e500_timer_intr_names[j].in_name); 1146 } 1147 1148 for (size_t j = 0; j < info->ii_ipi_sources; j++, evcnt++) { 1149 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1150 NULL, xname, e500_ipi_intr_names[j].in_name); 1151 } 1152 1153 for (size_t j = 0; j < info->ii_mi_sources; j++, evcnt++) { 1154 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1155 NULL, xname, e500_mi_intr_names[j].in_name); 1156 } 1157 1158 /* 1159 * Establish interrupt for this CPU. 1160 */ 1161 if (e500_intr_cpu_establish(ci, E500_CLOCK_TIMER, IPL_CLOCK, IST_TIMER, 1162 e500_clock_intr, NULL) == NULL) 1163 panic("%s: failed to establish clock interrupt!", __func__); 1164 1165 /* 1166 * Enable watchdog interrupts. 1167 */ 1168 uint32_t tcr = mfspr(SPR_TCR); 1169 tcr |= TCR_WIE; 1170 mtspr(SPR_TCR, tcr); 1171 } 1172
Indexes created Mon Sep 29 21:09:56 GMT 2025