e500_intr.c revision 1.8
1 /* $NetBSD: e500_intr.c,v 1.8 2011/06/05 16:52:24 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include "opt_mpc85xx.h" 38 39 #define __INTR_PRIVATE 40 41 #include <sys/param.h> 42 #include <sys/proc.h> 43 #include <sys/intr.h> 44 #include <sys/cpu.h> 45 #include <sys/kmem.h> 46 #include <sys/atomic.h> 47 #include <sys/bus.h> 48 #include <sys/xcall.h> 49 #include <sys/bitops.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <powerpc/spr.h> 54 #include <powerpc/booke/spr.h> 55 56 #include <powerpc/booke/cpuvar.h> 57 #include <powerpc/booke/e500reg.h> 58 #include <powerpc/booke/e500var.h> 59 #include <powerpc/booke/openpicreg.h> 60 61 #define IPL2CTPR(ipl) ((ipl) + 15 - IPL_HIGH) 62 #define CTPR2IPL(ctpr) ((ctpr) - (15 - IPL_HIGH)) 63 64 #define IST_PERCPU_P(ist) ((ist) >= IST_TIMER) 65 66 #ifdef __HAVE_PREEMPTION 67 #define IPL_PREEMPT_SOFTMASK (1 << IPL_NONE) 68 #else 69 #define IPL_PREEMPT_SOFTMASK 0 70 #endif 71 72 #define IPL_SOFTMASK \ 73 ((1 << IPL_SOFTSERIAL) | (1 << IPL_SOFTNET ) \ 74 |(1 << IPL_SOFTBIO ) | (1 << IPL_SOFTCLOCK ) \ 75 |IPL_PREEMPT_SOFTMASK) 76 77 #define SOFTINT2IPL_MAP \ 78 ((IPL_SOFTSERIAL << (4*SOFTINT_SERIAL)) \ 79 |(IPL_SOFTNET << (4*SOFTINT_NET )) \ 80 |(IPL_SOFTBIO << (4*SOFTINT_BIO )) \ 81 |(IPL_SOFTCLOCK << (4*SOFTINT_CLOCK ))) 82 #define SOFTINT2IPL(si_level) ((SOFTINT2IPL_MAP >> (4 * si_level)) & 0x0f) 83 84 struct e500_intr_irq_info { 85 bus_addr_t irq_vpr; 86 bus_addr_t irq_dr; 87 u_int irq_vector; 88 }; 89 90 struct intr_source { 91 int (*is_func)(void *); 92 void *is_arg; 93 int8_t is_ipl; 94 uint8_t is_ist; 95 uint8_t is_irq; 96 bus_size_t is_vpr; 97 bus_size_t is_dr; 98 }; 99 100 #define INTR_SOURCE_INITIALIZER \ 101 { .is_func = e500_intr_spurious, .is_arg = NULL, \ 102 .is_irq = -1, .is_ipl = IPL_NONE, .is_ist = IST_NONE, } 103 104 struct e500_intr_name { 105 uint8_t in_irq; 106 const char in_name[15]; 107 }; 108 109 static const struct e500_intr_name e500_onchip_intr_names[] = { 110 { ISOURCE_L2, "l2" }, 111 { ISOURCE_ECM, "ecm" }, 112 { ISOURCE_DDR, "ddr" }, 113 { ISOURCE_LBC, "lbc" }, 114 { ISOURCE_DMA_CHAN1, "dma-chan1" }, 115 { ISOURCE_DMA_CHAN2, "dma-chan2" }, 116 { ISOURCE_DMA_CHAN3, "dma-chan3" }, 117 { ISOURCE_DMA_CHAN4, "dma-chan4" }, 118 { ISOURCE_PCI1, "pci1" }, 119 { ISOURCE_PCIEX2, "pcie2" }, 120 { ISOURCE_PCIEX , "pcie1" }, 121 { ISOURCE_PCIEX3, "pcie3" }, 122 { ISOURCE_USB1, "usb1" }, 123 { ISOURCE_ETSEC1_TX, "etsec1-tx" }, 124 { ISOURCE_ETSEC1_RX, "etsec1-rx" }, 125 { ISOURCE_ETSEC3_TX, "etsec3-tx" }, 126 { ISOURCE_ETSEC3_RX, "etsec3-rx" }, 127 { ISOURCE_ETSEC3_ERR, "etsec3-err" }, 128 { ISOURCE_ETSEC1_ERR, "etsec1-err" }, 129 { ISOURCE_ETSEC2_TX, "etsec2-tx" }, 130 { ISOURCE_ETSEC2_RX, "etsec2-rx" }, 131 { ISOURCE_ETSEC4_TX, "etsec4-tx" }, 132 { ISOURCE_ETSEC4_RX, "etsec4-rx" }, 133 { ISOURCE_ETSEC4_ERR, "etsec4-err" }, 134 { ISOURCE_ETSEC2_ERR, "etsec2-err" }, 135 { ISOURCE_DUART, "duart" }, 136 { ISOURCE_I2C, "i2c" }, 137 { ISOURCE_PERFMON, "perfmon" }, 138 { ISOURCE_SECURITY1, "sec1" }, 139 { ISOURCE_GPIO, "gpio" }, 140 { ISOURCE_SRIO_EWPU, "srio-ewpu" }, 141 { ISOURCE_SRIO_ODBELL, "srio-odbell" }, 142 { ISOURCE_SRIO_IDBELL, "srio-idbell" }, 143 { ISOURCE_SRIO_OMU1, "srio-omu1" }, 144 { ISOURCE_SRIO_IMU1, "srio-imu1" }, 145 { ISOURCE_SRIO_OMU2, "srio-omu2" }, 146 { ISOURCE_SRIO_IMU2, "srio-imu2" }, 147 { ISOURCE_SECURITY2, "sec2" }, 148 { ISOURCE_SPI, "spi" }, 149 { ISOURCE_ETSEC1_PTP, "etsec1-ptp" }, 150 { ISOURCE_ETSEC2_PTP, "etsec2-ptp" }, 151 { ISOURCE_ETSEC3_PTP, "etsec3-ptp" }, 152 { ISOURCE_ETSEC4_PTP, "etsec4-ptp" }, 153 { ISOURCE_ESDHC, "esdhc" }, 154 { 0, "" }, 155 }; 156 157 const struct e500_intr_name default_external_intr_names[] = { 158 { 0, "" }, 159 }; 160 161 static const struct e500_intr_name e500_msigroup_intr_names[] = { 162 { 0, "msigroup0" }, 163 { 1, "msigroup1" }, 164 { 2, "msigroup2" }, 165 { 3, "msigroup3" }, 166 { 4, "msigroup4" }, 167 { 5, "msigroup5" }, 168 { 6, "msigroup6" }, 169 { 7, "msigroup7" }, 170 { 0, "" }, 171 }; 172 173 static const struct e500_intr_name e500_timer_intr_names[] = { 174 { 0, "timer0" }, 175 { 1, "timer1" }, 176 { 2, "timer2" }, 177 { 3, "timer3" }, 178 { 0, "" }, 179 }; 180 181 static const struct e500_intr_name e500_ipi_intr_names[] = { 182 { 0, "ipi0" }, 183 { 1, "ipi1" }, 184 { 2, "ipi2" }, 185 { 3, "ipi3" }, 186 { 0, "" }, 187 }; 188 189 static const struct e500_intr_name e500_mi_intr_names[] = { 190 { 0, "mi0" }, 191 { 1, "mi1" }, 192 { 2, "mi2" }, 193 { 3, "mi3" }, 194 { 0, "" }, 195 }; 196 197 struct e500_intr_info { 198 u_int ii_external_sources; 199 uint32_t ii_onchip_bitmap[2]; 200 u_int ii_onchip_sources; 201 u_int ii_msigroup_sources; 202 u_int ii_ipi_sources; /* per-cpu */ 203 u_int ii_timer_sources; /* per-cpu */ 204 u_int ii_mi_sources; /* per-cpu */ 205 u_int ii_percpu_sources; 206 const struct e500_intr_name *ii_external_intr_names; 207 const struct e500_intr_name *ii_onchip_intr_names; 208 u_int8_t ii_ist_vectors[IST_MAX+1]; 209 }; 210 211 static kmutex_t e500_intr_lock __cacheline_aligned; 212 static struct e500_intr_info e500_intr_info; 213 214 #define INTR_INFO_DECL(lc_chip, UC_CHIP) \ 215 static const struct e500_intr_info lc_chip##_intr_info = { \ 216 .ii_external_sources = UC_CHIP ## _EXTERNALSOURCES, \ 217 .ii_onchip_bitmap = UC_CHIP ## _ONCHIPBITMAP, \ 218 .ii_onchip_sources = UC_CHIP ## _ONCHIPSOURCES, \ 219 .ii_msigroup_sources = UC_CHIP ## _MSIGROUPSOURCES, \ 220 .ii_timer_sources = UC_CHIP ## _TIMERSOURCES, \ 221 .ii_ipi_sources = UC_CHIP ## _IPISOURCES, \ 222 .ii_mi_sources = UC_CHIP ## _MISOURCES, \ 223 .ii_percpu_sources = UC_CHIP ## _TIMERSOURCES \ 224 + UC_CHIP ## _IPISOURCES + UC_CHIP ## _MISOURCES, \ 225 .ii_external_intr_names = lc_chip ## _external_intr_names, \ 226 .ii_onchip_intr_names = lc_chip ## _onchip_intr_names, \ 227 .ii_ist_vectors = { \ 228 [IST_NONE] = ~0, \ 229 [IST_EDGE] = 0, \ 230 [IST_LEVEL_LOW] = 0, \ 231 [IST_LEVEL_HIGH] = 0, \ 232 [IST_ONCHIP] = UC_CHIP ## _EXTERNALSOURCES, \ 233 [IST_MSIGROUP] = UC_CHIP ## _EXTERNALSOURCES \ 234 + UC_CHIP ## _ONCHIPSOURCES, \ 235 [IST_TIMER] = UC_CHIP ## _EXTERNALSOURCES \ 236 + UC_CHIP ## _ONCHIPSOURCES \ 237 + UC_CHIP ## _MSIGROUPSOURCES, \ 238 [IST_IPI] = UC_CHIP ## _EXTERNALSOURCES \ 239 + UC_CHIP ## _ONCHIPSOURCES \ 240 + UC_CHIP ## _MSIGROUPSOURCES \ 241 + UC_CHIP ## _TIMERSOURCES, \ 242 [IST_MI] = UC_CHIP ## _EXTERNALSOURCES \ 243 + UC_CHIP ## _ONCHIPSOURCES \ 244 + UC_CHIP ## _MSIGROUPSOURCES \ 245 + UC_CHIP ## _TIMERSOURCES \ 246 + UC_CHIP ## _IPISOURCES, \ 247 [IST_MAX] = UC_CHIP ## _EXTERNALSOURCES \ 248 + UC_CHIP ## _ONCHIPSOURCES \ 249 + UC_CHIP ## _MSIGROUPSOURCES \ 250 + UC_CHIP ## _TIMERSOURCES \ 251 + UC_CHIP ## _IPISOURCES \ 252 + UC_CHIP ## _MISOURCES, \ 253 }, \ 254 } 255 256 #ifdef MPC8536 257 #define mpc8536_external_intr_names default_external_intr_names 258 const struct e500_intr_name mpc8536_onchip_intr_names[] = { 259 { ISOURCE_SATA2, "sata2" }, 260 { ISOURCE_USB2, "usb2" }, 261 { ISOURCE_USB3, "usb3" }, 262 { ISOURCE_SATA1, "sata1" }, 263 { 0, "" }, 264 }; 265 266 INTR_INFO_DECL(mpc8536, MPC8536); 267 #endif 268 269 #ifdef MPC8544 270 #define mpc8544_external_intr_names default_external_intr_names 271 const struct e500_intr_name mpc8544_onchip_intr_names[] = { 272 { 0, "" }, 273 }; 274 275 INTR_INFO_DECL(mpc8544, MPC8544); 276 #endif 277 #ifdef MPC8548 278 #define mpc8548_external_intr_names default_external_intr_names 279 const struct e500_intr_name mpc8548_onchip_intr_names[] = { 280 { ISOURCE_PCI1, "pci1" }, 281 { ISOURCE_PCI2, "pci2" }, 282 { 0, "" }, 283 }; 284 285 INTR_INFO_DECL(mpc8548, MPC8548); 286 #endif 287 #ifdef MPC8555 288 #define mpc8555_external_intr_names default_external_intr_names 289 const struct e500_intr_name mpc8555_onchip_intr_names[] = { 290 { ISOURCE_PCI2, "pci2" }, 291 { ISOURCE_CPM, "CPM" }, 292 { 0, "" }, 293 }; 294 295 INTR_INFO_DECL(mpc8555, MPC8555); 296 #endif 297 #ifdef MPC8568 298 #define mpc8568_external_intr_names default_external_intr_names 299 const struct e500_intr_name mpc8568_onchip_intr_names[] = { 300 { ISOURCE_QEB_LOW, "QEB low" }, 301 { ISOURCE_QEB_PORT, "QEB port" }, 302 { ISOURCE_QEB_IECC, "QEB iram ecc" }, 303 { ISOURCE_QEB_MUECC, "QEB ram ecc" }, 304 { ISOURCE_TLU1, "tlu1" }, 305 { ISOURCE_QEB_HIGH, "QEB high" }, 306 { 0, "" }, 307 }; 308 309 INTR_INFO_DECL(mpc8568, MPC8568); 310 #endif 311 #ifdef MPC8572 312 #define mpc8572_external_intr_names default_external_intr_names 313 const struct e500_intr_name mpc8572_onchip_intr_names[] = { 314 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 315 { ISOURCE_FEC, "fec" }, 316 { ISOURCE_PME_GENERAL, "pme" }, 317 { ISOURCE_TLU1, "tlu1" }, 318 { ISOURCE_TLU2, "tlu2" }, 319 { ISOURCE_PME_CHAN1, "pme-chan1" }, 320 { ISOURCE_PME_CHAN2, "pme-chan2" }, 321 { ISOURCE_PME_CHAN3, "pme-chan3" }, 322 { ISOURCE_PME_CHAN4, "pme-chan4" }, 323 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 324 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 325 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 326 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 327 { 0, "" }, 328 }; 329 330 INTR_INFO_DECL(mpc8572, MPC8572); 331 #endif 332 #ifdef P2020 333 #define p20x0_external_intr_names default_external_intr_names 334 const struct e500_intr_name p20x0_onchip_intr_names[] = { 335 { ISOURCE_PCIEX3_MPC8572, "pcie3" }, 336 { ISOURCE_DMA2_CHAN1, "dma2-chan1" }, 337 { ISOURCE_DMA2_CHAN2, "dma2-chan2" }, 338 { ISOURCE_DMA2_CHAN3, "dma2-chan3" }, 339 { ISOURCE_DMA2_CHAN4, "dma2-chan4" }, 340 { 0, "" }, 341 }; 342 343 INTR_INFO_DECL(p20x0, P20x0); 344 #endif 345 346 static const char ist_names[][12] = { 347 [IST_NONE] = "none", 348 [IST_EDGE] = "edge", 349 [IST_LEVEL_LOW] = "level-", 350 [IST_LEVEL_HIGH] = "level+", 351 [IST_MSI] = "msi", 352 [IST_ONCHIP] = "onchip", 353 [IST_MSIGROUP] = "msigroup", 354 [IST_TIMER] = "timer", 355 [IST_IPI] = "ipi", 356 [IST_MI] = "msgint", 357 }; 358 359 static struct intr_source *e500_intr_sources; 360 static const struct intr_source *e500_intr_last_source; 361 362 static void *e500_intr_establish(int, int, int, int (*)(void *), void *); 363 static void e500_intr_disestablish(void *); 364 static void e500_intr_cpu_attach(struct cpu_info *ci); 365 static void e500_intr_cpu_hatch(struct cpu_info *ci); 366 static void e500_intr_cpu_send_ipi(cpuid_t, uintptr_t); 367 static void e500_intr_init(void); 368 static const char *e500_intr_string(int, int); 369 static void e500_critintr(struct trapframe *tf); 370 static void e500_decrintr(struct trapframe *tf); 371 static void e500_extintr(struct trapframe *tf); 372 static void e500_fitintr(struct trapframe *tf); 373 static void e500_wdogintr(struct trapframe *tf); 374 static void e500_spl0(void); 375 static int e500_splraise(int); 376 static void e500_splx(int); 377 #ifdef __HAVE_FAST_SOFTINTS 378 static void e500_softint_init_md(lwp_t *l, u_int si_level, uintptr_t *machdep_p); 379 static void e500_softint_trigger(uintptr_t machdep); 380 #endif 381 382 const struct intrsw e500_intrsw = { 383 .intrsw_establish = e500_intr_establish, 384 .intrsw_disestablish = e500_intr_disestablish, 385 .intrsw_init = e500_intr_init, 386 .intrsw_cpu_attach = e500_intr_cpu_attach, 387 .intrsw_cpu_hatch = e500_intr_cpu_hatch, 388 .intrsw_cpu_send_ipi = e500_intr_cpu_send_ipi, 389 .intrsw_string = e500_intr_string, 390 391 .intrsw_critintr = e500_critintr, 392 .intrsw_decrintr = e500_decrintr, 393 .intrsw_extintr = e500_extintr, 394 .intrsw_fitintr = e500_fitintr, 395 .intrsw_wdogintr = e500_wdogintr, 396 397 .intrsw_splraise = e500_splraise, 398 .intrsw_splx = e500_splx, 399 .intrsw_spl0 = e500_spl0, 400 401 #ifdef __HAVE_FAST_SOFTINTS 402 .intrsw_softint_init_md = e500_softint_init_md, 403 .intrsw_softint_trigger = e500_softint_trigger, 404 #endif 405 }; 406 407 static inline uint32_t 408 openpic_read(struct cpu_softc *cpu, bus_size_t offset) 409 { 410 411 return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh, 412 OPENPIC_BASE + offset); 413 } 414 415 static inline void 416 openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val) 417 { 418 419 return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, 420 OPENPIC_BASE + offset, val); 421 } 422 423 static const char * 424 e500_intr_external_name_lookup(int irq) 425 { 426 prop_array_t extirqs = board_info_get_object("external-irqs"); 427 prop_string_t irqname = prop_array_get(extirqs, irq); 428 KASSERT(irqname != NULL); 429 KASSERT(prop_object_type(irqname) == PROP_TYPE_STRING); 430 431 return prop_string_cstring_nocopy(irqname); 432 } 433 434 static const char * 435 e500_intr_name_lookup(const struct e500_intr_name *names, int irq) 436 { 437 for (; names->in_name[0] != '\0'; names++) { 438 if (names->in_irq == irq) 439 return names->in_name; 440 } 441 442 return NULL; 443 } 444 445 static const char * 446 e500_intr_onchip_name_lookup(int irq) 447 { 448 const char *name; 449 450 name = e500_intr_name_lookup(e500_intr_info.ii_onchip_intr_names, irq); 451 if (name == NULL) 452 name = e500_intr_name_lookup(e500_onchip_intr_names, irq); 453 454 return name; 455 } 456 457 #ifdef __HAVE_FAST_SOFTINTS 458 static inline void 459 e500_softint_deliver(struct cpu_info *ci, struct cpu_softc *cpu, 460 int ipl, int si_level) 461 { 462 KASSERT(ci->ci_data.cpu_softints & (1 << ipl)); 463 ci->ci_data.cpu_softints ^= 1 << ipl; 464 softint_fast_dispatch(cpu->cpu_softlwps[si_level], ipl); 465 KASSERT(cpu->cpu_softlwps[si_level]->l_ctxswtch == 0); 466 KASSERTMSG(ci->ci_cpl == IPL_HIGH, 467 ("%s: cpl (%d) != HIGH", __func__, ci->ci_cpl)); 468 } 469 470 static inline void 471 e500_softint(struct cpu_info *ci, struct cpu_softc *cpu, int old_ipl, 472 vaddr_t pc) 473 { 474 const u_int softint_mask = (IPL_SOFTMASK << old_ipl) & IPL_SOFTMASK; 475 u_int softints; 476 477 KASSERT(ci->ci_mtx_count == 0); 478 KASSERT(ci->ci_cpl == IPL_HIGH); 479 while ((softints = (ci->ci_data.cpu_softints & softint_mask)) != 0) { 480 KASSERT(old_ipl < IPL_SOFTSERIAL); 481 if (softints & (1 << IPL_SOFTSERIAL)) { 482 e500_softint_deliver(ci, cpu, IPL_SOFTSERIAL, 483 SOFTINT_SERIAL); 484 continue; 485 } 486 KASSERT(old_ipl < IPL_SOFTNET); 487 if (softints & (1 << IPL_SOFTNET)) { 488 e500_softint_deliver(ci, cpu, IPL_SOFTNET, 489 SOFTINT_NET); 490 continue; 491 } 492 KASSERT(old_ipl < IPL_SOFTBIO); 493 if (softints & (1 << IPL_SOFTBIO)) { 494 e500_softint_deliver(ci, cpu, IPL_SOFTBIO, 495 SOFTINT_BIO); 496 continue; 497 } 498 KASSERT(old_ipl < IPL_SOFTCLOCK); 499 if (softints & (1 << IPL_SOFTCLOCK)) { 500 e500_softint_deliver(ci, cpu, IPL_SOFTCLOCK, 501 SOFTINT_CLOCK); 502 continue; 503 } 504 #ifdef __HAVE_PREEMPTION 505 KASSERT(old_ipl == IPL_NONE); 506 if (softints & (1 << IPL_NONE)) { 507 ci->ci_data.cpu_softints ^= (1 << IPL_NONE); 508 kpreempt(pc); 509 } 510 #endif 511 } 512 } 513 #endif /* __HAVE_FAST_SOFTINTS */ 514 515 static inline void 516 e500_splset(struct cpu_info *ci, int ipl) 517 { 518 struct cpu_softc * const cpu = ci->ci_softc; 519 //KASSERT(!cpu_intr_p() || ipl >= IPL_VM); 520 KASSERT((curlwp->l_pflag & LP_INTR) == 0 || ipl != IPL_NONE); 521 #if 0 522 u_int ctpr = ipl; 523 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ci->ci_cpl); 524 #elif 0 525 u_int old_ctpr = (ci->ci_cpl >= IPL_VM ? 15 : ci->ci_cpl); 526 u_int ctpr = (ipl >= IPL_VM ? 15 : ipl); 527 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == old_ctpr); 528 #else 529 #ifdef DIAGNOSTIC 530 u_int old_ctpr = IPL2CTPR(ci->ci_cpl); 531 #endif 532 u_int ctpr = IPL2CTPR(ipl); 533 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == old_ctpr); 534 #endif 535 openpic_write(cpu, OPENPIC_CTPR, ctpr); 536 KASSERT(openpic_read(cpu, OPENPIC_CTPR) == ctpr); 537 ci->ci_cpl = ipl; 538 } 539 540 static void 541 e500_spl0(void) 542 { 543 struct cpu_info * const ci = curcpu(); 544 545 wrtee(0); 546 547 #ifdef __HAVE_FAST_SOFTINTS 548 if (__predict_false(ci->ci_data.cpu_softints != 0)) { 549 e500_splset(ci, IPL_HIGH); 550 e500_softint(ci, ci->ci_softc, IPL_NONE, 551 (vaddr_t)__builtin_return_address(0)); 552 } 553 #endif /* __HAVE_FAST_SOFTINTS */ 554 e500_splset(ci, IPL_NONE); 555 556 wrtee(PSL_EE); 557 } 558 559 static void 560 e500_splx(int ipl) 561 { 562 struct cpu_info * const ci = curcpu(); 563 const int old_ipl = ci->ci_cpl; 564 565 KASSERT(mfmsr() & PSL_CE); 566 567 if (ipl == old_ipl) 568 return; 569 570 if (__predict_false(ipl > old_ipl)) { 571 printf("%s: %p: cpl=%u: ignoring splx(%u) to raise ipl\n", 572 __func__, __builtin_return_address(0), old_ipl, ipl); 573 if (old_ipl == IPL_NONE) 574 Debugger(); 575 } 576 577 // const 578 register_t msr = wrtee(0); 579 #ifdef __HAVE_FAST_SOFTINTS 580 const u_int softints = (ci->ci_data.cpu_softints << ipl) & IPL_SOFTMASK; 581 if (__predict_false(softints != 0)) { 582 e500_splset(ci, IPL_HIGH); 583 e500_softint(ci, ci->ci_softc, ipl, 584 (vaddr_t)__builtin_return_address(0)); 585 } 586 #endif /* __HAVE_FAST_SOFTINTS */ 587 e500_splset(ci, ipl); 588 #if 1 589 if (ipl < IPL_VM && old_ipl >= IPL_VM) 590 msr = PSL_EE; 591 #endif 592 wrtee(msr); 593 } 594 595 static int 596 e500_splraise(int ipl) 597 { 598 struct cpu_info * const ci = curcpu(); 599 const int old_ipl = ci->ci_cpl; 600 601 KASSERT(mfmsr() & PSL_CE); 602 603 if (old_ipl < ipl) { 604 //const 605 register_t msr = wrtee(0); 606 e500_splset(ci, ipl); 607 #if 1 608 if (old_ipl < IPL_VM && ipl >= IPL_VM) 609 msr = 0; 610 #endif 611 wrtee(msr); 612 } else if (ipl == IPL_NONE) { 613 panic("%s: %p: cpl=%u: attempt to splraise(IPL_NONE)", 614 __func__, __builtin_return_address(0), old_ipl); 615 #if 0 616 } else if (old_ipl > ipl) { 617 printf("%s: %p: cpl=%u: ignoring splraise(%u) to lower ipl\n", 618 __func__, __builtin_return_address(0), old_ipl, ipl); 619 #endif 620 } 621 622 return old_ipl; 623 } 624 625 #ifdef __HAVE_FAST_SOFTINTS 626 static void 627 e500_softint_init_md(lwp_t *l, u_int si_level, uintptr_t *machdep_p) 628 { 629 struct cpu_info * const ci = l->l_cpu; 630 struct cpu_softc * const cpu = ci->ci_softc; 631 632 *machdep_p = 1 << SOFTINT2IPL(si_level); 633 KASSERT(*machdep_p & IPL_SOFTMASK); 634 cpu->cpu_softlwps[si_level] = l; 635 } 636 637 static void 638 e500_softint_trigger(uintptr_t machdep) 639 { 640 struct cpu_info * const ci = curcpu(); 641 642 atomic_or_uint(&ci->ci_data.cpu_softints, machdep); 643 } 644 #endif /* __HAVE_FAST_SOFTINTS */ 645 646 static int 647 e500_intr_spurious(void *arg) 648 { 649 return 0; 650 } 651 652 static bool 653 e500_intr_irq_info_get(struct cpu_info *ci, u_int irq, int ipl, int ist, 654 struct e500_intr_irq_info *ii) 655 { 656 const struct e500_intr_info * const info = &e500_intr_info; 657 bool ok; 658 659 #if DEBUG > 2 660 printf("%s(%p,irq=%u,ipl=%u,ist=%u,%p)\n", __func__, ci, irq, ipl, ist, ii); 661 #endif 662 663 if (ipl < IPL_VM || ipl > IPL_HIGH) { 664 #if DEBUG > 2 665 printf("%s:%d ipl=%u\n", __func__, __LINE__, ipl); 666 #endif 667 return false; 668 } 669 670 if (ist <= IST_NONE || ist >= IST_MAX) { 671 #if DEBUG > 2 672 printf("%s:%d ist=%u\n", __func__, __LINE__, ist); 673 #endif 674 return false; 675 } 676 677 ii->irq_vector = irq + info->ii_ist_vectors[ist]; 678 if (IST_PERCPU_P(ist) && ist != IST_IPI) 679 ii->irq_vector += ci->ci_cpuid * info->ii_percpu_sources; 680 681 switch (ist) { 682 default: 683 ii->irq_vpr = OPENPIC_EIVPR(irq); 684 ii->irq_dr = OPENPIC_EIDR(irq); 685 ok = irq < info->ii_external_sources 686 && (ist == IST_EDGE 687 || ist == IST_LEVEL_LOW 688 || ist == IST_LEVEL_HIGH); 689 break; 690 case IST_ONCHIP: 691 ii->irq_vpr = OPENPIC_IIVPR(irq); 692 ii->irq_dr = OPENPIC_IIDR(irq); 693 ok = irq < 32 * __arraycount(info->ii_onchip_bitmap); 694 #if DEBUG > 2 695 printf("%s: irq=%u: ok=%u\n", __func__, irq, ok); 696 #endif 697 ok = ok && (info->ii_onchip_bitmap[irq/32] & (1 << (irq & 31))); 698 #if DEBUG > 2 699 printf("%s: %08x%08x -> %08x%08x: ok=%u\n", __func__, 700 irq < 32 ? 0 : (1 << irq), irq < 32 ? (1 << irq) : 0, 701 info->ii_onchip_bitmap[1], info->ii_onchip_bitmap[0], 702 ok); 703 #endif 704 break; 705 case IST_MSIGROUP: 706 ii->irq_vpr = OPENPIC_MSIVPR(irq); 707 ii->irq_dr = OPENPIC_MSIDR(irq); 708 ok = irq < info->ii_msigroup_sources 709 && ipl == IPL_VM; 710 break; 711 case IST_TIMER: 712 ii->irq_vpr = OPENPIC_GTVPR(ci->ci_cpuid, irq); 713 ii->irq_dr = OPENPIC_GTDR(ci->ci_cpuid, irq); 714 ok = irq < info->ii_timer_sources; 715 #if DEBUG > 2 716 printf("%s: IST_TIMER irq=%u: ok=%u\n", __func__, irq, ok); 717 #endif 718 break; 719 case IST_IPI: 720 ii->irq_vpr = OPENPIC_IPIVPR(irq); 721 ii->irq_dr = OPENPIC_IPIDR(irq); 722 ok = irq < info->ii_ipi_sources; 723 break; 724 case IST_MI: 725 ii->irq_vpr = OPENPIC_MIVPR(irq); 726 ii->irq_dr = OPENPIC_MIDR(irq); 727 ok = irq < info->ii_mi_sources; 728 break; 729 } 730 731 return ok; 732 } 733 734 static const char * 735 e500_intr_string(int irq, int ist) 736 { 737 struct cpu_info * const ci = curcpu(); 738 struct cpu_softc * const cpu = ci->ci_softc; 739 struct e500_intr_irq_info ii; 740 741 if (!e500_intr_irq_info_get(ci, irq, IPL_VM, ist, &ii)) 742 return NULL; 743 744 return cpu->cpu_evcnt_intrs[ii.irq_vector].ev_name; 745 } 746 747 static void * 748 e500_intr_cpu_establish(struct cpu_info *ci, int irq, int ipl, int ist, 749 int (*handler)(void *), void *arg) 750 { 751 struct cpu_softc * const cpu = ci->ci_softc; 752 struct e500_intr_irq_info ii; 753 754 KASSERT(ipl >= IPL_VM && ipl <= IPL_HIGH); 755 KASSERT(ist > IST_NONE && ist < IST_MAX && ist != IST_MSI); 756 757 if (!e500_intr_irq_info_get(ci, irq, ipl, ist, &ii)) { 758 printf("%s: e500_intr_irq_info_get(%p,%u,%u,%u,%p) failed\n", 759 __func__, ci, irq, ipl, ist, &ii); 760 return NULL; 761 } 762 763 struct intr_source * const is = &e500_intr_sources[ii.irq_vector]; 764 mutex_enter(&e500_intr_lock); 765 if (is->is_ipl != IPL_NONE) 766 return NULL; 767 768 is->is_func = handler; 769 is->is_arg = arg; 770 is->is_ipl = ipl; 771 is->is_ist = ist; 772 is->is_irq = irq; 773 is->is_vpr = ii.irq_vpr; 774 is->is_dr = ii.irq_dr; 775 776 uint32_t vpr = VPR_PRIORITY_MAKE(IPL2CTPR(ipl)) 777 | VPR_VECTOR_MAKE(((ii.irq_vector + 1) << 4) | ipl) 778 | (ist == IST_LEVEL_LOW 779 ? VPR_LEVEL_LOW 780 : (ist == IST_LEVEL_HIGH 781 ? VPR_LEVEL_HIGH 782 : (ist == IST_ONCHIP 783 ? VPR_P_HIGH 784 : 0))); 785 786 /* 787 * All interrupts go to the primary except per-cpu interrupts which get 788 * routed to the appropriate cpu. 789 */ 790 uint32_t dr = openpic_read(cpu, ii.irq_dr); 791 792 dr |= 1 << (IST_PERCPU_P(ist) ? ci->ci_cpuid : 0); 793 794 /* 795 * Update the vector/priority and destination registers keeping the 796 * interrupt masked. 797 */ 798 const register_t msr = wrtee(0); /* disable interrupts */ 799 openpic_write(cpu, ii.irq_vpr, vpr | VPR_MSK); 800 openpic_write(cpu, ii.irq_dr, dr); 801 802 /* 803 * Now unmask the interrupt. 804 */ 805 openpic_write(cpu, ii.irq_vpr, vpr); 806 807 wrtee(msr); /* re-enable interrupts */ 808 809 mutex_exit(&e500_intr_lock); 810 811 return is; 812 } 813 814 static void * 815 e500_intr_establish(int irq, int ipl, int ist, 816 int (*handler)(void *), void *arg) 817 { 818 return e500_intr_cpu_establish(curcpu(), irq, ipl, ist, handler, arg); 819 } 820 821 static void 822 e500_intr_disestablish(void *vis) 823 { 824 struct cpu_softc * const cpu = curcpu()->ci_softc; 825 struct intr_source * const is = vis; 826 struct e500_intr_irq_info ii; 827 828 KASSERT(e500_intr_sources <= is); 829 KASSERT(is < e500_intr_last_source); 830 KASSERT(!cpu_intr_p()); 831 832 bool ok = e500_intr_irq_info_get(curcpu(), is->is_irq, is->is_ipl, 833 is->is_ist, &ii); 834 (void)ok; /* appease gcc */ 835 KASSERT(ok); 836 KASSERT(is - e500_intr_sources == ii.irq_vector); 837 838 mutex_enter(&e500_intr_lock); 839 /* 840 * Mask the source using the mask (MSK) bit in the vector/priority reg. 841 */ 842 uint32_t vpr = openpic_read(cpu, ii.irq_vpr); 843 openpic_write(cpu, ii.irq_vpr, VPR_MSK | vpr); 844 845 /* 846 * Wait for the Activity (A) bit for the source to be cleared. 847 */ 848 while (openpic_read(cpu, ii.irq_vpr) & VPR_A) 849 ; 850 851 /* 852 * Now the source can be modified. 853 */ 854 openpic_write(cpu, ii.irq_dr, 0); /* stop delivery */ 855 openpic_write(cpu, ii.irq_vpr, VPR_MSK); /* mask/reset it */ 856 857 *is = (struct intr_source)INTR_SOURCE_INITIALIZER; 858 859 mutex_exit(&e500_intr_lock); 860 } 861 862 static void 863 e500_critintr(struct trapframe *tf) 864 { 865 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 866 } 867 868 static void 869 e500_decrintr(struct trapframe *tf) 870 { 871 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 872 } 873 874 static void 875 e500_fitintr(struct trapframe *tf) 876 { 877 panic("%s: srr0/srr1=%#lx/%#lx", __func__, tf->tf_srr0, tf->tf_srr1); 878 } 879 880 static void 881 e500_wdogintr(struct trapframe *tf) 882 { 883 mtspr(SPR_TSR, TSR_ENW|TSR_WIS); 884 panic("%s: tf=%p tb=%"PRId64" srr0/srr1=%#lx/%#lx", __func__, tf, 885 mftb(), tf->tf_srr0, tf->tf_srr1); 886 } 887 888 static void 889 e500_extintr(struct trapframe *tf) 890 { 891 struct cpu_info * const ci = curcpu(); 892 struct cpu_softc * const cpu = ci->ci_softc; 893 const int old_ipl = ci->ci_cpl; 894 895 KASSERT(mfmsr() & PSL_CE); 896 897 #if 0 898 // printf("%s(%p): idepth=%d enter\n", __func__, tf, ci->ci_idepth); 899 if ((register_t)tf >= (register_t)curlwp->l_addr + USPACE 900 || (register_t)tf < (register_t)curlwp->l_addr + NBPG) { 901 printf("%s(entry): pid %d.%d (%s): srr0/srr1=%#lx/%#lx: invalid tf addr %p\n", 902 __func__, curlwp->l_proc->p_pid, curlwp->l_lid, 903 curlwp->l_proc->p_comm, tf->tf_srr0, tf->tf_srr1, tf); 904 } 905 #endif 906 907 908 ci->ci_data.cpu_nintr++; 909 tf->tf_cf.cf_idepth = ci->ci_idepth++; 910 cpu->cpu_pcpls[ci->ci_idepth] = old_ipl; 911 #if 1 912 if (mfmsr() & PSL_EE) 913 panic("%s(%p): MSR[EE] is on (%#lx)!", __func__, tf, mfmsr()); 914 if (old_ipl == IPL_HIGH 915 || IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 916 panic("%s(%p): old_ipl(%u) == IPL_HIGH(%u) " 917 "|| old_ipl + %u != OPENPIC_CTPR (%u)", 918 __func__, tf, old_ipl, IPL_HIGH, 919 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 920 #else 921 if (old_ipl >= IPL_VM) 922 panic("%s(%p): old_ipl(%u) >= IPL_VM(%u) CTPR=%u", 923 __func__, tf, old_ipl, IPL_VM, openpic_read(cpu, OPENPIC_CTPR)); 924 #endif 925 926 for (;;) { 927 /* 928 * Find out the pending interrupt. 929 */ 930 if (mfmsr() & PSL_EE) 931 panic("%s(%p): MSR[EE] turned on (%#lx)!", __func__, tf, mfmsr()); 932 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 933 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 934 __func__, tf, __LINE__, old_ipl, 935 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 936 const uint32_t iack = openpic_read(cpu, OPENPIC_IACK); 937 #ifdef DIAGNOSTIC 938 const int ipl = iack & 0xf; 939 #endif 940 const int irq = (iack >> 4) - 1; 941 #if 0 942 printf("%s: iack=%d ipl=%d irq=%d <%s>\n", 943 __func__, iack, ipl, irq, 944 (iack != IRQ_SPURIOUS ? 945 cpu->cpu_evcnt_intrs[irq].ev_name : "spurious")); 946 #endif 947 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 948 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 949 __func__, tf, __LINE__, old_ipl, 950 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 951 if (iack == IRQ_SPURIOUS) 952 break; 953 954 struct intr_source * const is = &e500_intr_sources[irq]; 955 if (__predict_true(is < e500_intr_last_source)) { 956 /* 957 * Timer interrupts get their argument overriden with 958 * the pointer to the trapframe. 959 */ 960 KASSERT(is->is_ipl == ipl); 961 void *arg = (is->is_ist == IST_TIMER ? tf : is->is_arg); 962 if (is->is_ipl <= old_ipl) 963 panic("%s(%p): %s (%u): is->is_ipl (%u) <= old_ipl (%u)\n", 964 __func__, tf, 965 cpu->cpu_evcnt_intrs[irq].ev_name, irq, 966 is->is_ipl, old_ipl); 967 KASSERT(is->is_ipl > old_ipl); 968 e500_splset(ci, is->is_ipl); /* change IPL */ 969 if (__predict_false(is->is_func == NULL)) { 970 aprint_error_dev(ci->ci_dev, 971 "interrupt from unestablished irq %d\n", 972 irq); 973 } else { 974 int (*func)(void *) = is->is_func; 975 wrtee(PSL_EE); 976 int rv = (*func)(arg); 977 wrtee(0); 978 #if DEBUG > 2 979 printf("%s: %s handler %p(%p) returned %d\n", 980 __func__, 981 cpu->cpu_evcnt_intrs[irq].ev_name, 982 func, arg, rv); 983 #endif 984 if (rv == 0) 985 cpu->cpu_evcnt_spurious_intr.ev_count++; 986 } 987 e500_splset(ci, old_ipl); /* restore IPL */ 988 cpu->cpu_evcnt_intrs[irq].ev_count++; 989 } else { 990 aprint_error_dev(ci->ci_dev, 991 "interrupt from illegal irq %d\n", irq); 992 cpu->cpu_evcnt_spurious_intr.ev_count++; 993 } 994 /* 995 * If this is a nested interrupt, simply ack it and exit 996 * because the loop we interrupted will complete looking 997 * for interrupts. 998 */ 999 if (mfmsr() & PSL_EE) 1000 panic("%s(%p): MSR[EE] left on (%#lx)!", __func__, tf, mfmsr()); 1001 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 1002 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 1003 __func__, tf, __LINE__, old_ipl, 1004 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 1005 1006 openpic_write(cpu, OPENPIC_EOI, 0); 1007 if (IPL2CTPR(old_ipl) != openpic_read(cpu, OPENPIC_CTPR)) 1008 panic("%s(%p): %d: old_ipl(%u) + %u != OPENPIC_CTPR (%u)", 1009 __func__, tf, __LINE__, old_ipl, 1010 15 - IPL_HIGH, openpic_read(cpu, OPENPIC_CTPR)); 1011 if (ci->ci_idepth > 0) 1012 break; 1013 } 1014 1015 ci->ci_idepth--; 1016 1017 #ifdef __HAVE_FAST_SOFTINTS 1018 /* 1019 * Before exiting, deal with any softints that need to be dealt with. 1020 */ 1021 const u_int softints = (ci->ci_data.cpu_softints << old_ipl) & IPL_SOFTMASK; 1022 if (__predict_false(softints != 0)) { 1023 KASSERT(old_ipl < IPL_VM); 1024 e500_splset(ci, IPL_HIGH); /* pop to high */ 1025 e500_softint(ci, cpu, old_ipl, /* deal with them */ 1026 tf->tf_srr0); 1027 e500_splset(ci, old_ipl); /* and drop back */ 1028 } 1029 #endif /* __HAVE_FAST_SOFTINTS */ 1030 #if 1 1031 KASSERT(ci->ci_cpl == old_ipl); 1032 #else 1033 e500_splset(ci, old_ipl); /* and drop back */ 1034 #endif 1035 1036 // printf("%s(%p): idepth=%d exit\n", __func__, tf, ci->ci_idepth); 1037 } 1038 1039 static void 1040 e500_intr_init(void) 1041 { 1042 struct cpu_info * const ci = curcpu(); 1043 struct cpu_softc * const cpu = ci->ci_softc; 1044 const uint32_t frr = openpic_read(cpu, OPENPIC_FRR); 1045 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1046 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1047 struct intr_source *is; 1048 struct e500_intr_info * const ii = &e500_intr_info; 1049 1050 const uint16_t svr = (mfspr(SPR_SVR) & ~0x80000) >> 16; 1051 switch (svr) { 1052 #ifdef MPC8536 1053 case SVR_MPC8536v1 >> 16: 1054 *ii = mpc8536_intr_info; 1055 break; 1056 #endif 1057 #ifdef MPC8544 1058 case SVR_MPC8544v1 >> 16: 1059 *ii = mpc8544_intr_info; 1060 break; 1061 #endif 1062 #ifdef MPC8548 1063 case SVR_MPC8543v1 >> 16: 1064 case SVR_MPC8548v1 >> 16: 1065 *ii = mpc8548_intr_info; 1066 break; 1067 #endif 1068 #ifdef MPC8555 1069 case SVR_MPC8541v1 >> 16: 1070 case SVR_MPC8555v1 >> 16: 1071 *ii = mpc8555_intr_info; 1072 break; 1073 #endif 1074 #ifdef MPC8568 1075 case SVR_MPC8568v1 >> 16: 1076 *ii = mpc8568_intr_info; 1077 break; 1078 #endif 1079 #ifdef MPC8572 1080 case SVR_MPC8572v1 >> 16: 1081 *ii = mpc8572_intr_info; 1082 break; 1083 #endif 1084 #ifdef P2020 1085 case SVR_P2010v2 >> 16: 1086 case SVR_P2020v2 >> 16: 1087 *ii = p20x0_intr_info; 1088 break; 1089 #endif 1090 default: 1091 panic("%s: don't know how to deal with SVR %#lx", 1092 __func__, mfspr(SPR_SVR)); 1093 } 1094 1095 /* 1096 * We need to be in mixed mode. 1097 */ 1098 openpic_write(cpu, OPENPIC_GCR, GCR_M); 1099 1100 /* 1101 * Make we and the openpic both agree about the current SPL level. 1102 */ 1103 e500_splset(ci, ci->ci_cpl); 1104 1105 /* 1106 * Allow the required number of interrupt sources. 1107 */ 1108 is = kmem_zalloc(nirq * sizeof(*is), KM_SLEEP); 1109 KASSERT(is); 1110 e500_intr_sources = is; 1111 e500_intr_last_source = is + nirq; 1112 1113 /* 1114 * Initialize all the external interrupts as active low. 1115 */ 1116 for (u_int irq = 0; irq < e500_intr_info.ii_external_sources; irq++) { 1117 openpic_write(cpu, OPENPIC_EIVPR(irq), 1118 VPR_VECTOR_MAKE(irq) | VPR_LEVEL_LOW); 1119 } 1120 } 1121 1122 static void 1123 e500_intr_cpu_attach(struct cpu_info *ci) 1124 { 1125 struct cpu_softc * const cpu = ci->ci_softc; 1126 const char * const xname = device_xname(ci->ci_dev); 1127 1128 const u_int32_t frr = openpic_read(cpu, OPENPIC_FRR); 1129 const u_int nirq = FRR_NIRQ_GET(frr) + 1; 1130 // const u_int ncpu = FRR_NCPU_GET(frr) + 1; 1131 1132 const struct e500_intr_info * const info = &e500_intr_info; 1133 1134 cpu->cpu_clock_gtbcr = OPENPIC_GTBCR(ci->ci_cpuid, E500_CLOCK_TIMER); 1135 1136 cpu->cpu_evcnt_intrs = 1137 kmem_zalloc(nirq * sizeof(cpu->cpu_evcnt_intrs[0]), KM_SLEEP); 1138 KASSERT(cpu->cpu_evcnt_intrs); 1139 1140 struct evcnt *evcnt = cpu->cpu_evcnt_intrs; 1141 for (size_t j = 0; j < info->ii_external_sources; j++, evcnt++) { 1142 const char *name = e500_intr_external_name_lookup(j); 1143 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, NULL, xname, name); 1144 } 1145 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_ONCHIP]); 1146 for (size_t j = 0; j < info->ii_onchip_sources; j++, evcnt++) { 1147 if (info->ii_onchip_bitmap[j / 32] & __BIT(j & 31)) { 1148 const char *name = e500_intr_onchip_name_lookup(j); 1149 if (name != NULL) { 1150 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1151 NULL, xname, name); 1152 #ifdef DIAGNOSTIC 1153 } else { 1154 printf("%s: missing evcnt for onchip irq %zu\n", 1155 __func__, j); 1156 #endif 1157 } 1158 } 1159 } 1160 1161 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_MSIGROUP]); 1162 for (size_t j = 0; j < info->ii_msigroup_sources; j++, evcnt++) { 1163 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1164 NULL, xname, e500_msigroup_intr_names[j].in_name); 1165 } 1166 1167 KASSERT(evcnt == cpu->cpu_evcnt_intrs + info->ii_ist_vectors[IST_TIMER]); 1168 evcnt += ci->ci_cpuid * info->ii_percpu_sources; 1169 for (size_t j = 0; j < info->ii_timer_sources; j++, evcnt++) { 1170 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1171 NULL, xname, e500_timer_intr_names[j].in_name); 1172 } 1173 1174 for (size_t j = 0; j < info->ii_ipi_sources; j++, evcnt++) { 1175 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1176 NULL, xname, e500_ipi_intr_names[j].in_name); 1177 } 1178 1179 for (size_t j = 0; j < info->ii_mi_sources; j++, evcnt++) { 1180 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 1181 NULL, xname, e500_mi_intr_names[j].in_name); 1182 } 1183 } 1184 1185 static void 1186 e500_intr_cpu_send_ipi(cpuid_t target, uint32_t ipimsg) 1187 { 1188 struct cpu_info * const ci = curcpu(); 1189 struct cpu_softc * const cpu = ci->ci_softc; 1190 uint32_t dstmask; 1191 1192 if (target >= ncpu) { 1193 CPU_INFO_ITERATOR cii; 1194 struct cpu_info *dst_ci; 1195 1196 KASSERT(target == IPI_DST_NOTME || target == IPI_DST_ALL); 1197 1198 dstmask = 0; 1199 for (CPU_INFO_FOREACH(cii, dst_ci)) { 1200 if (target == IPI_DST_ALL || ci != dst_ci) { 1201 dstmask |= 1 << cpu_index(ci); 1202 if (ipimsg) 1203 atomic_or_32(&dst_ci->ci_pending_ipis, 1204 ipimsg); 1205 } 1206 } 1207 } else { 1208 struct cpu_info * const dst_ci = cpu_lookup(target); 1209 KASSERT(target == cpu_index(dst_ci)); 1210 dstmask = (1 << target); 1211 if (ipimsg) 1212 atomic_or_32(&dst_ci->ci_pending_ipis, ipimsg); 1213 } 1214 1215 openpic_write(cpu, OPENPIC_IPIDR(0), dstmask); 1216 } 1217 1218 typedef void (*ipifunc_t)(void); 1219 1220 #ifdef __HAVE_PREEEMPTION 1221 static void 1222 e500_ipi_kpreempt(void) 1223 { 1224 e500_softint_trigger(1 << IPL_NONE); 1225 } 1226 #endif 1227 1228 static const ipifunc_t e500_ipifuncs[] = { 1229 [ilog2(IPI_XCALL)] = xc_ipi_handler, 1230 [ilog2(IPI_HALT)] = e500_ipi_halt, 1231 #ifdef __HAVE_PREEMPTION 1232 [ilog2(IPI_KPREEMPT)] = e500_ipi_kpreempt, 1233 #endif 1234 [ilog2(IPI_TLB1SYNC)] = e500_tlb1_sync, 1235 }; 1236 1237 static int 1238 e500_ipi_intr(void *v) 1239 { 1240 struct cpu_info * const ci = curcpu(); 1241 1242 ci->ci_ev_ipi.ev_count++; 1243 1244 uint32_t pending_ipis = atomic_swap_32(&ci->ci_pending_ipis, 0); 1245 for (u_int ipi = 31; pending_ipis != 0; ipi--, pending_ipis <<= 1) { 1246 const u_int bits = __builtin_clz(pending_ipis); 1247 ipi -= bits; 1248 pending_ipis <<= bits; 1249 KASSERT(e500_ipifuncs[ipi] != NULL); 1250 (*e500_ipifuncs[ipi])(); 1251 } 1252 1253 return 1; 1254 } 1255 1256 static void 1257 e500_intr_cpu_hatch(struct cpu_info *ci) 1258 { 1259 /* 1260 * Establish clock interrupt for this CPU. 1261 */ 1262 if (e500_intr_cpu_establish(ci, E500_CLOCK_TIMER, IPL_CLOCK, IST_TIMER, 1263 e500_clock_intr, NULL) == NULL) 1264 panic("%s: failed to establish clock interrupt!", __func__); 1265 1266 /* 1267 * Establish the IPI interrupts for this CPU. 1268 */ 1269 if (e500_intr_cpu_establish(ci, 0, IPL_VM, IST_IPI, e500_ipi_intr, 1270 NULL) == NULL) 1271 panic("%s: failed to establish ipi interrupt!", __func__); 1272 1273 /* 1274 * Enable watchdog interrupts. 1275 */ 1276 uint32_t tcr = mfspr(SPR_TCR); 1277 tcr |= TCR_WIE; 1278 mtspr(SPR_TCR, tcr); 1279 } 1280
Indexes created Tue Sep 30 07:10:03 GMT 2025