e500_timer.c revision 1.4.12.1
1 /* $NetBSD: e500_timer.c,v 1.4.12.1 2014/08/20 00:03:19 tls Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: e500_timer.c,v 1.4.12.1 2014/08/20 00:03:19 tls Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/kernel.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 #include <sys/intr.h> 45 #include <sys/cpu.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <powerpc/spr.h> 50 #include <powerpc/booke/spr.h> 51 #include <powerpc/booke/cpuvar.h> 52 #include <powerpc/booke/e500reg.h> 53 #include <powerpc/booke/e500var.h> 54 #include <powerpc/booke/openpicreg.h> 55 56 static u_long ns_per_tick; 57 58 static void init_ppcbooke_tc(void); 59 static u_int get_ppcbooke_timecount(struct timecounter *); 60 61 static struct timecounter ppcbooke_timecounter = { 62 get_ppcbooke_timecount, /* get_timecount */ 63 0, /* no poll_pps */ 64 ~0u, /* counter_mask */ 65 0, /* frequency */ 66 "ppc_timebase", /* name */ 67 100, /* quality */ 68 NULL, /* tc_priv */ 69 NULL /* tc_next */ 70 }; 71 72 static inline void 73 openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val) 74 { 75 76 return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, 77 OPENPIC_BASE + offset, val); 78 } 79 80 int 81 e500_clock_intr(void *v) 82 { 83 struct trapframe * const tf = v; 84 struct cpu_info * const ci = curcpu(); 85 struct cpu_softc * const cpu = ci->ci_softc; 86 u_int nticks; 87 88 /* 89 * Check whether we are initialized. 90 */ 91 if (!cpu->cpu_ticks_per_clock_intr) 92 return 0; 93 94 /* 95 * Now let's how delayed the clock interrupt was. Obviously it must 96 * at least one clock tick since the clock interrupt. But it might 97 * be more if interrupts were blocked for a long time. We keep 98 * suubtracting an interrupts We should be 99 * [well] within a single tick. 100 * We add back one tick (which should put us back above 0). If we 101 * are still below 0, keep adding ticks until we are above 0. 102 */ 103 const uint64_t now = mftb(); 104 uint64_t latency = now - (ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr); 105 #if 0 106 uint64_t orig_latency = latency; 107 #endif 108 if (now < ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr) 109 latency = 0; 110 111 nticks = 1 + latency / cpu->cpu_ticks_per_clock_intr; 112 latency %= cpu->cpu_ticks_per_clock_intr; 113 #if 0 114 for (nticks = 1; latency >= cpu->cpu_ticks_per_clock_intr; nticks++) { 115 latency -= cpu->cpu_ticks_per_clock_intr; 116 } 117 #endif 118 119 ci->ci_ev_clock.ev_count++; 120 cpu->cpu_ev_late_clock.ev_count += nticks - 1; 121 122 /* 123 * lasttb is used during microtime. Set it to the virtual 124 * start of this tick interval. 125 */ 126 #if 0 127 if (nticks > 10 || now - ci->ci_lastintr < 7 * cpu->cpu_ticks_per_clock_intr / 8) 128 printf("%s: nticks=%u lastintr=%#"PRIx64"(%#"PRIx64") now=%#"PRIx64" latency=%#"PRIx64" orig=%#"PRIx64"\n", __func__, 129 nticks, ci->ci_lastintr, now - latency, now, latency, orig_latency); 130 #endif 131 ci->ci_lastintr = now - latency; 132 ci->ci_lasttb = now; 133 134 wrtee(PSL_EE); /* Reenable interrupts */ 135 136 /* 137 * Do standard timer interrupt stuff. 138 */ 139 while (nticks-- > 0) { 140 hardclock(&tf->tf_cf); 141 } 142 143 wrtee(0); /* turn off interrupts */ 144 145 tf->tf_srr1 &= ~PSL_POW; /* make cpu_idle exit */ 146 147 return 1; 148 } 149 150 void 151 cpu_initclocks(void) 152 { 153 struct cpu_info * const ci = curcpu(); 154 struct cpu_softc * const cpu = ci->ci_softc; 155 156 cpu->cpu_ticks_per_clock_intr = (ci->ci_data.cpu_cc_freq + hz/2 - 1) / hz; 157 158 /* interrupt established in e500_intr_cpu_init */ 159 160 ci->ci_lastintr = ci->ci_lasttb = mftb(); 161 openpic_write(cpu, cpu->cpu_clock_gtbcr, 162 GTBCR_CI | cpu->cpu_ticks_per_clock_intr); 163 openpic_write(cpu, cpu->cpu_clock_gtbcr, 164 cpu->cpu_ticks_per_clock_intr); 165 166 if (CPU_IS_PRIMARY(ci)) 167 init_ppcbooke_tc(); 168 } 169 170 void 171 calc_delayconst(void) 172 { 173 struct cpu_info * const ci = curcpu(); 174 175 ci->ci_data.cpu_cc_freq = board_info_get_number("timebase-frequency"); 176 ns_per_tick = 1000000000 / (u_int)ci->ci_data.cpu_cc_freq; 177 } 178 179 static u_int 180 get_ppcbooke_timecount(struct timecounter *tc) 181 { 182 return mftbl(); 183 } 184 185 /* 186 * Wait for about n microseconds (at least!). 187 */ 188 void 189 delay(unsigned int n) 190 { 191 uint64_t tb; 192 u_long tbh, tbl, scratch; 193 194 tb = mftb(); 195 /* use 1000ULL to force 64 bit math to avoid 32 bit overflows */ 196 tb += (n * 1000ULL + ns_per_tick - 1) / ns_per_tick; 197 tbh = tb >> 32; 198 tbl = tb; 199 __asm volatile ( 200 "1: mfspr %0,%4" "\n" 201 " cmplw %0,%1" "\n" 202 " blt 1b" "\n" 203 " bgt 2f" "\n" 204 " mfspr %0,%3" "\n" 205 " cmplw %0,%2" "\n" 206 " blt 1b" "\n" 207 "2:" "\n" 208 : "=&r"(scratch) 209 : "r"(tbh), "r"(tbl), "n"(SPR_TBL), "n"(SPR_TBU) 210 : "cr0"); 211 } 212 213 /* 214 * Nothing to do. 215 */ 216 void 217 setstatclockrate(int arg) 218 { 219 220 /* Do nothing */ 221 } 222 223 static void 224 init_ppcbooke_tc(void) 225 { 226 /* from machdep initialization */ 227 ppcbooke_timecounter.tc_frequency = curcpu()->ci_data.cpu_cc_freq; 228 tc_init(&ppcbooke_timecounter); 229 } 230
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