fpu_implode.c revision 1.15
1 /* $NetBSD: fpu_implode.c,v 1.15 2022/09/02 12:22:49 rin Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * FPU subroutines: `implode' internal format numbers into the machine's 45 * `packed binary' format. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: fpu_implode.c,v 1.15 2022/09/02 12:22:49 rin Exp $"); 50 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 54 #include <powerpc/instr.h> 55 #include <machine/fpu.h> 56 #include <machine/ieee.h> 57 #include <machine/reg.h> 58 59 #include <powerpc/fpu/fpu_arith.h> 60 #include <powerpc/fpu/fpu_emu.h> 61 #include <powerpc/fpu/fpu_extern.h> 62 63 static int round(struct fpemu *, struct fpn *); 64 static int toinf(struct fpemu *, int); 65 static int round_int(struct fpn *, int *, int, int, int); 66 67 static u_int fpu_ftoi(struct fpemu *, struct fpn *, int); 68 static uint64_t fpu_ftox(struct fpemu *, struct fpn *, int); 69 static u_int fpu_ftos(struct fpemu *, struct fpn *, bool); 70 static uint64_t fpu_ftod(struct fpemu *, struct fpn *, bool); 71 72 /* 73 * Round a number (algorithm from Motorola MC68882 manual, modified for 74 * our internal format). Set inexact exception if rounding is required. 75 * Return true iff we rounded up. 76 * 77 * After rounding, we discard the guard and round bits by shifting right 78 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 79 * This saves effort later. 80 * 81 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 82 * responsibility to fix this if necessary. 83 */ 84 static int 85 round(struct fpemu *fe, struct fpn *fp) 86 { 87 u_int m0, m1, m2, m3; 88 int gr, s; 89 FPU_DECL_CARRY; 90 91 m0 = fp->fp_mant[0]; 92 m1 = fp->fp_mant[1]; 93 m2 = fp->fp_mant[2]; 94 m3 = fp->fp_mant[3]; 95 gr = m3 & 3; 96 s = fp->fp_sticky; 97 98 /* mant >>= FP_NG */ 99 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 100 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 101 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 102 m0 >>= FP_NG; 103 104 if ((gr | s) == 0) /* result is exact: no rounding needed */ 105 goto rounddown; 106 107 fe->fe_cx |= FPSCR_XX|FPSCR_FI; /* inexact */ 108 109 /* Go to rounddown to round down; break to round up. */ 110 switch ((fe->fe_fpscr) & FPSCR_RN) { 111 112 case FSR_RD_RN: 113 default: 114 /* 115 * Round only if guard is set (gr & 2). If guard is set, 116 * but round & sticky both clear, then we want to round 117 * but have a tie, so round to even, i.e., add 1 iff odd. 118 */ 119 if ((gr & 2) == 0) 120 goto rounddown; 121 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 122 break; 123 goto rounddown; 124 125 case FSR_RD_RZ: 126 /* Round towards zero, i.e., down. */ 127 goto rounddown; 128 129 case FSR_RD_RM: 130 /* Round towards -Inf: up if negative, down if positive. */ 131 if (fp->fp_sign) 132 break; 133 goto rounddown; 134 135 case FSR_RD_RP: 136 /* Round towards +Inf: up if positive, down otherwise. */ 137 if (!fp->fp_sign) 138 break; 139 goto rounddown; 140 } 141 142 /* Bump low bit of mantissa, with carry. */ 143 fe->fe_cx |= FPSCR_FR; 144 145 FPU_ADDS(m3, m3, 1); 146 FPU_ADDCS(m2, m2, 0); 147 FPU_ADDCS(m1, m1, 0); 148 FPU_ADDC(m0, m0, 0); 149 fp->fp_mant[0] = m0; 150 fp->fp_mant[1] = m1; 151 fp->fp_mant[2] = m2; 152 fp->fp_mant[3] = m3; 153 return (1); 154 155 rounddown: 156 fp->fp_mant[0] = m0; 157 fp->fp_mant[1] = m1; 158 fp->fp_mant[2] = m2; 159 fp->fp_mant[3] = m3; 160 return (0); 161 } 162 163 /* 164 * For overflow: return true if overflow is to go to +/-Inf, according 165 * to the sign of the overflowing result. If false, overflow is to go 166 * to the largest magnitude value instead. 167 */ 168 static int 169 toinf(struct fpemu *fe, int sign) 170 { 171 int inf; 172 173 /* look at rounding direction */ 174 switch ((fe->fe_fpscr) & FPSCR_RN) { 175 176 default: 177 case FSR_RD_RN: /* the nearest value is always Inf */ 178 inf = 1; 179 break; 180 181 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 182 inf = 0; 183 break; 184 185 case FSR_RD_RP: /* toward +Inf iff positive */ 186 inf = sign == 0; 187 break; 188 189 case FSR_RD_RM: /* toward -Inf iff negative */ 190 inf = sign; 191 break; 192 } 193 if (inf) 194 fe->fe_cx |= FPSCR_OX; 195 return (inf); 196 } 197 198 static int 199 round_int(struct fpn *fp, int *cx, int rn, int sign, int odd) 200 { 201 int g, rs; 202 203 g = fp->fp_mant[3] & 0x80000000; 204 rs = (fp->fp_mant[3] & 0x7fffffff) | fp->fp_sticky; 205 206 if ((g | rs) == 0) 207 return 0; /* exact */ 208 209 *cx |= FPSCR_XX | FPSCR_FI; 210 211 switch (rn) { 212 case FSR_RD_RN: 213 if (g && (rs | odd)) 214 break; 215 return 0; 216 case FSR_RD_RZ: 217 return 0; 218 case FSR_RD_RP: 219 if (!sign) 220 break; 221 return 0; 222 case FSR_RD_RM: 223 if (sign) 224 break; 225 return 0; 226 } 227 228 *cx |= FPSCR_FR; 229 return 1; 230 } 231 232 /* 233 * fpn -> int (int value returned as return value). 234 */ 235 static u_int 236 fpu_ftoi(struct fpemu *fe, struct fpn *fp, int rn) 237 { 238 u_int i; 239 int sign, exp, cx; 240 241 sign = fp->fp_sign; 242 cx = 0; 243 switch (fp->fp_class) { 244 case FPC_SNAN: 245 fe->fe_cx |= FPSCR_VXSNAN; 246 /* FALLTHROUGH */ 247 case FPC_QNAN: 248 sign = 1; 249 break; 250 251 case FPC_ZERO: 252 return (0); 253 254 case FPC_NUM: 255 /* 256 * If exp >= 2^32, overflow. Otherwise shift value right 257 * into last mantissa word (this will not exceed 0xffffffff), 258 * shifting any guard and round bits out into the sticky 259 * bit. Then ``round'' towards zero, i.e., just set an 260 * inexact exception if sticky is set (see round()). 261 * If the result is > 0x80000000, or is positive and equals 262 * 0x80000000, overflow; otherwise the last fraction word 263 * is the result. 264 */ 265 if ((exp = fp->fp_exp) >= 32) 266 break; 267 /* NB: the following includes exp < 0 cases */ 268 (void)fpu_shr(fp, FP_NMANT - 32 - 1 - exp); 269 i = fp->fp_mant[2]; 270 i += round_int(fp, &cx, rn, sign, i & 1); 271 if (i >= ((u_int)0x80000000 + sign)) 272 break; 273 fe->fe_cx |= cx; 274 return (sign ? -i : i); 275 276 case FPC_INF: 277 break; 278 } 279 /* overflow: replace any inexact exception with invalid */ 280 fe->fe_cx |= FPSCR_VXCVI; 281 return (0x7fffffff + sign); 282 } 283 284 /* 285 * fpn -> extended int (high bits of int value returned as return value). 286 */ 287 static uint64_t 288 fpu_ftox(struct fpemu *fe, struct fpn *fp, int rn) 289 { 290 uint64_t i; 291 int sign, exp, cx; 292 293 sign = fp->fp_sign; 294 cx = 0; 295 switch (fp->fp_class) { 296 case FPC_SNAN: 297 fe->fe_cx |= FPSCR_VXSNAN; 298 /* FALLTHROUGH */ 299 case FPC_QNAN: 300 sign = 1; 301 break; 302 303 case FPC_ZERO: 304 return (0); 305 306 case FPC_NUM: 307 /* 308 * If exp >= 2^64, overflow. Otherwise shift value right 309 * into last mantissa word (this will not exceed 0xffffffffffffffff), 310 * shifting any guard and round bits out into the sticky 311 * bit. Then ``round'' towards zero, i.e., just set an 312 * inexact exception if sticky is set (see round()). 313 * If the result is > 0x8000000000000000, or is positive and equals 314 * 0x8000000000000000, overflow; otherwise the last fraction word 315 * is the result. 316 */ 317 if ((exp = fp->fp_exp) >= 64) 318 break; 319 /* NB: the following includes exp < 0 cases */ 320 (void)fpu_shr(fp, FP_NMANT - 32 - 1 - exp); 321 i = ((uint64_t)fp->fp_mant[1] << 32) | fp->fp_mant[2]; 322 i += round_int(fp, &cx, rn, sign, i & 1); 323 if (i >= ((uint64_t)0x8000000000000000LL + sign)) 324 break; 325 fe->fe_cx |= cx; 326 return (sign ? -i : i); 327 328 case FPC_INF: 329 break; 330 } 331 /* overflow: replace any inexact exception with invalid */ 332 fe->fe_cx |= FPSCR_VXCVI; 333 return (0x7fffffffffffffffLL + sign); 334 } 335 336 #define FPRF_SIGN(sign) ((sign) ? FPSCR_FL : FPSCR_FG) 337 338 /* 339 * fpn -> single (32 bit single returned as return value). 340 * We assume <= 29 bits in a single-precision fraction (1.f part). 341 */ 342 static u_int 343 fpu_ftos(struct fpemu *fe, struct fpn *fp, bool fprf) 344 { 345 u_int sign = fp->fp_sign << 31; 346 int exp; 347 348 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 349 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 350 351 /* Take care of non-numbers first. */ 352 if (ISNAN(fp)) { 353 if (fprf) 354 fe->fe_cx |= FPSCR_C | FPSCR_FU; 355 /* 356 * Preserve upper bits of NaN, per SPARC V8 appendix N. 357 * Note that fp->fp_mant[0] has the quiet bit set, 358 * even if it is classified as a signalling NaN. 359 */ 360 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 361 exp = SNG_EXP_INFNAN; 362 goto done; 363 } 364 if (ISINF(fp)) { 365 if (fprf) 366 fe->fe_cx |= FPRF_SIGN(sign) | FPSCR_FU; 367 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 368 } 369 if (ISZERO(fp)) { 370 if (fprf) { 371 fe->fe_cx |= FPSCR_FE; 372 if (sign) 373 fe->fe_cx |= FPSCR_C; 374 } 375 return (sign); 376 } 377 378 /* 379 * Normals (including subnormals). Drop all the fraction bits 380 * (including the explicit ``implied'' 1 bit) down into the 381 * single-precision range. If the number is subnormal, move 382 * the ``implied'' 1 into the explicit range as well, and shift 383 * right to introduce leading zeroes. Rounding then acts 384 * differently for normals and subnormals: the largest subnormal 385 * may round to the smallest normal (1.0 x 2^minexp), or may 386 * remain subnormal. In the latter case, signal an underflow 387 * if the result was inexact or if underflow traps are enabled. 388 * 389 * Rounding a normal, on the other hand, always produces another 390 * normal (although either way the result might be too big for 391 * single precision, and cause an overflow). If rounding a 392 * normal produces 2.0 in the fraction, we need not adjust that 393 * fraction at all, since both 1.0 and 2.0 are zero under the 394 * fraction mask. 395 * 396 * Note that the guard and round bits vanish from the number after 397 * rounding. 398 */ 399 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 400 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 401 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 402 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) { 403 if (fprf) 404 fe->fe_cx |= FPRF_SIGN(sign); 405 return (sign | SNG_EXP(1) | 0); 406 } 407 if (fprf) 408 fe->fe_cx |= FPSCR_C | FPRF_SIGN(sign); 409 if ((fe->fe_cx & FPSCR_FI) || 410 (fe->fe_fpscr & FPSCR_UX)) 411 fe->fe_cx |= FPSCR_UX; 412 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 413 } 414 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 415 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 416 #ifdef DIAGNOSTIC 417 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 418 panic("fpu_ftos"); 419 #endif 420 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 421 exp++; 422 if (exp >= SNG_EXP_INFNAN) { 423 /* overflow to inf or to max single */ 424 if (toinf(fe, sign)) { 425 if (fprf) 426 fe->fe_cx |= FPRF_SIGN(sign) | FPSCR_FU; 427 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 428 } 429 if (fprf) 430 fe->fe_cx |= FPRF_SIGN(sign); 431 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 432 } 433 if (fprf) 434 fe->fe_cx |= FPRF_SIGN(sign); 435 done: 436 /* phew, made it */ 437 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 438 } 439 440 /* 441 * fpn -> double. Assumes <= 61 bits in double precision fraction. 442 * 443 * This code mimics fpu_ftos; see it for comments. 444 */ 445 static uint64_t 446 fpu_ftod(struct fpemu *fe, struct fpn *fp, bool fprf) 447 { 448 u_int sign = fp->fp_sign << 31; 449 int exp; 450 451 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 452 #define DBL_MASK (DBL_EXP(1) - 1) 453 #define HI_WORD(i) ((uint64_t)(i) << 32) 454 #define LO_WORD(i) ((uint32_t)(i)) 455 456 if (ISNAN(fp)) { 457 if (fprf) 458 fe->fe_cx |= FPSCR_C | FPSCR_FU; 459 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 460 exp = DBL_EXP_INFNAN; 461 goto done; 462 } 463 if (ISINF(fp)) { 464 if (fprf) 465 fe->fe_cx |= FPRF_SIGN(sign) | FPSCR_FU; 466 sign |= DBL_EXP(DBL_EXP_INFNAN); 467 goto zero; 468 } 469 if (ISZERO(fp)) { 470 if (fprf) { 471 fe->fe_cx |= FPSCR_FE; 472 if (sign) 473 fe->fe_cx |= FPSCR_C; 474 } 475 zero: return HI_WORD(sign); 476 } 477 478 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 479 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 480 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 481 if (fprf) 482 fe->fe_cx |= FPRF_SIGN(sign); 483 return HI_WORD(sign | DBL_EXP(1) | 0); 484 } 485 if (fprf) 486 fe->fe_cx |= FPSCR_C | FPRF_SIGN(sign); 487 if ((fe->fe_cx & FPSCR_FI) || 488 (fe->fe_fpscr & FPSCR_UX)) 489 fe->fe_cx |= FPSCR_UX; 490 exp = 0; 491 goto done; 492 } 493 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 494 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 495 exp++; 496 if (exp >= DBL_EXP_INFNAN) { 497 fe->fe_cx |= FPSCR_OX; 498 if (toinf(fe, sign)) { 499 if (fprf) 500 fe->fe_cx |= FPRF_SIGN(sign) | FPSCR_FU; 501 return HI_WORD(sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 502 } 503 if (fprf) 504 fe->fe_cx |= FPRF_SIGN(sign); 505 return HI_WORD(sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK) | 506 LO_WORD(~0); 507 } 508 if (fprf) 509 fe->fe_cx |= FPRF_SIGN(sign); 510 done: 511 return HI_WORD(sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)) | 512 LO_WORD(fp->fp_mant[3]); 513 } 514 515 /* 516 * Implode an fpn, writing the result into the given space. 517 */ 518 void 519 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space) 520 { 521 int rn; 522 bool fprf; 523 524 if (type & FTYPE_RD_RZ) 525 rn = FSR_RD_RZ; 526 else 527 rn = fe->fe_fpscr & FPSCR_RN; 528 fprf = type & FTYPE_FPRF; 529 type &= ~FTYPE_FLAG_MASK; 530 531 switch (type) { 532 533 case FTYPE_LNG: 534 /* FPRF is undefined. */ 535 *(uint64_t *)space = fpu_ftox(fe, fp, rn); 536 DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n", 537 space[0], space[1])); 538 break; 539 540 case FTYPE_INT: 541 /* FPRF is undefined. */ 542 space[0] = 0; 543 space[1] = fpu_ftoi(fe, fp, rn); 544 DPRINTF(FPE_REG, ("fpu_implode: int %x\n", 545 space[1])); 546 break; 547 548 case FTYPE_SNG: 549 space[0] = fpu_ftos(fe, fp, fprf); 550 DPRINTF(FPE_REG, ("fpu_implode: single %x\n", 551 space[0])); 552 break; 553 554 case FTYPE_DBL: 555 *(uint64_t *)space = fpu_ftod(fe, fp, fprf); 556 DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n", 557 space[0], space[1])); 558 break; break; 559 560 default: 561 panic("fpu_implode: invalid type %d", type); 562 } 563 } 564
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