cpu.c revision 1.2.6.2
1 1.2.6.2 nathanw /* $NetBSD: cpu.c,v 1.2.6.2 2002/04/01 07:42:01 nathanw Exp $ */ 2 1.2.6.2 nathanw 3 1.2.6.2 nathanw /* 4 1.2.6.2 nathanw * Copyright 2001 Wasabi Systems, Inc. 5 1.2.6.2 nathanw * All rights reserved. 6 1.2.6.2 nathanw * 7 1.2.6.2 nathanw * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 1.2.6.2 nathanw * 9 1.2.6.2 nathanw * Redistribution and use in source and binary forms, with or without 10 1.2.6.2 nathanw * modification, are permitted provided that the following conditions 11 1.2.6.2 nathanw * are met: 12 1.2.6.2 nathanw * 1. Redistributions of source code must retain the above copyright 13 1.2.6.2 nathanw * notice, this list of conditions and the following disclaimer. 14 1.2.6.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.6.2 nathanw * notice, this list of conditions and the following disclaimer in the 16 1.2.6.2 nathanw * documentation and/or other materials provided with the distribution. 17 1.2.6.2 nathanw * 3. All advertising materials mentioning features or use of this software 18 1.2.6.2 nathanw * must display the following acknowledgement: 19 1.2.6.2 nathanw * This product includes software developed for the NetBSD Project by 20 1.2.6.2 nathanw * Wasabi Systems, Inc. 21 1.2.6.2 nathanw * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 1.2.6.2 nathanw * or promote products derived from this software without specific prior 23 1.2.6.2 nathanw * written permission. 24 1.2.6.2 nathanw * 25 1.2.6.2 nathanw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 1.2.6.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.2.6.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.2.6.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 1.2.6.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.2.6.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.2.6.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.2.6.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.2.6.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.2.6.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.2.6.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 36 1.2.6.2 nathanw */ 37 1.2.6.2 nathanw 38 1.2.6.2 nathanw #include <sys/param.h> 39 1.2.6.2 nathanw #include <sys/systm.h> 40 1.2.6.2 nathanw #include <sys/device.h> 41 1.2.6.2 nathanw #include <sys/properties.h> 42 1.2.6.2 nathanw 43 1.2.6.2 nathanw #include <machine/autoconf.h> 44 1.2.6.2 nathanw #include <machine/dcr.h> 45 1.2.6.2 nathanw #include <machine/cpu.h> 46 1.2.6.2 nathanw 47 1.2.6.2 nathanw struct cputab { 48 1.2.6.2 nathanw int version; 49 1.2.6.2 nathanw char *name; 50 1.2.6.2 nathanw }; 51 1.2.6.2 nathanw static struct cputab models[] = { 52 1.2.6.2 nathanw { PVR_401A1 >> 16, "401A1" }, 53 1.2.6.2 nathanw { PVR_401B2 >> 16, "401B21" }, 54 1.2.6.2 nathanw { PVR_401C2 >> 16, "401C2" }, 55 1.2.6.2 nathanw { PVR_401D2 >> 16, "401D2" }, 56 1.2.6.2 nathanw { PVR_401E2 >> 16, "401E2" }, 57 1.2.6.2 nathanw { PVR_401F2 >> 16, "401F2" }, 58 1.2.6.2 nathanw { PVR_401G2 >> 16, "401G2" }, 59 1.2.6.2 nathanw { PVR_403 >> 16, "403" }, 60 1.2.6.2 nathanw { PVR_405GP >> 16, "405GP" }, 61 1.2.6.2 nathanw { 0, NULL } 62 1.2.6.2 nathanw }; 63 1.2.6.2 nathanw 64 1.2.6.2 nathanw static int cpumatch(struct device *, struct cfdata *, void *); 65 1.2.6.2 nathanw static void cpuattach(struct device *, struct device *, void *); 66 1.2.6.2 nathanw 67 1.2.6.2 nathanw /* 68 1.2.6.2 nathanw * Arguably the ECC stuff belongs somewhere else.... 69 1.2.6.2 nathanw */ 70 1.2.6.2 nathanw int intr_ecc(void *); 71 1.2.6.2 nathanw 72 1.2.6.2 nathanw u_quad_t intr_ecc_tb; 73 1.2.6.2 nathanw u_quad_t intr_ecc_iv; /* Interval */ 74 1.2.6.2 nathanw u_int32_t intr_ecc_cnt; 75 1.2.6.2 nathanw 76 1.2.6.2 nathanw struct cfattach cpu_ca = { 77 1.2.6.2 nathanw sizeof(struct device), cpumatch, cpuattach 78 1.2.6.2 nathanw }; 79 1.2.6.2 nathanw 80 1.2.6.2 nathanw int ncpus; 81 1.2.6.2 nathanw 82 1.2.6.2 nathanw struct cpu_info cpu_info_store; 83 1.2.6.2 nathanw 84 1.2.6.2 nathanw int cpufound = 0; 85 1.2.6.2 nathanw 86 1.2.6.2 nathanw static int 87 1.2.6.2 nathanw cpumatch(struct device *parent, struct cfdata *cf, void *aux) 88 1.2.6.2 nathanw { 89 1.2.6.2 nathanw struct mainbus_attach_args *maa = aux; 90 1.2.6.2 nathanw 91 1.2.6.2 nathanw /* make sure that we're looking for a CPU */ 92 1.2.6.2 nathanw if (strcmp(maa->mb_name, cf->cf_driver->cd_name) != 0) 93 1.2.6.2 nathanw return (0); 94 1.2.6.2 nathanw 95 1.2.6.2 nathanw return !cpufound; 96 1.2.6.2 nathanw } 97 1.2.6.2 nathanw 98 1.2.6.2 nathanw static void 99 1.2.6.2 nathanw cpuattach(struct device *parent, struct device *self, void *aux) 100 1.2.6.2 nathanw { 101 1.2.6.2 nathanw int pvr, cpu; 102 1.2.6.2 nathanw int own, pcf, cas, pcl, aid; 103 1.2.6.2 nathanw struct cputab *cp = models; 104 1.2.6.2 nathanw unsigned int processor_freq; 105 1.2.6.2 nathanw 106 1.2.6.2 nathanw if (board_info_get("processor-frequency", 107 1.2.6.2 nathanw &processor_freq, sizeof(processor_freq)) == -1) 108 1.2.6.2 nathanw panic("no processor-frequency"); 109 1.2.6.2 nathanw 110 1.2.6.2 nathanw cpufound++; 111 1.2.6.2 nathanw ncpus++; 112 1.2.6.2 nathanw 113 1.2.6.2 nathanw asm ("mfpvr %0" : "=r"(pvr)); 114 1.2.6.2 nathanw cpu = pvr >> 16; 115 1.2.6.2 nathanw 116 1.2.6.2 nathanw /* Break PVR up into separate fields and print them out. */ 117 1.2.6.2 nathanw own = (pvr >> 20) & 0xfff; 118 1.2.6.2 nathanw pcf = (pvr >> 16) & 0xf; 119 1.2.6.2 nathanw cas = (pvr >> 10) & 0x3f; 120 1.2.6.2 nathanw pcl = (pvr >> 6) & 0xf; 121 1.2.6.2 nathanw aid = pvr & 0x3f; 122 1.2.6.2 nathanw 123 1.2.6.2 nathanw while (cp->name) { 124 1.2.6.2 nathanw if (cp->version == cpu) 125 1.2.6.2 nathanw break; 126 1.2.6.2 nathanw cp++; 127 1.2.6.2 nathanw } 128 1.2.6.2 nathanw if (cp->name) 129 1.2.6.2 nathanw strcpy(cpu_model, cp->name); 130 1.2.6.2 nathanw else 131 1.2.6.2 nathanw sprintf(cpu_model, "Version 0x%x", cpu); 132 1.2.6.2 nathanw sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)", 133 1.2.6.2 nathanw (pvr >> 8) & 0xff, pvr & 0xff); 134 1.2.6.2 nathanw 135 1.2.6.2 nathanw #if 1 136 1.2.6.2 nathanw printf(": %dMHz %s\n", processor_freq / 1000 / 1000, 137 1.2.6.2 nathanw cpu_model); 138 1.2.6.2 nathanw #endif 139 1.2.6.2 nathanw 140 1.2.6.2 nathanw cpu_probe_cache(); 141 1.2.6.2 nathanw 142 1.2.6.2 nathanw printf("Instruction cache size %d line size %d\n", 143 1.2.6.2 nathanw curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 144 1.2.6.2 nathanw printf("Data cache size %d line size %d\n", 145 1.2.6.2 nathanw curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 146 1.2.6.2 nathanw 147 1.2.6.2 nathanw #ifdef DEBUG 148 1.2.6.2 nathanw /* It sux that the cache info here is useless. */ 149 1.2.6.2 nathanw printf("PVR: owner %x core family %x cache %x version %x asic %x\n", 150 1.2.6.2 nathanw own, pcf, cas, pcl, aid); 151 1.2.6.2 nathanw #endif 152 1.2.6.2 nathanw 153 1.2.6.2 nathanw /* Initialize ECC error-logging handler. This is always enabled, 154 1.2.6.2 nathanw * but it will never be called on systems that do not have ECC 155 1.2.6.2 nathanw * enabled by POST code in the bootloader. 156 1.2.6.2 nathanw */ 157 1.2.6.2 nathanw 158 1.2.6.2 nathanw printf("Enabling ecc handler\n"); 159 1.2.6.2 nathanw intr_ecc_tb = 0; 160 1.2.6.2 nathanw intr_ecc_iv = processor_freq; /* Set interval */ 161 1.2.6.2 nathanw intr_ecc_cnt = 0; 162 1.2.6.2 nathanw 163 1.2.6.2 nathanw intr_establish(16, IST_LEVEL, IPL_SERIAL, intr_ecc, NULL); 164 1.2.6.2 nathanw } 165 1.2.6.2 nathanw 166 1.2.6.2 nathanw /* 167 1.2.6.2 nathanw * This routine must be explicitly called to initialize the 168 1.2.6.2 nathanw * CPU cache information so cache flushe and memcpy operation 169 1.2.6.2 nathanw * work. 170 1.2.6.2 nathanw */ 171 1.2.6.2 nathanw void 172 1.2.6.2 nathanw cpu_probe_cache() 173 1.2.6.2 nathanw { 174 1.2.6.2 nathanw int version; 175 1.2.6.2 nathanw 176 1.2.6.2 nathanw /* 177 1.2.6.2 nathanw * First we need to identify the cpu and determine the 178 1.2.6.2 nathanw * cache line size, or things like memset/memcpy may lose 179 1.2.6.2 nathanw * badly. 180 1.2.6.2 nathanw */ 181 1.2.6.2 nathanw __asm __volatile("mfpvr %0" : "=r" (version)); 182 1.2.6.2 nathanw switch (version & 0xffff0000) { 183 1.2.6.2 nathanw case PVR_401A1: 184 1.2.6.2 nathanw curcpu()->ci_ci.dcache_size = 1024; 185 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 16; 186 1.2.6.2 nathanw curcpu()->ci_ci.icache_size = 2848; 187 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 16; 188 1.2.6.2 nathanw break; 189 1.2.6.2 nathanw case PVR_401B2: 190 1.2.6.2 nathanw curcpu()->ci_ci.dcache_size = 8192; 191 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 16; 192 1.2.6.2 nathanw curcpu()->ci_ci.icache_size = 16384; 193 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 16; 194 1.2.6.2 nathanw break; 195 1.2.6.2 nathanw case PVR_401C2: 196 1.2.6.2 nathanw curcpu()->ci_ci.dcache_size = 8192; 197 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 16; 198 1.2.6.2 nathanw curcpu()->ci_ci.icache_size = 0; 199 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 16; 200 1.2.6.2 nathanw break; 201 1.2.6.2 nathanw case PVR_401D2: 202 1.2.6.2 nathanw curcpu()->ci_ci.dcache_size = 2848; 203 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 16; 204 1.2.6.2 nathanw curcpu()->ci_ci.icache_size = 4096; 205 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 16; 206 1.2.6.2 nathanw break; 207 1.2.6.2 nathanw case PVR_401E2: 208 1.2.6.2 nathanw curcpu()->ci_ci.dcache_size = 0; 209 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 16; 210 1.2.6.2 nathanw curcpu()->ci_ci.icache_size = 0; 211 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 16; 212 1.2.6.2 nathanw break; 213 1.2.6.2 nathanw case PVR_401F2: 214 1.2.6.2 nathanw curcpu()->ci_ci.dcache_size = 2048; 215 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 16; 216 1.2.6.2 nathanw curcpu()->ci_ci.icache_size = 2848; 217 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 16; 218 1.2.6.2 nathanw break; 219 1.2.6.2 nathanw case PVR_401G2: 220 1.2.6.2 nathanw curcpu()->ci_ci.dcache_size = 2848; 221 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 16; 222 1.2.6.2 nathanw curcpu()->ci_ci.icache_size = 8192; 223 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 16; 224 1.2.6.2 nathanw break; 225 1.2.6.2 nathanw case PVR_403: 226 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 16; 227 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 16; 228 1.2.6.2 nathanw break; 229 1.2.6.2 nathanw case PVR_405GP: 230 1.2.6.2 nathanw curcpu()->ci_ci.dcache_size = 8192; 231 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 32; 232 1.2.6.2 nathanw curcpu()->ci_ci.icache_size = 8192; 233 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 32; 234 1.2.6.2 nathanw break; 235 1.2.6.2 nathanw default: 236 1.2.6.2 nathanw /* 237 1.2.6.2 nathanw * Unknown CPU type. For safety we'll specify a 238 1.2.6.2 nathanw * cache with a 4-byte line size. That way cache 239 1.2.6.2 nathanw * flush routines won't miss any lines. 240 1.2.6.2 nathanw */ 241 1.2.6.2 nathanw curcpu()->ci_ci.dcache_line_size = 4; 242 1.2.6.2 nathanw curcpu()->ci_ci.icache_line_size = 4; 243 1.2.6.2 nathanw break; 244 1.2.6.2 nathanw } 245 1.2.6.2 nathanw 246 1.2.6.2 nathanw } 247 1.2.6.2 nathanw 248 1.2.6.2 nathanw /* 249 1.2.6.2 nathanw * These small routines may have to be replaced, 250 1.2.6.2 nathanw * if/when we support processors other that the 604. 251 1.2.6.2 nathanw */ 252 1.2.6.2 nathanw 253 1.2.6.2 nathanw void 254 1.2.6.2 nathanw dcache_flush_page(vaddr_t va) 255 1.2.6.2 nathanw { 256 1.2.6.2 nathanw int i; 257 1.2.6.2 nathanw 258 1.2.6.2 nathanw if (curcpu()->ci_ci.dcache_line_size) 259 1.2.6.2 nathanw for (i = 0; i < NBPG; i += curcpu()->ci_ci.dcache_line_size) 260 1.2.6.2 nathanw asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 261 1.2.6.2 nathanw asm volatile("sync;isync" : : ); 262 1.2.6.2 nathanw } 263 1.2.6.2 nathanw 264 1.2.6.2 nathanw void 265 1.2.6.2 nathanw icache_flush_page(vaddr_t va) 266 1.2.6.2 nathanw { 267 1.2.6.2 nathanw int i; 268 1.2.6.2 nathanw 269 1.2.6.2 nathanw if (curcpu()->ci_ci.icache_line_size) 270 1.2.6.2 nathanw for (i = 0; i < NBPG; i += curcpu()->ci_ci.icache_line_size) 271 1.2.6.2 nathanw asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 272 1.2.6.2 nathanw asm volatile("sync;isync" : : ); 273 1.2.6.2 nathanw } 274 1.2.6.2 nathanw 275 1.2.6.2 nathanw void 276 1.2.6.2 nathanw dcache_flush(vaddr_t va, vsize_t len) 277 1.2.6.2 nathanw { 278 1.2.6.2 nathanw int i; 279 1.2.6.2 nathanw 280 1.2.6.2 nathanw if (len == 0) 281 1.2.6.2 nathanw return; 282 1.2.6.2 nathanw 283 1.2.6.2 nathanw /* Make sure we flush all cache lines */ 284 1.2.6.2 nathanw len += va & (curcpu()->ci_ci.dcache_line_size-1); 285 1.2.6.2 nathanw if (curcpu()->ci_ci.dcache_line_size) 286 1.2.6.2 nathanw for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 287 1.2.6.2 nathanw asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 288 1.2.6.2 nathanw asm volatile("sync;isync" : : ); 289 1.2.6.2 nathanw } 290 1.2.6.2 nathanw 291 1.2.6.2 nathanw void 292 1.2.6.2 nathanw icache_flush(vaddr_t va, vsize_t len) 293 1.2.6.2 nathanw { 294 1.2.6.2 nathanw int i; 295 1.2.6.2 nathanw 296 1.2.6.2 nathanw if (len == 0) 297 1.2.6.2 nathanw return; 298 1.2.6.2 nathanw 299 1.2.6.2 nathanw /* Make sure we flush all cache lines */ 300 1.2.6.2 nathanw len += va & (curcpu()->ci_ci.icache_line_size-1); 301 1.2.6.2 nathanw if (curcpu()->ci_ci.icache_line_size) 302 1.2.6.2 nathanw for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 303 1.2.6.2 nathanw asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 304 1.2.6.2 nathanw asm volatile("sync;isync" : : ); 305 1.2.6.2 nathanw } 306 1.2.6.2 nathanw 307 1.2.6.2 nathanw /* 308 1.2.6.2 nathanw * ECC fault handler. 309 1.2.6.2 nathanw */ 310 1.2.6.2 nathanw int 311 1.2.6.2 nathanw intr_ecc(void * arg) 312 1.2.6.2 nathanw { 313 1.2.6.2 nathanw u_int32_t esr, ear; 314 1.2.6.2 nathanw int ce, ue; 315 1.2.6.2 nathanw u_quad_t tb; 316 1.2.6.2 nathanw u_long tmp, msr, dat; 317 1.2.6.2 nathanw unsigned int memsiz; 318 1.2.6.2 nathanw 319 1.2.6.2 nathanw if (board_info_get("mem-size", &memsiz, sizeof(memsiz)) == -1) 320 1.2.6.2 nathanw panic("no mem-size"); 321 1.2.6.2 nathanw 322 1.2.6.2 nathanw /* This code needs to be improved to handle double-bit errors */ 323 1.2.6.2 nathanw /* in some intelligent fashion. */ 324 1.2.6.2 nathanw 325 1.2.6.2 nathanw mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 326 1.2.6.2 nathanw esr = mfdcr(DCR_SDRAM0_CFGDATA); 327 1.2.6.2 nathanw 328 1.2.6.2 nathanw mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_BEAR); 329 1.2.6.2 nathanw ear = mfdcr(DCR_SDRAM0_CFGDATA); 330 1.2.6.2 nathanw 331 1.2.6.2 nathanw /* Always clear the error to stop the intr ASAP. */ 332 1.2.6.2 nathanw 333 1.2.6.2 nathanw mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 334 1.2.6.2 nathanw mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff); 335 1.2.6.2 nathanw 336 1.2.6.2 nathanw if (esr == 0x00) { 337 1.2.6.2 nathanw /* No current error. Could happen due to intr. nesting */ 338 1.2.6.2 nathanw return(1); 339 1.2.6.2 nathanw }; 340 1.2.6.2 nathanw 341 1.2.6.2 nathanw /* Only report errors every once per second max. Do this using the TB, */ 342 1.2.6.2 nathanw /* because the system time (via microtime) may be adjusted when the date is set */ 343 1.2.6.2 nathanw /* and can't reliably be used to measure intervals. */ 344 1.2.6.2 nathanw 345 1.2.6.2 nathanw asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b" 346 1.2.6.2 nathanw : "=r"(tb), "=r"(tmp)); 347 1.2.6.2 nathanw intr_ecc_cnt++; 348 1.2.6.2 nathanw 349 1.2.6.2 nathanw if ((tb - intr_ecc_tb) < intr_ecc_iv) { 350 1.2.6.2 nathanw return(1); 351 1.2.6.2 nathanw }; 352 1.2.6.2 nathanw 353 1.2.6.2 nathanw ce = (esr & SDRAM0_ECCESR_CE) != 0x00; 354 1.2.6.2 nathanw ue = (esr & SDRAM0_ECCESR_UE) != 0x00; 355 1.2.6.2 nathanw 356 1.2.6.2 nathanw printf("ECC: Error CNT=%d ESR=%x EAR=%x %s BKNE=%d%d%d%d " 357 1.2.6.2 nathanw "BLCE=%d%d%d%d CBE=%d%d.\n", 358 1.2.6.2 nathanw intr_ecc_cnt, esr, ear, 359 1.2.6.2 nathanw (ue) ? "Uncorrectable" : "Correctable", 360 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_BKEN(0)) != 0x00), 361 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_BKEN(1)) != 0x00), 362 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_BKEN(2)) != 0x00), 363 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_BKEN(3)) != 0x00), 364 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_BLCEN(0)) != 0x00), 365 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_BLCEN(1)) != 0x00), 366 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_BLCEN(2)) != 0x00), 367 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_BLCEN(3)) != 0x00), 368 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_CBEN(0)) != 0x00), 369 1.2.6.2 nathanw ((esr & SDRAM0_ECCESR_CBEN(1)) != 0x00)); 370 1.2.6.2 nathanw 371 1.2.6.2 nathanw /* Should check for uncorrectable errors and panic... */ 372 1.2.6.2 nathanw 373 1.2.6.2 nathanw if (intr_ecc_cnt > 1000) { 374 1.2.6.2 nathanw printf("ECC: Too many errors, recycling entire " 375 1.2.6.2 nathanw "SDRAM (size = %d).\n", memsiz); 376 1.2.6.2 nathanw 377 1.2.6.2 nathanw /* Can this code be changed to run without disabling data MMU and disabling intrs? */ 378 1.2.6.2 nathanw /* Does kernel always map all of physical RAM VA=PA? If so, just loop over lowmem. */ 379 1.2.6.2 nathanw 380 1.2.6.2 nathanw asm volatile( 381 1.2.6.2 nathanw "mfmsr %0;" 382 1.2.6.2 nathanw "li %1, 0x00;" 383 1.2.6.2 nathanw "ori %1, %1, 0x8010;" 384 1.2.6.2 nathanw "andc %1, %0, %1;" 385 1.2.6.2 nathanw "mtmsr %1;" 386 1.2.6.2 nathanw "sync;isync;" 387 1.2.6.2 nathanw "li %1, 0x00;" 388 1.2.6.2 nathanw "1:" 389 1.2.6.2 nathanw "dcbt 0, %1;" 390 1.2.6.2 nathanw "sync;isync;" 391 1.2.6.2 nathanw "lwz %2, 0(%1);" 392 1.2.6.2 nathanw "stw %2, 0(%1);" 393 1.2.6.2 nathanw "sync;isync;" 394 1.2.6.2 nathanw "dcbf 0, %1;" 395 1.2.6.2 nathanw "sync;isync;" 396 1.2.6.2 nathanw "addi %1, %1, 0x20;" 397 1.2.6.2 nathanw "addic. %3, %3, -0x20;" 398 1.2.6.2 nathanw "bge 1b;" 399 1.2.6.2 nathanw "mtmsr %0;" 400 1.2.6.2 nathanw "sync;isync;" 401 1.2.6.2 nathanw : "=&r" (msr), "=&r" (tmp), "=&r" (dat) 402 1.2.6.2 nathanw : "r" (memsiz) : "0" ); 403 1.2.6.2 nathanw 404 1.2.6.2 nathanw mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 405 1.2.6.2 nathanw esr = mfdcr(DCR_SDRAM0_CFGDATA); 406 1.2.6.2 nathanw 407 1.2.6.2 nathanw mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 408 1.2.6.2 nathanw mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff); 409 1.2.6.2 nathanw 410 1.2.6.2 nathanw /* Correctable errors here are OK, mem should be clean now. */ 411 1.2.6.2 nathanw /* Should check for uncorrectable errors and panic... */ 412 1.2.6.2 nathanw printf("ECC: Recycling complete, ESR=%x. " 413 1.2.6.2 nathanw "Checking for persistent errors.\n", esr); 414 1.2.6.2 nathanw 415 1.2.6.2 nathanw asm volatile( 416 1.2.6.2 nathanw "mfmsr %0;" 417 1.2.6.2 nathanw "li %1, 0x00;" 418 1.2.6.2 nathanw "ori %1, %1, 0x8010;" 419 1.2.6.2 nathanw "andc %1, %0, %1;" 420 1.2.6.2 nathanw "mtmsr %1;" 421 1.2.6.2 nathanw "sync;isync;" 422 1.2.6.2 nathanw "li %1, 0x00;" 423 1.2.6.2 nathanw "1:" 424 1.2.6.2 nathanw "dcbt 0, %1;" 425 1.2.6.2 nathanw "sync;isync;" 426 1.2.6.2 nathanw "lwz %2, 0(%1);" 427 1.2.6.2 nathanw "stw %2, 0(%1);" 428 1.2.6.2 nathanw "sync;isync;" 429 1.2.6.2 nathanw "dcbf 0, %1;" 430 1.2.6.2 nathanw "sync;isync;" 431 1.2.6.2 nathanw "addi %1, %1, 0x20;" 432 1.2.6.2 nathanw "addic. %3, %3, -0x20;" 433 1.2.6.2 nathanw "bge 1b;" 434 1.2.6.2 nathanw "mtmsr %0;" 435 1.2.6.2 nathanw "sync;isync;" 436 1.2.6.2 nathanw : "=&r" (msr), "=&r" (tmp), "=&r" (dat) 437 1.2.6.2 nathanw : "r" (memsiz) : "0" ); 438 1.2.6.2 nathanw 439 1.2.6.2 nathanw mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 440 1.2.6.2 nathanw esr = mfdcr(DCR_SDRAM0_CFGDATA); 441 1.2.6.2 nathanw 442 1.2.6.2 nathanw /* If esr is non zero here, we're screwed. Should check this and panic. */ 443 1.2.6.2 nathanw printf("ECC: Persistent error check complete, " 444 1.2.6.2 nathanw "final ESR=%x.\n", esr); 445 1.2.6.2 nathanw }; 446 1.2.6.2 nathanw 447 1.2.6.2 nathanw intr_ecc_tb = tb; 448 1.2.6.2 nathanw intr_ecc_cnt = 0; 449 1.2.6.2 nathanw 450 1.2.6.2 nathanw return(1); 451 1.2.6.2 nathanw }; 452
Indexes created Tue Sep 30 20:09:53 GMT 2025