cpu.c revision 1.1
1 /* $NetBSD: cpu.c,v 1.1 2002/03/13 00:38:17 eeh Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 42 #include <machine/autoconf.h> 43 #include <machine/dcr.h> 44 45 struct cputab { 46 int version; 47 char *name; 48 }; 49 static struct cputab models[] = { 50 { PVR_401A1 >> 16, "401A1" }, 51 { PVR_401B2 >> 16, "401B21" }, 52 { PVR_401C2 >> 16, "401C2" }, 53 { PVR_401D2 >> 16, "401D2" }, 54 { PVR_401E2 >> 16, "401E2" }, 55 { PVR_401F2 >> 16, "401F2" }, 56 { PVR_401G2 >> 16, "401G2" }, 57 { PVR_403 >> 16, "403" }, 58 { PVR_405GP >> 16, "405GP" }, 59 { 0, NULL } 60 }; 61 62 static int cpumatch(struct device *, struct cfdata *, void *); 63 static void cpuattach(struct device *, struct device *, void *); 64 65 /* 66 * Arguably the ECC stuff belongs somewhere else.... 67 */ 68 int intr_ecc(void *); 69 70 u_quad_t intr_ecc_tb; 71 u_quad_t intr_ecc_iv; /* Interval */ 72 u_int32_t intr_ecc_cnt; 73 74 struct cfattach cpu_ca = { 75 sizeof(struct device), cpumatch, cpuattach 76 }; 77 78 int ncpus; 79 80 struct cpu_info cpu_info_store; 81 82 int cpufound = 0; 83 84 static int 85 cpumatch(struct device *parent, struct cfdata *cf, void *aux) 86 { 87 struct mainbus_attach_args *maa = aux; 88 89 /* make sure that we're looking for a CPU */ 90 if (strcmp(maa->mb_name, cf->cf_driver->cd_name) != 0) 91 return (0); 92 93 return !cpufound; 94 } 95 96 static void 97 cpuattach(struct device *parent, struct device *self, void *aux) 98 { 99 int pvr, cpu; 100 int own, pcf, cas, pcl, aid; 101 struct cputab *cp = models; 102 103 cpufound++; 104 ncpus++; 105 106 asm ("mfpvr %0" : "=r"(pvr)); 107 cpu = pvr >> 16; 108 109 /* Break PVR up into separate fields and print them out. */ 110 own = (pvr >> 20) & 0xfff; 111 pcf = (pvr >> 16) & 0xf; 112 cas = (pvr >> 10) & 0x3f; 113 pcl = (pvr >> 6) & 0xf; 114 aid = pvr & 0x3f; 115 116 while (cp->name) { 117 if (cp->version == cpu) 118 break; 119 cp++; 120 } 121 if (cp->name) 122 strcpy(cpu_model, cp->name); 123 else 124 sprintf(cpu_model, "Version 0x%x", cpu); 125 sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)", 126 (pvr >> 8) & 0xff, pvr & 0xff); 127 128 #if 1 129 printf(": %dMHz %s\n", board_data.processor_speed / 1000 / 1000, 130 cpu_model); 131 #endif 132 133 cpu_probe_cache(); 134 135 printf("Instruction cache size %d line size %d\n", 136 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 137 printf("Data cache size %d line size %d\n", 138 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 139 140 #ifdef DEBUG 141 /* It sux that the cache info here is useless. */ 142 printf("PVR: owner %x core family %x cache %x version %x asic %x\n", 143 own, pcf, cas, pcl, aid); 144 #endif 145 146 /* Initialize ECC error-logging handler. This is always enabled, 147 * but it will never be called on systems that do not have ECC 148 * enabled by POST code in the bootloader. 149 */ 150 151 printf("Enabling ecc handler\n"); 152 intr_ecc_tb = 0; 153 intr_ecc_iv = board_data.processor_speed; /* Set interval */ 154 intr_ecc_cnt = 0; 155 156 intr_establish(16, IST_LEVEL, IPL_SERIAL, intr_ecc, NULL); 157 } 158 159 /* 160 * This routine must be explicitly called to initialize the 161 * CPU cache information so cache flushe and memcpy operation 162 * work. 163 */ 164 void 165 cpu_probe_cache() 166 { 167 int version; 168 169 /* 170 * First we need to identify the cpu and determine the 171 * cache line size, or things like memset/memcpy may lose 172 * badly. 173 */ 174 __asm __volatile("mfpvr %0" : "=r" (version)); 175 switch (version & 0xffff0000) { 176 case PVR_401A1: 177 curcpu()->ci_ci.dcache_size = 1024; 178 curcpu()->ci_ci.dcache_line_size = 16; 179 curcpu()->ci_ci.icache_size = 2848; 180 curcpu()->ci_ci.icache_line_size = 16; 181 break; 182 case PVR_401B2: 183 curcpu()->ci_ci.dcache_size = 8192; 184 curcpu()->ci_ci.dcache_line_size = 16; 185 curcpu()->ci_ci.icache_size = 16384; 186 curcpu()->ci_ci.icache_line_size = 16; 187 break; 188 case PVR_401C2: 189 curcpu()->ci_ci.dcache_size = 8192; 190 curcpu()->ci_ci.dcache_line_size = 16; 191 curcpu()->ci_ci.icache_size = 0; 192 curcpu()->ci_ci.icache_line_size = 16; 193 break; 194 case PVR_401D2: 195 curcpu()->ci_ci.dcache_size = 2848; 196 curcpu()->ci_ci.dcache_line_size = 16; 197 curcpu()->ci_ci.icache_size = 4096; 198 curcpu()->ci_ci.icache_line_size = 16; 199 break; 200 case PVR_401E2: 201 curcpu()->ci_ci.dcache_size = 0; 202 curcpu()->ci_ci.dcache_line_size = 16; 203 curcpu()->ci_ci.icache_size = 0; 204 curcpu()->ci_ci.icache_line_size = 16; 205 break; 206 case PVR_401F2: 207 curcpu()->ci_ci.dcache_size = 2048; 208 curcpu()->ci_ci.dcache_line_size = 16; 209 curcpu()->ci_ci.icache_size = 2848; 210 curcpu()->ci_ci.icache_line_size = 16; 211 break; 212 case PVR_401G2: 213 curcpu()->ci_ci.dcache_size = 2848; 214 curcpu()->ci_ci.dcache_line_size = 16; 215 curcpu()->ci_ci.icache_size = 8192; 216 curcpu()->ci_ci.icache_line_size = 16; 217 break; 218 case PVR_403: 219 curcpu()->ci_ci.dcache_line_size = 16; 220 curcpu()->ci_ci.icache_line_size = 16; 221 break; 222 case PVR_405GP: 223 curcpu()->ci_ci.dcache_size = 8192; 224 curcpu()->ci_ci.dcache_line_size = 32; 225 curcpu()->ci_ci.icache_size = 8192; 226 curcpu()->ci_ci.icache_line_size = 32; 227 break; 228 default: 229 /* 230 * Unknown CPU type. For safety we'll specify a 231 * cache with a 4-byte line size. That way cache 232 * flush routines won't miss any lines. 233 */ 234 curcpu()->ci_ci.dcache_line_size = 4; 235 curcpu()->ci_ci.icache_line_size = 4; 236 break; 237 } 238 239 } 240 241 /* 242 * These small routines may have to be replaced, 243 * if/when we support processors other that the 604. 244 */ 245 246 void 247 dcache_flush_page(vaddr_t va) 248 { 249 int i; 250 251 if (curcpu()->ci_ci.dcache_line_size) 252 for (i = 0; i < NBPG; i += curcpu()->ci_ci.dcache_line_size) 253 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 254 asm volatile("sync;isync" : : ); 255 } 256 257 void 258 icache_flush_page(vaddr_t va) 259 { 260 int i; 261 262 if (curcpu()->ci_ci.icache_line_size) 263 for (i = 0; i < NBPG; i += curcpu()->ci_ci.icache_line_size) 264 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 265 asm volatile("sync;isync" : : ); 266 } 267 268 void 269 dcache_flush(vaddr_t va, vsize_t len) 270 { 271 int i; 272 273 if (len == 0) 274 return; 275 276 /* Make sure we flush all cache lines */ 277 len += va & (curcpu()->ci_ci.dcache_line_size-1); 278 if (curcpu()->ci_ci.dcache_line_size) 279 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 280 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 281 asm volatile("sync;isync" : : ); 282 } 283 284 void 285 icache_flush(vaddr_t va, vsize_t len) 286 { 287 int i; 288 289 if (len == 0) 290 return; 291 292 /* Make sure we flush all cache lines */ 293 len += va & (curcpu()->ci_ci.icache_line_size-1); 294 if (curcpu()->ci_ci.icache_line_size) 295 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 296 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 297 asm volatile("sync;isync" : : ); 298 } 299 300 /* 301 * ECC fault handler. 302 */ 303 int 304 intr_ecc(void * arg) 305 { 306 u_int32_t esr, ear; 307 int ce, ue; 308 u_quad_t tb; 309 u_long tmp, msr, dat; 310 311 /* This code needs to be improved to handle double-bit errors */ 312 /* in some intelligent fashion. */ 313 314 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 315 esr = mfdcr(DCR_SDRAM0_CFGDATA); 316 317 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_BEAR); 318 ear = mfdcr(DCR_SDRAM0_CFGDATA); 319 320 /* Always clear the error to stop the intr ASAP. */ 321 322 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 323 mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff); 324 325 if (esr == 0x00) { 326 /* No current error. Could happen due to intr. nesting */ 327 return(1); 328 }; 329 330 /* Only report errors every once per second max. Do this using the TB, */ 331 /* because the system time (via microtime) may be adjusted when the date is set */ 332 /* and can't reliably be used to measure intervals. */ 333 334 asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b" 335 : "=r"(tb), "=r"(tmp)); 336 intr_ecc_cnt++; 337 338 if ((tb - intr_ecc_tb) < intr_ecc_iv) { 339 return(1); 340 }; 341 342 ce = (esr & SDRAM0_ECCESR_CE) != 0x00; 343 ue = (esr & SDRAM0_ECCESR_UE) != 0x00; 344 345 printf("ECC: Error CNT=%d ESR=%x EAR=%x %s BKNE=%d%d%d%d " 346 "BLCE=%d%d%d%d CBE=%d%d.\n", 347 intr_ecc_cnt, esr, ear, 348 (ue) ? "Uncorrectable" : "Correctable", 349 ((esr & SDRAM0_ECCESR_BKEN(0)) != 0x00), 350 ((esr & SDRAM0_ECCESR_BKEN(1)) != 0x00), 351 ((esr & SDRAM0_ECCESR_BKEN(2)) != 0x00), 352 ((esr & SDRAM0_ECCESR_BKEN(3)) != 0x00), 353 ((esr & SDRAM0_ECCESR_BLCEN(0)) != 0x00), 354 ((esr & SDRAM0_ECCESR_BLCEN(1)) != 0x00), 355 ((esr & SDRAM0_ECCESR_BLCEN(2)) != 0x00), 356 ((esr & SDRAM0_ECCESR_BLCEN(3)) != 0x00), 357 ((esr & SDRAM0_ECCESR_CBEN(0)) != 0x00), 358 ((esr & SDRAM0_ECCESR_CBEN(1)) != 0x00)); 359 360 /* Should check for uncorrectable errors and panic... */ 361 362 if (intr_ecc_cnt > 1000) { 363 printf("ECC: Too many errors, recycling entire " 364 "SDRAM (size = %d).\n", board_data.mem_size); 365 366 /* Can this code be changed to run without disabling data MMU and disabling intrs? */ 367 /* Does kernel always map all of physical RAM VA=PA? If so, just loop over lowmem. */ 368 369 asm volatile( 370 "mfmsr %0;" 371 "li %1, 0x00;" 372 "ori %1, %1, 0x8010;" 373 "andc %1, %0, %1;" 374 "mtmsr %1;" 375 "sync;isync;" 376 "li %1, 0x00;" 377 "1:" 378 "dcbt 0, %1;" 379 "sync;isync;" 380 "lwz %2, 0(%1);" 381 "stw %2, 0(%1);" 382 "sync;isync;" 383 "dcbf 0, %1;" 384 "sync;isync;" 385 "addi %1, %1, 0x20;" 386 "addic. %3, %3, -0x20;" 387 "bge 1b;" 388 "mtmsr %0;" 389 "sync;isync;" 390 : "=&r" (msr), "=&r" (tmp), "=&r" (dat) 391 : "r" (board_data.mem_size) : "0" ); 392 393 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 394 esr = mfdcr(DCR_SDRAM0_CFGDATA); 395 396 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 397 mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff); 398 399 /* Correctable errors here are OK, mem should be clean now. */ 400 /* Should check for uncorrectable errors and panic... */ 401 printf("ECC: Recycling complete, ESR=%x. " 402 "Checking for persistent errors.\n", esr); 403 404 asm volatile( 405 "mfmsr %0;" 406 "li %1, 0x00;" 407 "ori %1, %1, 0x8010;" 408 "andc %1, %0, %1;" 409 "mtmsr %1;" 410 "sync;isync;" 411 "li %1, 0x00;" 412 "1:" 413 "dcbt 0, %1;" 414 "sync;isync;" 415 "lwz %2, 0(%1);" 416 "stw %2, 0(%1);" 417 "sync;isync;" 418 "dcbf 0, %1;" 419 "sync;isync;" 420 "addi %1, %1, 0x20;" 421 "addic. %3, %3, -0x20;" 422 "bge 1b;" 423 "mtmsr %0;" 424 "sync;isync;" 425 : "=&r" (msr), "=&r" (tmp), "=&r" (dat) 426 : "r" (board_data.mem_size) : "0" ); 427 428 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 429 esr = mfdcr(DCR_SDRAM0_CFGDATA); 430 431 /* If esr is non zero here, we're screwed. Should check this and panic. */ 432 printf("ECC: Persistent error check complete, " 433 "final ESR=%x.\n", esr); 434 }; 435 436 intr_ecc_tb = tb; 437 intr_ecc_cnt = 0; 438 439 return(1); 440 }; 441
Indexes created Fri Sep 26 08:10:20 GMT 2025