cpu.c revision 1.10
1 /* $NetBSD: cpu.c,v 1.10 2002/10/02 04:10:09 thorpej Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/properties.h> 42 43 #include <machine/cpu.h> 44 #include <powerpc/ibm4xx/dev/plbvar.h> 45 46 struct cputab { 47 int version; 48 char *name; 49 }; 50 static struct cputab models[] = { 51 { PVR_401A1 >> 16, "401A1" }, 52 { PVR_401B2 >> 16, "401B21" }, 53 { PVR_401C2 >> 16, "401C2" }, 54 { PVR_401D2 >> 16, "401D2" }, 55 { PVR_401E2 >> 16, "401E2" }, 56 { PVR_401F2 >> 16, "401F2" }, 57 { PVR_401G2 >> 16, "401G2" }, 58 { PVR_403 >> 16, "403" }, 59 { PVR_405GP >> 16, "405GP" }, 60 { 0, NULL } 61 }; 62 63 static int cpumatch(struct device *, struct cfdata *, void *); 64 static void cpuattach(struct device *, struct device *, void *); 65 66 CFATTACH_DECL(cpu, sizeof(struct device), 67 cpumatch, cpuattach, NULL, NULL); 68 69 int ncpus; 70 71 struct cpu_info cpu_info_store; 72 73 int cpufound = 0; 74 75 static int 76 cpumatch(struct device *parent, struct cfdata *cf, void *aux) 77 { 78 struct plb_attach_args *paa = aux; 79 80 /* make sure that we're looking for a CPU */ 81 if (strcmp(paa->plb_name, cf->cf_name) != 0) 82 return (0); 83 84 return !cpufound; 85 } 86 87 static void 88 cpuattach(struct device *parent, struct device *self, void *aux) 89 { 90 int pvr, cpu; 91 int own, pcf, cas, pcl, aid; 92 struct cputab *cp = models; 93 unsigned int processor_freq; 94 95 if (board_info_get("processor-frequency", 96 &processor_freq, sizeof(processor_freq)) == -1) 97 panic("no processor-frequency"); 98 99 cpufound++; 100 ncpus++; 101 102 asm ("mfpvr %0" : "=r"(pvr)); 103 cpu = pvr >> 16; 104 105 /* Break PVR up into separate fields and print them out. */ 106 own = (pvr >> 20) & 0xfff; 107 pcf = (pvr >> 16) & 0xf; 108 cas = (pvr >> 10) & 0x3f; 109 pcl = (pvr >> 6) & 0xf; 110 aid = pvr & 0x3f; 111 112 while (cp->name) { 113 if (cp->version == cpu) 114 break; 115 cp++; 116 } 117 if (cp->name) 118 strcpy(cpu_model, cp->name); 119 else 120 sprintf(cpu_model, "Version 0x%x", cpu); 121 sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)", 122 (pvr >> 8) & 0xff, pvr & 0xff); 123 124 #if 1 125 printf(": %dMHz %s\n", processor_freq / 1000 / 1000, 126 cpu_model); 127 #endif 128 129 cpu_probe_cache(); 130 131 printf("Instruction cache size %d line size %d\n", 132 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 133 printf("Data cache size %d line size %d\n", 134 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 135 136 #ifdef DEBUG 137 /* It sux that the cache info here is useless. */ 138 printf("PVR: owner %x core family %x cache %x version %x asic %x\n", 139 own, pcf, cas, pcl, aid); 140 #endif 141 } 142 143 /* 144 * This routine must be explicitly called to initialize the 145 * CPU cache information so cache flushe and memcpy operation 146 * work. 147 */ 148 void 149 cpu_probe_cache() 150 { 151 int version; 152 153 /* 154 * First we need to identify the cpu and determine the 155 * cache line size, or things like memset/memcpy may lose 156 * badly. 157 */ 158 __asm __volatile("mfpvr %0" : "=r" (version)); 159 switch (version & 0xffff0000) { 160 case PVR_401A1: 161 curcpu()->ci_ci.dcache_size = 1024; 162 curcpu()->ci_ci.dcache_line_size = 16; 163 curcpu()->ci_ci.icache_size = 2848; 164 curcpu()->ci_ci.icache_line_size = 16; 165 break; 166 case PVR_401B2: 167 curcpu()->ci_ci.dcache_size = 8192; 168 curcpu()->ci_ci.dcache_line_size = 16; 169 curcpu()->ci_ci.icache_size = 16384; 170 curcpu()->ci_ci.icache_line_size = 16; 171 break; 172 case PVR_401C2: 173 curcpu()->ci_ci.dcache_size = 8192; 174 curcpu()->ci_ci.dcache_line_size = 16; 175 curcpu()->ci_ci.icache_size = 0; 176 curcpu()->ci_ci.icache_line_size = 16; 177 break; 178 case PVR_401D2: 179 curcpu()->ci_ci.dcache_size = 2848; 180 curcpu()->ci_ci.dcache_line_size = 16; 181 curcpu()->ci_ci.icache_size = 4096; 182 curcpu()->ci_ci.icache_line_size = 16; 183 break; 184 case PVR_401E2: 185 curcpu()->ci_ci.dcache_size = 0; 186 curcpu()->ci_ci.dcache_line_size = 16; 187 curcpu()->ci_ci.icache_size = 0; 188 curcpu()->ci_ci.icache_line_size = 16; 189 break; 190 case PVR_401F2: 191 curcpu()->ci_ci.dcache_size = 2048; 192 curcpu()->ci_ci.dcache_line_size = 16; 193 curcpu()->ci_ci.icache_size = 2848; 194 curcpu()->ci_ci.icache_line_size = 16; 195 break; 196 case PVR_401G2: 197 curcpu()->ci_ci.dcache_size = 2848; 198 curcpu()->ci_ci.dcache_line_size = 16; 199 curcpu()->ci_ci.icache_size = 8192; 200 curcpu()->ci_ci.icache_line_size = 16; 201 break; 202 case PVR_403: 203 curcpu()->ci_ci.dcache_line_size = 16; 204 curcpu()->ci_ci.icache_line_size = 16; 205 break; 206 case PVR_405GP: 207 curcpu()->ci_ci.dcache_size = 8192; 208 curcpu()->ci_ci.dcache_line_size = 32; 209 curcpu()->ci_ci.icache_size = 8192; 210 curcpu()->ci_ci.icache_line_size = 32; 211 break; 212 default: 213 /* 214 * Unknown CPU type. For safety we'll specify a 215 * cache with a 4-byte line size. That way cache 216 * flush routines won't miss any lines. 217 */ 218 curcpu()->ci_ci.dcache_line_size = 4; 219 curcpu()->ci_ci.icache_line_size = 4; 220 break; 221 } 222 223 } 224 225 /* 226 * These small routines may have to be replaced, 227 * if/when we support processors other that the 604. 228 */ 229 230 void 231 dcache_flush_page(vaddr_t va) 232 { 233 int i; 234 235 if (curcpu()->ci_ci.dcache_line_size) 236 for (i = 0; i < NBPG; i += curcpu()->ci_ci.dcache_line_size) 237 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 238 asm volatile("sync;isync" : : ); 239 } 240 241 void 242 icache_flush_page(vaddr_t va) 243 { 244 int i; 245 246 if (curcpu()->ci_ci.icache_line_size) 247 for (i = 0; i < NBPG; i += curcpu()->ci_ci.icache_line_size) 248 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 249 asm volatile("sync;isync" : : ); 250 } 251 252 void 253 dcache_flush(vaddr_t va, vsize_t len) 254 { 255 int i; 256 257 if (len == 0) 258 return; 259 260 /* Make sure we flush all cache lines */ 261 len += va & (curcpu()->ci_ci.dcache_line_size-1); 262 if (curcpu()->ci_ci.dcache_line_size) 263 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 264 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 265 asm volatile("sync;isync" : : ); 266 } 267 268 void 269 icache_flush(vaddr_t va, vsize_t len) 270 { 271 int i; 272 273 if (len == 0) 274 return; 275 276 /* Make sure we flush all cache lines */ 277 len += va & (curcpu()->ci_ci.icache_line_size-1); 278 if (curcpu()->ci_ci.icache_line_size) 279 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 280 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 281 asm volatile("sync;isync" : : ); 282 } 283
Indexes created Fri Sep 26 20:09:58 GMT 2025