cpu.c revision 1.13
1 /* $NetBSD: cpu.c,v 1.13 2003/04/02 04:22:03 thorpej Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/properties.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <machine/cpu.h> 46 #include <powerpc/ibm4xx/dev/plbvar.h> 47 48 struct cputab { 49 int version; 50 char *name; 51 }; 52 static struct cputab models[] = { 53 { PVR_401A1 >> 16, "401A1" }, 54 { PVR_401B2 >> 16, "401B21" }, 55 { PVR_401C2 >> 16, "401C2" }, 56 { PVR_401D2 >> 16, "401D2" }, 57 { PVR_401E2 >> 16, "401E2" }, 58 { PVR_401F2 >> 16, "401F2" }, 59 { PVR_401G2 >> 16, "401G2" }, 60 { PVR_403 >> 16, "403" }, 61 { PVR_405GP >> 16, "405GP" }, 62 { 0, NULL } 63 }; 64 65 static int cpumatch(struct device *, struct cfdata *, void *); 66 static void cpuattach(struct device *, struct device *, void *); 67 68 CFATTACH_DECL(cpu, sizeof(struct device), 69 cpumatch, cpuattach, NULL, NULL); 70 71 int ncpus; 72 73 struct cpu_info cpu_info[1]; 74 75 int cpufound = 0; 76 77 static int 78 cpumatch(struct device *parent, struct cfdata *cf, void *aux) 79 { 80 struct plb_attach_args *paa = aux; 81 82 /* make sure that we're looking for a CPU */ 83 if (strcmp(paa->plb_name, cf->cf_name) != 0) 84 return (0); 85 86 return !cpufound; 87 } 88 89 static void 90 cpuattach(struct device *parent, struct device *self, void *aux) 91 { 92 int pvr, cpu; 93 int own, pcf, cas, pcl, aid; 94 struct cputab *cp = models; 95 unsigned int processor_freq; 96 97 if (board_info_get("processor-frequency", 98 &processor_freq, sizeof(processor_freq)) == -1) 99 panic("no processor-frequency"); 100 101 cpufound++; 102 ncpus++; 103 104 asm ("mfpvr %0" : "=r"(pvr)); 105 cpu = pvr >> 16; 106 107 /* Break PVR up into separate fields and print them out. */ 108 own = (pvr >> 20) & 0xfff; 109 pcf = (pvr >> 16) & 0xf; 110 cas = (pvr >> 10) & 0x3f; 111 pcl = (pvr >> 6) & 0xf; 112 aid = pvr & 0x3f; 113 114 while (cp->name) { 115 if (cp->version == cpu) 116 break; 117 cp++; 118 } 119 if (cp->name) 120 strcpy(cpu_model, cp->name); 121 else 122 sprintf(cpu_model, "Version 0x%x", cpu); 123 sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)", 124 (pvr >> 8) & 0xff, pvr & 0xff); 125 126 #if 1 127 printf(": %dMHz %s\n", processor_freq / 1000 / 1000, 128 cpu_model); 129 #endif 130 131 cpu_probe_cache(); 132 133 printf("Instruction cache size %d line size %d\n", 134 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 135 printf("Data cache size %d line size %d\n", 136 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 137 138 #ifdef DEBUG 139 /* It sux that the cache info here is useless. */ 140 printf("PVR: owner %x core family %x cache %x version %x asic %x\n", 141 own, pcf, cas, pcl, aid); 142 #endif 143 } 144 145 /* 146 * This routine must be explicitly called to initialize the 147 * CPU cache information so cache flushe and memcpy operation 148 * work. 149 */ 150 void 151 cpu_probe_cache() 152 { 153 int version; 154 155 /* 156 * First we need to identify the cpu and determine the 157 * cache line size, or things like memset/memcpy may lose 158 * badly. 159 */ 160 __asm __volatile("mfpvr %0" : "=r" (version)); 161 switch (version & 0xffff0000) { 162 case PVR_401A1: 163 curcpu()->ci_ci.dcache_size = 1024; 164 curcpu()->ci_ci.dcache_line_size = 16; 165 curcpu()->ci_ci.icache_size = 2848; 166 curcpu()->ci_ci.icache_line_size = 16; 167 break; 168 case PVR_401B2: 169 curcpu()->ci_ci.dcache_size = 8192; 170 curcpu()->ci_ci.dcache_line_size = 16; 171 curcpu()->ci_ci.icache_size = 16384; 172 curcpu()->ci_ci.icache_line_size = 16; 173 break; 174 case PVR_401C2: 175 curcpu()->ci_ci.dcache_size = 8192; 176 curcpu()->ci_ci.dcache_line_size = 16; 177 curcpu()->ci_ci.icache_size = 0; 178 curcpu()->ci_ci.icache_line_size = 16; 179 break; 180 case PVR_401D2: 181 curcpu()->ci_ci.dcache_size = 2848; 182 curcpu()->ci_ci.dcache_line_size = 16; 183 curcpu()->ci_ci.icache_size = 4096; 184 curcpu()->ci_ci.icache_line_size = 16; 185 break; 186 case PVR_401E2: 187 curcpu()->ci_ci.dcache_size = 0; 188 curcpu()->ci_ci.dcache_line_size = 16; 189 curcpu()->ci_ci.icache_size = 0; 190 curcpu()->ci_ci.icache_line_size = 16; 191 break; 192 case PVR_401F2: 193 curcpu()->ci_ci.dcache_size = 2048; 194 curcpu()->ci_ci.dcache_line_size = 16; 195 curcpu()->ci_ci.icache_size = 2848; 196 curcpu()->ci_ci.icache_line_size = 16; 197 break; 198 case PVR_401G2: 199 curcpu()->ci_ci.dcache_size = 2848; 200 curcpu()->ci_ci.dcache_line_size = 16; 201 curcpu()->ci_ci.icache_size = 8192; 202 curcpu()->ci_ci.icache_line_size = 16; 203 break; 204 case PVR_403: 205 curcpu()->ci_ci.dcache_size = 8192; 206 curcpu()->ci_ci.dcache_line_size = 16; 207 curcpu()->ci_ci.icache_size = 16384; 208 curcpu()->ci_ci.icache_line_size = 16; 209 break; 210 case PVR_405GP: 211 curcpu()->ci_ci.dcache_size = 8192; 212 curcpu()->ci_ci.dcache_line_size = 32; 213 curcpu()->ci_ci.icache_size = 8192; 214 curcpu()->ci_ci.icache_line_size = 32; 215 break; 216 default: 217 /* 218 * Unknown CPU type. For safety we'll specify a 219 * cache with a 4-byte line size. That way cache 220 * flush routines won't miss any lines. 221 */ 222 curcpu()->ci_ci.dcache_line_size = 4; 223 curcpu()->ci_ci.icache_line_size = 4; 224 break; 225 } 226 227 } 228 229 /* 230 * These small routines may have to be replaced, 231 * if/when we support processors other that the 604. 232 */ 233 234 void 235 dcache_flush_page(vaddr_t va) 236 { 237 int i; 238 239 if (curcpu()->ci_ci.dcache_line_size) 240 for (i = 0; i < PAGE_SIZE; 241 i += curcpu()->ci_ci.dcache_line_size) 242 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 243 asm volatile("sync;isync" : : ); 244 } 245 246 void 247 icache_flush_page(vaddr_t va) 248 { 249 int i; 250 251 if (curcpu()->ci_ci.icache_line_size) 252 for (i = 0; i < PAGE_SIZE; 253 i += curcpu()->ci_ci.icache_line_size) 254 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 255 asm volatile("sync;isync" : : ); 256 } 257 258 void 259 dcache_flush(vaddr_t va, vsize_t len) 260 { 261 int i; 262 263 if (len == 0) 264 return; 265 266 /* Make sure we flush all cache lines */ 267 len += va & (curcpu()->ci_ci.dcache_line_size-1); 268 if (curcpu()->ci_ci.dcache_line_size) 269 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 270 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 271 asm volatile("sync;isync" : : ); 272 } 273 274 void 275 icache_flush(vaddr_t va, vsize_t len) 276 { 277 int i; 278 279 if (len == 0) 280 return; 281 282 /* Make sure we flush all cache lines */ 283 len += va & (curcpu()->ci_ci.icache_line_size-1); 284 if (curcpu()->ci_ci.icache_line_size) 285 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 286 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 287 asm volatile("sync;isync" : : ); 288 } 289
Indexes created Fri Sep 26 08:10:20 GMT 2025