cpu.c revision 1.15
1 /* $NetBSD: cpu.c,v 1.15 2003/06/13 04:29:39 simonb Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/properties.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <machine/cpu.h> 46 #include <powerpc/ibm4xx/dev/plbvar.h> 47 48 struct cputab { 49 int version; 50 char *name; 51 }; 52 static struct cputab models[] = { 53 { PVR_401A1 >> 16, "401A1" }, 54 { PVR_401B2 >> 16, "401B21" }, 55 { PVR_401C2 >> 16, "401C2" }, 56 { PVR_401D2 >> 16, "401D2" }, 57 { PVR_401E2 >> 16, "401E2" }, 58 { PVR_401F2 >> 16, "401F2" }, 59 { PVR_401G2 >> 16, "401G2" }, 60 { PVR_403 >> 16, "403" }, 61 { PVR_405GP >> 16, "405GP" }, 62 { PVR_405GPR >> 16, "405GPr" }, 63 { 0, NULL } 64 }; 65 66 static int cpumatch(struct device *, struct cfdata *, void *); 67 static void cpuattach(struct device *, struct device *, void *); 68 69 CFATTACH_DECL(cpu, sizeof(struct device), 70 cpumatch, cpuattach, NULL, NULL); 71 72 int ncpus; 73 74 struct cpu_info cpu_info[1]; 75 76 int cpufound = 0; 77 78 static int 79 cpumatch(struct device *parent, struct cfdata *cf, void *aux) 80 { 81 struct plb_attach_args *paa = aux; 82 83 /* make sure that we're looking for a CPU */ 84 if (strcmp(paa->plb_name, cf->cf_name) != 0) 85 return (0); 86 87 return !cpufound; 88 } 89 90 static void 91 cpuattach(struct device *parent, struct device *self, void *aux) 92 { 93 int pvr, cpu; 94 int own, pcf, cas, pcl, aid; 95 struct cputab *cp = models; 96 unsigned int processor_freq; 97 98 if (board_info_get("processor-frequency", 99 &processor_freq, sizeof(processor_freq)) == -1) 100 panic("no processor-frequency"); 101 102 cpufound++; 103 ncpus++; 104 105 asm ("mfpvr %0" : "=r"(pvr)); 106 cpu = pvr >> 16; 107 108 /* Break PVR up into separate fields and print them out. */ 109 own = (pvr >> 20) & 0xfff; 110 pcf = (pvr >> 16) & 0xf; 111 cas = (pvr >> 10) & 0x3f; 112 pcl = (pvr >> 6) & 0xf; 113 aid = pvr & 0x3f; 114 115 while (cp->name) { 116 if (cp->version == cpu) 117 break; 118 cp++; 119 } 120 if (cp->name) 121 strcpy(cpu_model, cp->name); 122 else 123 sprintf(cpu_model, "Version 0x%x", cpu); 124 sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)", 125 (pvr >> 8) & 0xff, pvr & 0xff); 126 127 #if 1 128 printf(": %dMHz %s\n", processor_freq / 1000 / 1000, 129 cpu_model); 130 #endif 131 132 cpu_probe_cache(); 133 134 printf("Instruction cache size %d line size %d\n", 135 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 136 printf("Data cache size %d line size %d\n", 137 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 138 139 #ifdef DEBUG 140 /* It sux that the cache info here is useless. */ 141 printf("PVR: owner %x core family %x cache %x version %x asic %x\n", 142 own, pcf, cas, pcl, aid); 143 #endif 144 } 145 146 /* 147 * This routine must be explicitly called to initialize the 148 * CPU cache information so cache flushe and memcpy operation 149 * work. 150 */ 151 void 152 cpu_probe_cache() 153 { 154 int version; 155 156 /* 157 * First we need to identify the cpu and determine the 158 * cache line size, or things like memset/memcpy may lose 159 * badly. 160 */ 161 __asm __volatile("mfpvr %0" : "=r" (version)); 162 switch (version & 0xffff0000) { 163 case PVR_401A1: 164 curcpu()->ci_ci.dcache_size = 1024; 165 curcpu()->ci_ci.dcache_line_size = 16; 166 curcpu()->ci_ci.icache_size = 2848; 167 curcpu()->ci_ci.icache_line_size = 16; 168 break; 169 case PVR_401B2: 170 curcpu()->ci_ci.dcache_size = 8192; 171 curcpu()->ci_ci.dcache_line_size = 16; 172 curcpu()->ci_ci.icache_size = 16384; 173 curcpu()->ci_ci.icache_line_size = 16; 174 break; 175 case PVR_401C2: 176 curcpu()->ci_ci.dcache_size = 8192; 177 curcpu()->ci_ci.dcache_line_size = 16; 178 curcpu()->ci_ci.icache_size = 0; 179 curcpu()->ci_ci.icache_line_size = 16; 180 break; 181 case PVR_401D2: 182 curcpu()->ci_ci.dcache_size = 2848; 183 curcpu()->ci_ci.dcache_line_size = 16; 184 curcpu()->ci_ci.icache_size = 4096; 185 curcpu()->ci_ci.icache_line_size = 16; 186 break; 187 case PVR_401E2: 188 curcpu()->ci_ci.dcache_size = 0; 189 curcpu()->ci_ci.dcache_line_size = 16; 190 curcpu()->ci_ci.icache_size = 0; 191 curcpu()->ci_ci.icache_line_size = 16; 192 break; 193 case PVR_401F2: 194 curcpu()->ci_ci.dcache_size = 2048; 195 curcpu()->ci_ci.dcache_line_size = 16; 196 curcpu()->ci_ci.icache_size = 2848; 197 curcpu()->ci_ci.icache_line_size = 16; 198 break; 199 case PVR_401G2: 200 curcpu()->ci_ci.dcache_size = 2848; 201 curcpu()->ci_ci.dcache_line_size = 16; 202 curcpu()->ci_ci.icache_size = 8192; 203 curcpu()->ci_ci.icache_line_size = 16; 204 break; 205 case PVR_403: 206 curcpu()->ci_ci.dcache_size = 8192; 207 curcpu()->ci_ci.dcache_line_size = 16; 208 curcpu()->ci_ci.icache_size = 16384; 209 curcpu()->ci_ci.icache_line_size = 16; 210 break; 211 case PVR_405GP: 212 curcpu()->ci_ci.dcache_size = 8192; 213 curcpu()->ci_ci.dcache_line_size = 32; 214 curcpu()->ci_ci.icache_size = 8192; 215 curcpu()->ci_ci.icache_line_size = 32; 216 break; 217 case PVR_405GPR: 218 curcpu()->ci_ci.dcache_size = 16384; 219 curcpu()->ci_ci.dcache_line_size = 32; 220 curcpu()->ci_ci.icache_size = 16384; 221 curcpu()->ci_ci.icache_line_size = 32; 222 break; 223 default: 224 /* 225 * Unknown CPU type. For safety we'll specify a 226 * cache with a 4-byte line size. That way cache 227 * flush routines won't miss any lines. 228 */ 229 curcpu()->ci_ci.dcache_line_size = 4; 230 curcpu()->ci_ci.icache_line_size = 4; 231 break; 232 } 233 234 } 235 236 /* 237 * These small routines may have to be replaced, 238 * if/when we support processors other that the 604. 239 */ 240 241 void 242 dcache_flush_page(vaddr_t va) 243 { 244 int i; 245 246 if (curcpu()->ci_ci.dcache_line_size) 247 for (i = 0; i < PAGE_SIZE; 248 i += curcpu()->ci_ci.dcache_line_size) 249 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 250 asm volatile("sync;isync" : : ); 251 } 252 253 void 254 icache_flush_page(vaddr_t va) 255 { 256 int i; 257 258 if (curcpu()->ci_ci.icache_line_size) 259 for (i = 0; i < PAGE_SIZE; 260 i += curcpu()->ci_ci.icache_line_size) 261 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 262 asm volatile("sync;isync" : : ); 263 } 264 265 void 266 dcache_flush(vaddr_t va, vsize_t len) 267 { 268 int i; 269 270 if (len == 0) 271 return; 272 273 /* Make sure we flush all cache lines */ 274 len += va & (curcpu()->ci_ci.dcache_line_size-1); 275 if (curcpu()->ci_ci.dcache_line_size) 276 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 277 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 278 asm volatile("sync;isync" : : ); 279 } 280 281 void 282 icache_flush(vaddr_t va, vsize_t len) 283 { 284 int i; 285 286 if (len == 0) 287 return; 288 289 /* Make sure we flush all cache lines */ 290 len += va & (curcpu()->ci_ci.icache_line_size-1); 291 if (curcpu()->ci_ci.icache_line_size) 292 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 293 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 294 asm volatile("sync;isync" : : ); 295 } 296
Indexes created Fri Sep 26 20:09:58 GMT 2025