cpu.c revision 1.23
1 /* $NetBSD: cpu.c,v 1.23 2006/05/05 18:04:42 thorpej Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.23 2006/05/05 18:04:42 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <prop/proplib.h> 48 49 #include <machine/cpu.h> 50 #include <powerpc/ibm4xx/dev/plbvar.h> 51 52 struct cputab { 53 int version; 54 const char *name; 55 }; 56 static struct cputab models[] = { 57 { PVR_401A1 >> 16, "401A1" }, 58 { PVR_401B2 >> 16, "401B21" }, 59 { PVR_401C2 >> 16, "401C2" }, 60 { PVR_401D2 >> 16, "401D2" }, 61 { PVR_401E2 >> 16, "401E2" }, 62 { PVR_401F2 >> 16, "401F2" }, 63 { PVR_401G2 >> 16, "401G2" }, 64 { PVR_403 >> 16, "403" }, 65 { PVR_405GP >> 16, "405GP" }, 66 { PVR_405GPR >> 16, "405GPr" }, 67 { 0, NULL } 68 }; 69 70 static int cpumatch(struct device *, struct cfdata *, void *); 71 static void cpuattach(struct device *, struct device *, void *); 72 73 CFATTACH_DECL(cpu, sizeof(struct device), 74 cpumatch, cpuattach, NULL, NULL); 75 76 int ncpus; 77 78 struct cpu_info cpu_info[1]; 79 80 char cpu_model[80]; 81 82 int cpufound = 0; 83 84 static int 85 cpumatch(struct device *parent, struct cfdata *cf, void *aux) 86 { 87 struct plb_attach_args *paa = aux; 88 89 /* make sure that we're looking for a CPU */ 90 if (strcmp(paa->plb_name, cf->cf_name) != 0) 91 return (0); 92 93 return !cpufound; 94 } 95 96 static void 97 cpuattach(struct device *parent, struct device *self, void *aux) 98 { 99 int pvr, cpu; 100 int own, pcf, cas, pcl, aid; 101 struct cputab *cp = models; 102 unsigned int processor_freq; 103 prop_number_t freq; 104 105 freq = prop_dictionary_get(board_properties, "processor-frequency"); 106 KASSERT(freq != NULL); 107 processor_freq = (unsigned int) prop_number_integer_value(freq); 108 109 cpufound++; 110 ncpus++; 111 112 __asm ("mfpvr %0" : "=r"(pvr)); 113 cpu = pvr >> 16; 114 115 /* Break PVR up into separate fields and print them out. */ 116 own = (pvr >> 20) & 0xfff; 117 pcf = (pvr >> 16) & 0xf; 118 cas = (pvr >> 10) & 0x3f; 119 pcl = (pvr >> 6) & 0xf; 120 aid = pvr & 0x3f; 121 122 while (cp->name) { 123 if (cp->version == cpu) 124 break; 125 cp++; 126 } 127 if (cp->name) 128 strcpy(cpu_model, cp->name); 129 else 130 sprintf(cpu_model, "Version 0x%x", cpu); 131 sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)", 132 (pvr >> 8) & 0xff, pvr & 0xff); 133 134 #if 1 135 printf(": %dMHz %s\n", processor_freq / 1000 / 1000, 136 cpu_model); 137 #endif 138 139 cpu_probe_cache(); 140 141 printf("Instruction cache size %d line size %d\n", 142 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 143 printf("Data cache size %d line size %d\n", 144 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 145 146 #ifdef DEBUG 147 /* It sux that the cache info here is useless. */ 148 printf("PVR: owner %x core family %x cache %x version %x asic %x\n", 149 own, pcf, cas, pcl, aid); 150 #endif 151 } 152 153 /* 154 * This routine must be explicitly called to initialize the 155 * CPU cache information so cache flushe and memcpy operation 156 * work. 157 */ 158 void 159 cpu_probe_cache() 160 { 161 int pvr; 162 163 /* 164 * First we need to identify the CPU and determine the 165 * cache line size, or things like memset/memcpy may lose 166 * badly. 167 */ 168 __asm volatile("mfpvr %0" : "=r" (pvr)); 169 switch (pvr & 0xffff0000) { 170 case PVR_401A1: 171 curcpu()->ci_ci.dcache_size = 1024; 172 curcpu()->ci_ci.dcache_line_size = 16; 173 curcpu()->ci_ci.icache_size = 2848; 174 curcpu()->ci_ci.icache_line_size = 16; 175 break; 176 case PVR_401B2: 177 curcpu()->ci_ci.dcache_size = 8192; 178 curcpu()->ci_ci.dcache_line_size = 16; 179 curcpu()->ci_ci.icache_size = 16384; 180 curcpu()->ci_ci.icache_line_size = 16; 181 break; 182 case PVR_401C2: 183 curcpu()->ci_ci.dcache_size = 8192; 184 curcpu()->ci_ci.dcache_line_size = 16; 185 curcpu()->ci_ci.icache_size = 0; 186 curcpu()->ci_ci.icache_line_size = 16; 187 break; 188 case PVR_401D2: 189 curcpu()->ci_ci.dcache_size = 2848; 190 curcpu()->ci_ci.dcache_line_size = 16; 191 curcpu()->ci_ci.icache_size = 4096; 192 curcpu()->ci_ci.icache_line_size = 16; 193 break; 194 case PVR_401E2: 195 curcpu()->ci_ci.dcache_size = 0; 196 curcpu()->ci_ci.dcache_line_size = 16; 197 curcpu()->ci_ci.icache_size = 0; 198 curcpu()->ci_ci.icache_line_size = 16; 199 break; 200 case PVR_401F2: 201 curcpu()->ci_ci.dcache_size = 2048; 202 curcpu()->ci_ci.dcache_line_size = 16; 203 curcpu()->ci_ci.icache_size = 2848; 204 curcpu()->ci_ci.icache_line_size = 16; 205 break; 206 case PVR_401G2: 207 curcpu()->ci_ci.dcache_size = 2848; 208 curcpu()->ci_ci.dcache_line_size = 16; 209 curcpu()->ci_ci.icache_size = 8192; 210 curcpu()->ci_ci.icache_line_size = 16; 211 break; 212 case PVR_403: 213 curcpu()->ci_ci.dcache_size = 8192; 214 curcpu()->ci_ci.dcache_line_size = 16; 215 curcpu()->ci_ci.icache_size = 16384; 216 curcpu()->ci_ci.icache_line_size = 16; 217 break; 218 case PVR_405GP: 219 curcpu()->ci_ci.dcache_size = 8192; 220 curcpu()->ci_ci.dcache_line_size = 32; 221 curcpu()->ci_ci.icache_size = 8192; 222 curcpu()->ci_ci.icache_line_size = 32; 223 break; 224 case PVR_405GPR: 225 curcpu()->ci_ci.dcache_size = 16384; 226 curcpu()->ci_ci.dcache_line_size = 32; 227 curcpu()->ci_ci.icache_size = 16384; 228 curcpu()->ci_ci.icache_line_size = 32; 229 break; 230 default: 231 /* 232 * Unknown CPU type. For safety we'll specify a 233 * cache with a 4-byte line size. That way cache 234 * flush routines won't miss any lines. 235 */ 236 curcpu()->ci_ci.dcache_line_size = 4; 237 curcpu()->ci_ci.icache_line_size = 4; 238 break; 239 } 240 241 } 242 243 /* 244 * These small routines may have to be replaced, 245 * if/when we support processors other that the 604. 246 */ 247 248 void 249 dcache_flush_page(vaddr_t va) 250 { 251 int i; 252 253 if (curcpu()->ci_ci.dcache_line_size) 254 for (i = 0; i < PAGE_SIZE; 255 i += curcpu()->ci_ci.dcache_line_size) 256 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 257 __asm volatile("sync;isync" : : ); 258 } 259 260 void 261 icache_flush_page(vaddr_t va) 262 { 263 int i; 264 265 if (curcpu()->ci_ci.icache_line_size) 266 for (i = 0; i < PAGE_SIZE; 267 i += curcpu()->ci_ci.icache_line_size) 268 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 269 __asm volatile("sync;isync" : : ); 270 } 271 272 void 273 dcache_flush(vaddr_t va, vsize_t len) 274 { 275 int i; 276 277 if (len == 0) 278 return; 279 280 /* Make sure we flush all cache lines */ 281 len += va & (curcpu()->ci_ci.dcache_line_size-1); 282 if (curcpu()->ci_ci.dcache_line_size) 283 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 284 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 285 __asm volatile("sync;isync" : : ); 286 } 287 288 void 289 icache_flush(vaddr_t va, vsize_t len) 290 { 291 int i; 292 293 if (len == 0) 294 return; 295 296 /* Make sure we flush all cache lines */ 297 len += va & (curcpu()->ci_ci.icache_line_size-1); 298 if (curcpu()->ci_ci.icache_line_size) 299 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 300 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 301 __asm volatile("sync;isync" : : ); 302 } 303
Indexes created Fri Sep 26 20:09:58 GMT 2025