cpu.c revision 1.24
1 /* $NetBSD: cpu.c,v 1.24 2006/06/30 17:54:51 freza Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.24 2006/06/30 17:54:51 freza Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/evcnt.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <prop/proplib.h> 49 50 #include <machine/cpu.h> 51 #include <powerpc/ibm4xx/dev/plbvar.h> 52 53 struct cputab { 54 int version; 55 const char *name; 56 }; 57 static struct cputab models[] = { 58 { PVR_401A1 >> 16, "401A1" }, 59 { PVR_401B2 >> 16, "401B21" }, 60 { PVR_401C2 >> 16, "401C2" }, 61 { PVR_401D2 >> 16, "401D2" }, 62 { PVR_401E2 >> 16, "401E2" }, 63 { PVR_401F2 >> 16, "401F2" }, 64 { PVR_401G2 >> 16, "401G2" }, 65 { PVR_403 >> 16, "403" }, 66 { PVR_405GP >> 16, "405GP" }, 67 { PVR_405GPR >> 16, "405GPr" }, 68 { 0, NULL } 69 }; 70 71 static int cpumatch(struct device *, struct cfdata *, void *); 72 static void cpuattach(struct device *, struct device *, void *); 73 74 CFATTACH_DECL(cpu, sizeof(struct device), 75 cpumatch, cpuattach, NULL, NULL); 76 77 int ncpus; 78 79 struct cpu_info cpu_info[1] = { 80 { 81 /* XXX add more ci_ev_* as we teach 4xx about them */ 82 .ci_ev_clock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 83 NULL, "cpu0", "clock"), 84 .ci_ev_statclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 85 NULL, "cpu0", "stat clock"), 86 .ci_ev_softclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 87 NULL, "cpu0", "soft clock"), 88 .ci_ev_softnet = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 89 NULL, "cpu0", "soft net"), 90 .ci_ev_softserial = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 91 NULL, "cpu0", "soft serial"), 92 } 93 }; 94 95 char cpu_model[80]; 96 97 int cpufound = 0; 98 99 static int 100 cpumatch(struct device *parent, struct cfdata *cf, void *aux) 101 { 102 struct plb_attach_args *paa = aux; 103 104 /* make sure that we're looking for a CPU */ 105 if (strcmp(paa->plb_name, cf->cf_name) != 0) 106 return (0); 107 108 return !cpufound; 109 } 110 111 static void 112 cpuattach(struct device *parent, struct device *self, void *aux) 113 { 114 int pvr, cpu; 115 int own, pcf, cas, pcl, aid; 116 struct cputab *cp = models; 117 unsigned int processor_freq; 118 prop_number_t freq; 119 120 freq = prop_dictionary_get(board_properties, "processor-frequency"); 121 KASSERT(freq != NULL); 122 processor_freq = (unsigned int) prop_number_integer_value(freq); 123 124 cpufound++; 125 ncpus++; 126 127 __asm ("mfpvr %0" : "=r"(pvr)); 128 cpu = pvr >> 16; 129 130 /* Break PVR up into separate fields and print them out. */ 131 own = (pvr >> 20) & 0xfff; 132 pcf = (pvr >> 16) & 0xf; 133 cas = (pvr >> 10) & 0x3f; 134 pcl = (pvr >> 6) & 0xf; 135 aid = pvr & 0x3f; 136 137 while (cp->name) { 138 if (cp->version == cpu) 139 break; 140 cp++; 141 } 142 if (cp->name) 143 strcpy(cpu_model, cp->name); 144 else 145 sprintf(cpu_model, "Version 0x%x", cpu); 146 sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)", 147 (pvr >> 8) & 0xff, pvr & 0xff); 148 149 #if 1 150 printf(": %dMHz %s\n", processor_freq / 1000 / 1000, 151 cpu_model); 152 #endif 153 154 cpu_probe_cache(); 155 156 printf("Instruction cache size %d line size %d\n", 157 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 158 printf("Data cache size %d line size %d\n", 159 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 160 161 #ifdef DEBUG 162 /* It sux that the cache info here is useless. */ 163 printf("PVR: owner %x core family %x cache %x version %x asic %x\n", 164 own, pcf, cas, pcl, aid); 165 #endif 166 } 167 168 /* 169 * This routine must be explicitly called to initialize the 170 * CPU cache information so cache flushe and memcpy operation 171 * work. 172 */ 173 void 174 cpu_probe_cache() 175 { 176 int pvr; 177 178 /* 179 * First we need to identify the CPU and determine the 180 * cache line size, or things like memset/memcpy may lose 181 * badly. 182 */ 183 __asm volatile("mfpvr %0" : "=r" (pvr)); 184 switch (pvr & 0xffff0000) { 185 case PVR_401A1: 186 curcpu()->ci_ci.dcache_size = 1024; 187 curcpu()->ci_ci.dcache_line_size = 16; 188 curcpu()->ci_ci.icache_size = 2848; 189 curcpu()->ci_ci.icache_line_size = 16; 190 break; 191 case PVR_401B2: 192 curcpu()->ci_ci.dcache_size = 8192; 193 curcpu()->ci_ci.dcache_line_size = 16; 194 curcpu()->ci_ci.icache_size = 16384; 195 curcpu()->ci_ci.icache_line_size = 16; 196 break; 197 case PVR_401C2: 198 curcpu()->ci_ci.dcache_size = 8192; 199 curcpu()->ci_ci.dcache_line_size = 16; 200 curcpu()->ci_ci.icache_size = 0; 201 curcpu()->ci_ci.icache_line_size = 16; 202 break; 203 case PVR_401D2: 204 curcpu()->ci_ci.dcache_size = 2848; 205 curcpu()->ci_ci.dcache_line_size = 16; 206 curcpu()->ci_ci.icache_size = 4096; 207 curcpu()->ci_ci.icache_line_size = 16; 208 break; 209 case PVR_401E2: 210 curcpu()->ci_ci.dcache_size = 0; 211 curcpu()->ci_ci.dcache_line_size = 16; 212 curcpu()->ci_ci.icache_size = 0; 213 curcpu()->ci_ci.icache_line_size = 16; 214 break; 215 case PVR_401F2: 216 curcpu()->ci_ci.dcache_size = 2048; 217 curcpu()->ci_ci.dcache_line_size = 16; 218 curcpu()->ci_ci.icache_size = 2848; 219 curcpu()->ci_ci.icache_line_size = 16; 220 break; 221 case PVR_401G2: 222 curcpu()->ci_ci.dcache_size = 2848; 223 curcpu()->ci_ci.dcache_line_size = 16; 224 curcpu()->ci_ci.icache_size = 8192; 225 curcpu()->ci_ci.icache_line_size = 16; 226 break; 227 case PVR_403: 228 curcpu()->ci_ci.dcache_size = 8192; 229 curcpu()->ci_ci.dcache_line_size = 16; 230 curcpu()->ci_ci.icache_size = 16384; 231 curcpu()->ci_ci.icache_line_size = 16; 232 break; 233 case PVR_405GP: 234 curcpu()->ci_ci.dcache_size = 8192; 235 curcpu()->ci_ci.dcache_line_size = 32; 236 curcpu()->ci_ci.icache_size = 8192; 237 curcpu()->ci_ci.icache_line_size = 32; 238 break; 239 case PVR_405GPR: 240 curcpu()->ci_ci.dcache_size = 16384; 241 curcpu()->ci_ci.dcache_line_size = 32; 242 curcpu()->ci_ci.icache_size = 16384; 243 curcpu()->ci_ci.icache_line_size = 32; 244 break; 245 default: 246 /* 247 * Unknown CPU type. For safety we'll specify a 248 * cache with a 4-byte line size. That way cache 249 * flush routines won't miss any lines. 250 */ 251 curcpu()->ci_ci.dcache_line_size = 4; 252 curcpu()->ci_ci.icache_line_size = 4; 253 break; 254 } 255 256 } 257 258 /* 259 * These small routines may have to be replaced, 260 * if/when we support processors other that the 604. 261 */ 262 263 void 264 dcache_flush_page(vaddr_t va) 265 { 266 int i; 267 268 if (curcpu()->ci_ci.dcache_line_size) 269 for (i = 0; i < PAGE_SIZE; 270 i += curcpu()->ci_ci.dcache_line_size) 271 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 272 __asm volatile("sync;isync" : : ); 273 } 274 275 void 276 icache_flush_page(vaddr_t va) 277 { 278 int i; 279 280 if (curcpu()->ci_ci.icache_line_size) 281 for (i = 0; i < PAGE_SIZE; 282 i += curcpu()->ci_ci.icache_line_size) 283 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 284 __asm volatile("sync;isync" : : ); 285 } 286 287 void 288 dcache_flush(vaddr_t va, vsize_t len) 289 { 290 int i; 291 292 if (len == 0) 293 return; 294 295 /* Make sure we flush all cache lines */ 296 len += va & (curcpu()->ci_ci.dcache_line_size-1); 297 if (curcpu()->ci_ci.dcache_line_size) 298 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 299 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 300 __asm volatile("sync;isync" : : ); 301 } 302 303 void 304 icache_flush(vaddr_t va, vsize_t len) 305 { 306 int i; 307 308 if (len == 0) 309 return; 310 311 /* Make sure we flush all cache lines */ 312 len += va & (curcpu()->ci_ci.icache_line_size-1); 313 if (curcpu()->ci_ci.icache_line_size) 314 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 315 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 316 __asm volatile("sync;isync" : : ); 317 } 318
Indexes created Mon Sep 29 21:09:56 GMT 2025