cpu.c revision 1.25
1 /* $NetBSD: cpu.c,v 1.25 2006/08/31 21:32:27 freza Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.25 2006/08/31 21:32:27 freza Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/evcnt.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <prop/proplib.h> 49 50 #include <machine/cpu.h> 51 #include <powerpc/ibm4xx/dev/plbvar.h> 52 53 struct cputab { 54 u_int version; 55 u_int mask; 56 const char *name; 57 }; 58 static struct cputab models[] = { 59 { PVR_401A1, 0xffff0000, "401A1" }, 60 { PVR_401B2, 0xffff0000, "401B21" }, 61 { PVR_401C2, 0xffff0000, "401C2" }, 62 { PVR_401D2, 0xffff0000, "401D2" }, 63 { PVR_401E2, 0xffff0000, "401E2" }, 64 { PVR_401F2, 0xffff0000, "401F2" }, 65 { PVR_401G2, 0xffff0000, "401G2" }, 66 { PVR_403, 0xffff0000, "403" }, 67 { PVR_405GP, 0xffff0000, "405GP" }, 68 { PVR_405GPR, 0xffff0000, "405GPr" }, 69 { PVR_405D5X1, 0xfffff000, "Xilinx Virtex II Pro" }, 70 { PVR_405D5X2, 0xfffff000, "Xilinx Virtex 4 FX" }, 71 { 0, 0, NULL } 72 }; 73 74 static int cpumatch(struct device *, struct cfdata *, void *); 75 static void cpuattach(struct device *, struct device *, void *); 76 77 CFATTACH_DECL(cpu, sizeof(struct device), 78 cpumatch, cpuattach, NULL, NULL); 79 80 int ncpus; 81 82 struct cpu_info cpu_info[1] = { 83 { 84 /* XXX add more ci_ev_* as we teach 4xx about them */ 85 .ci_ev_clock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 86 NULL, "cpu0", "clock"), 87 .ci_ev_statclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 88 NULL, "cpu0", "stat clock"), 89 .ci_ev_softclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 90 NULL, "cpu0", "soft clock"), 91 .ci_ev_softnet = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 92 NULL, "cpu0", "soft net"), 93 .ci_ev_softserial = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 94 NULL, "cpu0", "soft serial"), 95 } 96 }; 97 98 char cpu_model[80]; 99 100 int cpufound = 0; 101 102 static int 103 cpumatch(struct device *parent, struct cfdata *cf, void *aux) 104 { 105 struct plb_attach_args *paa = aux; 106 107 /* make sure that we're looking for a CPU */ 108 if (strcmp(paa->plb_name, cf->cf_name) != 0) 109 return (0); 110 111 return !cpufound; 112 } 113 114 static void 115 cpuattach(struct device *parent, struct device *self, void *aux) 116 { 117 struct cputab *cp = models; 118 u_int pvr; 119 u_int processor_freq; 120 prop_number_t freq; 121 122 freq = prop_dictionary_get(board_properties, "processor-frequency"); 123 KASSERT(freq != NULL); 124 processor_freq = (unsigned int) prop_number_integer_value(freq); 125 126 cpufound++; 127 ncpus++; 128 129 pvr = mfpvr(); 130 while (cp->name) { 131 if ((pvr & cp->mask) == cp->version) 132 break; 133 cp++; 134 } 135 if (cp->name) 136 strcpy(cpu_model, cp->name); 137 else 138 sprintf(cpu_model, "Version 0x%x", pvr); 139 140 printf(": %dMHz %s (PVR 0x%x)\n", processor_freq / 1000 / 1000, 141 cp->name ? cp->name : "unknown model", pvr); 142 143 cpu_probe_cache(); 144 145 /* We would crash later on anyway so just make the reason obvious */ 146 if (curcpu()->ci_ci.icache_size == 0 && 147 curcpu()->ci_ci.dcache_size == 0) 148 panic("%s could not detect cache size", device_xname(self)); 149 150 printf("%s: Instruction cache size %d line size %d\n", 151 device_xname(self), 152 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 153 printf("%s: Data cache size %d line size %d\n", 154 device_xname(self), 155 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 156 } 157 158 /* 159 * This routine must be explicitly called to initialize the 160 * CPU cache information so cache flushe and memcpy operation 161 * work. 162 */ 163 void 164 cpu_probe_cache() 165 { 166 /* 167 * First we need to identify the CPU and determine the 168 * cache line size, or things like memset/memcpy may lose 169 * badly. 170 */ 171 switch (mfpvr() & 0xffff0000) { 172 case PVR_401A1: 173 curcpu()->ci_ci.dcache_size = 1024; 174 curcpu()->ci_ci.dcache_line_size = 16; 175 curcpu()->ci_ci.icache_size = 2848; 176 curcpu()->ci_ci.icache_line_size = 16; 177 break; 178 case PVR_401B2: 179 curcpu()->ci_ci.dcache_size = 8192; 180 curcpu()->ci_ci.dcache_line_size = 16; 181 curcpu()->ci_ci.icache_size = 16384; 182 curcpu()->ci_ci.icache_line_size = 16; 183 break; 184 case PVR_401C2: 185 curcpu()->ci_ci.dcache_size = 8192; 186 curcpu()->ci_ci.dcache_line_size = 16; 187 curcpu()->ci_ci.icache_size = 0; 188 curcpu()->ci_ci.icache_line_size = 16; 189 break; 190 case PVR_401D2: 191 curcpu()->ci_ci.dcache_size = 2848; 192 curcpu()->ci_ci.dcache_line_size = 16; 193 curcpu()->ci_ci.icache_size = 4096; 194 curcpu()->ci_ci.icache_line_size = 16; 195 break; 196 case PVR_401E2: 197 curcpu()->ci_ci.dcache_size = 0; 198 curcpu()->ci_ci.dcache_line_size = 16; 199 curcpu()->ci_ci.icache_size = 0; 200 curcpu()->ci_ci.icache_line_size = 16; 201 break; 202 case PVR_401F2: 203 curcpu()->ci_ci.dcache_size = 2048; 204 curcpu()->ci_ci.dcache_line_size = 16; 205 curcpu()->ci_ci.icache_size = 2848; 206 curcpu()->ci_ci.icache_line_size = 16; 207 break; 208 case PVR_401G2: 209 curcpu()->ci_ci.dcache_size = 2848; 210 curcpu()->ci_ci.dcache_line_size = 16; 211 curcpu()->ci_ci.icache_size = 8192; 212 curcpu()->ci_ci.icache_line_size = 16; 213 break; 214 case PVR_403: 215 curcpu()->ci_ci.dcache_size = 8192; 216 curcpu()->ci_ci.dcache_line_size = 16; 217 curcpu()->ci_ci.icache_size = 16384; 218 curcpu()->ci_ci.icache_line_size = 16; 219 break; 220 case PVR_405GP: 221 curcpu()->ci_ci.dcache_size = 8192; 222 curcpu()->ci_ci.dcache_line_size = 32; 223 curcpu()->ci_ci.icache_size = 8192; 224 curcpu()->ci_ci.icache_line_size = 32; 225 break; 226 case PVR_405GPR: 227 case PVR_405D5X1: 228 case PVR_405D5X2: 229 curcpu()->ci_ci.dcache_size = 16384; 230 curcpu()->ci_ci.dcache_line_size = 32; 231 curcpu()->ci_ci.icache_size = 16384; 232 curcpu()->ci_ci.icache_line_size = 32; 233 break; 234 default: 235 /* 236 * Unknown CPU type. For safety we'll specify a 237 * cache with a 4-byte line size. That way cache 238 * flush routines won't miss any lines. 239 */ 240 curcpu()->ci_ci.dcache_line_size = 4; 241 curcpu()->ci_ci.icache_line_size = 4; 242 break; 243 } 244 245 } 246 247 /* 248 * These small routines may have to be replaced, 249 * if/when we support processors other that the 604. 250 */ 251 252 void 253 dcache_flush_page(vaddr_t va) 254 { 255 int i; 256 257 if (curcpu()->ci_ci.dcache_line_size) 258 for (i = 0; i < PAGE_SIZE; 259 i += curcpu()->ci_ci.dcache_line_size) 260 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 261 __asm volatile("sync;isync" : : ); 262 } 263 264 void 265 icache_flush_page(vaddr_t va) 266 { 267 int i; 268 269 if (curcpu()->ci_ci.icache_line_size) 270 for (i = 0; i < PAGE_SIZE; 271 i += curcpu()->ci_ci.icache_line_size) 272 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 273 __asm volatile("sync;isync" : : ); 274 } 275 276 void 277 dcache_flush(vaddr_t va, vsize_t len) 278 { 279 int i; 280 281 if (len == 0) 282 return; 283 284 /* Make sure we flush all cache lines */ 285 len += va & (curcpu()->ci_ci.dcache_line_size-1); 286 if (curcpu()->ci_ci.dcache_line_size) 287 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 288 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 289 __asm volatile("sync;isync" : : ); 290 } 291 292 void 293 icache_flush(vaddr_t va, vsize_t len) 294 { 295 int i; 296 297 if (len == 0) 298 return; 299 300 /* Make sure we flush all cache lines */ 301 len += va & (curcpu()->ci_ci.icache_line_size-1); 302 if (curcpu()->ci_ci.icache_line_size) 303 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 304 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 305 __asm volatile("sync;isync" : : ); 306 } 307
Indexes created Fri Sep 26 20:09:58 GMT 2025