cpu.c revision 1.29
1 /* $NetBSD: cpu.c,v 1.29 2011/06/05 17:03:17 matt Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.29 2011/06/05 17:03:17 matt Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/evcnt.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <prop/proplib.h> 49 50 #include <machine/cpu.h> 51 #include <powerpc/ibm4xx/dev/plbvar.h> 52 53 struct cputab { 54 u_int version; 55 u_int mask; 56 const char *name; 57 }; 58 static struct cputab models[] = { 59 { PVR_401A1, 0xffff0000, "401A1" }, 60 { PVR_401B2, 0xffff0000, "401B21" }, 61 { PVR_401C2, 0xffff0000, "401C2" }, 62 { PVR_401D2, 0xffff0000, "401D2" }, 63 { PVR_401E2, 0xffff0000, "401E2" }, 64 { PVR_401F2, 0xffff0000, "401F2" }, 65 { PVR_401G2, 0xffff0000, "401G2" }, 66 { PVR_403, 0xffff0000, "403" }, 67 { PVR_405GP, 0xffff0000, "405GP" }, 68 { PVR_405GPR, 0xffff0000, "405GPr" }, 69 { PVR_405D5X1, 0xfffff000, "Xilinx Virtex II Pro" }, 70 { PVR_405D5X2, 0xfffff000, "Xilinx Virtex 4 FX" }, 71 { PVR_405EX, 0xffff0000, "405EX" }, 72 { 0, 0, NULL } 73 }; 74 75 static int cpumatch(device_t, cfdata_t, void *); 76 static void cpuattach(device_t, device_t, void *); 77 78 CFATTACH_DECL_NEW(cpu, 0, 79 cpumatch, cpuattach, NULL, NULL); 80 81 int ncpus; 82 83 struct cpu_info cpu_info[1] = { 84 { 85 /* XXX add more ci_ev_* as we teach 4xx about them */ 86 .ci_ev_clock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 87 NULL, "cpu0", "clock"), 88 .ci_ev_statclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 89 NULL, "cpu0", "stat clock"), 90 .ci_ev_softclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 91 NULL, "cpu0", "soft clock"), 92 .ci_ev_softnet = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 93 NULL, "cpu0", "soft net"), 94 .ci_ev_softserial = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, 95 NULL, "cpu0", "soft serial"), 96 .ci_curlwp = &lwp0, 97 } 98 }; 99 100 char cpu_model[80]; 101 102 int cpufound = 0; 103 104 static int 105 cpumatch(device_t parent, cfdata_t cf, void *aux) 106 { 107 struct plb_attach_args *paa = aux; 108 109 /* make sure that we're looking for a CPU */ 110 if (strcmp(paa->plb_name, cf->cf_name) != 0) 111 return (0); 112 113 return !cpufound; 114 } 115 116 static void 117 cpuattach(device_t parent, device_t self, void *aux) 118 { 119 struct cputab *cp = models; 120 u_int pvr; 121 u_int processor_freq; 122 prop_number_t freq; 123 124 freq = prop_dictionary_get(board_properties, "processor-frequency"); 125 KASSERT(freq != NULL); 126 processor_freq = (unsigned int) prop_number_integer_value(freq); 127 128 cpufound++; 129 ncpus++; 130 131 pvr = mfpvr(); 132 while (cp->name) { 133 if ((pvr & cp->mask) == cp->version) 134 break; 135 cp++; 136 } 137 if (cp->name) 138 strcpy(cpu_model, cp->name); 139 else 140 sprintf(cpu_model, "Version 0x%x", pvr); 141 142 printf(": %dMHz %s (PVR 0x%x)\n", processor_freq / 1000 / 1000, 143 cp->name ? cp->name : "unknown model", pvr); 144 145 cpu_probe_cache(); 146 147 /* We would crash later on anyway so just make the reason obvious */ 148 if (curcpu()->ci_ci.icache_size == 0 && 149 curcpu()->ci_ci.dcache_size == 0) 150 panic("%s could not detect cache size", device_xname(self)); 151 152 printf("%s: Instruction cache size %d line size %d\n", 153 device_xname(self), 154 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 155 printf("%s: Data cache size %d line size %d\n", 156 device_xname(self), 157 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 158 } 159 160 /* 161 * This routine must be explicitly called to initialize the 162 * CPU cache information so cache flushe and memcpy operation 163 * work. 164 */ 165 void 166 cpu_probe_cache(void) 167 { 168 struct cputab *cp = models; 169 u_int pvr; 170 171 pvr = mfpvr(); 172 while (cp->name) { 173 if ((pvr & cp->mask) == cp->version) 174 break; 175 cp++; 176 } 177 178 /* 179 * First we need to identify the CPU and determine the 180 * cache line size, or things like memset/memcpy may lose 181 * badly. 182 */ 183 switch (cp->version) { 184 case PVR_401A1: 185 curcpu()->ci_ci.dcache_size = 1024; 186 curcpu()->ci_ci.dcache_line_size = 16; 187 curcpu()->ci_ci.icache_size = 2848; 188 curcpu()->ci_ci.icache_line_size = 16; 189 break; 190 case PVR_401B2: 191 curcpu()->ci_ci.dcache_size = 8192; 192 curcpu()->ci_ci.dcache_line_size = 16; 193 curcpu()->ci_ci.icache_size = 16384; 194 curcpu()->ci_ci.icache_line_size = 16; 195 break; 196 case PVR_401C2: 197 curcpu()->ci_ci.dcache_size = 8192; 198 curcpu()->ci_ci.dcache_line_size = 16; 199 curcpu()->ci_ci.icache_size = 0; 200 curcpu()->ci_ci.icache_line_size = 16; 201 break; 202 case PVR_401D2: 203 curcpu()->ci_ci.dcache_size = 2848; 204 curcpu()->ci_ci.dcache_line_size = 16; 205 curcpu()->ci_ci.icache_size = 4096; 206 curcpu()->ci_ci.icache_line_size = 16; 207 break; 208 case PVR_401E2: 209 curcpu()->ci_ci.dcache_size = 0; 210 curcpu()->ci_ci.dcache_line_size = 16; 211 curcpu()->ci_ci.icache_size = 0; 212 curcpu()->ci_ci.icache_line_size = 16; 213 break; 214 case PVR_401F2: 215 curcpu()->ci_ci.dcache_size = 2048; 216 curcpu()->ci_ci.dcache_line_size = 16; 217 curcpu()->ci_ci.icache_size = 2848; 218 curcpu()->ci_ci.icache_line_size = 16; 219 break; 220 case PVR_401G2: 221 curcpu()->ci_ci.dcache_size = 2848; 222 curcpu()->ci_ci.dcache_line_size = 16; 223 curcpu()->ci_ci.icache_size = 8192; 224 curcpu()->ci_ci.icache_line_size = 16; 225 break; 226 case PVR_403: 227 curcpu()->ci_ci.dcache_size = 8192; 228 curcpu()->ci_ci.dcache_line_size = 16; 229 curcpu()->ci_ci.icache_size = 16384; 230 curcpu()->ci_ci.icache_line_size = 16; 231 break; 232 case PVR_405GP: 233 curcpu()->ci_ci.dcache_size = 8192; 234 curcpu()->ci_ci.dcache_line_size = 32; 235 curcpu()->ci_ci.icache_size = 8192; 236 curcpu()->ci_ci.icache_line_size = 32; 237 break; 238 case PVR_405GPR: 239 case PVR_405D5X1: 240 case PVR_405D5X2: 241 case PVR_405EX: 242 curcpu()->ci_ci.dcache_size = 16384; 243 curcpu()->ci_ci.dcache_line_size = 32; 244 curcpu()->ci_ci.icache_size = 16384; 245 curcpu()->ci_ci.icache_line_size = 32; 246 break; 247 default: 248 /* 249 * Unknown CPU type. For safety we'll specify a 250 * cache with a 4-byte line size. That way cache 251 * flush routines won't miss any lines. 252 */ 253 curcpu()->ci_ci.dcache_line_size = 4; 254 curcpu()->ci_ci.icache_line_size = 4; 255 break; 256 } 257 } 258 259 /* 260 * These small routines may have to be replaced, 261 * if/when we support processors other that the 604. 262 */ 263 264 void 265 dcache_flush_page(vaddr_t va) 266 { 267 int i; 268 269 if (curcpu()->ci_ci.dcache_line_size) 270 for (i = 0; i < PAGE_SIZE; 271 i += curcpu()->ci_ci.dcache_line_size) 272 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 273 __asm volatile("sync;isync" : : ); 274 } 275 276 void 277 icache_flush_page(vaddr_t va) 278 { 279 int i; 280 281 if (curcpu()->ci_ci.icache_line_size) 282 for (i = 0; i < PAGE_SIZE; 283 i += curcpu()->ci_ci.icache_line_size) 284 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 285 __asm volatile("sync;isync" : : ); 286 } 287 288 void 289 dcache_flush(vaddr_t va, vsize_t len) 290 { 291 int i; 292 293 if (len == 0) 294 return; 295 296 /* Make sure we flush all cache lines */ 297 len += va & (curcpu()->ci_ci.dcache_line_size-1); 298 if (curcpu()->ci_ci.dcache_line_size) 299 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 300 __asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 301 __asm volatile("sync;isync" : : ); 302 } 303 304 void 305 icache_flush(vaddr_t va, vsize_t len) 306 { 307 int i; 308 309 if (len == 0) 310 return; 311 312 /* Make sure we flush all cache lines */ 313 len += va & (curcpu()->ci_ci.icache_line_size-1); 314 if (curcpu()->ci_ci.icache_line_size) 315 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 316 __asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 317 __asm volatile("sync;isync" : : ); 318 } 319
Indexes created Fri Sep 26 20:09:58 GMT 2025