cpu.c revision 1.5
1 /* $NetBSD: cpu.c,v 1.5 2002/08/23 12:46:49 scw Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/properties.h> 42 43 #include <machine/dcr.h> 44 #include <machine/cpu.h> 45 #include <powerpc/ibm4xx/dev/plbvar.h> 46 47 struct cputab { 48 int version; 49 char *name; 50 }; 51 static struct cputab models[] = { 52 { PVR_401A1 >> 16, "401A1" }, 53 { PVR_401B2 >> 16, "401B21" }, 54 { PVR_401C2 >> 16, "401C2" }, 55 { PVR_401D2 >> 16, "401D2" }, 56 { PVR_401E2 >> 16, "401E2" }, 57 { PVR_401F2 >> 16, "401F2" }, 58 { PVR_401G2 >> 16, "401G2" }, 59 { PVR_403 >> 16, "403" }, 60 { PVR_405GP >> 16, "405GP" }, 61 { 0, NULL } 62 }; 63 64 static int cpumatch(struct device *, struct cfdata *, void *); 65 static void cpuattach(struct device *, struct device *, void *); 66 67 /* 68 * Arguably the ECC stuff belongs somewhere else.... 69 */ 70 int intr_ecc(void *); 71 72 u_quad_t intr_ecc_tb; 73 u_quad_t intr_ecc_iv; /* Interval */ 74 u_int32_t intr_ecc_cnt; 75 76 struct cfattach cpu_ca = { 77 sizeof(struct device), cpumatch, cpuattach 78 }; 79 80 int ncpus; 81 82 struct cpu_info cpu_info_store; 83 84 int cpufound = 0; 85 86 static int 87 cpumatch(struct device *parent, struct cfdata *cf, void *aux) 88 { 89 struct plb_attach_args *paa = aux; 90 91 /* make sure that we're looking for a CPU */ 92 if (strcmp(paa->plb_name, cf->cf_driver->cd_name) != 0) 93 return (0); 94 95 return !cpufound; 96 } 97 98 static void 99 cpuattach(struct device *parent, struct device *self, void *aux) 100 { 101 int pvr, cpu; 102 int own, pcf, cas, pcl, aid; 103 struct cputab *cp = models; 104 unsigned int processor_freq; 105 int eccirq; 106 107 if (board_info_get("processor-frequency", 108 &processor_freq, sizeof(processor_freq)) == -1) 109 panic("no processor-frequency"); 110 111 cpufound++; 112 ncpus++; 113 114 asm ("mfpvr %0" : "=r"(pvr)); 115 cpu = pvr >> 16; 116 117 /* Break PVR up into separate fields and print them out. */ 118 own = (pvr >> 20) & 0xfff; 119 pcf = (pvr >> 16) & 0xf; 120 cas = (pvr >> 10) & 0x3f; 121 pcl = (pvr >> 6) & 0xf; 122 aid = pvr & 0x3f; 123 124 while (cp->name) { 125 if (cp->version == cpu) 126 break; 127 cp++; 128 } 129 if (cp->name) 130 strcpy(cpu_model, cp->name); 131 else 132 sprintf(cpu_model, "Version 0x%x", cpu); 133 sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)", 134 (pvr >> 8) & 0xff, pvr & 0xff); 135 136 #if 1 137 printf(": %dMHz %s\n", processor_freq / 1000 / 1000, 138 cpu_model); 139 #endif 140 141 cpu_probe_cache(); 142 143 printf("Instruction cache size %d line size %d\n", 144 curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size); 145 printf("Data cache size %d line size %d\n", 146 curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size); 147 148 #ifdef DEBUG 149 /* It sux that the cache info here is useless. */ 150 printf("PVR: owner %x core family %x cache %x version %x asic %x\n", 151 own, pcf, cas, pcl, aid); 152 #endif 153 154 /* 155 * If there is no ECC irq property, assume the hardware 156 * doesn't support it. 157 * 158 * XXX: ECC handling needs to be pulled out of here so it 159 * doesn't add unnecessary code to ports which don't need it. 160 */ 161 if (board_info_get("4xx-ecc-irq", &eccirq, sizeof(eccirq)) == -1) 162 return; 163 164 /* Initialize ECC error-logging handler. This is always enabled, 165 * but it will never be called on systems that do not have ECC 166 * enabled by POST code in the bootloader. 167 */ 168 169 printf("Enabling ecc handler\n"); 170 intr_ecc_tb = 0; 171 intr_ecc_iv = processor_freq; /* Set interval */ 172 intr_ecc_cnt = 0; 173 174 intr_establish(eccirq, IST_LEVEL, IPL_SERIAL, intr_ecc, NULL); 175 } 176 177 /* 178 * This routine must be explicitly called to initialize the 179 * CPU cache information so cache flushe and memcpy operation 180 * work. 181 */ 182 void 183 cpu_probe_cache() 184 { 185 int version; 186 187 /* 188 * First we need to identify the cpu and determine the 189 * cache line size, or things like memset/memcpy may lose 190 * badly. 191 */ 192 __asm __volatile("mfpvr %0" : "=r" (version)); 193 switch (version & 0xffff0000) { 194 case PVR_401A1: 195 curcpu()->ci_ci.dcache_size = 1024; 196 curcpu()->ci_ci.dcache_line_size = 16; 197 curcpu()->ci_ci.icache_size = 2848; 198 curcpu()->ci_ci.icache_line_size = 16; 199 break; 200 case PVR_401B2: 201 curcpu()->ci_ci.dcache_size = 8192; 202 curcpu()->ci_ci.dcache_line_size = 16; 203 curcpu()->ci_ci.icache_size = 16384; 204 curcpu()->ci_ci.icache_line_size = 16; 205 break; 206 case PVR_401C2: 207 curcpu()->ci_ci.dcache_size = 8192; 208 curcpu()->ci_ci.dcache_line_size = 16; 209 curcpu()->ci_ci.icache_size = 0; 210 curcpu()->ci_ci.icache_line_size = 16; 211 break; 212 case PVR_401D2: 213 curcpu()->ci_ci.dcache_size = 2848; 214 curcpu()->ci_ci.dcache_line_size = 16; 215 curcpu()->ci_ci.icache_size = 4096; 216 curcpu()->ci_ci.icache_line_size = 16; 217 break; 218 case PVR_401E2: 219 curcpu()->ci_ci.dcache_size = 0; 220 curcpu()->ci_ci.dcache_line_size = 16; 221 curcpu()->ci_ci.icache_size = 0; 222 curcpu()->ci_ci.icache_line_size = 16; 223 break; 224 case PVR_401F2: 225 curcpu()->ci_ci.dcache_size = 2048; 226 curcpu()->ci_ci.dcache_line_size = 16; 227 curcpu()->ci_ci.icache_size = 2848; 228 curcpu()->ci_ci.icache_line_size = 16; 229 break; 230 case PVR_401G2: 231 curcpu()->ci_ci.dcache_size = 2848; 232 curcpu()->ci_ci.dcache_line_size = 16; 233 curcpu()->ci_ci.icache_size = 8192; 234 curcpu()->ci_ci.icache_line_size = 16; 235 break; 236 case PVR_403: 237 curcpu()->ci_ci.dcache_line_size = 16; 238 curcpu()->ci_ci.icache_line_size = 16; 239 break; 240 case PVR_405GP: 241 curcpu()->ci_ci.dcache_size = 8192; 242 curcpu()->ci_ci.dcache_line_size = 32; 243 curcpu()->ci_ci.icache_size = 8192; 244 curcpu()->ci_ci.icache_line_size = 32; 245 break; 246 default: 247 /* 248 * Unknown CPU type. For safety we'll specify a 249 * cache with a 4-byte line size. That way cache 250 * flush routines won't miss any lines. 251 */ 252 curcpu()->ci_ci.dcache_line_size = 4; 253 curcpu()->ci_ci.icache_line_size = 4; 254 break; 255 } 256 257 } 258 259 /* 260 * These small routines may have to be replaced, 261 * if/when we support processors other that the 604. 262 */ 263 264 void 265 dcache_flush_page(vaddr_t va) 266 { 267 int i; 268 269 if (curcpu()->ci_ci.dcache_line_size) 270 for (i = 0; i < NBPG; i += curcpu()->ci_ci.dcache_line_size) 271 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 272 asm volatile("sync;isync" : : ); 273 } 274 275 void 276 icache_flush_page(vaddr_t va) 277 { 278 int i; 279 280 if (curcpu()->ci_ci.icache_line_size) 281 for (i = 0; i < NBPG; i += curcpu()->ci_ci.icache_line_size) 282 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 283 asm volatile("sync;isync" : : ); 284 } 285 286 void 287 dcache_flush(vaddr_t va, vsize_t len) 288 { 289 int i; 290 291 if (len == 0) 292 return; 293 294 /* Make sure we flush all cache lines */ 295 len += va & (curcpu()->ci_ci.dcache_line_size-1); 296 if (curcpu()->ci_ci.dcache_line_size) 297 for (i = 0; i < len; i += curcpu()->ci_ci.dcache_line_size) 298 asm volatile("dcbf %0,%1" : : "r" (va), "r" (i)); 299 asm volatile("sync;isync" : : ); 300 } 301 302 void 303 icache_flush(vaddr_t va, vsize_t len) 304 { 305 int i; 306 307 if (len == 0) 308 return; 309 310 /* Make sure we flush all cache lines */ 311 len += va & (curcpu()->ci_ci.icache_line_size-1); 312 if (curcpu()->ci_ci.icache_line_size) 313 for (i = 0; i < len; i += curcpu()->ci_ci.icache_line_size) 314 asm volatile("icbi %0,%1" : : "r" (va), "r" (i)); 315 asm volatile("sync;isync" : : ); 316 } 317 318 /* 319 * ECC fault handler. 320 */ 321 int 322 intr_ecc(void * arg) 323 { 324 u_int32_t esr, ear; 325 int ce, ue; 326 u_quad_t tb; 327 u_long tmp, msr, dat; 328 unsigned int memsiz; 329 330 if (board_info_get("mem-size", &memsiz, sizeof(memsiz)) == -1) 331 panic("no mem-size"); 332 333 /* This code needs to be improved to handle double-bit errors */ 334 /* in some intelligent fashion. */ 335 336 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 337 esr = mfdcr(DCR_SDRAM0_CFGDATA); 338 339 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_BEAR); 340 ear = mfdcr(DCR_SDRAM0_CFGDATA); 341 342 /* Always clear the error to stop the intr ASAP. */ 343 344 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 345 mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff); 346 347 if (esr == 0x00) { 348 /* No current error. Could happen due to intr. nesting */ 349 return(1); 350 }; 351 352 /* Only report errors every once per second max. Do this using the TB, */ 353 /* because the system time (via microtime) may be adjusted when the date is set */ 354 /* and can't reliably be used to measure intervals. */ 355 356 asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b" 357 : "=r"(tb), "=r"(tmp)); 358 intr_ecc_cnt++; 359 360 if ((tb - intr_ecc_tb) < intr_ecc_iv) { 361 return(1); 362 }; 363 364 ce = (esr & SDRAM0_ECCESR_CE) != 0x00; 365 ue = (esr & SDRAM0_ECCESR_UE) != 0x00; 366 367 printf("ECC: Error CNT=%d ESR=%x EAR=%x %s BKNE=%d%d%d%d " 368 "BLCE=%d%d%d%d CBE=%d%d.\n", 369 intr_ecc_cnt, esr, ear, 370 (ue) ? "Uncorrectable" : "Correctable", 371 ((esr & SDRAM0_ECCESR_BKEN(0)) != 0x00), 372 ((esr & SDRAM0_ECCESR_BKEN(1)) != 0x00), 373 ((esr & SDRAM0_ECCESR_BKEN(2)) != 0x00), 374 ((esr & SDRAM0_ECCESR_BKEN(3)) != 0x00), 375 ((esr & SDRAM0_ECCESR_BLCEN(0)) != 0x00), 376 ((esr & SDRAM0_ECCESR_BLCEN(1)) != 0x00), 377 ((esr & SDRAM0_ECCESR_BLCEN(2)) != 0x00), 378 ((esr & SDRAM0_ECCESR_BLCEN(3)) != 0x00), 379 ((esr & SDRAM0_ECCESR_CBEN(0)) != 0x00), 380 ((esr & SDRAM0_ECCESR_CBEN(1)) != 0x00)); 381 382 /* Should check for uncorrectable errors and panic... */ 383 384 if (intr_ecc_cnt > 1000) { 385 printf("ECC: Too many errors, recycling entire " 386 "SDRAM (size = %d).\n", memsiz); 387 388 /* Can this code be changed to run without disabling data MMU and disabling intrs? */ 389 /* Does kernel always map all of physical RAM VA=PA? If so, just loop over lowmem. */ 390 391 asm volatile( 392 "mfmsr %0;" 393 "li %1, 0x00;" 394 "ori %1, %1, 0x8010;" 395 "andc %1, %0, %1;" 396 "mtmsr %1;" 397 "sync;isync;" 398 "li %1, 0x00;" 399 "1:" 400 "dcbt 0, %1;" 401 "sync;isync;" 402 "lwz %2, 0(%1);" 403 "stw %2, 0(%1);" 404 "sync;isync;" 405 "dcbf 0, %1;" 406 "sync;isync;" 407 "addi %1, %1, 0x20;" 408 "addic. %3, %3, -0x20;" 409 "bge 1b;" 410 "mtmsr %0;" 411 "sync;isync;" 412 : "=&r" (msr), "=&r" (tmp), "=&r" (dat) 413 : "r" (memsiz) : "0" ); 414 415 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 416 esr = mfdcr(DCR_SDRAM0_CFGDATA); 417 418 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 419 mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff); 420 421 /* Correctable errors here are OK, mem should be clean now. */ 422 /* Should check for uncorrectable errors and panic... */ 423 printf("ECC: Recycling complete, ESR=%x. " 424 "Checking for persistent errors.\n", esr); 425 426 asm volatile( 427 "mfmsr %0;" 428 "li %1, 0x00;" 429 "ori %1, %1, 0x8010;" 430 "andc %1, %0, %1;" 431 "mtmsr %1;" 432 "sync;isync;" 433 "li %1, 0x00;" 434 "1:" 435 "dcbt 0, %1;" 436 "sync;isync;" 437 "lwz %2, 0(%1);" 438 "stw %2, 0(%1);" 439 "sync;isync;" 440 "dcbf 0, %1;" 441 "sync;isync;" 442 "addi %1, %1, 0x20;" 443 "addic. %3, %3, -0x20;" 444 "bge 1b;" 445 "mtmsr %0;" 446 "sync;isync;" 447 : "=&r" (msr), "=&r" (tmp), "=&r" (dat) 448 : "r" (memsiz) : "0" ); 449 450 mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR); 451 esr = mfdcr(DCR_SDRAM0_CFGDATA); 452 453 /* If esr is non zero here, we're screwed. Should check this and panic. */ 454 printf("ECC: Persistent error check complete, " 455 "final ESR=%x.\n", esr); 456 }; 457 458 intr_ecc_tb = tb; 459 intr_ecc_cnt = 0; 460 461 return(1); 462 }; 463
Indexes created Tue Sep 30 20:09:53 GMT 2025