ibm405gp.c revision 1.6
1 /* $NetBSD: ibm405gp.c,v 1.6 2011/06/22 18:06:34 matt Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ibm405gp.c,v 1.6 2011/06/22 18:06:34 matt Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/systm.h> 44 #include <sys/extent.h> 45 #include <sys/bus.h> 46 47 #include <dev/pci/pcivar.h> 48 49 #include <powerpc/ibm4xx/ibm405gp.h> 50 #include <powerpc/ibm4xx/pci_machdep.h> 51 #include <powerpc/ibm4xx/dev/pcicreg.h> 52 53 static struct powerpc_bus_space pcicfg_tag = { 54 _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 55 IBM405GP_PCIL0_BASE, 0x0, 0x40 56 }; 57 static char ex_storage[EXTENT_FIXED_STORAGE_SIZE(1)] 58 __attribute__((aligned(8))); 59 static bus_space_tag_t pcicfg_iot = &pcicfg_tag; 60 static bus_space_handle_t pcicfg_ioh = 0; 61 62 #define PCI0_MEM_BASE 0x80000000 63 64 static struct genppc_pci_chipset genppc_ibm4xx_chipset = { 65 .pc_conf_v = NULL, 66 .pc_attach_hook = ibm4xx_pci_attach_hook, 67 .pc_bus_maxdevs = ibm4xx_pci_bus_maxdevs, 68 .pc_make_tag = ibm4xx_pci_make_tag, 69 .pc_conf_read = ibm4xx_pci_conf_read, 70 .pc_conf_write = ibm4xx_pci_conf_write, 71 72 .pc_intr_v = &genppc_ibm4xx_chipset, 73 .pc_intr_map = genppc_pci_intr_map, 74 .pc_intr_string = genppc_pci_intr_string, 75 .pc_intr_evcnt = genppc_pci_intr_evcnt, 76 .pc_intr_establish = genppc_pci_intr_establish, 77 .pc_intr_disestablish = genppc_pci_intr_disestablish, 78 .pc_intr_setattr = ibm4xx_pci_intr_setattr, 79 80 .pc_conf_interrupt = ibm4xx_pci_conf_interrupt, 81 .pc_decompose_tag = ibm4xx_pci_decompose_tag, 82 .pc_conf_hook = ibm4xx_pci_conf_hook, 83 }; 84 85 pci_chipset_tag_t 86 ibm4xx_get_pci_chipset_tag(void) 87 { 88 return &genppc_ibm4xx_chipset; 89 } 90 91 static void 92 setup_pcicfg_window(void) 93 { 94 if (pcicfg_ioh) 95 return; 96 if (bus_space_init(&pcicfg_tag, 97 "pcicfg", ex_storage, sizeof(ex_storage)) || 98 bus_space_map(pcicfg_iot, 0, 0x40 , 0, &pcicfg_ioh)) 99 panic("Cannot map PCI configuration registers"); 100 } 101 102 /* 103 * Setup proper Local<->PCI mapping 104 * PCI memory window: 256M @ PCI0MEMBASE with direct memory translation 105 */ 106 void 107 ibm4xx_setup_pci(void) 108 { 109 pci_chipset_tag_t pc = &genppc_ibm4xx_chipset; 110 pcitag_t tag; 111 112 setup_pcicfg_window(); 113 114 /* Disable all three memory mappers */ 115 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA, 0x00000000); /* disabled */ 116 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1MA, 0x00000000); /* disabled */ 117 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2MA, 0x00000000); /* disabled */ 118 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS, 0x00000000); /* Can't really disable PTM1. */ 119 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2MS, 0x00000000); /* disabled */ 120 121 122 /* Setup memory map #0 */ 123 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA, 0xF0000001); /* 256M non-prefetchable, enabled */ 124 125 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0LA, PCI0_MEM_BASE); 126 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCILA, PCI0_MEM_BASE); 127 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCIHA, 0); 128 129 /* Configure PCI bridge */ 130 tag = pci_make_tag(pc, 0, 0, 0); 131 // x = pci_conf_read(pc, tag, PCI0_CMD); /* Read PCI command register */ 132 // pci_conf_write(pc, tag, PCI0_CMD, x | MA | ME); /* enable bus mastering and memory space */ 133 134 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS, 0xF0000001); /* Enable PTM1 */ 135 bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1LA, 0); 136 pci_conf_write(pc, tag, PCIC_PTM1BAR, 0); /* Set up proper PCI->Local address base. Always enabled */ 137 pci_conf_write(pc, tag, PCIC_PTM2BAR, 0); 138 } 139 140 void 141 ibm4xx_show_pci_map(void) 142 { 143 pci_chipset_tag_t pc = &genppc_ibm4xx_chipset; 144 paddr_t la, lm, pl, ph; 145 pcitag_t tag; 146 147 setup_pcicfg_window(); 148 149 printf("Local -> PCI map\n"); 150 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0LA); 151 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0MA); 152 pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCILA); 153 ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM0PCIHA); 154 printf("0: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl, 155 (lm & 2) ? "":"not ", 156 (lm & 1) ? "enabled":"disabled"); 157 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1LA); 158 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1MA); 159 pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1PCILA); 160 ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM1PCIHA); 161 printf("1: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl, 162 (lm & 2) ? "":"not ", 163 (lm & 1) ? "enabled":"disabled"); 164 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2LA); 165 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2MA); 166 pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2PCILA); 167 ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PMM2PCIHA); 168 printf("2: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl, 169 (lm & 2) ? "":"not ", 170 (lm & 1) ? "enabled":"disabled"); 171 printf("PCI -> Local map\n"); 172 173 tag = pci_make_tag(pc, 0, 0, 0); 174 pl = pci_conf_read(pc, tag, PCIC_PTM1BAR); 175 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1LA); 176 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM1MS); 177 printf("1: %08lx -> %08lx,%08lx %s\n", pl, la, lm, 178 (lm & 1)?"enabled":"disabled"); 179 pl = pci_conf_read(pc, tag, PCIC_PTM2BAR); 180 la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2LA); 181 lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL_PTM2MS); 182 printf("2: %08lx -> %08lx,%08lx %s\n", pl, la, lm, 183 (lm & 1)?"enabled":"disabled"); 184 } 185
Indexes created Mon Sep 22 10:09:38 GMT 2025