if_emac.c revision 1.32.16.1
1 /* $NetBSD: if_emac.c,v 1.32.16.1 2008/10/19 22:15:54 haad Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Jason Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_emac.c,v 1.32.16.1 2008/10/19 22:15:54 haad Exp $"); 40 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 50 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #if NBPFILTER > 0 58 #include <net/bpf.h> 59 #endif 60 61 #include <powerpc/ibm4xx/dev/opbvar.h> 62 63 #include <powerpc/ibm4xx/ibm405gp.h> 64 #include <powerpc/ibm4xx/mal405gp.h> 65 #include <powerpc/ibm4xx/dcr405gp.h> 66 #include <powerpc/ibm4xx/dev/emacreg.h> 67 #include <powerpc/ibm4xx/dev/if_emacreg.h> 68 69 #include <dev/mii/miivar.h> 70 71 /* 72 * Transmit descriptor list size. There are two Tx channels, each with 73 * up to 256 hardware descriptors available. We currently use one Tx 74 * channel. We tell the upper layers that they can queue a lot of 75 * packets, and we go ahead and manage up to 64 of them at a time. We 76 * allow up to 16 DMA segments per packet. 77 */ 78 #define EMAC_NTXSEGS 16 79 #define EMAC_TXQUEUELEN 64 80 #define EMAC_TXQUEUELEN_MASK (EMAC_TXQUEUELEN - 1) 81 #define EMAC_TXQUEUE_GC (EMAC_TXQUEUELEN / 4) 82 #define EMAC_NTXDESC 256 83 #define EMAC_NTXDESC_MASK (EMAC_NTXDESC - 1) 84 #define EMAC_NEXTTX(x) (((x) + 1) & EMAC_NTXDESC_MASK) 85 #define EMAC_NEXTTXS(x) (((x) + 1) & EMAC_TXQUEUELEN_MASK) 86 87 /* 88 * Receive descriptor list size. There is one Rx channel with up to 256 89 * hardware descriptors available. We allocate 64 receive descriptors, 90 * each with a 2k buffer (MCLBYTES). 91 */ 92 #define EMAC_NRXDESC 64 93 #define EMAC_NRXDESC_MASK (EMAC_NRXDESC - 1) 94 #define EMAC_NEXTRX(x) (((x) + 1) & EMAC_NRXDESC_MASK) 95 #define EMAC_PREVRX(x) (((x) - 1) & EMAC_NRXDESC_MASK) 96 97 /* 98 * Transmit/receive descriptors that are DMA'd to the EMAC. 99 */ 100 struct emac_control_data { 101 struct mal_descriptor ecd_txdesc[EMAC_NTXDESC]; 102 struct mal_descriptor ecd_rxdesc[EMAC_NRXDESC]; 103 }; 104 105 #define EMAC_CDOFF(x) offsetof(struct emac_control_data, x) 106 #define EMAC_CDTXOFF(x) EMAC_CDOFF(ecd_txdesc[(x)]) 107 #define EMAC_CDRXOFF(x) EMAC_CDOFF(ecd_rxdesc[(x)]) 108 109 /* 110 * Software state for transmit jobs. 111 */ 112 struct emac_txsoft { 113 struct mbuf *txs_mbuf; /* head of mbuf chain */ 114 bus_dmamap_t txs_dmamap; /* our DMA map */ 115 int txs_firstdesc; /* first descriptor in packet */ 116 int txs_lastdesc; /* last descriptor in packet */ 117 int txs_ndesc; /* # of descriptors used */ 118 }; 119 120 /* 121 * Software state for receive descriptors. 122 */ 123 struct emac_rxsoft { 124 struct mbuf *rxs_mbuf; /* head of mbuf chain */ 125 bus_dmamap_t rxs_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct emac_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 void *sc_powerhook; /* power management hook */ 139 140 struct mii_data sc_mii; /* MII/media information */ 141 struct callout sc_callout; /* tick callout */ 142 143 u_int32_t sc_mr1; /* copy of Mode Register 1 */ 144 145 bus_dmamap_t sc_cddmamap; /* control data dma map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* Software state for transmit/receive descriptors. */ 149 struct emac_txsoft sc_txsoft[EMAC_TXQUEUELEN]; 150 struct emac_rxsoft sc_rxsoft[EMAC_NRXDESC]; 151 152 /* Control data structures. */ 153 struct emac_control_data *sc_control_data; 154 #define sc_txdescs sc_control_data->ecd_txdesc 155 #define sc_rxdescs sc_control_data->ecd_rxdesc 156 157 #ifdef EMAC_EVENT_COUNTERS 158 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 159 struct evcnt sc_ev_txintr; /* Tx interrupts */ 160 struct evcnt sc_ev_rxde; /* Rx descriptor interrupts */ 161 struct evcnt sc_ev_txde; /* Tx descriptor interrupts */ 162 struct evcnt sc_ev_wol; /* Wake-On-Lan interrupts */ 163 struct evcnt sc_ev_serr; /* MAL system error interrupts */ 164 struct evcnt sc_ev_intr; /* General EMAC interrupts */ 165 166 struct evcnt sc_ev_txreap; /* Calls to Tx descriptor reaper */ 167 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 168 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 169 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 170 struct evcnt sc_ev_tu; /* Tx underrun */ 171 #endif /* EMAC_EVENT_COUNTERS */ 172 173 int sc_txfree; /* number of free Tx descriptors */ 174 int sc_txnext; /* next ready Tx descriptor */ 175 176 int sc_txsfree; /* number of free Tx jobs */ 177 int sc_txsnext; /* next ready Tx job */ 178 int sc_txsdirty; /* dirty Tx jobs */ 179 180 int sc_rxptr; /* next ready RX descriptor/descsoft */ 181 }; 182 183 #ifdef EMAC_EVENT_COUNTERS 184 #define EMAC_EVCNT_INCR(ev) (ev)->ev_count++ 185 #else 186 #define EMAC_EVCNT_INCR(ev) /* nothing */ 187 #endif 188 189 #define EMAC_CDTXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDTXOFF((x))) 190 #define EMAC_CDRXADDR(sc, x) ((sc)->sc_cddma + EMAC_CDRXOFF((x))) 191 192 #define EMAC_CDTXSYNC(sc, x, n, ops) \ 193 do { \ 194 int __x, __n; \ 195 \ 196 __x = (x); \ 197 __n = (n); \ 198 \ 199 /* If it will wrap around, sync to the end of the ring. */ \ 200 if ((__x + __n) > EMAC_NTXDESC) { \ 201 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 202 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * \ 203 (EMAC_NTXDESC - __x), (ops)); \ 204 __n -= (EMAC_NTXDESC - __x); \ 205 __x = 0; \ 206 } \ 207 \ 208 /* Now sync whatever is left. */ \ 209 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 210 EMAC_CDTXOFF(__x), sizeof(struct mal_descriptor) * __n, (ops)); \ 211 } while (/*CONSTCOND*/0) 212 213 #define EMAC_CDRXSYNC(sc, x, ops) \ 214 do { \ 215 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 216 EMAC_CDRXOFF((x)), sizeof(struct mal_descriptor), (ops)); \ 217 } while (/*CONSTCOND*/0) 218 219 #define EMAC_INIT_RXDESC(sc, x) \ 220 do { \ 221 struct emac_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 222 struct mal_descriptor *__rxd = &(sc)->sc_rxdescs[(x)]; \ 223 struct mbuf *__m = __rxs->rxs_mbuf; \ 224 \ 225 /* \ 226 * Note: We scoot the packet forward 2 bytes in the buffer \ 227 * so that the payload after the Ethernet header is aligned \ 228 * to a 4-byte boundary. \ 229 */ \ 230 __m->m_data = __m->m_ext.ext_buf + 2; \ 231 \ 232 __rxd->md_data = __rxs->rxs_dmamap->dm_segs[0].ds_addr + 2; \ 233 __rxd->md_data_len = __m->m_ext.ext_size - 2; \ 234 __rxd->md_stat_ctrl = MAL_RX_EMPTY | MAL_RX_INTERRUPT | \ 235 /* Set wrap on last descriptor. */ \ 236 (((x) == EMAC_NRXDESC - 1) ? MAL_RX_WRAP : 0); \ 237 EMAC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 238 } while (/*CONSTCOND*/0) 239 240 #define EMAC_WRITE(sc, reg, val) \ 241 bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 242 #define EMAC_READ(sc, reg) \ 243 bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg)) 244 245 #define EMAC_SET_FILTER(aht, category) \ 246 do { \ 247 (aht)[3 - ((category) >> 4)] |= 1 << ((category) & 0xf); \ 248 } while (/*CONSTCOND*/0) 249 250 static int emac_match(struct device *, struct cfdata *, void *); 251 static void emac_attach(struct device *, struct device *, void *); 252 253 static int emac_add_rxbuf(struct emac_softc *, int); 254 static int emac_init(struct ifnet *); 255 static int emac_ioctl(struct ifnet *, u_long, void *); 256 static void emac_reset(struct emac_softc *); 257 static void emac_rxdrain(struct emac_softc *); 258 static int emac_txreap(struct emac_softc *); 259 static void emac_shutdown(void *); 260 static void emac_start(struct ifnet *); 261 static void emac_stop(struct ifnet *, int); 262 static void emac_watchdog(struct ifnet *); 263 static int emac_set_filter(struct emac_softc *); 264 265 static int emac_wol_intr(void *); 266 static int emac_serr_intr(void *); 267 static int emac_txeob_intr(void *); 268 static int emac_rxeob_intr(void *); 269 static int emac_txde_intr(void *); 270 static int emac_rxde_intr(void *); 271 static int emac_intr(void *); 272 273 static int emac_mii_readreg(struct device *, int, int); 274 static void emac_mii_statchg(struct device *); 275 static void emac_mii_tick(void *); 276 static uint32_t emac_mii_wait(struct emac_softc *); 277 static void emac_mii_writereg(struct device *, int, int, int); 278 279 int emac_copy_small = 0; 280 281 CFATTACH_DECL(emac, sizeof(struct emac_softc), 282 emac_match, emac_attach, NULL, NULL); 283 284 static int 285 emac_match(struct device *parent, struct cfdata *cf, void *aux) 286 { 287 struct opb_attach_args *oaa = aux; 288 289 /* match only on-chip ethernet devices */ 290 if (strcmp(oaa->opb_name, cf->cf_name) == 0) 291 return (1); 292 293 return (0); 294 } 295 296 static void 297 emac_attach(struct device *parent, struct device *self, void *aux) 298 { 299 struct opb_attach_args *oaa = aux; 300 struct emac_softc *sc = (struct emac_softc *)self; 301 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 302 struct mii_data *mii = &sc->sc_mii; 303 bus_dma_segment_t seg; 304 int error, i, nseg; 305 const uint8_t *enaddr; 306 prop_data_t ea; 307 308 bus_space_map(oaa->opb_bt, oaa->opb_addr, EMAC_NREG, 0, &sc->sc_sh); 309 sc->sc_st = oaa->opb_bt; 310 sc->sc_dmat = oaa->opb_dmat; 311 312 printf(": 405GP EMAC\n"); 313 314 callout_init(&sc->sc_callout, 0); 315 316 /* 317 * Set up Mode Register 1 - set receive and transmit FIFOs to maximum 318 * size, allow transmit of multiple packets (only channel 0 is used). 319 * 320 * XXX: Allow pause packets?? 321 */ 322 sc->sc_mr1 = MR1_RFS_4KB | MR1_TFS_2KB | MR1_TR0_MULTIPLE; 323 324 intr_establish(oaa->opb_irq , IST_LEVEL, IPL_NET, emac_wol_intr, sc); 325 intr_establish(oaa->opb_irq + 1, IST_LEVEL, IPL_NET, emac_serr_intr, sc); 326 intr_establish(oaa->opb_irq + 2, IST_LEVEL, IPL_NET, emac_txeob_intr, sc); 327 intr_establish(oaa->opb_irq + 3, IST_LEVEL, IPL_NET, emac_rxeob_intr, sc); 328 intr_establish(oaa->opb_irq + 4, IST_LEVEL, IPL_NET, emac_txde_intr, sc); 329 intr_establish(oaa->opb_irq + 5, IST_LEVEL, IPL_NET, emac_rxde_intr, sc); 330 intr_establish(oaa->opb_irq + 6, IST_LEVEL, IPL_NET, emac_intr, sc); 331 printf("%s: interrupting at irqs %d .. %d\n", sc->sc_dev.dv_xname, 332 oaa->opb_irq, oaa->opb_irq + 6); 333 334 /* 335 * Allocate the control data structures, and create and load the 336 * DMA map for it. 337 */ 338 if ((error = bus_dmamem_alloc(sc->sc_dmat, 339 sizeof(struct emac_control_data), 0, 0, &seg, 1, &nseg, 0)) != 0) { 340 printf("%s: unable to allocate control data, error = %d\n", 341 sc->sc_dev.dv_xname, error); 342 goto fail_0; 343 } 344 345 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 346 sizeof(struct emac_control_data), (void **)&sc->sc_control_data, 347 BUS_DMA_COHERENT)) != 0) { 348 printf("%s: unable to map control data, error = %d\n", 349 sc->sc_dev.dv_xname, error); 350 goto fail_1; 351 } 352 353 if ((error = bus_dmamap_create(sc->sc_dmat, 354 sizeof(struct emac_control_data), 1, 355 sizeof(struct emac_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 356 printf("%s: unable to create control data DMA map, " 357 "error = %d\n", sc->sc_dev.dv_xname, error); 358 goto fail_2; 359 } 360 361 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 362 sc->sc_control_data, sizeof(struct emac_control_data), NULL, 363 0)) != 0) { 364 printf("%s: unable to load control data DMA map, error = %d\n", 365 sc->sc_dev.dv_xname, error); 366 goto fail_3; 367 } 368 369 /* 370 * Create the transmit buffer DMA maps. 371 */ 372 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 373 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 374 EMAC_NTXSEGS, MCLBYTES, 0, 0, 375 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 376 printf("%s: unable to create tx DMA map %d, " 377 "error = %d\n", sc->sc_dev.dv_xname, i, error); 378 goto fail_4; 379 } 380 } 381 382 /* 383 * Create the receive buffer DMA maps. 384 */ 385 for (i = 0; i < EMAC_NRXDESC; i++) { 386 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 387 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 388 printf("%s: unable to create rx DMA map %d, " 389 "error = %d\n", sc->sc_dev.dv_xname, i, error); 390 goto fail_5; 391 } 392 sc->sc_rxsoft[i].rxs_mbuf = NULL; 393 } 394 395 /* 396 * Reset the chip to a known state. 397 */ 398 emac_reset(sc); 399 400 /* Fetch the Ethernet address. */ 401 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 402 if (ea == NULL) { 403 printf("%s: unable to get mac-addr property\n", 404 sc->sc_dev.dv_xname); 405 return; 406 } 407 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 408 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 409 enaddr = prop_data_data_nocopy(ea); 410 411 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 412 ether_sprintf(enaddr)); 413 414 /* 415 * Initialise the media structures. 416 */ 417 mii->mii_ifp = ifp; 418 mii->mii_readreg = emac_mii_readreg; 419 mii->mii_writereg = emac_mii_writereg; 420 mii->mii_statchg = emac_mii_statchg; 421 422 sc->sc_ethercom.ec_mii = mii; 423 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 424 mii_attach(&sc->sc_dev, mii, 0xffffffff, 425 MII_PHY_ANY, MII_OFFSET_ANY, 0); 426 if (LIST_FIRST(&mii->mii_phys) == NULL) { 427 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 428 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 429 } else 430 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 431 432 ifp = &sc->sc_ethercom.ec_if; 433 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 434 ifp->if_softc = sc; 435 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 436 ifp->if_ioctl = emac_ioctl; 437 ifp->if_start = emac_start; 438 ifp->if_watchdog = emac_watchdog; 439 ifp->if_init = emac_init; 440 ifp->if_stop = emac_stop; 441 IFQ_SET_READY(&ifp->if_snd); 442 443 /* 444 * We can support 802.1Q VLAN-sized frames. 445 */ 446 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 447 448 /* 449 * Attach the interface. 450 */ 451 if_attach(ifp); 452 ether_ifattach(ifp, enaddr); 453 454 #ifdef EMAC_EVENT_COUNTERS 455 /* 456 * Attach the event counters. 457 */ 458 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 459 NULL, sc->sc_dev.dv_xname, "rxintr"); 460 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 461 NULL, sc->sc_dev.dv_xname, "txintr"); 462 evcnt_attach_dynamic(&sc->sc_ev_rxde, EVCNT_TYPE_INTR, 463 NULL, sc->sc_dev.dv_xname, "rxde"); 464 evcnt_attach_dynamic(&sc->sc_ev_txde, EVCNT_TYPE_INTR, 465 NULL, sc->sc_dev.dv_xname, "txde"); 466 evcnt_attach_dynamic(&sc->sc_ev_wol, EVCNT_TYPE_INTR, 467 NULL, sc->sc_dev.dv_xname, "wol"); 468 evcnt_attach_dynamic(&sc->sc_ev_serr, EVCNT_TYPE_INTR, 469 NULL, sc->sc_dev.dv_xname, "serr"); 470 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 471 NULL, sc->sc_dev.dv_xname, "intr"); 472 473 evcnt_attach_dynamic(&sc->sc_ev_txreap, EVCNT_TYPE_MISC, 474 NULL, sc->sc_dev.dv_xname, "txreap"); 475 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 476 NULL, sc->sc_dev.dv_xname, "txsstall"); 477 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 478 NULL, sc->sc_dev.dv_xname, "txdstall"); 479 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 480 NULL, sc->sc_dev.dv_xname, "txdrop"); 481 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 482 NULL, sc->sc_dev.dv_xname, "tu"); 483 #endif /* EMAC_EVENT_COUNTERS */ 484 485 /* 486 * Make sure the interface is shutdown during reboot. 487 */ 488 sc->sc_sdhook = shutdownhook_establish(emac_shutdown, sc); 489 if (sc->sc_sdhook == NULL) 490 printf("%s: WARNING: unable to establish shutdown hook\n", 491 sc->sc_dev.dv_xname); 492 493 return; 494 495 /* 496 * Free any resources we've allocated during the failed attach 497 * attempt. Do this in reverse order and fall through. 498 */ 499 fail_5: 500 for (i = 0; i < EMAC_NRXDESC; i++) { 501 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 502 bus_dmamap_destroy(sc->sc_dmat, 503 sc->sc_rxsoft[i].rxs_dmamap); 504 } 505 fail_4: 506 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 507 if (sc->sc_txsoft[i].txs_dmamap != NULL) 508 bus_dmamap_destroy(sc->sc_dmat, 509 sc->sc_txsoft[i].txs_dmamap); 510 } 511 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 512 fail_3: 513 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 514 fail_2: 515 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 516 sizeof(struct emac_control_data)); 517 fail_1: 518 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 519 fail_0: 520 return; 521 } 522 523 /* 524 * Device shutdown routine. 525 */ 526 static void 527 emac_shutdown(void *arg) 528 { 529 struct emac_softc *sc = arg; 530 531 emac_stop(&sc->sc_ethercom.ec_if, 0); 532 } 533 534 /* ifnet interface function */ 535 static void 536 emac_start(struct ifnet *ifp) 537 { 538 struct emac_softc *sc = ifp->if_softc; 539 struct mbuf *m0; 540 struct emac_txsoft *txs; 541 bus_dmamap_t dmamap; 542 int error, firsttx, nexttx, lasttx, ofree, seg; 543 544 lasttx = 0; /* XXX gcc */ 545 546 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 547 return; 548 549 /* 550 * Remember the previous number of free descriptors. 551 */ 552 ofree = sc->sc_txfree; 553 554 /* 555 * Loop through the send queue, setting up transmit descriptors 556 * until we drain the queue, or use up all available transmit 557 * descriptors. 558 */ 559 for (;;) { 560 /* Grab a packet off the queue. */ 561 IFQ_POLL(&ifp->if_snd, m0); 562 if (m0 == NULL) 563 break; 564 565 /* 566 * Get a work queue entry. Reclaim used Tx descriptors if 567 * we are running low. 568 */ 569 if (sc->sc_txsfree < EMAC_TXQUEUE_GC) { 570 emac_txreap(sc); 571 if (sc->sc_txsfree == 0) { 572 EMAC_EVCNT_INCR(&sc->sc_ev_txsstall); 573 break; 574 } 575 } 576 577 txs = &sc->sc_txsoft[sc->sc_txsnext]; 578 dmamap = txs->txs_dmamap; 579 580 /* 581 * Load the DMA map. If this fails, the packet either 582 * didn't fit in the alloted number of segments, or we 583 * were short on resources. In this case, we'll copy 584 * and try again. 585 */ 586 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 587 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 588 if (error) { 589 if (error == EFBIG) { 590 EMAC_EVCNT_INCR(&sc->sc_ev_txdrop); 591 printf("%s: Tx packet consumes too many " 592 "DMA segments, dropping...\n", 593 sc->sc_dev.dv_xname); 594 IFQ_DEQUEUE(&ifp->if_snd, m0); 595 m_freem(m0); 596 continue; 597 } 598 /* Short on resources, just stop for now. */ 599 break; 600 } 601 602 /* 603 * Ensure we have enough descriptors free to describe 604 * the packet. 605 */ 606 if (dmamap->dm_nsegs > sc->sc_txfree) { 607 /* 608 * Not enough free descriptors to transmit this 609 * packet. We haven't committed anything yet, 610 * so just unload the DMA map, put the packet 611 * back on the queue, and punt. Notify the upper 612 * layer that there are not more slots left. 613 * 614 */ 615 ifp->if_flags |= IFF_OACTIVE; 616 bus_dmamap_unload(sc->sc_dmat, dmamap); 617 EMAC_EVCNT_INCR(&sc->sc_ev_txdstall); 618 break; 619 } 620 621 IFQ_DEQUEUE(&ifp->if_snd, m0); 622 623 /* 624 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 625 */ 626 627 /* Sync the DMA map. */ 628 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 629 BUS_DMASYNC_PREWRITE); 630 631 /* 632 * Store a pointer to the packet so that we can free it 633 * later. 634 */ 635 txs->txs_mbuf = m0; 636 txs->txs_firstdesc = sc->sc_txnext; 637 txs->txs_ndesc = dmamap->dm_nsegs; 638 639 /* 640 * Initialize the transmit descriptor. 641 */ 642 firsttx = sc->sc_txnext; 643 for (nexttx = sc->sc_txnext, seg = 0; 644 seg < dmamap->dm_nsegs; 645 seg++, nexttx = EMAC_NEXTTX(nexttx)) { 646 /* 647 * If this is the first descriptor we're 648 * enqueueing, don't set the TX_READY bit just 649 * yet. That could cause a race condition. 650 * We'll do it below. 651 */ 652 sc->sc_txdescs[nexttx].md_data = 653 dmamap->dm_segs[seg].ds_addr; 654 sc->sc_txdescs[nexttx].md_data_len = 655 dmamap->dm_segs[seg].ds_len; 656 sc->sc_txdescs[nexttx].md_stat_ctrl = 657 (sc->sc_txdescs[nexttx].md_stat_ctrl & MAL_TX_WRAP) | 658 (nexttx == firsttx ? 0 : MAL_TX_READY) | 659 EMAC_TXC_GFCS | EMAC_TXC_GPAD; 660 lasttx = nexttx; 661 } 662 663 /* Set the LAST bit on the last segment. */ 664 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; 665 666 /* 667 * Set up last segment descriptor to send an interrupt after 668 * that descriptor is transmitted, and bypass existing Tx 669 * descriptor reaping method (for now...). 670 */ 671 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT; 672 673 674 txs->txs_lastdesc = lasttx; 675 676 /* Sync the descriptors we're using. */ 677 EMAC_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 679 680 /* 681 * The entire packet chain is set up. Give the 682 * first descriptor to the chip now. 683 */ 684 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; 685 EMAC_CDTXSYNC(sc, firsttx, 1, 686 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 687 /* 688 * Tell the EMAC that a new packet is available. 689 */ 690 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0); 691 692 /* Advance the tx pointer. */ 693 sc->sc_txfree -= txs->txs_ndesc; 694 sc->sc_txnext = nexttx; 695 696 sc->sc_txsfree--; 697 sc->sc_txsnext = EMAC_NEXTTXS(sc->sc_txsnext); 698 699 #if NBPFILTER > 0 700 /* 701 * Pass the packet to any BPF listeners. 702 */ 703 if (ifp->if_bpf) 704 bpf_mtap(ifp->if_bpf, m0); 705 #endif /* NBPFILTER > 0 */ 706 } 707 708 if (sc->sc_txfree == 0) { 709 /* No more slots left; notify upper layer. */ 710 ifp->if_flags |= IFF_OACTIVE; 711 } 712 713 if (sc->sc_txfree != ofree) { 714 /* Set a watchdog timer in case the chip flakes out. */ 715 ifp->if_timer = 5; 716 } 717 } 718 719 static int 720 emac_init(struct ifnet *ifp) 721 { 722 struct emac_softc *sc = ifp->if_softc; 723 struct emac_rxsoft *rxs; 724 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 725 int error, i; 726 727 error = 0; 728 729 /* Cancel any pending I/O. */ 730 emac_stop(ifp, 0); 731 732 /* Reset the chip to a known state. */ 733 emac_reset(sc); 734 735 /* 736 * Initialise the transmit descriptor ring. 737 */ 738 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 739 /* set wrap on last descriptor */ 740 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; 741 EMAC_CDTXSYNC(sc, 0, EMAC_NTXDESC, 742 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 743 sc->sc_txfree = EMAC_NTXDESC; 744 sc->sc_txnext = 0; 745 746 /* 747 * Initialise the transmit job descriptors. 748 */ 749 for (i = 0; i < EMAC_TXQUEUELEN; i++) 750 sc->sc_txsoft[i].txs_mbuf = NULL; 751 sc->sc_txsfree = EMAC_TXQUEUELEN; 752 sc->sc_txsnext = 0; 753 sc->sc_txsdirty = 0; 754 755 /* 756 * Initialise the receiver descriptor and receive job 757 * descriptor rings. 758 */ 759 for (i = 0; i < EMAC_NRXDESC; i++) { 760 rxs = &sc->sc_rxsoft[i]; 761 if (rxs->rxs_mbuf == NULL) { 762 if ((error = emac_add_rxbuf(sc, i)) != 0) { 763 printf("%s: unable to allocate or map rx " 764 "buffer %d, error = %d\n", 765 sc->sc_dev.dv_xname, i, error); 766 /* 767 * XXX Should attempt to run with fewer receive 768 * XXX buffers instead of just failing. 769 */ 770 emac_rxdrain(sc); 771 goto out; 772 } 773 } else 774 EMAC_INIT_RXDESC(sc, i); 775 } 776 sc->sc_rxptr = 0; 777 778 /* 779 * Set the current media. 780 */ 781 if ((error = ether_mediachange(ifp)) != 0) 782 goto out; 783 784 /* 785 * Give the transmit and receive rings to the MAL. 786 */ 787 mtdcr(DCR_MAL0_TXCTP0R, EMAC_CDTXADDR(sc, 0)); 788 mtdcr(DCR_MAL0_RXCTP0R, EMAC_CDRXADDR(sc, 0)); 789 790 /* 791 * Load the MAC address. 792 */ 793 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]); 794 EMAC_WRITE(sc, EMAC_IALR, 795 enaddr[2] << 24 | enaddr[3] << 16 | enaddr[4] << 8 | enaddr[5]); 796 797 /* 798 * Set the receive channel buffer size (in units of 16 bytes). 799 */ 800 #if MCLBYTES > (4096 - 16) /* XXX! */ 801 # error MCLBYTES > max rx channel buffer size 802 #endif 803 mtdcr(DCR_MAL0_RCBS0, MCLBYTES / 16); 804 805 /* Set fifos, media modes. */ 806 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1); 807 808 /* 809 * Enable Individual and (possibly) Broadcast Address modes, 810 * runt packets, and strip padding. 811 */ 812 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | 813 (ifp->if_flags & IFF_PROMISC ? RMR_PME : 0) | 814 (ifp->if_flags & IFF_BROADCAST ? RMR_BAE : 0)); 815 816 /* 817 * Set multicast filter. 818 */ 819 emac_set_filter(sc); 820 821 /* 822 * Set low- and urgent-priority request thresholds. 823 */ 824 EMAC_WRITE(sc, EMAC_TMR1, 825 ((7 << TMR1_TLR_SHIFT) & TMR1_TLR_MASK) | /* 16 word burst */ 826 ((15 << TMR1_TUR_SHIFT) & TMR1_TUR_MASK)); 827 /* 828 * Set Transmit Request Threshold Register. 829 */ 830 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256); 831 832 /* 833 * Set high and low receive watermarks. 834 */ 835 EMAC_WRITE(sc, EMAC_RWMR, 836 30 << RWMR_RLWM_SHIFT | 64 << RWMR_RLWM_SHIFT); 837 838 /* 839 * Set frame gap. 840 */ 841 EMAC_WRITE(sc, EMAC_IPGVR, 8); 842 843 /* 844 * Set interrupt status enable bits for EMAC and MAL. 845 */ 846 EMAC_WRITE(sc, EMAC_ISER, 847 ISR_BP | ISR_SE | ISR_ALE | ISR_BFCS | ISR_PTLE | ISR_ORE | ISR_IRE); 848 mtdcr(DCR_MAL0_IER, MAL0_IER_DE | MAL0_IER_NWE | MAL0_IER_TO | 849 MAL0_IER_OPB | MAL0_IER_PLB); 850 851 /* 852 * Enable the transmit and receive channel on the MAL. 853 */ 854 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 855 mtdcr(DCR_MAL0_TXCASR, MAL0_TXCASR_CHAN0); 856 857 /* 858 * Enable the transmit and receive channel on the EMAC. 859 */ 860 EMAC_WRITE(sc, EMAC_MR0, MR0_TXE | MR0_RXE); 861 862 /* 863 * Start the one second MII clock. 864 */ 865 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 866 867 /* 868 * ... all done! 869 */ 870 ifp->if_flags |= IFF_RUNNING; 871 ifp->if_flags &= ~IFF_OACTIVE; 872 873 out: 874 if (error) { 875 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 876 ifp->if_timer = 0; 877 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 878 } 879 return (error); 880 } 881 882 static int 883 emac_add_rxbuf(struct emac_softc *sc, int idx) 884 { 885 struct emac_rxsoft *rxs = &sc->sc_rxsoft[idx]; 886 struct mbuf *m; 887 int error; 888 889 MGETHDR(m, M_DONTWAIT, MT_DATA); 890 if (m == NULL) 891 return (ENOBUFS); 892 893 MCLGET(m, M_DONTWAIT); 894 if ((m->m_flags & M_EXT) == 0) { 895 m_freem(m); 896 return (ENOBUFS); 897 } 898 899 if (rxs->rxs_mbuf != NULL) 900 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 901 902 rxs->rxs_mbuf = m; 903 904 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 905 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 906 if (error) { 907 printf("%s: can't load rx DMA map %d, error = %d\n", 908 sc->sc_dev.dv_xname, idx, error); 909 panic("emac_add_rxbuf"); /* XXX */ 910 } 911 912 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 913 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 914 915 EMAC_INIT_RXDESC(sc, idx); 916 917 return (0); 918 } 919 920 /* ifnet interface function */ 921 static void 922 emac_watchdog(struct ifnet *ifp) 923 { 924 struct emac_softc *sc = ifp->if_softc; 925 926 /* 927 * Since we're not interrupting every packet, sweep 928 * up before we report an error. 929 */ 930 emac_txreap(sc); 931 932 if (sc->sc_txfree != EMAC_NTXDESC) { 933 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 934 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 935 sc->sc_txnext); 936 ifp->if_oerrors++; 937 938 /* Reset the interface. */ 939 (void)emac_init(ifp); 940 } else if (ifp->if_flags & IFF_DEBUG) 941 printf("%s: recovered from device timeout\n", 942 sc->sc_dev.dv_xname); 943 944 /* try to get more packets going */ 945 emac_start(ifp); 946 } 947 948 static void 949 emac_rxdrain(struct emac_softc *sc) 950 { 951 struct emac_rxsoft *rxs; 952 int i; 953 954 for (i = 0; i < EMAC_NRXDESC; i++) { 955 rxs = &sc->sc_rxsoft[i]; 956 if (rxs->rxs_mbuf != NULL) { 957 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 958 m_freem(rxs->rxs_mbuf); 959 rxs->rxs_mbuf = NULL; 960 } 961 } 962 } 963 964 /* ifnet interface function */ 965 static void 966 emac_stop(struct ifnet *ifp, int disable) 967 { 968 struct emac_softc *sc = ifp->if_softc; 969 struct emac_txsoft *txs; 970 int i; 971 972 /* Stop the one second clock. */ 973 callout_stop(&sc->sc_callout); 974 975 /* Down the MII */ 976 mii_down(&sc->sc_mii); 977 978 /* Disable interrupts. */ 979 #if 0 /* Can't disable MAL interrupts without a reset... */ 980 EMAC_WRITE(sc, EMAC_ISER, 0); 981 #endif 982 mtdcr(DCR_MAL0_IER, 0); 983 984 /* Disable the receive and transmit channels. */ 985 mtdcr(DCR_MAL0_RXCARR, MAL0_RXCARR_CHAN0); 986 mtdcr(DCR_MAL0_TXCARR, MAL0_TXCARR_CHAN0 | MAL0_TXCARR_CHAN1); 987 988 /* Disable the transmit enable and receive MACs. */ 989 EMAC_WRITE(sc, EMAC_MR0, 990 EMAC_READ(sc, EMAC_MR0) & ~(MR0_TXE | MR0_RXE)); 991 992 /* Release any queued transmit buffers. */ 993 for (i = 0; i < EMAC_TXQUEUELEN; i++) { 994 txs = &sc->sc_txsoft[i]; 995 if (txs->txs_mbuf != NULL) { 996 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 997 m_freem(txs->txs_mbuf); 998 txs->txs_mbuf = NULL; 999 } 1000 } 1001 1002 if (disable) 1003 emac_rxdrain(sc); 1004 1005 /* 1006 * Mark the interface down and cancel the watchdog timer. 1007 */ 1008 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1009 ifp->if_timer = 0; 1010 } 1011 1012 /* ifnet interface function */ 1013 static int 1014 emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1015 { 1016 struct emac_softc *sc = ifp->if_softc; 1017 int s, error; 1018 1019 s = splnet(); 1020 1021 error = ether_ioctl(ifp, cmd, data); 1022 if (error == ENETRESET) { 1023 /* 1024 * Multicast list has changed; set the hardware filter 1025 * accordingly. 1026 */ 1027 if (ifp->if_flags & IFF_RUNNING) 1028 error = emac_set_filter(sc); 1029 else 1030 error = 0; 1031 } 1032 1033 /* try to get more packets going */ 1034 emac_start(ifp); 1035 1036 splx(s); 1037 return (error); 1038 } 1039 1040 static void 1041 emac_reset(struct emac_softc *sc) 1042 { 1043 1044 /* reset the MAL */ 1045 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR); 1046 1047 EMAC_WRITE(sc, EMAC_MR0, MR0_SRST); 1048 delay(5); 1049 1050 /* XXX: check if MR0_SRST is clear until a timeout instead? */ 1051 EMAC_WRITE(sc, EMAC_MR0, EMAC_READ(sc, EMAC_MR0) & ~MR0_SRST); 1052 1053 /* XXX clear interrupts in EMAC_ISR just to be sure?? */ 1054 1055 /* set the MAL config register */ 1056 mtdcr(DCR_MAL0_CFG, MAL0_CFG_PLBB | MAL0_CFG_OPBBL | MAL0_CFG_LEA | 1057 MAL0_CFG_SD | MAL0_CFG_PLBLT); 1058 } 1059 1060 static int 1061 emac_set_filter(struct emac_softc *sc) 1062 { 1063 struct ether_multistep step; 1064 struct ether_multi *enm; 1065 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1066 uint32_t rmr, crc, gaht[4] = {0, 0, 0, 0}; 1067 int category, cnt = 0; 1068 1069 rmr = EMAC_READ(sc, EMAC_RMR); 1070 rmr &= ~(RMR_PMME | RMR_MAE); 1071 ifp->if_flags &= ~IFF_ALLMULTI; 1072 1073 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1074 while (enm != NULL) { 1075 if (memcmp(enm->enm_addrlo, 1076 enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1077 /* 1078 * We must listen to a range of multicast addresses. 1079 * For now, just accept all multicasts, rather than 1080 * trying to set only those filter bits needed to match 1081 * the range. (At this time, the only use of address 1082 * ranges is for IP multicast routing, for which the 1083 * range is big enough to require all bits set.) 1084 */ 1085 gaht[0] = gaht[1] = gaht[2] = gaht[3] = 0xffff; 1086 break; 1087 } 1088 1089 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1090 1091 /* Just want the 6 most significant bits. */ 1092 category = crc >> 26; 1093 EMAC_SET_FILTER(gaht, category); 1094 1095 ETHER_NEXT_MULTI(step, enm); 1096 cnt++; 1097 } 1098 1099 if ((gaht[0] & gaht[1] & gaht[2] & gaht[3]) == 0xffff) { 1100 /* All categories are true. */ 1101 ifp->if_flags |= IFF_ALLMULTI; 1102 rmr |= RMR_PMME; 1103 } else if (cnt != 0) { 1104 /* Some categories are true. */ 1105 EMAC_WRITE(sc, EMAC_GAHT1, gaht[0]); 1106 EMAC_WRITE(sc, EMAC_GAHT2, gaht[1]); 1107 EMAC_WRITE(sc, EMAC_GAHT3, gaht[2]); 1108 EMAC_WRITE(sc, EMAC_GAHT4, gaht[3]); 1109 1110 rmr |= RMR_MAE; 1111 } 1112 EMAC_WRITE(sc, EMAC_RMR, rmr); 1113 1114 return 0; 1115 } 1116 1117 /* 1118 * EMAC General interrupt handler 1119 */ 1120 static int 1121 emac_intr(void *arg) 1122 { 1123 struct emac_softc *sc = arg; 1124 uint32_t status; 1125 1126 EMAC_EVCNT_INCR(&sc->sc_ev_intr); 1127 status = EMAC_READ(sc, EMAC_ISR); 1128 1129 /* Clear the interrupt status bits. */ 1130 EMAC_WRITE(sc, EMAC_ISR, status); 1131 1132 return (0); 1133 } 1134 1135 /* 1136 * EMAC Wake-On-LAN interrupt handler 1137 */ 1138 static int 1139 emac_wol_intr(void *arg) 1140 { 1141 struct emac_softc *sc = arg; 1142 1143 EMAC_EVCNT_INCR(&sc->sc_ev_wol); 1144 printf("%s: emac_wol_intr\n", sc->sc_dev.dv_xname); 1145 return (0); 1146 } 1147 1148 /* 1149 * MAL System ERRor interrupt handler 1150 */ 1151 static int 1152 emac_serr_intr(void *arg) 1153 { 1154 #ifdef EMAC_EVENT_COUNTERS 1155 struct emac_softc *sc = arg; 1156 #endif 1157 u_int32_t esr; 1158 1159 EMAC_EVCNT_INCR(&sc->sc_ev_serr); 1160 esr = mfdcr(DCR_MAL0_ESR); 1161 1162 /* Clear the interrupt status bits. */ 1163 mtdcr(DCR_MAL0_ESR, esr); 1164 return (0); 1165 } 1166 1167 /* 1168 * MAL Transmit End-Of-Buffer interrupt handler. 1169 * NOTE: This shouldn't be called! 1170 */ 1171 static int 1172 emac_txeob_intr(void *arg) 1173 { 1174 struct emac_softc *sc = arg; 1175 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1176 int handled; 1177 1178 EMAC_EVCNT_INCR(&sc->sc_ev_txintr); 1179 handled = emac_txreap(arg); 1180 1181 /* try to get more packets going */ 1182 emac_start(ifp); 1183 1184 return (handled); 1185 1186 } 1187 1188 /* 1189 * Reap completed Tx descriptors. 1190 */ 1191 static int 1192 emac_txreap(struct emac_softc *sc) 1193 { 1194 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1195 struct emac_txsoft *txs; 1196 int handled, i; 1197 u_int32_t txstat; 1198 1199 EMAC_EVCNT_INCR(&sc->sc_ev_txreap); 1200 handled = 0; 1201 1202 /* Clear the interrupt */ 1203 mtdcr(DCR_MAL0_TXEOBISR, mfdcr(DCR_MAL0_TXEOBISR)); 1204 1205 ifp->if_flags &= ~IFF_OACTIVE; 1206 1207 /* 1208 * Go through our Tx list and free mbufs for those 1209 * frames that have been transmitted. 1210 */ 1211 for (i = sc->sc_txsdirty; sc->sc_txsfree != EMAC_TXQUEUELEN; 1212 i = EMAC_NEXTTXS(i), sc->sc_txsfree++) { 1213 txs = &sc->sc_txsoft[i]; 1214 1215 EMAC_CDTXSYNC(sc, txs->txs_lastdesc, 1216 txs->txs_dmamap->dm_nsegs, 1217 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1218 1219 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; 1220 if (txstat & MAL_TX_READY) 1221 break; 1222 1223 handled = 1; 1224 1225 /* 1226 * Check for errors and collisions. 1227 */ 1228 if (txstat & (EMAC_TXS_UR | EMAC_TXS_ED)) 1229 ifp->if_oerrors++; 1230 1231 #ifdef EMAC_EVENT_COUNTERS 1232 if (txstat & EMAC_TXS_UR) 1233 EMAC_EVCNT_INCR(&sc->sc_ev_tu); 1234 #endif /* EMAC_EVENT_COUNTERS */ 1235 1236 if (txstat & (EMAC_TXS_EC | EMAC_TXS_MC | EMAC_TXS_SC | EMAC_TXS_LC)) { 1237 if (txstat & EMAC_TXS_EC) 1238 ifp->if_collisions += 16; 1239 else if (txstat & EMAC_TXS_MC) 1240 ifp->if_collisions += 2; /* XXX? */ 1241 else if (txstat & EMAC_TXS_SC) 1242 ifp->if_collisions++; 1243 if (txstat & EMAC_TXS_LC) 1244 ifp->if_collisions++; 1245 } else 1246 ifp->if_opackets++; 1247 1248 if (ifp->if_flags & IFF_DEBUG) { 1249 if (txstat & EMAC_TXS_ED) 1250 printf("%s: excessive deferral\n", 1251 sc->sc_dev.dv_xname); 1252 if (txstat & EMAC_TXS_EC) 1253 printf("%s: excessive collisions\n", 1254 sc->sc_dev.dv_xname); 1255 } 1256 1257 sc->sc_txfree += txs->txs_ndesc; 1258 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1259 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1260 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1261 m_freem(txs->txs_mbuf); 1262 txs->txs_mbuf = NULL; 1263 } 1264 1265 /* Update the dirty transmit buffer pointer. */ 1266 sc->sc_txsdirty = i; 1267 1268 /* 1269 * If there are no more pending transmissions, cancel the watchdog 1270 * timer. 1271 */ 1272 if (sc->sc_txsfree == EMAC_TXQUEUELEN) 1273 ifp->if_timer = 0; 1274 1275 return (handled); 1276 } 1277 1278 /* 1279 * MAL Receive End-Of-Buffer interrupt handler 1280 */ 1281 static int 1282 emac_rxeob_intr(void *arg) 1283 { 1284 struct emac_softc *sc = arg; 1285 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1286 struct emac_rxsoft *rxs; 1287 struct mbuf *m; 1288 u_int32_t rxstat; 1289 int i, len; 1290 1291 EMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 1292 1293 /* Clear the interrupt */ 1294 mtdcr(DCR_MAL0_RXEOBISR, mfdcr(DCR_MAL0_RXEOBISR)); 1295 1296 for (i = sc->sc_rxptr;; i = EMAC_NEXTRX(i)) { 1297 rxs = &sc->sc_rxsoft[i]; 1298 1299 EMAC_CDRXSYNC(sc, i, 1300 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1301 1302 rxstat = sc->sc_rxdescs[i].md_stat_ctrl; 1303 1304 if (rxstat & MAL_RX_EMPTY) 1305 /* 1306 * We have processed all of the receive buffers. 1307 */ 1308 break; 1309 1310 /* 1311 * If an error occurred, update stats, clear the status 1312 * word, and leave the packet buffer in place. It will 1313 * simply be reused the next time the ring comes around. 1314 */ 1315 if (rxstat & (EMAC_RXS_OE | EMAC_RXS_BP | EMAC_RXS_SE | 1316 EMAC_RXS_AE | EMAC_RXS_BFCS | EMAC_RXS_PTL | EMAC_RXS_ORE | 1317 EMAC_RXS_IRE)) { 1318 #define PRINTERR(bit, str) \ 1319 if (rxstat & (bit)) \ 1320 printf("%s: receive error: %s\n", \ 1321 sc->sc_dev.dv_xname, str) 1322 ifp->if_ierrors++; 1323 PRINTERR(EMAC_RXS_OE, "overrun error"); 1324 PRINTERR(EMAC_RXS_BP, "bad packet"); 1325 PRINTERR(EMAC_RXS_RP, "runt packet"); 1326 PRINTERR(EMAC_RXS_SE, "short event"); 1327 PRINTERR(EMAC_RXS_AE, "alignment error"); 1328 PRINTERR(EMAC_RXS_BFCS, "bad FCS"); 1329 PRINTERR(EMAC_RXS_PTL, "packet too long"); 1330 PRINTERR(EMAC_RXS_ORE, "out of range error"); 1331 PRINTERR(EMAC_RXS_IRE, "in range error"); 1332 #undef PRINTERR 1333 EMAC_INIT_RXDESC(sc, i); 1334 continue; 1335 } 1336 1337 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1338 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1339 1340 /* 1341 * No errors; receive the packet. Note, the 405GP emac 1342 * includes the CRC with every packet. 1343 */ 1344 len = sc->sc_rxdescs[i].md_data_len - ETHER_CRC_LEN; 1345 1346 /* 1347 * If the packet is small enough to fit in a 1348 * single header mbuf, allocate one and copy 1349 * the data into it. This greatly reduces 1350 * memory consumption when we receive lots 1351 * of small packets. 1352 * 1353 * Otherwise, we add a new buffer to the receive 1354 * chain. If this fails, we drop the packet and 1355 * recycle the old buffer. 1356 */ 1357 if (emac_copy_small != 0 && len <= MHLEN) { 1358 MGETHDR(m, M_DONTWAIT, MT_DATA); 1359 if (m == NULL) 1360 goto dropit; 1361 memcpy(mtod(m, void *), 1362 mtod(rxs->rxs_mbuf, void *), len); 1363 EMAC_INIT_RXDESC(sc, i); 1364 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1365 rxs->rxs_dmamap->dm_mapsize, 1366 BUS_DMASYNC_PREREAD); 1367 } else { 1368 m = rxs->rxs_mbuf; 1369 if (emac_add_rxbuf(sc, i) != 0) { 1370 dropit: 1371 ifp->if_ierrors++; 1372 EMAC_INIT_RXDESC(sc, i); 1373 bus_dmamap_sync(sc->sc_dmat, 1374 rxs->rxs_dmamap, 0, 1375 rxs->rxs_dmamap->dm_mapsize, 1376 BUS_DMASYNC_PREREAD); 1377 continue; 1378 } 1379 } 1380 1381 ifp->if_ipackets++; 1382 m->m_pkthdr.rcvif = ifp; 1383 m->m_pkthdr.len = m->m_len = len; 1384 1385 #if NBPFILTER > 0 1386 /* 1387 * Pass this up to any BPF listeners, but only 1388 * pass if up the stack if it's for us. 1389 */ 1390 if (ifp->if_bpf) 1391 bpf_mtap(ifp->if_bpf, m); 1392 #endif /* NBPFILTER > 0 */ 1393 1394 /* Pass it on. */ 1395 (*ifp->if_input)(ifp, m); 1396 } 1397 1398 /* Update the receive pointer. */ 1399 sc->sc_rxptr = i; 1400 1401 return (0); 1402 } 1403 1404 /* 1405 * MAL Transmit Descriptor Error interrupt handler 1406 */ 1407 static int 1408 emac_txde_intr(void *arg) 1409 { 1410 struct emac_softc *sc = arg; 1411 1412 EMAC_EVCNT_INCR(&sc->sc_ev_txde); 1413 printf("%s: emac_txde_intr\n", sc->sc_dev.dv_xname); 1414 return (0); 1415 } 1416 1417 /* 1418 * MAL Receive Descriptor Error interrupt handler 1419 */ 1420 static int 1421 emac_rxde_intr(void *arg) 1422 { 1423 int i; 1424 struct emac_softc *sc = arg; 1425 1426 EMAC_EVCNT_INCR(&sc->sc_ev_rxde); 1427 printf("%s: emac_rxde_intr\n", sc->sc_dev.dv_xname); 1428 /* 1429 * XXX! 1430 * This is a bit drastic; we just drop all descriptors that aren't 1431 * "clean". We should probably send any that are up the stack. 1432 */ 1433 for (i = 0; i < EMAC_NRXDESC; i++) { 1434 EMAC_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1435 1436 if (sc->sc_rxdescs[i].md_data_len != MCLBYTES) { 1437 EMAC_INIT_RXDESC(sc, i); 1438 } 1439 1440 } 1441 1442 /* Reenable the receive channel */ 1443 mtdcr(DCR_MAL0_RXCASR, MAL0_RXCASR_CHAN0); 1444 1445 /* Clear the interrupt */ 1446 mtdcr(DCR_MAL0_RXDEIR, mfdcr(DCR_MAL0_RXDEIR)); 1447 1448 return (0); 1449 } 1450 1451 static uint32_t 1452 emac_mii_wait(struct emac_softc *sc) 1453 { 1454 int i; 1455 uint32_t reg; 1456 1457 /* wait for PHY data transfer to complete */ 1458 i = 0; 1459 while ((reg = EMAC_READ(sc, EMAC_STACR) & STACR_OC) == 0) { 1460 delay(7); 1461 if (i++ > 5) { 1462 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1463 return (0); 1464 } 1465 } 1466 return (reg); 1467 } 1468 1469 static int 1470 emac_mii_readreg(struct device *self, int phy, int reg) 1471 { 1472 struct emac_softc *sc = (struct emac_softc *)self; 1473 uint32_t sta_reg; 1474 1475 /* wait for PHY data transfer to complete */ 1476 if (emac_mii_wait(sc) == 0) 1477 return (0); 1478 1479 sta_reg = reg << STACR_PRASHIFT; 1480 sta_reg |= STACR_READ; 1481 sta_reg |= phy << STACR_PCDASHIFT; 1482 1483 sta_reg &= ~STACR_OPBC_MASK; 1484 sta_reg |= STACR_OPBC_50MHZ; 1485 1486 1487 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1488 1489 if ((sta_reg = emac_mii_wait(sc)) == 0) 1490 return (0); 1491 sta_reg = EMAC_READ(sc, EMAC_STACR); 1492 if ((sta_reg & STACR_PHYE) != 0) 1493 return (0); 1494 return (sta_reg >> STACR_PHYDSHIFT); 1495 } 1496 1497 static void 1498 emac_mii_writereg(struct device *self, int phy, int reg, int val) 1499 { 1500 struct emac_softc *sc = (struct emac_softc *)self; 1501 uint32_t sta_reg; 1502 1503 /* wait for PHY data transfer to complete */ 1504 if (emac_mii_wait(sc) == 0) 1505 return; 1506 1507 sta_reg = reg << STACR_PRASHIFT; 1508 sta_reg |= STACR_WRITE; 1509 sta_reg |= phy << STACR_PCDASHIFT; 1510 1511 sta_reg &= ~STACR_OPBC_MASK; 1512 sta_reg |= STACR_OPBC_50MHZ; 1513 1514 sta_reg |= val << STACR_PHYDSHIFT; 1515 1516 EMAC_WRITE(sc, EMAC_STACR, sta_reg); 1517 1518 if ((sta_reg = emac_mii_wait(sc)) == 0) 1519 return; 1520 if ((sta_reg & STACR_PHYE) != 0) 1521 /* error */ 1522 return; 1523 } 1524 1525 static void 1526 emac_mii_statchg(struct device *self) 1527 { 1528 struct emac_softc *sc = (void *)self; 1529 1530 if (sc->sc_mii.mii_media_active & IFM_FDX) 1531 sc->sc_mr1 |= MR1_FDE; 1532 else 1533 sc->sc_mr1 &= ~(MR1_FDE | MR1_EIFC); 1534 1535 /* XXX 802.1x flow-control? */ 1536 1537 /* 1538 * MR1 can only be written immediately after a reset... 1539 */ 1540 emac_reset(sc); 1541 } 1542 1543 static void 1544 emac_mii_tick(void *arg) 1545 { 1546 struct emac_softc *sc = arg; 1547 int s; 1548 1549 if (!device_is_active(&sc->sc_dev)) 1550 return; 1551 1552 s = splnet(); 1553 mii_tick(&sc->sc_mii); 1554 splx(s); 1555 1556 callout_reset(&sc->sc_callout, hz, emac_mii_tick, sc); 1557 } 1558
Indexes created Mon Sep 29 21:09:56 GMT 2025