ibm40x_machdep.c revision 1.2 1 1.2 pk /* $NetBSD: ibm40x_machdep.c,v 1.2 2003/12/30 12:33:19 pk Exp $ */
2 1.1 shige
3 1.1 shige /*
4 1.1 shige * Copyright 2001, 2002 Wasabi Systems, Inc.
5 1.1 shige * All rights reserved.
6 1.1 shige *
7 1.1 shige * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 1.1 shige *
9 1.1 shige * Redistribution and use in source and binary forms, with or without
10 1.1 shige * modification, are permitted provided that the following conditions
11 1.1 shige * are met:
12 1.1 shige * 1. Redistributions of source code must retain the above copyright
13 1.1 shige * notice, this list of conditions and the following disclaimer.
14 1.1 shige * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 shige * notice, this list of conditions and the following disclaimer in the
16 1.1 shige * documentation and/or other materials provided with the distribution.
17 1.1 shige * 3. All advertising materials mentioning features or use of this software
18 1.1 shige * must display the following acknowledgement:
19 1.1 shige * This product includes software developed for the NetBSD Project by
20 1.1 shige * Wasabi Systems, Inc.
21 1.1 shige * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1 shige * or promote products derived from this software without specific prior
23 1.1 shige * written permission.
24 1.1 shige *
25 1.1 shige * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1 shige * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 shige * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 shige * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1 shige * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 shige * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 shige * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 shige * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 shige * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 shige * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 shige * POSSIBILITY OF SUCH DAMAGE.
36 1.1 shige */
37 1.1 shige
38 1.1 shige /*
39 1.1 shige * Copyright (C) 1995, 1996 Wolfgang Solfrank.
40 1.1 shige * Copyright (C) 1995, 1996 TooLs GmbH.
41 1.1 shige * All rights reserved.
42 1.1 shige *
43 1.1 shige * Redistribution and use in source and binary forms, with or without
44 1.1 shige * modification, are permitted provided that the following conditions
45 1.1 shige * are met:
46 1.1 shige * 1. Redistributions of source code must retain the above copyright
47 1.1 shige * notice, this list of conditions and the following disclaimer.
48 1.1 shige * 2. Redistributions in binary form must reproduce the above copyright
49 1.1 shige * notice, this list of conditions and the following disclaimer in the
50 1.1 shige * documentation and/or other materials provided with the distribution.
51 1.1 shige * 3. All advertising materials mentioning features or use of this software
52 1.1 shige * must display the following acknowledgement:
53 1.1 shige * This product includes software developed by TooLs GmbH.
54 1.1 shige * 4. The name of TooLs GmbH may not be used to endorse or promote products
55 1.1 shige * derived from this software without specific prior written permission.
56 1.1 shige *
57 1.1 shige * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
58 1.1 shige * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
59 1.1 shige * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
60 1.1 shige * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
61 1.1 shige * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
62 1.1 shige * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
63 1.1 shige * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
64 1.1 shige * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
65 1.1 shige * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
66 1.1 shige * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 1.1 shige */
68 1.1 shige
69 1.1 shige #include <sys/cdefs.h>
70 1.2 pk __KERNEL_RCSID(0, "$NetBSD: ibm40x_machdep.c,v 1.2 2003/12/30 12:33:19 pk Exp $");
71 1.1 shige
72 1.1 shige #include "opt_compat_netbsd.h"
73 1.1 shige #include "opt_ddb.h"
74 1.1 shige #include "opt_kgdb.h"
75 1.1 shige #include "opt_ipkdb.h"
76 1.1 shige
77 1.1 shige #include <sys/param.h>
78 1.1 shige #include <sys/buf.h>
79 1.1 shige #include <sys/exec.h>
80 1.1 shige #include <sys/malloc.h>
81 1.1 shige #include <sys/mbuf.h>
82 1.1 shige #include <sys/mount.h>
83 1.1 shige #include <sys/msgbuf.h>
84 1.1 shige #include <sys/proc.h>
85 1.1 shige #include <sys/reboot.h>
86 1.1 shige #include <sys/sa.h>
87 1.1 shige #include <sys/syscallargs.h>
88 1.1 shige #include <sys/syslog.h>
89 1.1 shige #include <sys/systm.h>
90 1.1 shige #include <sys/kernel.h>
91 1.1 shige #include <sys/user.h>
92 1.1 shige #include <sys/boot_flag.h>
93 1.1 shige #include <sys/properties.h>
94 1.1 shige #include <sys/ksyms.h>
95 1.1 shige
96 1.1 shige #include <uvm/uvm_extern.h>
97 1.1 shige
98 1.1 shige #include <net/netisr.h>
99 1.1 shige
100 1.1 shige #if defined(DDB)
101 1.1 shige #include <machine/db_machdep.h>
102 1.1 shige #include <ddb/db_extern.h>
103 1.1 shige #endif
104 1.1 shige
105 1.1 shige #if defined(KGDB)
106 1.1 shige #include <sys/kgdb.h>
107 1.1 shige #endif
108 1.1 shige
109 1.1 shige #if defined(IPKDB)
110 1.1 shige #include <ipkdb/ipkdb.h>
111 1.1 shige #endif
112 1.1 shige
113 1.1 shige #include <machine/bus.h>
114 1.1 shige #include <machine/trap.h>
115 1.1 shige #include <machine/powerpc.h>
116 1.1 shige #include <powerpc/spr.h>
117 1.1 shige #include <powerpc/ibm4xx/dcr405gp.h>
118 1.1 shige
119 1.1 shige /*
120 1.1 shige * Global variables used here and there
121 1.1 shige */
122 1.1 shige struct vm_map *exec_map = NULL;
123 1.1 shige struct vm_map *mb_map = NULL;
124 1.1 shige struct vm_map *phys_map = NULL;
125 1.1 shige
126 1.1 shige char machine[] = MACHINE; /* from <machine/param.h> */
127 1.1 shige char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
128 1.1 shige
129 1.1 shige #define MEMREGIONS 8
130 1.1 shige struct mem_region physmemr[MEMREGIONS]; /* Hard code memory */
131 1.1 shige struct mem_region availmemr[MEMREGIONS];/* Who's supposed to set these up? */
132 1.1 shige
133 1.1 shige struct board_cfg_data board_data;
134 1.1 shige struct propdb *board_info = NULL;
135 1.1 shige
136 1.1 shige extern struct user *proc0paddr;
137 1.1 shige
138 1.1 shige paddr_t msgbuf_paddr;
139 1.1 shige vaddr_t msgbuf_vaddr;
140 1.1 shige
141 1.1 shige
142 1.1 shige void
143 1.1 shige ibm4xx_init_board_data(void *info_block, u_int startkernel)
144 1.1 shige {
145 1.1 shige /* Initialize cache info for memcpy, etc. */
146 1.1 shige cpu_probe_cache();
147 1.1 shige
148 1.1 shige /* Save info block */
149 1.1 shige memcpy(&board_data, info_block, sizeof(board_data));
150 1.1 shige
151 1.1 shige memset(physmemr, 0, sizeof physmemr);
152 1.1 shige memset(availmemr, 0, sizeof availmemr);
153 1.1 shige physmemr[0].start = 0;
154 1.1 shige physmemr[0].size = board_data.mem_size & ~PGOFSET;
155 1.1 shige /* Lower memory reserved by eval board BIOS */
156 1.1 shige availmemr[0].start = startkernel;
157 1.1 shige availmemr[0].size = board_data.mem_size - availmemr[0].start;
158 1.1 shige }
159 1.1 shige
160 1.1 shige void
161 1.1 shige ibm4xx_init(void (*handler)(void))
162 1.1 shige {
163 1.1 shige extern int defaulttrap, defaultsize;
164 1.1 shige extern int sctrap, scsize;
165 1.1 shige extern int alitrap, alisize;
166 1.1 shige extern int dsitrap, dsisize;
167 1.1 shige extern int isitrap, isisize;
168 1.1 shige extern int mchktrap, mchksize;
169 1.1 shige extern int tlbimiss4xx, tlbim4size;
170 1.1 shige extern int tlbdmiss4xx, tlbdm4size;
171 1.1 shige extern int pitfitwdog, pitfitwdogsize;
172 1.1 shige extern int debugtrap, debugsize;
173 1.1 shige extern int errata51handler, errata51size;
174 1.1 shige #ifdef DDB
175 1.1 shige extern int ddblow, ddbsize;
176 1.1 shige #endif
177 1.1 shige #ifdef IPKDB
178 1.1 shige extern int ipkdblow, ipkdbsize;
179 1.1 shige #endif
180 1.1 shige uintptr_t exc;
181 1.1 shige struct cpu_info * const ci = curcpu();
182 1.1 shige
183 1.1 shige /* Initialize cache info for memcpy, etc. */
184 1.1 shige cpu_probe_cache();
185 1.1 shige
186 1.1 shige /*
187 1.1 shige * Initialize lwp0 and current pcb and pmap pointers.
188 1.1 shige */
189 1.1 shige KASSERT(ci != NULL);
190 1.1 shige KASSERT(curcpu() == ci);
191 1.1 shige lwp0.l_cpu = ci;
192 1.1 shige lwp0.l_addr = proc0paddr;
193 1.1 shige memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr);
194 1.1 shige KASSERT(lwp0.l_cpu != NULL);
195 1.1 shige
196 1.1 shige curpcb = &proc0paddr->u_pcb;
197 1.1 shige memset(curpcb, 0, sizeof(*curpcb));
198 1.1 shige curpcb->pcb_pm = pmap_kernel();
199 1.1 shige
200 1.1 shige /*
201 1.1 shige * Set up trap vectors
202 1.1 shige */
203 1.1 shige for (exc = EXC_RSVD; exc <= EXC_LAST; exc += 0x100)
204 1.1 shige switch (exc) {
205 1.1 shige default:
206 1.1 shige memcpy((void *)exc, &defaulttrap, (size_t)&defaultsize);
207 1.1 shige break;
208 1.1 shige case EXC_EXI:
209 1.1 shige /*
210 1.1 shige * This one is (potentially) installed during autoconf
211 1.1 shige */
212 1.1 shige break;
213 1.1 shige case EXC_SC:
214 1.1 shige memcpy((void *)EXC_SC, &sctrap, (size_t)&scsize);
215 1.1 shige break;
216 1.1 shige case EXC_ALI:
217 1.1 shige memcpy((void *)EXC_ALI, &alitrap, (size_t)&alisize);
218 1.1 shige break;
219 1.1 shige case EXC_DSI:
220 1.1 shige memcpy((void *)EXC_DSI, &dsitrap, (size_t)&dsisize);
221 1.1 shige break;
222 1.1 shige case EXC_ISI:
223 1.1 shige memcpy((void *)EXC_ISI, &isitrap, (size_t)&isisize);
224 1.1 shige break;
225 1.1 shige case EXC_MCHK:
226 1.1 shige memcpy((void *)EXC_MCHK, &mchktrap, (size_t)&mchksize);
227 1.1 shige break;
228 1.1 shige case EXC_ITMISS:
229 1.1 shige memcpy((void *)EXC_ITMISS, &tlbimiss4xx,
230 1.1 shige (size_t)&tlbim4size);
231 1.1 shige break;
232 1.1 shige case EXC_DTMISS:
233 1.1 shige memcpy((void *)EXC_DTMISS, &tlbdmiss4xx,
234 1.1 shige (size_t)&tlbdm4size);
235 1.1 shige break;
236 1.1 shige /*
237 1.1 shige * EXC_PIT, EXC_FIT, EXC_WDOG handlers
238 1.1 shige * are spaced by 0x10 bytes only..
239 1.1 shige */
240 1.1 shige case EXC_PIT:
241 1.1 shige memcpy((void *)EXC_PIT, &pitfitwdog,
242 1.1 shige (size_t)&pitfitwdogsize);
243 1.1 shige break;
244 1.1 shige case EXC_DEBUG:
245 1.1 shige memcpy((void *)EXC_DEBUG, &debugtrap,
246 1.1 shige (size_t)&debugsize);
247 1.1 shige break;
248 1.1 shige case EXC_DTMISS|EXC_ALI:
249 1.1 shige /* PPC405GP Rev D errata item 51 */
250 1.1 shige memcpy((void *)(EXC_DTMISS|EXC_ALI), &errata51handler,
251 1.1 shige (size_t)&errata51size);
252 1.1 shige break;
253 1.1 shige #if defined(DDB) || defined(IPKDB)
254 1.1 shige case EXC_PGM:
255 1.1 shige #if defined(DDB)
256 1.1 shige memcpy((void *)exc, &ddblow, (size_t)&ddbsize);
257 1.1 shige #elif defined(IPKDB)
258 1.1 shige memcpy((void *)exc, &ipkdblow, (size_t)&ipkdbsize);
259 1.1 shige #endif
260 1.1 shige #endif /* DDB | IPKDB */
261 1.1 shige break;
262 1.1 shige }
263 1.1 shige
264 1.1 shige __syncicache((void *)EXC_RST, EXC_LAST - EXC_RST + 0x100);
265 1.1 shige mtspr(SPR_EVPR, 0); /* Set Exception vector base */
266 1.1 shige
267 1.1 shige consinit();
268 1.1 shige
269 1.1 shige /* Handle trap instruction as PGM exception */
270 1.1 shige {
271 1.1 shige int dbcr0;
272 1.1 shige asm volatile("mfspr %0,%1":"=r"(dbcr0):"K"(SPR_DBCR0));
273 1.1 shige asm volatile("mtspr %0,%1"::"K"(SPR_DBCR0),"r"(dbcr0 & ~DBCR0_TDE));
274 1.1 shige }
275 1.1 shige
276 1.1 shige /*
277 1.1 shige * external interrupt handler install
278 1.1 shige */
279 1.1 shige if (handler)
280 1.1 shige ibm4xx_install_extint(handler);
281 1.1 shige
282 1.1 shige /*
283 1.1 shige * Now enable translation (and machine checks/recoverable interrupts).
284 1.1 shige */
285 1.1 shige asm volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0; isync"
286 1.1 shige : : "r"(0), "K"(PSL_IR|PSL_DR));
287 1.1 shige /* XXXX PSL_ME - With ME set kernel gets stuck... */
288 1.1 shige
289 1.1 shige KASSERT(curcpu() == ci);
290 1.1 shige }
291 1.1 shige
292 1.1 shige void
293 1.1 shige ibm4xx_install_extint(void (*handler)(void))
294 1.1 shige {
295 1.1 shige extern int extint, extsize;
296 1.1 shige extern u_long extint_call;
297 1.1 shige u_long offset = (u_long)handler - (u_long)&extint_call;
298 1.1 shige int msr;
299 1.1 shige
300 1.1 shige #ifdef DIAGNOSTIC
301 1.1 shige if (offset > 0x1ffffff)
302 1.1 shige panic("install_extint: too far away");
303 1.1 shige #endif
304 1.1 shige asm volatile ("mfmsr %0; wrteei 0" : "=r"(msr));
305 1.1 shige extint_call = (extint_call & 0xfc000003) | offset;
306 1.1 shige memcpy((void *)EXC_EXI, &extint, (size_t)&extsize);
307 1.1 shige __syncicache((void *)&extint_call, sizeof extint_call);
308 1.1 shige __syncicache((void *)EXC_EXI, (int)&extsize);
309 1.1 shige asm volatile ("mtmsr %0" :: "r"(msr));
310 1.1 shige }
311 1.1 shige
312 1.1 shige /*
313 1.1 shige * Machine dependent startup code.
314 1.1 shige */
315 1.1 shige
316 1.1 shige char msgbuf[MSGBUFSIZE];
317 1.1 shige
318 1.1 shige void
319 1.1 shige ibm4xx_startup(const char *model)
320 1.1 shige {
321 1.1 shige vaddr_t minaddr, maxaddr;
322 1.1 shige char pbuf[9];
323 1.1 shige
324 1.1 shige KASSERT(curcpu() != NULL);
325 1.1 shige KASSERT(lwp0.l_cpu != NULL);
326 1.1 shige KASSERT(curcpu()->ci_intstk != 0);
327 1.1 shige KASSERT(curcpu()->ci_intrdepth == -1);
328 1.1 shige
329 1.1 shige /*
330 1.1 shige * Initialize error message buffer (at end of core).
331 1.1 shige */
332 1.1 shige #if 0 /* For some reason this fails... --Artem
333 1.1 shige * Besides, do we really have to put it at the end of core?
334 1.1 shige * Let's use static buffer for now
335 1.1 shige */
336 1.1 shige if (!(msgbuf_vaddr = uvm_km_alloc(kernel_map, round_page(MSGBUFSIZE))))
337 1.1 shige panic("startup: no room for message buffer");
338 1.1 shige for (i = 0; i < btoc(MSGBUFSIZE); i++)
339 1.1 shige pmap_kenter_pa(msgbuf_vaddr + i * PAGE_SIZE,
340 1.1 shige msgbuf_paddr + i * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE);
341 1.1 shige initmsgbuf((caddr_t)msgbuf_vaddr, round_page(MSGBUFSIZE));
342 1.1 shige #else
343 1.1 shige initmsgbuf((caddr_t)msgbuf, round_page(MSGBUFSIZE));
344 1.1 shige #endif
345 1.1 shige
346 1.1 shige printf("%s", version);
347 1.1 shige if (model != NULL)
348 1.1 shige printf("Model: %s\n", model);
349 1.1 shige
350 1.1 shige format_bytes(pbuf, sizeof(pbuf), ctob(physmem));
351 1.1 shige printf("total memory = %s\n", pbuf);
352 1.1 shige
353 1.1 shige minaddr = 0;
354 1.1 shige /*
355 1.1 shige * Allocate a submap for exec arguments. This map effectively
356 1.1 shige * limits the number of processes exec'ing at any time.
357 1.1 shige */
358 1.1 shige exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
359 1.1 shige 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL);
360 1.1 shige
361 1.1 shige /*
362 1.1 shige * Allocate a submap for physio
363 1.1 shige */
364 1.1 shige phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
365 1.1 shige VM_PHYS_SIZE, 0, FALSE, NULL);
366 1.1 shige
367 1.1 shige /*
368 1.1 shige * No need to allocate an mbuf cluster submap. Mbuf clusters
369 1.1 shige * are allocated via the pool allocator, and we use direct-mapped
370 1.1 shige * pool pages.
371 1.1 shige */
372 1.1 shige
373 1.1 shige format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free));
374 1.1 shige printf("avail memory = %s\n", pbuf);
375 1.1 shige }
376 1.1 shige
377 1.1 shige void
378 1.1 shige ibm4xx_setup_propdb(void)
379 1.1 shige {
380 1.1 shige /*
381 1.1 shige * Set up the board properties database.
382 1.1 shige */
383 1.1 shige if (!(board_info = propdb_create("board info")))
384 1.1 shige panic("Cannot create board info database");
385 1.1 shige
386 1.1 shige if (board_info_set("mem-size", &board_data.mem_size,
387 1.1 shige sizeof(&board_data.mem_size), PROP_CONST, 0))
388 1.1 shige panic("setting mem-size");
389 1.1 shige if (board_info_set("sip0-mac-addr", &board_data.mac_address_pci,
390 1.1 shige sizeof(&board_data.mac_address_pci), PROP_CONST, 0))
391 1.1 shige panic("setting sip0-mac-addr");
392 1.1 shige if (board_info_set("processor-frequency", &board_data.processor_speed,
393 1.1 shige sizeof(&board_data.processor_speed), PROP_CONST, 0))
394 1.1 shige panic("setting processor-frequency");
395 1.1 shige }
396 1.1 shige
397 1.1 shige
398 1.1 shige /*
399 1.1 shige * Crash dump handling.
400 1.1 shige */
401 1.1 shige void
402 1.1 shige ibm4xx_dumpsys(void)
403 1.1 shige {
404 1.1 shige printf("dumpsys: TBD\n");
405 1.1 shige }
406 1.1 shige
407 1.1 shige /*
408 1.1 shige * Soft networking interrupts.
409 1.1 shige */
410 1.1 shige void
411 1.1 shige softnet(void)
412 1.1 shige {
413 1.1 shige int isr;
414 1.1 shige
415 1.1 shige isr = netisr;
416 1.1 shige netisr = 0;
417 1.1 shige
418 1.1 shige #define DONETISR(bit, fn) do { \
419 1.1 shige if (isr & (1 << bit)) \
420 1.1 shige fn(); \
421 1.1 shige } while (0)
422 1.1 shige
423 1.1 shige #include <net/netisr_dispatch.h>
424 1.1 shige
425 1.1 shige #undef DONETISR
426 1.1 shige
427 1.1 shige }
428 1.1 shige
429 1.1 shige /*
430 1.1 shige * Soft tty interrupts.
431 1.1 shige */
432 1.1 shige #include "com.h"
433 1.1 shige void
434 1.1 shige softserial(void)
435 1.1 shige {
436 1.1 shige #if NCOM > 0
437 1.1 shige void comsoft(void); /* XXX from dev/ic/com.c */
438 1.1 shige
439 1.1 shige comsoft();
440 1.1 shige #endif
441 1.1 shige }
442 1.1 shige
443 1.1 shige void
444 1.1 shige mem_regions(struct mem_region **mem, struct mem_region **avail)
445 1.1 shige {
446 1.1 shige *mem = physmemr;
447 1.1 shige *avail = availmemr;
448 1.1 shige }
449