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pchb.c revision 1.13
      1 /*	$NetBSD: pchb.c,v 1.13 2020/07/06 09:34:17 rin Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.13 2020/07/06 09:34:17 rin Exp $");
     34 
     35 #include "pci.h"
     36 
     37 #ifdef _KERNEL_OPT
     38 #include "opt_pci.h"
     39 #endif
     40 
     41 #include <sys/types.h>
     42 #include <sys/param.h>
     43 #include <sys/systm.h>
     44 #include <sys/device.h>
     45 #include <sys/extent.h>
     46 #include <sys/malloc.h>
     47 
     48 #define _IBM4XX_BUS_DMA_PRIVATE
     49 
     50 #include <powerpc/ibm4xx/ibm405gp.h>
     51 #include <powerpc/ibm4xx/pci_machdep.h>
     52 #include <powerpc/ibm4xx/dev/plbvar.h>
     53 
     54 #include <dev/pci/pcivar.h>
     55 #include <dev/pci/pcireg.h>
     56 #include <dev/pci/pcidevs.h>
     57 #include <dev/pci/pciconf.h>
     58 
     59 static int	pchbmatch(device_t, cfdata_t, void *);
     60 static void	pchbattach(device_t, device_t, void *);
     61 static int	pchbprint(void *, const char *);
     62 
     63 CFATTACH_DECL_NEW(pchb, 0,
     64     pchbmatch, pchbattach, NULL, NULL);
     65 
     66 static int pcifound = 0;
     67 
     68 /* IO window located @ e8000000 and maps to 0-0xffff */
     69 static struct powerpc_bus_space pchb_io_tag = {
     70 	_BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_IO_TYPE,
     71 	IBM405GP_PLB_PCI_IO_START,		/* offset */
     72 	IBM405GP_PCI_PCI_IO_START,		/* extent base */
     73 	IBM405GP_PCI_PCI_IO_START + 0xffff,	/* extent limit */
     74 };
     75 
     76 /* PCI memory window is directly mapped */
     77 static struct powerpc_bus_space pchb_mem_tag = {
     78 	_BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE,
     79 	0x00000000,					/* offset */
     80 	IBM405GP_PCI_MEM_START,			/* extent base */
     81 	IBM405GP_PCI_MEM_START + 0x1fffffff,	/* extent limit */
     82 };
     83 
     84 
     85 static int
     86 pchbmatch(device_t parent, cfdata_t cf, void *aux)
     87 {
     88 	struct plb_attach_args *paa = aux;
     89 	/* XXX chipset tag unused by walnut, so just pass 0 */
     90 	pci_chipset_tag_t pc = ibm4xx_get_pci_chipset_tag();
     91 	pcitag_t tag;
     92 	int class, id;
     93 
     94 	/* match only pchb devices */
     95 	if (strcmp(paa->plb_name, cf->cf_name) != 0)
     96 		return 0;
     97 
     98 	ibm4xx_pci_machdep_init();
     99 	tag = pci_make_tag(pc, 0, 0, 0);
    100 
    101 	class = pci_conf_read(pc, tag, PCI_CLASS_REG);
    102 	id = pci_conf_read(pc, tag, PCI_ID_REG);
    103 
    104 	/*
    105 	 * Match all known PCI host chipsets.
    106 	 */
    107 	if (PCI_CLASS(class) == PCI_CLASS_BRIDGE &&
    108 	    PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_HOST) {
    109 		switch (PCI_VENDOR(id)) {
    110 		case PCI_VENDOR_IBM:
    111 			switch (PCI_PRODUCT(id)) {
    112 			case PCI_PRODUCT_IBM_405GP:
    113 				return (!pcifound);
    114 			}
    115 			break;
    116 		}
    117 	}
    118 	return (0);
    119 }
    120 
    121 static void
    122 pchbattach(device_t parent, device_t self, void *aux)
    123 {
    124 	struct plb_attach_args *paa = aux;
    125 	struct pcibus_attach_args pba;
    126 	char devinfo[256];
    127 #ifdef PCI_CONFIGURE_VERBOSE
    128 	extern int pci_conf_debug;
    129 
    130 	pci_conf_debug = 1;
    131 #endif
    132 	pci_chipset_tag_t pc = ibm4xx_get_pci_chipset_tag();
    133 	pcitag_t tag;
    134 	int class, id;
    135 
    136 	ibm4xx_pci_machdep_init();
    137 	tag = pci_make_tag(pc, 0, 0, 0);
    138 
    139 	class = pci_conf_read(pc, tag, PCI_CLASS_REG);
    140 	id = pci_conf_read(pc, tag, PCI_ID_REG);
    141 
    142 	aprint_normal("\n");
    143 	pcifound++;
    144 	/*
    145 	 * All we do is print out a description.  Eventually, we
    146 	 * might want to add code that does something that's
    147 	 * possibly chipset-specific.
    148 	 */
    149 
    150 	pci_devinfo(id, class, 0, devinfo, sizeof(devinfo));
    151 	aprint_normal_dev(self, "%s (rev. 0x%02x)\n", devinfo,
    152 	    PCI_REVISION(class));
    153 
    154 	ibm4xx_pci_machdep_init(); /* Redundant... */
    155 	ibm4xx_setup_pci();
    156 #ifdef PCI_CONFIGURE_VERBOSE
    157 	ibm4xx_show_pci_map();
    158 #endif
    159 
    160 	if (bus_space_init(&pchb_io_tag, "pchbio", NULL, 0))
    161 		panic("pchbattach: can't init IO tag");
    162 	if (bus_space_init(&pchb_mem_tag, "pchbmem", NULL, 0))
    163 		panic("pchbattach: can't init MEM tag");
    164 
    165 #ifdef PCI_NETBSD_CONFIGURE
    166 	struct extent *memext = extent_create("pcimem",
    167 	    IBM405GP_PCI_MEM_START,
    168 	    IBM405GP_PCI_MEM_START + 0x1fffffff, NULL, 0,
    169 	    EX_WAITOK);
    170 	struct extent *ioext = extent_create("pciio",
    171 	    IBM405GP_PCI_PCI_IO_START,
    172 	    IBM405GP_PCI_PCI_IO_START + 0xffff, NULL, 0, EX_WAITOK);
    173 	pci_configure_bus(pc, ioext, memext, NULL, 0, 32);
    174 	extent_destroy(ioext);
    175 	extent_destroy(memext);
    176 #endif /* PCI_NETBSD_CONFIGURE */
    177 
    178 #ifdef PCI_CONFIGURE_VERBOSE
    179 	printf("running config_found PCI\n");
    180 #endif
    181 	/* IO window located @ e8000000 and maps to 0-0xffff */
    182 	pba.pba_iot = &pchb_io_tag;
    183 	/* PCI memory window is directly mapped */
    184 	pba.pba_memt = &pchb_mem_tag;
    185 	pba.pba_dmat = paa->plb_dmat;
    186 	pba.pba_dmat64 = NULL;
    187 	pba.pba_pc = pc;
    188 	pba.pba_bus = 0;
    189 	pba.pba_bridgetag = NULL;
    190 	pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
    191 	config_found_ia(self, "pcibus", &pba, pchbprint);
    192 }
    193 
    194 
    195 static int
    196 pchbprint(void *aux, const char *p)
    197 {
    198 
    199 	if (p == NULL)
    200 		return (UNCONF);
    201 	return (QUIET);
    202 }
    203 
    204 #if 0
    205 static void
    206 scan_pci_bus(void)
    207 {
    208 	pci_chipset_tag_t pc = ibm4xx_get_pci_chipset_tag();
    209 	pcitag_t tag;
    210 	int i, x;
    211 
    212 	for (i=0;i<32;i++){
    213 		tag = pci_make_tag(pc, 0, i, 0);
    214 		x = pci_conf_read(pc, tag, 0);
    215 		printf("%d tag=%08x : %08x\n", i, tag, x);
    216 #if 0
    217 		if (PCI_VENDOR(x) == PCI_VENDOR_INTEL
    218 		    && PCI_PRODUCT(x) == PCI_PRODUCT_INTEL_80960_RP) {
    219 			/* Do not configure PCI bus analyzer */
    220 			continue;
    221 		}
    222 		x = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
    223 		x |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
    224 		pci_conf_write(0, tag, PCI_COMMAND_STATUS_REG, x);
    225 #endif
    226 	}
    227 }
    228 #endif
    229