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pci_machdep.c revision 1.5.62.1
      1  1.5.62.1     yamt /*	$NetBSD: pci_machdep.c,v 1.5.62.1 2009/05/04 08:11:43 yamt Exp $	*/
      2       1.1    shige 
      3       1.1    shige /*
      4       1.1    shige  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
      5       1.1    shige  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
      6       1.1    shige  *
      7       1.1    shige  * Redistribution and use in source and binary forms, with or without
      8       1.1    shige  * modification, are permitted provided that the following conditions
      9       1.1    shige  * are met:
     10       1.1    shige  * 1. Redistributions of source code must retain the above copyright
     11       1.1    shige  *    notice, this list of conditions and the following disclaimer.
     12       1.1    shige  * 2. Redistributions in binary form must reproduce the above copyright
     13       1.1    shige  *    notice, this list of conditions and the following disclaimer in the
     14       1.1    shige  *    documentation and/or other materials provided with the distribution.
     15       1.1    shige  * 3. All advertising materials mentioning features or use of this software
     16       1.1    shige  *    must display the following acknowledgement:
     17       1.1    shige  *	This product includes software developed by Charles M. Hannum.
     18       1.1    shige  * 4. The name of the author may not be used to endorse or promote products
     19       1.1    shige  *    derived from this software without specific prior written permission.
     20       1.1    shige  *
     21       1.1    shige  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22       1.1    shige  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23       1.1    shige  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24       1.1    shige  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25       1.1    shige  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26       1.1    shige  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27       1.1    shige  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28       1.1    shige  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29       1.1    shige  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30       1.1    shige  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31       1.1    shige  */
     32       1.1    shige 
     33       1.1    shige /*
     34       1.1    shige  * Machine-specific functions for PCI autoconfiguration.
     35       1.1    shige  *
     36       1.1    shige  * On PCs, there are two methods of generating PCI configuration cycles.
     37       1.1    shige  * We try to detect the appropriate mechanism for this machine and set
     38       1.1    shige  * up a few function pointers to access the correct method directly.
     39       1.1    shige  *
     40       1.1    shige  * The configuration method can be hard-coded in the config file by
     41       1.1    shige  * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
     42       1.1    shige  * as defined section 3.6.4.1, `Generating Configuration Cycles'.
     43       1.1    shige  */
     44       1.1    shige 
     45       1.1    shige #include <sys/cdefs.h>
     46  1.5.62.1     yamt __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.5.62.1 2009/05/04 08:11:43 yamt Exp $");
     47       1.1    shige 
     48       1.1    shige #include <sys/types.h>
     49       1.1    shige #include <sys/param.h>
     50       1.1    shige #include <sys/time.h>
     51       1.1    shige #include <sys/systm.h>
     52       1.1    shige #include <sys/errno.h>
     53       1.1    shige #include <sys/device.h>
     54       1.1    shige #include <sys/extent.h>
     55       1.1    shige 
     56       1.1    shige #include <uvm/uvm_extern.h>
     57       1.1    shige 
     58       1.1    shige #include <machine/bus.h>
     59       1.1    shige #include <machine/intr.h>
     60       1.1    shige 
     61       1.1    shige #include <dev/pci/pcivar.h>
     62       1.1    shige #include <dev/pci/pcireg.h>
     63       1.1    shige #include <dev/pci/pcidevs.h>
     64       1.1    shige #include <dev/pci/pciconf.h>
     65       1.1    shige 
     66       1.1    shige #include <powerpc/ibm4xx/ibm405gp.h>
     67       1.1    shige #include <powerpc/ibm4xx/dev/pcicreg.h>
     68       1.1    shige 
     69       1.1    shige static struct powerpc_bus_space pci_iot = {
     70       1.1    shige 	_BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE,
     71       1.1    shige 	0x00000000,
     72       1.1    shige 	IBM405GP_PCIC0_BASE,		/* extent base */
     73       1.1    shige 	IBM405GP_PCIC0_BASE + 8,	/* extent limit */
     74       1.1    shige };
     75       1.1    shige 
     76       1.1    shige static bus_space_handle_t pci_ioh;
     77       1.1    shige 
     78       1.1    shige void
     79       1.1    shige pci_machdep_init(void)
     80       1.1    shige {
     81       1.1    shige 
     82       1.1    shige 	if (pci_ioh == 0 &&
     83       1.1    shige 	   (bus_space_init(&pci_iot, "pcicfg", NULL, 0) ||
     84       1.1    shige 	    bus_space_map(&pci_iot, IBM405GP_PCIC0_BASE, 8, 0, &pci_ioh)))
     85       1.1    shige 		panic("Cannot map PCI registers");
     86       1.1    shige }
     87       1.1    shige 
     88       1.1    shige void
     89       1.1    shige pci_attach_hook(struct device *parent, struct device *self,
     90       1.1    shige 		struct pcibus_attach_args *pba)
     91       1.1    shige {
     92       1.1    shige 
     93       1.1    shige #ifdef PCI_CONFIGURE_VERBOSE
     94       1.1    shige 	printf("pci_attach_hook\n");
     95       1.1    shige 	ibm4xx_show_pci_map();
     96       1.1    shige #endif
     97       1.1    shige 	ibm4xx_setup_pci();
     98       1.1    shige #ifdef PCI_CONFIGURE_VERBOSE
     99       1.1    shige 	ibm4xx_show_pci_map();
    100       1.1    shige #endif
    101       1.1    shige }
    102       1.1    shige 
    103       1.1    shige int
    104       1.1    shige pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
    105       1.1    shige {
    106       1.1    shige 
    107       1.1    shige 	/*
    108       1.1    shige 	 * Bus number is irrelevant.  Configuration Mechanism 1 is in
    109       1.1    shige 	 * use, can have devices 0-32 (i.e. the `normal' range).
    110       1.1    shige 	 */
    111       1.4    shige 	return 31;
    112       1.1    shige }
    113       1.1    shige 
    114       1.1    shige pcitag_t
    115       1.1    shige pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
    116       1.1    shige {
    117       1.1    shige 	pcitag_t tag;
    118       1.1    shige 
    119       1.1    shige 	if (bus >= 256 || device >= 32 || function >= 8)
    120       1.1    shige 		panic("pci_make_tag: bad request");
    121       1.1    shige 
    122       1.1    shige 	/* XXX magic number */
    123       1.1    shige 	tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8);
    124       1.1    shige 
    125       1.1    shige 	return tag;
    126       1.1    shige }
    127       1.1    shige 
    128       1.1    shige void
    129       1.1    shige pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
    130       1.1    shige {
    131       1.1    shige 
    132       1.1    shige 	if (bp != NULL)
    133       1.1    shige 		*bp = (tag >> 16) & 0xff;
    134       1.1    shige 	if (dp != NULL)
    135       1.1    shige 		*dp = (tag >> 11) & 0x1f;
    136       1.1    shige 	if (fp != NULL)
    137       1.1    shige 		*fp = (tag >> 8) & 0x07;
    138       1.1    shige }
    139       1.1    shige 
    140       1.1    shige pcireg_t
    141       1.1    shige pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
    142       1.1    shige {
    143       1.1    shige 	pcireg_t data;
    144       1.1    shige 
    145       1.1    shige 	/* 405GT BIOS disables interrupts here. Should we? --Art */
    146       1.1    shige 	bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);
    147       1.1    shige 	data = bus_space_read_4(&pci_iot, pci_ioh, PCIC_CFGDATA);
    148       1.1    shige 	/* 405GP pass2 errata #6 */
    149       1.1    shige 	bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0);
    150       1.1    shige 	return data;
    151       1.1    shige }
    152       1.1    shige 
    153       1.1    shige void
    154       1.1    shige pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
    155       1.1    shige {
    156       1.1    shige 
    157       1.1    shige 	bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);
    158       1.1    shige 	bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGDATA, data);
    159       1.1    shige 	/* 405GP pass2 errata #6 */
    160       1.1    shige 	bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0);
    161       1.1    shige }
    162       1.1    shige 
    163       1.1    shige const char *
    164       1.1    shige pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
    165       1.1    shige {
    166       1.1    shige 	static char irqstr[8];		/* 4 + 2 + NUL + sanity */
    167       1.1    shige 
    168       1.5    freza 	/* Make sure it looks sane, intr_establish does the real check. */
    169       1.5    freza 	if (ih < 0 || ih > 99)
    170       1.5    freza 		panic("pci_intr_string: handle %d won't fit two digits", ih);
    171       1.1    shige 
    172       1.1    shige 	sprintf(irqstr, "irq %d", ih);
    173       1.1    shige 	return (irqstr);
    174       1.1    shige 
    175       1.1    shige }
    176       1.1    shige 
    177       1.1    shige const struct evcnt *
    178       1.1    shige pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
    179       1.1    shige {
    180       1.1    shige 
    181       1.1    shige 	/* XXX for now, no evcnt parent reported */
    182       1.1    shige 	return NULL;
    183       1.1    shige }
    184       1.1    shige 
    185  1.5.62.1     yamt int
    186  1.5.62.1     yamt pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
    187  1.5.62.1     yamt 		 int attr, uint64_t data)
    188  1.5.62.1     yamt {
    189  1.5.62.1     yamt 
    190  1.5.62.1     yamt 	switch (attr) {
    191  1.5.62.1     yamt 	case PCI_INTR_MPSAFE:
    192  1.5.62.1     yamt 		return 0;
    193  1.5.62.1     yamt 	default:
    194  1.5.62.1     yamt 		return ENODEV;
    195  1.5.62.1     yamt 	}
    196  1.5.62.1     yamt }
    197  1.5.62.1     yamt 
    198       1.1    shige void *
    199       1.1    shige pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
    200       1.1    shige 		   int (*func)(void *), void *arg)
    201       1.1    shige {
    202       1.1    shige 	return intr_establish(ih, IST_LEVEL, level, func, arg);
    203       1.1    shige }
    204       1.1    shige 
    205       1.1    shige void
    206       1.1    shige pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
    207       1.1    shige {
    208       1.1    shige 
    209       1.1    shige 	intr_disestablish(cookie);
    210       1.1    shige }
    211       1.1    shige 
    212       1.1    shige /* Avoid overconfiguration */
    213       1.1    shige int
    214       1.1    shige pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
    215       1.1    shige {
    216       1.1    shige 
    217       1.1    shige 	if ((PCI_VENDOR(id) == PCI_VENDOR_IBM && PCI_PRODUCT(id) == PCI_PRODUCT_IBM_405GP) ||
    218       1.1    shige 	    (PCI_VENDOR(id) == PCI_VENDOR_INTEL && PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_80960_RP)) {
    219       1.1    shige 		/* Don't configure the bridge and PCI probe. */
    220       1.1    shige 		return 0;
    221       1.1    shige 	}
    222       1.3  gdamore 	return PCI_CONF_DEFAULT;
    223       1.1    shige }
    224