pciex.c revision 1.1
1 /* $NetBSD: pciex.c,v 1.1 2026/06/14 00:02:35 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2012, 2014, 2024, 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * IBM PLB-PCIE root complex 33 * as found on the 440SPe/460EX family of SoCs 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pciex.c,v 1.1 2026/06/14 00:02:35 rkujawa Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_pci.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/extent.h> 47 #include <sys/bus.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pciconf.h> 52 53 #include <powerpc/pcb.h> 54 55 #include <powerpc/ibm4xx/amcc460ex.h> 56 #include <powerpc/ibm4xx/cpu.h> 57 #include <powerpc/ibm4xx/spr.h> 58 #include <powerpc/ibm4xx/dev/plbvar.h> 59 #include <powerpc/ibm4xx/pci_machdep.h> 60 #include <powerpc/pci_machdep.h> 61 62 #define PCIEX_NPORTS 2 63 64 /* PEGPL DCR offsets */ 65 #define PEGPL_CFGBAH 0x00 66 #define PEGPL_CFGBAL 0x01 67 #define PEGPL_CFGMSK 0x02 68 #define PEGPL_OMR1BAH 0x06 69 #define PEGPL_OMR1BAL 0x07 70 #define PEGPL_OMR1MSKH 0x08 71 #define PEGPL_OMR1MSKL 0x09 72 73 struct pciex_softc { 74 struct genppc_pci_chipset sc_pc; /* must be first */ 75 device_t sc_dev; 76 int sc_port; 77 bus_space_handle_t sc_cfgh; 78 }; 79 80 static int pciex_match(device_t, cfdata_t, void *); 81 static void pciex_attach(device_t, device_t, void *); 82 static int pciex_print(void *, const char *); 83 84 CFATTACH_DECL_NEW(pciex, sizeof(struct pciex_softc), 85 pciex_match, pciex_attach, NULL, NULL); 86 87 static pcireg_t pciex_conf_read(void *, pcitag_t, int); 88 static void pciex_conf_write(void *, pcitag_t, int, pcireg_t); 89 static void pciex_attach_hook(device_t, device_t, 90 struct pcibus_attach_args *); 91 static int pciex_conf_hook(void *, int, int, int, pcireg_t); 92 static int pciex_intr_map(const struct pci_attach_args *, 93 pci_intr_handle_t *); 94 static void pciex_conf_interrupt(void *, int, int, int, int, int *); 95 96 /* ECAM config windows */ 97 static struct powerpc_bus_space pciex_cfg_tag[PCIEX_NPORTS] = { 98 { 99 _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE, 100 0x00000000, 101 AMCC460EX_PCIE0_CFG_PLBA, 102 AMCC460EX_PCIE0_CFG_PLBA + AMCC460EX_PCIE_CFG_SIZE, 103 }, 104 { 105 _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE, 106 0x00000000, 107 AMCC460EX_PCIE1_CFG_PLBA, 108 AMCC460EX_PCIE1_CFG_PLBA + AMCC460EX_PCIE_CFG_SIZE, 109 }, 110 }; 111 112 static struct powerpc_bus_space pciex_mem_tag[PCIEX_NPORTS] = { 113 { 114 _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE, 115 AMCC460EX_PCIE0_MEM_PLBA - AMCC460EX_PCIE_MEM_BASE, 116 AMCC460EX_PCIE_MEM_BASE, 117 AMCC460EX_PCIE_MEM_BASE + AMCC460EX_PCIE_MEM_SIZE, 118 }, 119 { 120 _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE, 121 AMCC460EX_PCIE1_MEM_PLBA - AMCC460EX_PCIE_MEM_BASE, 122 AMCC460EX_PCIE_MEM_BASE, 123 AMCC460EX_PCIE_MEM_BASE + AMCC460EX_PCIE_MEM_SIZE, 124 }, 125 }; 126 127 static const struct genppc_pci_chipset pciex_chipset_template = { 128 .pc_conf_v = NULL, /* set to softc */ 129 .pc_attach_hook = pciex_attach_hook, 130 .pc_bus_maxdevs = ibm4xx_pci_bus_maxdevs, 131 .pc_make_tag = ibm4xx_pci_make_tag, 132 .pc_conf_read = pciex_conf_read, 133 .pc_conf_write = pciex_conf_write, 134 135 .pc_intr_v = NULL, /* set to softc */ 136 .pc_intr_map = pciex_intr_map, 137 .pc_intr_string = genppc_pci_intr_string, 138 .pc_intr_evcnt = genppc_pci_intr_evcnt, 139 .pc_intr_establish = genppc_pci_intr_establish, 140 .pc_intr_disestablish = genppc_pci_intr_disestablish, 141 .pc_intr_setattr = ibm4xx_pci_intr_setattr, 142 .pc_intr_type = genppc_pci_intr_type, 143 .pc_intr_alloc = genppc_pci_intr_alloc, 144 .pc_intr_release = genppc_pci_intr_release, 145 .pc_intx_alloc = genppc_pci_intx_alloc, 146 147 .pc_msi_v = NULL, /* set to softc */ 148 GENPPC_PCI_MSI_INITIALIZER, 149 150 .pc_msix_v = NULL, /* set to softc */ 151 GENPPC_PCI_MSIX_INITIALIZER, 152 153 .pc_conf_interrupt = pciex_conf_interrupt, 154 .pc_decompose_tag = ibm4xx_pci_decompose_tag, 155 .pc_conf_hook = pciex_conf_hook, 156 }; 157 158 static int 159 pciex_port_inta(int port) 160 { 161 162 return port == 0 ? AMCC460EX_PCIE0_INTA_IRQ : AMCC460EX_PCIE1_INTA_IRQ; 163 } 164 165 static void 166 pciex_attach_hook(device_t parent, device_t self, 167 struct pcibus_attach_args *pba) 168 { 169 } 170 171 static int 172 pciex_conf_hook(void *v, int bus, int dev, int func, pcireg_t id) 173 { 174 175 return PCI_CONF_DEFAULT; 176 } 177 178 /* 179 * INTA-INTD are wired to consecutive UIC3 inputs per port. 180 * At least on 460EX, this may or may not be true for other SoCs... 181 */ 182 static int 183 pciex_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 184 { 185 struct pciex_softc *sc = pa->pa_pc->pc_intr_v; 186 187 if (pa->pa_intrpin == 0 || pa->pa_intrpin > 4) 188 return 1; 189 *ihp = pciex_port_inta(sc->sc_port) + pa->pa_intrpin - 1; 190 return 0; 191 } 192 193 static void 194 pciex_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, 195 int *iline) 196 { 197 struct pciex_softc *sc = v; 198 199 *iline = pciex_port_inta(sc->sc_port) + (pin - 1 + swiz + dev) % 4; 200 } 201 202 /* 203 * Config access: ECAM offset is the standard tag (bus<<16|dev<<11| 204 * func<<8) shifted left by 4. 205 */ 206 static pcireg_t 207 pciex_conf_read(void *v, pcitag_t tag, int reg) 208 { 209 struct pciex_softc *sc = v; 210 struct faultbuf env; 211 pcireg_t data; 212 int bus; 213 214 if ((unsigned int)reg >= PCI_CONF_SIZE) 215 return (pcireg_t) -1; 216 ibm4xx_pci_decompose_tag(v, tag, &bus, NULL, NULL); 217 if (bus >= AMCC460EX_PCIE_CFG_SIZE >> 20) 218 return (pcireg_t) -1; 219 220 if (setfault(&env)) { 221 curpcb->pcb_onfault = NULL; 222 return (pcireg_t) -1; 223 } 224 data = bus_space_read_4(&pciex_cfg_tag[sc->sc_port], sc->sc_cfgh, 225 (tag << 4) | reg); 226 curpcb->pcb_onfault = NULL; 227 return data; 228 } 229 230 static void 231 pciex_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 232 { 233 struct pciex_softc *sc = v; 234 struct faultbuf env; 235 int bus; 236 237 if ((unsigned int)reg >= PCI_CONF_SIZE) 238 return; 239 ibm4xx_pci_decompose_tag(v, tag, &bus, NULL, NULL); 240 if (bus >= AMCC460EX_PCIE_CFG_SIZE >> 20) 241 return; 242 243 if (setfault(&env)) { 244 curpcb->pcb_onfault = NULL; 245 return; 246 } 247 bus_space_write_4(&pciex_cfg_tag[sc->sc_port], sc->sc_cfgh, 248 (tag << 4) | reg, data); 249 curpcb->pcb_onfault = NULL; 250 } 251 252 /* 253 * Program the PEGPL config and outbound memory windows. 254 * mtdcr() needs compile-time constant DCR numbers. 255 */ 256 #define PCIEX_PROGRAM_PORT(base, cfg_plba, mem_plba) \ 257 do { \ 258 mtdcr((base) + PEGPL_CFGMSK, 0); \ 259 mtdcr((base) + PEGPL_CFGBAH, AMCC460EX_PCIE_CFG_PA_HIGH); \ 260 mtdcr((base) + PEGPL_CFGBAL, (cfg_plba)); \ 261 mtdcr((base) + PEGPL_CFGMSK, \ 262 ~(AMCC460EX_PCIE_CFG_SIZE - 1) | 1); \ 263 mtdcr((base) + PEGPL_OMR1BAH, AMCC460EX_PCIE_MEM_PA_HIGH); \ 264 mtdcr((base) + PEGPL_OMR1BAL, (mem_plba)); \ 265 mtdcr((base) + PEGPL_OMR1MSKH, 0x7fffffff); \ 266 mtdcr((base) + PEGPL_OMR1MSKL, \ 267 ~(AMCC460EX_PCIE_MEM_SIZE - 1) | 3); \ 268 } while (0) 269 270 static void 271 pciex_setup_windows(int port) 272 { 273 274 if (port == 0) 275 PCIEX_PROGRAM_PORT(AMCC460EX_PCIE0_DCR_BASE, 276 AMCC460EX_PCIE0_CFG_PLBA, AMCC460EX_PCIE0_MEM_PLBA); 277 else 278 PCIEX_PROGRAM_PORT(AMCC460EX_PCIE1_DCR_BASE, 279 AMCC460EX_PCIE1_CFG_PLBA, AMCC460EX_PCIE1_MEM_PLBA); 280 } 281 282 static int 283 pciex_match(device_t parent, cfdata_t cf, void *aux) 284 { 285 struct plb_attach_args *paa = aux; 286 287 if (strcmp(paa->plb_name, cf->cf_name) != 0) 288 return 0; 289 if (cf->cf_unit >= PCIEX_NPORTS) 290 return 0; 291 292 return 1; 293 } 294 295 static void 296 pciex_attach(device_t parent, device_t self, void *aux) 297 { 298 struct pciex_softc *sc = device_private(self); 299 struct plb_attach_args *paa = aux; 300 struct pcibus_attach_args pba; 301 pci_chipset_tag_t pc; 302 303 sc->sc_dev = self; 304 sc->sc_port = device_unit(self); 305 sc->sc_pc = pciex_chipset_template; 306 sc->sc_pc.pc_conf_v = sc; 307 sc->sc_pc.pc_intr_v = sc; 308 sc->sc_pc.pc_msi_v = sc; 309 sc->sc_pc.pc_msix_v = sc; 310 pc = &sc->sc_pc; 311 312 aprint_normal(": PLB-PCIE root complex, port %d\n", sc->sc_port); 313 314 /* 315 * Touch the port only if firmware trained the link 316 */ 317 if ((mfsdr(sc->sc_port ? AMCC460EX_PESDR1_LOOP : 318 AMCC460EX_PESDR0_LOOP) & AMCC460EX_PESDR_LOOP_LNKUP) == 0) { 319 aprint_normal_dev(self, 320 "link is not up, port not configured by firmware\n"); 321 return; 322 } 323 324 if (bus_space_init(&pciex_cfg_tag[sc->sc_port], "pciexcfg", NULL, 0) || 325 bus_space_map(&pciex_cfg_tag[sc->sc_port], 326 pciex_cfg_tag[sc->sc_port].pbs_base, AMCC460EX_PCIE_CFG_SIZE, 327 0, &sc->sc_cfgh)) { 328 aprint_error_dev(self, "can't map config window\n"); 329 return; 330 } 331 if (bus_space_init(&pciex_mem_tag[sc->sc_port], "pciexmem", NULL, 0)) { 332 aprint_error_dev(self, "can't init MEM tag\n"); 333 return; 334 } 335 336 pciex_setup_windows(sc->sc_port); 337 338 #ifdef PCI_NETBSD_CONFIGURE 339 struct pciconf_resources *pcires = pciconf_resource_init(); 340 341 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 342 AMCC460EX_PCIE_MEM_BASE, AMCC460EX_PCIE_MEM_SIZE); 343 344 pci_configure_bus(pc, pcires, 0, 32); 345 pciconf_resource_fini(pcires); 346 #endif 347 348 pba.pba_iot = NULL; 349 pba.pba_memt = &pciex_mem_tag[sc->sc_port]; 350 pba.pba_dmat = paa->plb_dmat; 351 pba.pba_dmat64 = NULL; 352 pba.pba_pc = pc; 353 pba.pba_bus = 0; 354 pba.pba_bridgetag = NULL; 355 pba.pba_flags = PCI_FLAGS_MEM_OKAY; 356 config_found(self, &pba, pciex_print, CFARGS_NONE); 357 } 358 359 static int 360 pciex_print(void *aux, const char *p) 361 { 362 363 if (p == NULL) 364 return UNCONF; 365 return QUIET; 366 } 367
Indexes created Tue Jul 07 00:25:39 UTC 2026