pic_uic.c revision 1.1.2.2
1 1.1.2.2 cherry /* $NetBSD: pic_uic.c,v 1.1.2.2 2011/06/23 14:19:29 cherry Exp $ */ 2 1.1.2.2 cherry 3 1.1.2.2 cherry /* 4 1.1.2.2 cherry * Copyright 2002 Wasabi Systems, Inc. 5 1.1.2.2 cherry * All rights reserved. 6 1.1.2.2 cherry * 7 1.1.2.2 cherry * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 1.1.2.2 cherry * 9 1.1.2.2 cherry * Redistribution and use in source and binary forms, with or without 10 1.1.2.2 cherry * modification, are permitted provided that the following conditions 11 1.1.2.2 cherry * are met: 12 1.1.2.2 cherry * 1. Redistributions of source code must retain the above copyright 13 1.1.2.2 cherry * notice, this list of conditions and the following disclaimer. 14 1.1.2.2 cherry * 2. Redistributions in binary form must reproduce the above copyright 15 1.1.2.2 cherry * notice, this list of conditions and the following disclaimer in the 16 1.1.2.2 cherry * documentation and/or other materials provided with the distribution. 17 1.1.2.2 cherry * 3. All advertising materials mentioning features or use of this software 18 1.1.2.2 cherry * must display the following acknowledgement: 19 1.1.2.2 cherry * This product includes software developed for the NetBSD Project by 20 1.1.2.2 cherry * Wasabi Systems, Inc. 21 1.1.2.2 cherry * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 1.1.2.2 cherry * or promote products derived from this software without specific prior 23 1.1.2.2 cherry * written permission. 24 1.1.2.2 cherry * 25 1.1.2.2 cherry * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 1.1.2.2 cherry * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.1.2.2 cherry * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.1.2.2 cherry * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 1.1.2.2 cherry * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.1.2.2 cherry * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.1.2.2 cherry * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.1.2.2 cherry * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.1.2.2 cherry * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.1.2.2 cherry * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.1.2.2 cherry * POSSIBILITY OF SUCH DAMAGE. 36 1.1.2.2 cherry */ 37 1.1.2.2 cherry 38 1.1.2.2 cherry #include <sys/cdefs.h> 39 1.1.2.2 cherry __KERNEL_RCSID(0, "$NetBSD: pic_uic.c,v 1.1.2.2 2011/06/23 14:19:29 cherry Exp $"); 40 1.1.2.2 cherry 41 1.1.2.2 cherry #include <sys/param.h> 42 1.1.2.2 cherry #include <sys/malloc.h> 43 1.1.2.2 cherry #include <sys/kernel.h> 44 1.1.2.2 cherry #include <sys/evcnt.h> 45 1.1.2.2 cherry #include <sys/cpu.h> 46 1.1.2.2 cherry 47 1.1.2.2 cherry #include <machine/intr.h> 48 1.1.2.2 cherry #include <machine/psl.h> 49 1.1.2.2 cherry 50 1.1.2.2 cherry #include <powerpc/spr.h> 51 1.1.2.2 cherry #include <powerpc/ibm4xx/spr.h> 52 1.1.2.2 cherry #include <powerpc/ibm4xx/cpu.h> 53 1.1.2.2 cherry 54 1.1.2.2 cherry #include <powerpc/pic/picvar.h> 55 1.1.2.2 cherry 56 1.1.2.2 cherry 57 1.1.2.2 cherry /* 58 1.1.2.2 cherry * Number of interrupts (hard + soft), irq number legality test, 59 1.1.2.2 cherry * mapping of irq number to mask and a way to pick irq number 60 1.1.2.2 cherry * off a mask of active intrs. 61 1.1.2.2 cherry */ 62 1.1.2.2 cherry #define IRQ_TO_MASK(irq) (0x80000000UL >> ((irq) & 0x1f)) 63 1.1.2.2 cherry #define IRQ_OF_MASK(mask) __builtin_clz(mask) 64 1.1.2.2 cherry 65 1.1.2.2 cherry static void uic_enable_irq(struct pic_ops *, int, int); 66 1.1.2.2 cherry static void uic_disable_irq(struct pic_ops *, int); 67 1.1.2.2 cherry static int uic_get_irq(struct pic_ops *, int); 68 1.1.2.2 cherry static void uic_ack_irq(struct pic_ops *, int); 69 1.1.2.2 cherry static void uic_establish_irq(struct pic_ops *, int, int, int); 70 1.1.2.2 cherry 71 1.1.2.2 cherry struct uic { 72 1.1.2.2 cherry uint32_t uic_intr_enable; /* cached intr enable mask */ 73 1.1.2.2 cherry uint32_t (*uic_mf_intr_status)(void); 74 1.1.2.2 cherry uint32_t (*uic_mf_intr_enable)(void); 75 1.1.2.2 cherry void (*uic_mt_intr_enable)(uint32_t); 76 1.1.2.2 cherry void (*uic_mt_intr_ack)(uint32_t); 77 1.1.2.2 cherry }; 78 1.1.2.2 cherry 79 1.1.2.2 cherry /* 80 1.1.2.2 cherry * Platform specific code may override any of the above. 81 1.1.2.2 cherry */ 82 1.1.2.2 cherry #ifdef PPC_IBM403 83 1.1.2.2 cherry 84 1.1.2.2 cherry #include <powerpc/ibm4xx/dcr403cgx.h> 85 1.1.2.2 cherry 86 1.1.2.2 cherry static uint32_t 87 1.1.2.2 cherry uic403_mfdcr_intr_status(void) 88 1.1.2.2 cherry { 89 1.1.2.2 cherry return mfdcr(DCR_EXISR); 90 1.1.2.2 cherry } 91 1.1.2.2 cherry 92 1.1.2.2 cherry static uint32_t 93 1.1.2.2 cherry uic403_mfdcr_intr_enable(void) 94 1.1.2.2 cherry { 95 1.1.2.2 cherry return mfdcr(DCR_EXIER); 96 1.1.2.2 cherry } 97 1.1.2.2 cherry 98 1.1.2.2 cherry static void 99 1.1.2.2 cherry uic403_mtdcr_intr_ack(uint32_t v) 100 1.1.2.2 cherry { 101 1.1.2.2 cherry mtdcr(DCR_EXISR, v); 102 1.1.2.2 cherry } 103 1.1.2.2 cherry 104 1.1.2.2 cherry static void 105 1.1.2.2 cherry uic403_mtdcr_intr_enable(uint32_t v) 106 1.1.2.2 cherry { 107 1.1.2.2 cherry mtdcr(DCR_EXIER, v); 108 1.1.2.2 cherry } 109 1.1.2.2 cherry 110 1.1.2.2 cherry struct uic uic403 = { 111 1.1.2.2 cherry .uic_intr_enable = 0, 112 1.1.2.2 cherry .uic_mf_intr_status = uic403_mfdcr_intr_status, 113 1.1.2.2 cherry .uic_mf_intr_enable = uic403_mfdcr_intr_enable, 114 1.1.2.2 cherry .uic_mt_intr_enable = uic403_mtdcr_intr_enable, 115 1.1.2.2 cherry .uic_mt_intr_ack = uic403_mtdcr_intr_ack, 116 1.1.2.2 cherry }; 117 1.1.2.2 cherry 118 1.1.2.2 cherry struct pic_ops pic_uic403 = { 119 1.1.2.2 cherry .pic_cookie = &uic403, 120 1.1.2.2 cherry .pic_numintrs = 32, 121 1.1.2.2 cherry .pic_enable_irq = uic_enable_irq, 122 1.1.2.2 cherry .pic_reenable_irq = uic_enable_irq, 123 1.1.2.2 cherry .pic_disable_irq = uic_disable_irq, 124 1.1.2.2 cherry .pic_establish_irq = uic_establish_irq, 125 1.1.2.2 cherry .pic_get_irq = uic_get_irq, 126 1.1.2.2 cherry .pic_ack_irq = uic_ack_irq, 127 1.1.2.2 cherry .pic_finish_setup = NULL, 128 1.1.2.2 cherry .pic_name = "uic0" 129 1.1.2.2 cherry }; 130 1.1.2.2 cherry 131 1.1.2.2 cherry #else /* Generic 405/440/460 Universal Interrupt Controller */ 132 1.1.2.2 cherry 133 1.1.2.2 cherry #include <powerpc/ibm4xx/dcr4xx.h> 134 1.1.2.2 cherry 135 1.1.2.2 cherry #include "opt_uic.h" 136 1.1.2.2 cherry 137 1.1.2.2 cherry /* 405EP/405GP/405GPr/Virtex-4 */ 138 1.1.2.2 cherry 139 1.1.2.2 cherry static uint32_t 140 1.1.2.2 cherry uic0_mfdcr_intr_status(void) 141 1.1.2.2 cherry { 142 1.1.2.2 cherry return mfdcr(DCR_UIC0_BASE + DCR_UIC_MSR); 143 1.1.2.2 cherry } 144 1.1.2.2 cherry 145 1.1.2.2 cherry static uint32_t 146 1.1.2.2 cherry uic0_mfdcr_intr_enable(void) 147 1.1.2.2 cherry { 148 1.1.2.2 cherry return mfdcr(DCR_UIC0_BASE + DCR_UIC_ER); 149 1.1.2.2 cherry } 150 1.1.2.2 cherry 151 1.1.2.2 cherry static void 152 1.1.2.2 cherry uic0_mtdcr_intr_ack(uint32_t v) 153 1.1.2.2 cherry { 154 1.1.2.2 cherry mtdcr(DCR_UIC0_BASE + DCR_UIC_SR, v); 155 1.1.2.2 cherry } 156 1.1.2.2 cherry 157 1.1.2.2 cherry static void 158 1.1.2.2 cherry uic0_mtdcr_intr_enable(uint32_t v) 159 1.1.2.2 cherry { 160 1.1.2.2 cherry mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, v); 161 1.1.2.2 cherry } 162 1.1.2.2 cherry 163 1.1.2.2 cherry struct uic uic0 = { 164 1.1.2.2 cherry .uic_intr_enable = 0, 165 1.1.2.2 cherry .uic_mf_intr_status = uic0_mfdcr_intr_status, 166 1.1.2.2 cherry .uic_mf_intr_enable = uic0_mfdcr_intr_enable, 167 1.1.2.2 cherry .uic_mt_intr_enable = uic0_mtdcr_intr_enable, 168 1.1.2.2 cherry .uic_mt_intr_ack = uic0_mtdcr_intr_ack, 169 1.1.2.2 cherry }; 170 1.1.2.2 cherry 171 1.1.2.2 cherry struct pic_ops pic_uic0 = { 172 1.1.2.2 cherry .pic_cookie = &uic0, 173 1.1.2.2 cherry .pic_numintrs = 32, 174 1.1.2.2 cherry .pic_enable_irq = uic_enable_irq, 175 1.1.2.2 cherry .pic_reenable_irq = uic_enable_irq, 176 1.1.2.2 cherry .pic_disable_irq = uic_disable_irq, 177 1.1.2.2 cherry .pic_establish_irq = uic_establish_irq, 178 1.1.2.2 cherry .pic_get_irq = uic_get_irq, 179 1.1.2.2 cherry .pic_ack_irq = uic_ack_irq, 180 1.1.2.2 cherry .pic_finish_setup = NULL, 181 1.1.2.2 cherry .pic_name = "uic0" 182 1.1.2.2 cherry }; 183 1.1.2.2 cherry 184 1.1.2.2 cherry #ifdef MULTIUIC 185 1.1.2.2 cherry 186 1.1.2.2 cherry /* 440EP/440GP/440SP/405EX/440SPe/440GX */ 187 1.1.2.2 cherry 188 1.1.2.2 cherry static uint32_t 189 1.1.2.2 cherry uic1_mfdcr_intr_status(void) 190 1.1.2.2 cherry { 191 1.1.2.2 cherry return mfdcr(DCR_UIC1_BASE + DCR_UIC_MSR); 192 1.1.2.2 cherry } 193 1.1.2.2 cherry 194 1.1.2.2 cherry static uint32_t 195 1.1.2.2 cherry uic1_mfdcr_intr_enable(void) 196 1.1.2.2 cherry { 197 1.1.2.2 cherry return mfdcr(DCR_UIC1_BASE + DCR_UIC_ER); 198 1.1.2.2 cherry } 199 1.1.2.2 cherry 200 1.1.2.2 cherry static void 201 1.1.2.2 cherry uic1_mtdcr_intr_ack(uint32_t v) 202 1.1.2.2 cherry { 203 1.1.2.2 cherry mtdcr(DCR_UIC1_BASE + DCR_UIC_SR, v); 204 1.1.2.2 cherry } 205 1.1.2.2 cherry 206 1.1.2.2 cherry static void 207 1.1.2.2 cherry uic1_mtdcr_intr_enable(uint32_t v) 208 1.1.2.2 cherry { 209 1.1.2.2 cherry mtdcr(DCR_UIC1_BASE + DCR_UIC_ER, v); 210 1.1.2.2 cherry } 211 1.1.2.2 cherry 212 1.1.2.2 cherry extern struct pic_ops pic_uic1; 213 1.1.2.2 cherry 214 1.1.2.2 cherry static void 215 1.1.2.2 cherry uic1_finish_setup(struct pic_ops *pic) 216 1.1.2.2 cherry { 217 1.1.2.2 cherry intr_establish(30, IPL_NONE, IST_LEVEL, pic_handle_intr, &pic_uic1); 218 1.1.2.2 cherry } 219 1.1.2.2 cherry 220 1.1.2.2 cherry struct uic uic1 = { 221 1.1.2.2 cherry .uic_intr_enable = 0, 222 1.1.2.2 cherry .uic_mf_intr_status = uic1_mfdcr_intr_status, 223 1.1.2.2 cherry .uic_mf_intr_enable = uic1_mfdcr_intr_enable, 224 1.1.2.2 cherry .uic_mt_intr_enable = uic1_mtdcr_intr_enable, 225 1.1.2.2 cherry .uic_mt_intr_ack = uic1_mtdcr_intr_ack, 226 1.1.2.2 cherry }; 227 1.1.2.2 cherry 228 1.1.2.2 cherry struct pic_ops pic_uic1 = { 229 1.1.2.2 cherry .pic_cookie = &uic1, 230 1.1.2.2 cherry .pic_numintrs = 32, 231 1.1.2.2 cherry .pic_enable_irq = uic_enable_irq, 232 1.1.2.2 cherry .pic_reenable_irq = uic_enable_irq, 233 1.1.2.2 cherry .pic_disable_irq = uic_disable_irq, 234 1.1.2.2 cherry .pic_establish_irq = uic_establish_irq, 235 1.1.2.2 cherry .pic_get_irq = uic_get_irq, 236 1.1.2.2 cherry .pic_ack_irq = uic_ack_irq, 237 1.1.2.2 cherry .pic_finish_setup = uic1_finish_setup, 238 1.1.2.2 cherry .pic_name = "uic1" 239 1.1.2.2 cherry }; 240 1.1.2.2 cherry 241 1.1.2.2 cherry /* 440EP/440GP/440SP/405EX/440SPe */ 242 1.1.2.2 cherry 243 1.1.2.2 cherry static uint32_t 244 1.1.2.2 cherry uic2_mfdcr_intr_status(void) 245 1.1.2.2 cherry { 246 1.1.2.2 cherry return mfdcr(DCR_UIC2_BASE + DCR_UIC_MSR); 247 1.1.2.2 cherry } 248 1.1.2.2 cherry 249 1.1.2.2 cherry static uint32_t 250 1.1.2.2 cherry uic2_mfdcr_intr_enable(void) 251 1.1.2.2 cherry { 252 1.1.2.2 cherry return mfdcr(DCR_UIC2_BASE + DCR_UIC_ER); 253 1.1.2.2 cherry } 254 1.1.2.2 cherry 255 1.1.2.2 cherry static void 256 1.1.2.2 cherry uic2_mtdcr_intr_ack(uint32_t v) 257 1.1.2.2 cherry { 258 1.1.2.2 cherry mtdcr(DCR_UIC2_BASE + DCR_UIC_SR, v); 259 1.1.2.2 cherry } 260 1.1.2.2 cherry 261 1.1.2.2 cherry static void 262 1.1.2.2 cherry uic2_mtdcr_intr_enable(uint32_t v) 263 1.1.2.2 cherry { 264 1.1.2.2 cherry mtdcr(DCR_UIC2_BASE + DCR_UIC_ER, v); 265 1.1.2.2 cherry } 266 1.1.2.2 cherry 267 1.1.2.2 cherry extern struct pic_ops pic_uic2; 268 1.1.2.2 cherry 269 1.1.2.2 cherry static void 270 1.1.2.2 cherry uic2_finish_setup(struct pic_ops *pic) 271 1.1.2.2 cherry { 272 1.1.2.2 cherry intr_establish(28, IPL_NONE, IST_LEVEL, pic_handle_intr, &pic_uic2); 273 1.1.2.2 cherry } 274 1.1.2.2 cherry 275 1.1.2.2 cherry static struct uic uic2 = { 276 1.1.2.2 cherry .uic_intr_enable = 0, 277 1.1.2.2 cherry .uic_mf_intr_status = uic2_mfdcr_intr_status, 278 1.1.2.2 cherry .uic_mf_intr_enable = uic2_mfdcr_intr_enable, 279 1.1.2.2 cherry .uic_mt_intr_enable = uic2_mtdcr_intr_enable, 280 1.1.2.2 cherry .uic_mt_intr_ack = uic2_mtdcr_intr_ack, 281 1.1.2.2 cherry }; 282 1.1.2.2 cherry 283 1.1.2.2 cherry struct pic_ops pic_uic2 = { 284 1.1.2.2 cherry .pic_cookie = &uic2, 285 1.1.2.2 cherry .pic_numintrs = 32, 286 1.1.2.2 cherry .pic_enable_irq = uic_enable_irq, 287 1.1.2.2 cherry .pic_reenable_irq = uic_enable_irq, 288 1.1.2.2 cherry .pic_disable_irq = uic_disable_irq, 289 1.1.2.2 cherry .pic_establish_irq = uic_establish_irq, 290 1.1.2.2 cherry .pic_get_irq = uic_get_irq, 291 1.1.2.2 cherry .pic_ack_irq = uic_ack_irq, 292 1.1.2.2 cherry .pic_finish_setup = uic2_finish_setup, 293 1.1.2.2 cherry .pic_name = "uic2" 294 1.1.2.2 cherry }; 295 1.1.2.2 cherry 296 1.1.2.2 cherry #endif /* MULTIUIC */ 297 1.1.2.2 cherry #endif /* !PPC_IBM403 */ 298 1.1.2.2 cherry 299 1.1.2.2 cherry /* Write External Enable Immediate */ 300 1.1.2.2 cherry #define wrteei(en) __asm volatile ("wrteei %0" : : "K"(en)) 301 1.1.2.2 cherry 302 1.1.2.2 cherry /* Enforce In Order Execution of I/O */ 303 1.1.2.2 cherry #define eieio() __asm volatile ("eieio") 304 1.1.2.2 cherry 305 1.1.2.2 cherry /* 306 1.1.2.2 cherry * Set up interrupt mapping array. 307 1.1.2.2 cherry */ 308 1.1.2.2 cherry void 309 1.1.2.2 cherry intr_init(void) 310 1.1.2.2 cherry { 311 1.1.2.2 cherry #ifdef PPC_IBM403 312 1.1.2.2 cherry struct pic_ops * const pic = &pic_uic403; 313 1.1.2.2 cherry #else 314 1.1.2.2 cherry struct pic_ops * const pic = &pic_uic0; 315 1.1.2.2 cherry #endif 316 1.1.2.2 cherry struct uic * const uic = pic->pic_cookie; 317 1.1.2.2 cherry 318 1.1.2.2 cherry uic->uic_mt_intr_enable(0x00000000); /* mask all */ 319 1.1.2.2 cherry uic->uic_mt_intr_ack(0xffffffff); /* acknowledge all */ 320 1.1.2.2 cherry 321 1.1.2.2 cherry pic_add(pic); 322 1.1.2.2 cherry } 323 1.1.2.2 cherry 324 1.1.2.2 cherry static void 325 1.1.2.2 cherry uic_disable_irq(struct pic_ops *pic, int irq) 326 1.1.2.2 cherry { 327 1.1.2.2 cherry struct uic * const uic = pic->pic_cookie; 328 1.1.2.2 cherry const uint32_t irqmask = IRQ_TO_MASK(irq); 329 1.1.2.2 cherry if ((uic->uic_intr_enable & irqmask) == 0) 330 1.1.2.2 cherry return; 331 1.1.2.2 cherry uic->uic_intr_enable ^= irqmask; 332 1.1.2.2 cherry (*uic->uic_mt_intr_enable)(uic->uic_intr_enable); 333 1.1.2.2 cherry #ifdef IRQ_DEBUG 334 1.1.2.2 cherry printf("%s: %s: irq=%d, mask=%08x\n", __func__, 335 1.1.2.2 cherry pic->pic_name, irq, irqmask); 336 1.1.2.2 cherry #endif 337 1.1.2.2 cherry } 338 1.1.2.2 cherry 339 1.1.2.2 cherry static void 340 1.1.2.2 cherry uic_enable_irq(struct pic_ops *pic, int irq, int type) 341 1.1.2.2 cherry { 342 1.1.2.2 cherry struct uic * const uic = pic->pic_cookie; 343 1.1.2.2 cherry const uint32_t irqmask = IRQ_TO_MASK(irq); 344 1.1.2.2 cherry if ((uic->uic_intr_enable & irqmask) != 0) 345 1.1.2.2 cherry return; 346 1.1.2.2 cherry uic->uic_intr_enable ^= irqmask; 347 1.1.2.2 cherry (*uic->uic_mt_intr_enable)(uic->uic_intr_enable); 348 1.1.2.2 cherry #ifdef IRQ_DEBUG 349 1.1.2.2 cherry printf("%s: %s: irq=%d, mask=%08x\n", __func__, 350 1.1.2.2 cherry pic->pic_name, irq, irqmask); 351 1.1.2.2 cherry #endif 352 1.1.2.2 cherry } 353 1.1.2.2 cherry 354 1.1.2.2 cherry static void 355 1.1.2.2 cherry uic_ack_irq(struct pic_ops *pic, int irq) 356 1.1.2.2 cherry { 357 1.1.2.2 cherry struct uic * const uic = pic->pic_cookie; 358 1.1.2.2 cherry const uint32_t irqmask = IRQ_TO_MASK(irq); 359 1.1.2.2 cherry 360 1.1.2.2 cherry (*uic->uic_mt_intr_ack)(irqmask); 361 1.1.2.2 cherry } 362 1.1.2.2 cherry 363 1.1.2.2 cherry static int 364 1.1.2.2 cherry uic_get_irq(struct pic_ops *pic, int dummy) 365 1.1.2.2 cherry { 366 1.1.2.2 cherry struct uic * const uic = pic->pic_cookie; 367 1.1.2.2 cherry 368 1.1.2.2 cherry const uint32_t irqmask = (*uic->uic_mf_intr_status)(); 369 1.1.2.2 cherry if (irqmask == 0) 370 1.1.2.2 cherry return 255; 371 1.1.2.2 cherry return IRQ_OF_MASK(irqmask); 372 1.1.2.2 cherry } 373 1.1.2.2 cherry 374 1.1.2.2 cherry /* 375 1.1.2.2 cherry * Register an interrupt handler. 376 1.1.2.2 cherry */ 377 1.1.2.2 cherry static void 378 1.1.2.2 cherry uic_establish_irq(struct pic_ops *pic, int irq, int type, int ipl) 379 1.1.2.2 cherry { 380 1.1.2.2 cherry } 381
Indexes created Tue Sep 30 20:09:53 GMT 2025