pic_uic.c revision 1.6
1 /* $NetBSD: pic_uic.c,v 1.6 2020/07/06 09:34:16 rin Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pic_uic.c,v 1.6 2020/07/06 09:34:16 rin Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/kernel.h> 43 #include <sys/evcnt.h> 44 #include <sys/cpu.h> 45 46 #include <machine/intr.h> 47 #include <machine/psl.h> 48 49 #include <powerpc/spr.h> 50 #include <powerpc/ibm4xx/spr.h> 51 #include <powerpc/ibm4xx/cpu.h> 52 53 #include <powerpc/pic/picvar.h> 54 55 /* 56 * Number of interrupts (hard + soft), irq number legality test, 57 * mapping of irq number to mask and a way to pick irq number 58 * off a mask of active intrs. 59 */ 60 #define IRQ_TO_MASK(irq) (0x80000000UL >> ((irq) & 0x1f)) 61 #define IRQ_OF_MASK(mask) __builtin_clz(mask) 62 63 static void uic_enable_irq(struct pic_ops *, int, int); 64 static void uic_disable_irq(struct pic_ops *, int); 65 static int uic_get_irq(struct pic_ops *, int); 66 static void uic_ack_irq(struct pic_ops *, int); 67 static void uic_establish_irq(struct pic_ops *, int, int, int); 68 69 struct uic { 70 uint32_t uic_intr_enable; /* cached intr enable mask */ 71 uint32_t (*uic_mf_intr_status)(void); 72 uint32_t (*uic_mf_intr_enable)(void); 73 void (*uic_mt_intr_enable)(uint32_t); 74 void (*uic_mt_intr_ack)(uint32_t); 75 }; 76 77 /* 78 * Platform specific code may override any of the above. 79 */ 80 #ifdef PPC_IBM403 81 82 #include <powerpc/ibm4xx/dcr403cgx.h> 83 84 static uint32_t 85 uic403_mfdcr_intr_status(void) 86 { 87 return mfdcr(DCR_EXISR); 88 } 89 90 static uint32_t 91 uic403_mfdcr_intr_enable(void) 92 { 93 return mfdcr(DCR_EXIER); 94 } 95 96 static void 97 uic403_mtdcr_intr_ack(uint32_t v) 98 { 99 mtdcr(DCR_EXISR, v); 100 } 101 102 static void 103 uic403_mtdcr_intr_enable(uint32_t v) 104 { 105 mtdcr(DCR_EXIER, v); 106 } 107 108 struct uic uic403 = { 109 .uic_intr_enable = 0, 110 .uic_mf_intr_status = uic403_mfdcr_intr_status, 111 .uic_mf_intr_enable = uic403_mfdcr_intr_enable, 112 .uic_mt_intr_enable = uic403_mtdcr_intr_enable, 113 .uic_mt_intr_ack = uic403_mtdcr_intr_ack, 114 }; 115 116 struct pic_ops pic_uic403 = { 117 .pic_cookie = &uic403, 118 .pic_numintrs = 32, 119 .pic_enable_irq = uic_enable_irq, 120 .pic_reenable_irq = uic_enable_irq, 121 .pic_disable_irq = uic_disable_irq, 122 .pic_establish_irq = uic_establish_irq, 123 .pic_get_irq = uic_get_irq, 124 .pic_ack_irq = uic_ack_irq, 125 .pic_finish_setup = NULL, 126 .pic_name = "uic0" 127 }; 128 129 #else /* Generic 405/440/460 Universal Interrupt Controller */ 130 131 #include <powerpc/ibm4xx/dcr4xx.h> 132 133 #include "opt_uic.h" 134 135 /* 405EP/405GP/405GPr/Virtex-4 */ 136 137 static uint32_t 138 uic0_mfdcr_intr_status(void) 139 { 140 return mfdcr(DCR_UIC0_BASE + DCR_UIC_MSR); 141 } 142 143 static uint32_t 144 uic0_mfdcr_intr_enable(void) 145 { 146 return mfdcr(DCR_UIC0_BASE + DCR_UIC_ER); 147 } 148 149 static void 150 uic0_mtdcr_intr_ack(uint32_t v) 151 { 152 mtdcr(DCR_UIC0_BASE + DCR_UIC_SR, v); 153 } 154 155 static void 156 uic0_mtdcr_intr_enable(uint32_t v) 157 { 158 mtdcr(DCR_UIC0_BASE + DCR_UIC_ER, v); 159 } 160 161 struct uic uic0 = { 162 .uic_intr_enable = 0, 163 .uic_mf_intr_status = uic0_mfdcr_intr_status, 164 .uic_mf_intr_enable = uic0_mfdcr_intr_enable, 165 .uic_mt_intr_enable = uic0_mtdcr_intr_enable, 166 .uic_mt_intr_ack = uic0_mtdcr_intr_ack, 167 }; 168 169 struct pic_ops pic_uic0 = { 170 .pic_cookie = &uic0, 171 .pic_numintrs = 32, 172 .pic_enable_irq = uic_enable_irq, 173 .pic_reenable_irq = uic_enable_irq, 174 .pic_disable_irq = uic_disable_irq, 175 .pic_establish_irq = uic_establish_irq, 176 .pic_get_irq = uic_get_irq, 177 .pic_ack_irq = uic_ack_irq, 178 .pic_finish_setup = NULL, 179 .pic_name = "uic0" 180 }; 181 182 #ifdef MULTIUIC 183 184 /* 440EP/440GP/440SP/405EX/440SPe/440GX */ 185 186 static uint32_t 187 uic1_mfdcr_intr_status(void) 188 { 189 return mfdcr(DCR_UIC1_BASE + DCR_UIC_MSR); 190 } 191 192 static uint32_t 193 uic1_mfdcr_intr_enable(void) 194 { 195 return mfdcr(DCR_UIC1_BASE + DCR_UIC_ER); 196 } 197 198 static void 199 uic1_mtdcr_intr_ack(uint32_t v) 200 { 201 mtdcr(DCR_UIC1_BASE + DCR_UIC_SR, v); 202 } 203 204 static void 205 uic1_mtdcr_intr_enable(uint32_t v) 206 { 207 mtdcr(DCR_UIC1_BASE + DCR_UIC_ER, v); 208 } 209 210 extern struct pic_ops pic_uic1; 211 212 static void 213 uic1_finish_setup(struct pic_ops *pic) 214 { 215 intr_establish(30, IST_LEVEL, IPL_HIGH, pic_handle_intr, &pic_uic1); 216 } 217 218 struct uic uic1 = { 219 .uic_intr_enable = 0, 220 .uic_mf_intr_status = uic1_mfdcr_intr_status, 221 .uic_mf_intr_enable = uic1_mfdcr_intr_enable, 222 .uic_mt_intr_enable = uic1_mtdcr_intr_enable, 223 .uic_mt_intr_ack = uic1_mtdcr_intr_ack, 224 }; 225 226 struct pic_ops pic_uic1 = { 227 .pic_cookie = &uic1, 228 .pic_numintrs = 32, 229 .pic_enable_irq = uic_enable_irq, 230 .pic_reenable_irq = uic_enable_irq, 231 .pic_disable_irq = uic_disable_irq, 232 .pic_establish_irq = uic_establish_irq, 233 .pic_get_irq = uic_get_irq, 234 .pic_ack_irq = uic_ack_irq, 235 .pic_finish_setup = uic1_finish_setup, 236 .pic_name = "uic1" 237 }; 238 239 /* 440EP/440GP/440SP/405EX/440SPe */ 240 241 static uint32_t 242 uic2_mfdcr_intr_status(void) 243 { 244 return mfdcr(DCR_UIC2_BASE + DCR_UIC_MSR); 245 } 246 247 static uint32_t 248 uic2_mfdcr_intr_enable(void) 249 { 250 return mfdcr(DCR_UIC2_BASE + DCR_UIC_ER); 251 } 252 253 static void 254 uic2_mtdcr_intr_ack(uint32_t v) 255 { 256 mtdcr(DCR_UIC2_BASE + DCR_UIC_SR, v); 257 } 258 259 static void 260 uic2_mtdcr_intr_enable(uint32_t v) 261 { 262 mtdcr(DCR_UIC2_BASE + DCR_UIC_ER, v); 263 } 264 265 extern struct pic_ops pic_uic2; 266 267 static void 268 uic2_finish_setup(struct pic_ops *pic) 269 { 270 intr_establish(28, IST_LEVEL, IPL_HIGH, pic_handle_intr, &pic_uic2); 271 } 272 273 static struct uic uic2 = { 274 .uic_intr_enable = 0, 275 .uic_mf_intr_status = uic2_mfdcr_intr_status, 276 .uic_mf_intr_enable = uic2_mfdcr_intr_enable, 277 .uic_mt_intr_enable = uic2_mtdcr_intr_enable, 278 .uic_mt_intr_ack = uic2_mtdcr_intr_ack, 279 }; 280 281 struct pic_ops pic_uic2 = { 282 .pic_cookie = &uic2, 283 .pic_numintrs = 32, 284 .pic_enable_irq = uic_enable_irq, 285 .pic_reenable_irq = uic_enable_irq, 286 .pic_disable_irq = uic_disable_irq, 287 .pic_establish_irq = uic_establish_irq, 288 .pic_get_irq = uic_get_irq, 289 .pic_ack_irq = uic_ack_irq, 290 .pic_finish_setup = uic2_finish_setup, 291 .pic_name = "uic2" 292 }; 293 294 #endif /* MULTIUIC */ 295 #endif /* !PPC_IBM403 */ 296 297 /* 298 * Set up interrupt mapping array. 299 */ 300 void 301 intr_init(void) 302 { 303 #ifdef PPC_IBM403 304 struct pic_ops * const pic = &pic_uic403; 305 #else 306 struct pic_ops * const pic = &pic_uic0; 307 #endif 308 struct uic * const uic = pic->pic_cookie; 309 310 uic->uic_mt_intr_enable(0x00000000); /* mask all */ 311 uic->uic_mt_intr_ack(0xffffffff); /* acknowledge all */ 312 313 pic_add(pic); 314 } 315 316 static void 317 uic_disable_irq(struct pic_ops *pic, int irq) 318 { 319 struct uic * const uic = pic->pic_cookie; 320 const uint32_t irqmask = IRQ_TO_MASK(irq); 321 if ((uic->uic_intr_enable & irqmask) == 0) 322 return; 323 uic->uic_intr_enable ^= irqmask; 324 (*uic->uic_mt_intr_enable)(uic->uic_intr_enable); 325 #ifdef IRQ_DEBUG 326 printf("%s: %s: irq=%d, mask=%08x\n", __func__, 327 pic->pic_name, irq, irqmask); 328 #endif 329 } 330 331 static void 332 uic_enable_irq(struct pic_ops *pic, int irq, int type) 333 { 334 struct uic * const uic = pic->pic_cookie; 335 const uint32_t irqmask = IRQ_TO_MASK(irq); 336 if ((uic->uic_intr_enable & irqmask) != 0) 337 return; 338 uic->uic_intr_enable ^= irqmask; 339 (*uic->uic_mt_intr_enable)(uic->uic_intr_enable); 340 #ifdef IRQ_DEBUG 341 printf("%s: %s: irq=%d, mask=%08x\n", __func__, 342 pic->pic_name, irq, irqmask); 343 #endif 344 } 345 346 static void 347 uic_ack_irq(struct pic_ops *pic, int irq) 348 { 349 struct uic * const uic = pic->pic_cookie; 350 const uint32_t irqmask = IRQ_TO_MASK(irq); 351 352 (*uic->uic_mt_intr_ack)(irqmask); 353 } 354 355 static int 356 uic_get_irq(struct pic_ops *pic, int dummy) 357 { 358 struct uic * const uic = pic->pic_cookie; 359 360 const uint32_t irqmask = (*uic->uic_mf_intr_status)(); 361 if (irqmask == 0) 362 return 255; 363 return IRQ_OF_MASK(irqmask); 364 } 365 366 /* 367 * Register an interrupt handler. 368 */ 369 static void 370 uic_establish_irq(struct pic_ops *pic, int irq, int type, int ipl) 371 { 372 } 373
Indexes created Tue Sep 30 17:09:57 GMT 2025