trap.c revision 1.64 1 1.64 rmind /* $NetBSD: trap.c,v 1.64 2012/02/19 21:06:22 rmind Exp $ */
2 1.1 simonb
3 1.1 simonb /*
4 1.1 simonb * Copyright 2001 Wasabi Systems, Inc.
5 1.1 simonb * All rights reserved.
6 1.1 simonb *
7 1.1 simonb * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 1.1 simonb *
9 1.1 simonb * Redistribution and use in source and binary forms, with or without
10 1.1 simonb * modification, are permitted provided that the following conditions
11 1.1 simonb * are met:
12 1.1 simonb * 1. Redistributions of source code must retain the above copyright
13 1.1 simonb * notice, this list of conditions and the following disclaimer.
14 1.1 simonb * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 simonb * notice, this list of conditions and the following disclaimer in the
16 1.1 simonb * documentation and/or other materials provided with the distribution.
17 1.1 simonb * 3. All advertising materials mentioning features or use of this software
18 1.1 simonb * must display the following acknowledgement:
19 1.1 simonb * This product includes software developed for the NetBSD Project by
20 1.1 simonb * Wasabi Systems, Inc.
21 1.1 simonb * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1 simonb * or promote products derived from this software without specific prior
23 1.1 simonb * written permission.
24 1.1 simonb *
25 1.1 simonb * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1 simonb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 simonb * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 simonb * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1 simonb * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 simonb * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 simonb * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 simonb * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 simonb * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 simonb * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 simonb * POSSIBILITY OF SUCH DAMAGE.
36 1.1 simonb */
37 1.1 simonb
38 1.1 simonb /*
39 1.1 simonb * Copyright (C) 1995, 1996 Wolfgang Solfrank.
40 1.1 simonb * Copyright (C) 1995, 1996 TooLs GmbH.
41 1.1 simonb * All rights reserved.
42 1.1 simonb *
43 1.1 simonb * Redistribution and use in source and binary forms, with or without
44 1.1 simonb * modification, are permitted provided that the following conditions
45 1.1 simonb * are met:
46 1.1 simonb * 1. Redistributions of source code must retain the above copyright
47 1.1 simonb * notice, this list of conditions and the following disclaimer.
48 1.1 simonb * 2. Redistributions in binary form must reproduce the above copyright
49 1.1 simonb * notice, this list of conditions and the following disclaimer in the
50 1.1 simonb * documentation and/or other materials provided with the distribution.
51 1.1 simonb * 3. All advertising materials mentioning features or use of this software
52 1.1 simonb * must display the following acknowledgement:
53 1.1 simonb * This product includes software developed by TooLs GmbH.
54 1.1 simonb * 4. The name of TooLs GmbH may not be used to endorse or promote products
55 1.1 simonb * derived from this software without specific prior written permission.
56 1.1 simonb *
57 1.1 simonb * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
58 1.1 simonb * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
59 1.1 simonb * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
60 1.1 simonb * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
61 1.1 simonb * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
62 1.1 simonb * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
63 1.1 simonb * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
64 1.1 simonb * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
65 1.1 simonb * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
66 1.1 simonb * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 1.1 simonb */
68 1.14 lukem
69 1.14 lukem #include <sys/cdefs.h>
70 1.64 rmind __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.64 2012/02/19 21:06:22 rmind Exp $");
71 1.1 simonb
72 1.1 simonb #include "opt_altivec.h"
73 1.1 simonb #include "opt_ddb.h"
74 1.44 garbled #include "opt_kgdb.h"
75 1.1 simonb
76 1.1 simonb #include <sys/param.h>
77 1.1 simonb #include <sys/proc.h>
78 1.1 simonb #include <sys/reboot.h>
79 1.1 simonb #include <sys/syscall.h>
80 1.1 simonb #include <sys/systm.h>
81 1.20 cl #include <sys/userret.h>
82 1.34 yamt #include <sys/kauth.h>
83 1.61 matt #include <sys/cpu.h>
84 1.1 simonb
85 1.44 garbled #if defined(KGDB)
86 1.44 garbled #include <sys/kgdb.h>
87 1.44 garbled #endif
88 1.44 garbled
89 1.1 simonb #include <uvm/uvm_extern.h>
90 1.1 simonb
91 1.1 simonb #include <dev/cons.h>
92 1.1 simonb
93 1.1 simonb #include <machine/fpu.h>
94 1.1 simonb #include <machine/frame.h>
95 1.1 simonb #include <machine/pcb.h>
96 1.1 simonb #include <machine/psl.h>
97 1.1 simonb #include <machine/trap.h>
98 1.1 simonb
99 1.61 matt #include <powerpc/db_machdep.h>
100 1.1 simonb #include <powerpc/spr.h>
101 1.54 matt #include <powerpc/ibm4xx/spr.h>
102 1.61 matt
103 1.61 matt #include <powerpc/ibm4xx/cpu.h>
104 1.1 simonb #include <powerpc/ibm4xx/pmap.h>
105 1.1 simonb #include <powerpc/ibm4xx/tlb.h>
106 1.61 matt
107 1.1 simonb #include <powerpc/fpu/fpu_extern.h>
108 1.1 simonb
109 1.1 simonb /* These definitions should probably be somewhere else XXX */
110 1.1 simonb #define FIRSTARG 3 /* first argument is in reg 3 */
111 1.1 simonb #define NARGREG 8 /* 8 args are in registers */
112 1.40 christos #define MOREARGS(sp) ((void *)((int)(sp) + 8)) /* more args go here */
113 1.1 simonb
114 1.63 kiyohara static int fix_unaligned(struct lwp *l, struct trapframe *tf);
115 1.1 simonb
116 1.50 dsl void trap(struct trapframe *); /* Called from locore / trap_subr */
117 1.1 simonb /* Why are these not defined in a header? */
118 1.50 dsl int badaddr(void *, size_t);
119 1.50 dsl int badaddr_read(void *, size_t, int *);
120 1.50 dsl int ctx_setup(int, int);
121 1.1 simonb
122 1.1 simonb #ifdef DEBUG
123 1.1 simonb #define TDB_ALL 0x1
124 1.1 simonb int trapdebug = /* TDB_ALL */ 0;
125 1.1 simonb #define DBPRINTF(x, y) if (trapdebug & (x)) printf y
126 1.1 simonb #else
127 1.1 simonb #define DBPRINTF(x, y)
128 1.1 simonb #endif
129 1.1 simonb
130 1.1 simonb void
131 1.58 matt trap(struct trapframe *tf)
132 1.1 simonb {
133 1.10 thorpej struct lwp *l = curlwp;
134 1.55 chs struct proc *p = l->l_proc;
135 1.53 rmind struct pcb *pcb;
136 1.58 matt int type = tf->tf_exc;
137 1.1 simonb int ftype, rv;
138 1.18 eeh ksiginfo_t ksi;
139 1.1 simonb
140 1.55 chs KASSERT(l->l_stat == LSONPROC);
141 1.1 simonb
142 1.58 matt if (tf->tf_srr1 & PSL_PR) {
143 1.35 ad LWP_CACHE_CREDS(l, p);
144 1.1 simonb type |= EXC_USER;
145 1.35 ad }
146 1.1 simonb
147 1.1 simonb ftype = VM_PROT_READ;
148 1.1 simonb
149 1.13 simonb DBPRINTF(TDB_ALL, ("trap(%x) at %lx from frame %p &frame %p\n",
150 1.58 matt type, tf->tf_srr0, tf, &tf));
151 1.1 simonb
152 1.1 simonb switch (type) {
153 1.1 simonb case EXC_DEBUG|EXC_USER:
154 1.13 simonb {
155 1.13 simonb int srr2, srr3;
156 1.13 simonb
157 1.28 perry __asm volatile("mfspr %0,0x3f0" :
158 1.13 simonb "=r" (rv), "=r" (srr2), "=r" (srr3) :);
159 1.13 simonb printf("debug reg is %x srr2 %x srr3 %x\n", rv, srr2,
160 1.13 simonb srr3);
161 1.13 simonb /* XXX fall through or break here?! */
162 1.13 simonb }
163 1.1 simonb /*
164 1.1 simonb * DEBUG intr -- probably single-step.
165 1.1 simonb */
166 1.1 simonb case EXC_TRC|EXC_USER:
167 1.58 matt tf->tf_srr1 &= ~PSL_SE;
168 1.19 thorpej KSI_INIT_TRAP(&ksi);
169 1.17 matt ksi.ksi_signo = SIGTRAP;
170 1.17 matt ksi.ksi_trap = EXC_TRC;
171 1.58 matt ksi.ksi_addr = (void *)tf->tf_srr0;
172 1.17 matt trapsignal(l, &ksi);
173 1.1 simonb break;
174 1.7 simonb
175 1.13 simonb /*
176 1.13 simonb * If we could not find and install appropriate TLB entry, fall through.
177 1.13 simonb */
178 1.7 simonb
179 1.1 simonb case EXC_DSI:
180 1.1 simonb /* FALLTHROUGH */
181 1.1 simonb case EXC_DTMISS:
182 1.1 simonb {
183 1.1 simonb struct vm_map *map;
184 1.1 simonb vaddr_t va;
185 1.11 matt struct faultbuf *fb = NULL;
186 1.1 simonb
187 1.58 matt va = tf->tf_dear;
188 1.58 matt if (tf->tf_pid == KERNEL_PID) {
189 1.1 simonb map = kernel_map;
190 1.1 simonb } else {
191 1.1 simonb map = &p->p_vmspace->vm_map;
192 1.1 simonb }
193 1.1 simonb
194 1.58 matt if (tf->tf_esr & (ESR_DST|ESR_DIZ))
195 1.3 chs ftype = VM_PROT_WRITE;
196 1.1 simonb
197 1.13 simonb DBPRINTF(TDB_ALL,
198 1.13 simonb ("trap(EXC_DSI) at %lx %s fault on %p esr %x\n",
199 1.58 matt tf->tf_srr0,
200 1.13 simonb (ftype & VM_PROT_WRITE) ? "write" : "read",
201 1.58 matt (void *)va, tf->tf_esr));
202 1.58 matt
203 1.55 chs pcb = lwp_getpcb(l);
204 1.55 chs fb = pcb->pcb_onfault;
205 1.55 chs pcb->pcb_onfault = NULL;
206 1.32 drochner rv = uvm_fault(map, trunc_page(va), ftype);
207 1.55 chs pcb->pcb_onfault = fb;
208 1.1 simonb if (rv == 0)
209 1.1 simonb goto done;
210 1.55 chs if (fb != NULL) {
211 1.58 matt tf->tf_pid = KERNEL_PID;
212 1.58 matt tf->tf_srr0 = fb->fb_pc;
213 1.58 matt tf->tf_srr1 |= PSL_IR; /* Re-enable IMMU */
214 1.58 matt tf->tf_cr = fb->fb_cr;
215 1.58 matt tf->tf_fixreg[1] = fb->fb_sp;
216 1.58 matt tf->tf_fixreg[2] = fb->fb_r2;
217 1.58 matt tf->tf_fixreg[3] = 1; /* Return TRUE */
218 1.58 matt memcpy(&tf->tf_fixreg[13], fb->fb_fixreg,
219 1.11 matt sizeof(fb->fb_fixreg));
220 1.1 simonb goto done;
221 1.1 simonb }
222 1.1 simonb }
223 1.1 simonb goto brain_damage;
224 1.7 simonb
225 1.1 simonb case EXC_DSI|EXC_USER:
226 1.1 simonb /* FALLTHROUGH */
227 1.1 simonb case EXC_DTMISS|EXC_USER:
228 1.58 matt if (tf->tf_esr & (ESR_DST|ESR_DIZ))
229 1.3 chs ftype = VM_PROT_WRITE;
230 1.1 simonb
231 1.13 simonb DBPRINTF(TDB_ALL,
232 1.13 simonb ("trap(EXC_DSI|EXC_USER) at %lx %s fault on %lx %x\n",
233 1.58 matt tf->tf_srr0, (ftype & VM_PROT_WRITE) ? "write" : "read",
234 1.58 matt tf->tf_dear, tf->tf_esr));
235 1.13 simonb KASSERT(l == curlwp && (l->l_stat == LSONPROC));
236 1.55 chs // KASSERT(curpcb->pcb_onfault == NULL);
237 1.58 matt rv = uvm_fault(&p->p_vmspace->vm_map, trunc_page(tf->tf_dear),
238 1.32 drochner ftype);
239 1.1 simonb if (rv == 0) {
240 1.13 simonb break;
241 1.1 simonb }
242 1.19 thorpej KSI_INIT_TRAP(&ksi);
243 1.17 matt ksi.ksi_signo = SIGSEGV;
244 1.17 matt ksi.ksi_trap = EXC_DSI;
245 1.58 matt ksi.ksi_addr = (void *)tf->tf_dear;
246 1.1 simonb if (rv == ENOMEM) {
247 1.10 thorpej printf("UVM: pid %d (%s) lid %d, uid %d killed: "
248 1.13 simonb "out of swap\n",
249 1.13 simonb p->p_pid, p->p_comm, l->l_lid,
250 1.36 ad l->l_cred ?
251 1.36 ad kauth_cred_geteuid(l->l_cred) : -1);
252 1.17 matt ksi.ksi_signo = SIGKILL;
253 1.1 simonb }
254 1.17 matt trapsignal(l, &ksi);
255 1.1 simonb break;
256 1.15 chs
257 1.1 simonb case EXC_ITMISS|EXC_USER:
258 1.1 simonb case EXC_ISI|EXC_USER:
259 1.15 chs ftype = VM_PROT_EXECUTE;
260 1.13 simonb DBPRINTF(TDB_ALL,
261 1.15 chs ("trap(EXC_ISI|EXC_USER) at %lx execute fault tf %p\n",
262 1.58 matt tf->tf_srr0, tf));
263 1.55 chs // KASSERT(curpcb->pcb_onfault == NULL);
264 1.58 matt rv = uvm_fault(&p->p_vmspace->vm_map, trunc_page(tf->tf_srr0),
265 1.32 drochner ftype);
266 1.1 simonb if (rv == 0) {
267 1.13 simonb break;
268 1.1 simonb }
269 1.19 thorpej KSI_INIT_TRAP(&ksi);
270 1.17 matt ksi.ksi_signo = SIGSEGV;
271 1.17 matt ksi.ksi_trap = EXC_ISI;
272 1.58 matt ksi.ksi_addr = (void *)tf->tf_srr0;
273 1.21 drochner ksi.ksi_code = (rv == EACCES ? SEGV_ACCERR : SEGV_MAPERR);
274 1.17 matt trapsignal(l, &ksi);
275 1.1 simonb break;
276 1.1 simonb
277 1.1 simonb case EXC_AST|EXC_USER:
278 1.62 matt cpu_ast(l, curcpu());
279 1.1 simonb break;
280 1.1 simonb
281 1.1 simonb case EXC_ALI|EXC_USER:
282 1.58 matt if (fix_unaligned(l, tf) != 0) {
283 1.19 thorpej KSI_INIT_TRAP(&ksi);
284 1.17 matt ksi.ksi_signo = SIGBUS;
285 1.17 matt ksi.ksi_trap = EXC_ALI;
286 1.58 matt ksi.ksi_addr = (void *)tf->tf_dear;
287 1.17 matt trapsignal(l, &ksi);
288 1.17 matt } else
289 1.58 matt tf->tf_srr0 += 4;
290 1.1 simonb break;
291 1.1 simonb
292 1.1 simonb case EXC_PGM|EXC_USER:
293 1.7 simonb /*
294 1.7 simonb * Illegal insn:
295 1.1 simonb *
296 1.7 simonb * let's try to see if it's FPU and can be emulated.
297 1.1 simonb */
298 1.57 matt curcpu()->ci_data.cpu_ntrap++;
299 1.53 rmind pcb = lwp_getpcb(l);
300 1.53 rmind
301 1.58 matt if (!(l->l_md.md_flags & MDLWP_USEDFPU)) {
302 1.53 rmind memset(&pcb->pcb_fpu, 0, sizeof(pcb->pcb_fpu));
303 1.58 matt l->l_md.md_flags |= MDLWP_USEDFPU;
304 1.1 simonb }
305 1.1 simonb
306 1.58 matt if ((rv = fpu_emulate(tf, (struct fpreg *)&pcb->pcb_fpu))) {
307 1.19 thorpej KSI_INIT_TRAP(&ksi);
308 1.17 matt ksi.ksi_signo = rv;
309 1.17 matt ksi.ksi_trap = EXC_PGM;
310 1.58 matt ksi.ksi_addr = (void *)tf->tf_srr0;
311 1.17 matt trapsignal(l, &ksi);
312 1.1 simonb }
313 1.1 simonb break;
314 1.1 simonb
315 1.1 simonb case EXC_MCHK:
316 1.1 simonb {
317 1.11 matt struct faultbuf *fb;
318 1.1 simonb
319 1.53 rmind pcb = lwp_getpcb(l);
320 1.53 rmind if ((fb = pcb->pcb_onfault) != NULL) {
321 1.58 matt tf->tf_pid = KERNEL_PID;
322 1.58 matt tf->tf_srr0 = fb->fb_pc;
323 1.58 matt tf->tf_srr1 |= PSL_IR; /* Re-enable IMMU */
324 1.58 matt tf->tf_fixreg[1] = fb->fb_sp;
325 1.58 matt tf->tf_fixreg[2] = fb->fb_r2;
326 1.58 matt tf->tf_fixreg[3] = 1; /* Return TRUE */
327 1.58 matt tf->tf_cr = fb->fb_cr;
328 1.58 matt memcpy(&tf->tf_fixreg[13], fb->fb_fixreg,
329 1.11 matt sizeof(fb->fb_fixreg));
330 1.1 simonb goto done;
331 1.1 simonb }
332 1.1 simonb }
333 1.1 simonb goto brain_damage;
334 1.1 simonb default:
335 1.13 simonb brain_damage:
336 1.58 matt printf("trap type 0x%x at 0x%lx\n", type, tf->tf_srr0);
337 1.44 garbled #if defined(DDB) || defined(KGDB)
338 1.58 matt if (kdb_trap(type, tf))
339 1.1 simonb goto done;
340 1.1 simonb #endif
341 1.1 simonb #ifdef TRAP_PANICWAIT
342 1.1 simonb printf("Press a key to panic.\n");
343 1.1 simonb cngetc();
344 1.1 simonb #endif
345 1.1 simonb panic("trap");
346 1.1 simonb }
347 1.1 simonb
348 1.20 cl /* Invoke MI userret code */
349 1.20 cl mi_userret(l);
350 1.13 simonb done:
351 1.9 thorpej return;
352 1.1 simonb }
353 1.1 simonb
354 1.1 simonb int
355 1.1 simonb ctx_setup(int ctx, int srr1)
356 1.1 simonb {
357 1.1 simonb volatile struct pmap *pm;
358 1.1 simonb
359 1.1 simonb /* Update PID if we're returning to user mode. */
360 1.1 simonb if (srr1 & PSL_PR) {
361 1.1 simonb pm = curproc->p_vmspace->vm_map.pmap;
362 1.1 simonb if (!pm->pm_ctx) {
363 1.26 scw ctx_alloc(__UNVOLATILE(pm));
364 1.1 simonb }
365 1.1 simonb ctx = pm->pm_ctx;
366 1.1 simonb if (srr1 & PSL_SE) {
367 1.1 simonb int dbreg, mask = 0x48000000;
368 1.1 simonb /*
369 1.1 simonb * Set the Internal Debug and
370 1.1 simonb * Instruction Completion bits of
371 1.1 simonb * the DBCR0 register.
372 1.1 simonb *
373 1.1 simonb * XXX this is also used by jtag debuggers...
374 1.1 simonb */
375 1.28 perry __asm volatile("mfspr %0,0x3f2;"
376 1.13 simonb "or %0,%0,%1;"
377 1.13 simonb "mtspr 0x3f2,%0;" :
378 1.13 simonb "=&r" (dbreg) : "r" (mask));
379 1.1 simonb }
380 1.1 simonb }
381 1.1 simonb else if (!ctx) {
382 1.1 simonb ctx = KERNEL_PID;
383 1.1 simonb }
384 1.1 simonb return (ctx);
385 1.1 simonb }
386 1.1 simonb
387 1.1 simonb /*
388 1.1 simonb * Used by copyin()/copyout()
389 1.1 simonb */
390 1.50 dsl extern vaddr_t vmaprange(struct proc *, vaddr_t, vsize_t, int);
391 1.50 dsl extern void vunmaprange(vaddr_t, vsize_t);
392 1.50 dsl static int bigcopyin(const void *, void *, size_t );
393 1.50 dsl static int bigcopyout(const void *, void *, size_t );
394 1.1 simonb
395 1.1 simonb int
396 1.1 simonb copyin(const void *udaddr, void *kaddr, size_t len)
397 1.1 simonb {
398 1.1 simonb struct pmap *pm = curproc->p_vmspace->vm_map.pmap;
399 1.55 chs int rv, msr, pid, tmp, ctx, count = 0;
400 1.11 matt struct faultbuf env;
401 1.1 simonb
402 1.1 simonb /* For bigger buffers use the faster copy */
403 1.46 hpeyerl if (len > 1024)
404 1.25 simonb return (bigcopyin(udaddr, kaddr, len));
405 1.1 simonb
406 1.55 chs if ((rv = setfault(&env))) {
407 1.55 chs curpcb->pcb_onfault = NULL;
408 1.55 chs return rv;
409 1.1 simonb }
410 1.1 simonb
411 1.1 simonb if (!(ctx = pm->pm_ctx)) {
412 1.1 simonb /* No context -- assign it one */
413 1.1 simonb ctx_alloc(pm);
414 1.1 simonb ctx = pm->pm_ctx;
415 1.1 simonb }
416 1.1 simonb
417 1.46 hpeyerl __asm volatile(
418 1.46 hpeyerl " mfmsr %[msr];" /* Save MSR */
419 1.46 hpeyerl " li %[pid],0x20; "
420 1.46 hpeyerl " andc %[pid],%[msr],%[pid]; mtmsr %[pid];" /* Disable IMMU */
421 1.46 hpeyerl " mfpid %[pid];" /* Save old PID */
422 1.46 hpeyerl " sync; isync;"
423 1.46 hpeyerl
424 1.46 hpeyerl " srwi. %[count],%[len],0x2;" /* How many words? */
425 1.46 hpeyerl " beq- 2f;" /* No words. Go do bytes */
426 1.46 hpeyerl " mtctr %[count];"
427 1.46 hpeyerl "1: mtpid %[ctx]; sync;"
428 1.47 simonb " lswi %[tmp],%[udaddr],4;" /* Load user word */
429 1.46 hpeyerl " addi %[udaddr],%[udaddr],0x4;" /* next udaddr word */
430 1.46 hpeyerl " sync; isync;"
431 1.46 hpeyerl " mtpid %[pid];sync;"
432 1.47 simonb " stswi %[tmp],%[kaddr],4;" /* Store kernel word */
433 1.46 hpeyerl " dcbf 0,%[kaddr];" /* flush cache */
434 1.46 hpeyerl " addi %[kaddr],%[kaddr],0x4;" /* next udaddr word */
435 1.46 hpeyerl " sync; isync;"
436 1.46 hpeyerl " bdnz 1b;" /* repeat */
437 1.46 hpeyerl
438 1.46 hpeyerl "2: andi. %[count],%[len],0x3;" /* How many remaining bytes? */
439 1.46 hpeyerl " addi %[count],%[count],0x1;"
440 1.46 hpeyerl " mtctr %[count];"
441 1.46 hpeyerl "3: bdz 10f;" /* while count */
442 1.46 hpeyerl " mtpid %[ctx];sync;"
443 1.46 hpeyerl " lbz %[tmp],0(%[udaddr]);" /* Load user byte */
444 1.46 hpeyerl " addi %[udaddr],%[udaddr],0x1;" /* next udaddr byte */
445 1.46 hpeyerl " sync; isync;"
446 1.46 hpeyerl " mtpid %[pid]; sync;"
447 1.63 kiyohara " stb %[tmp],0(%[kaddr]);" /* Store kernel byte */
448 1.46 hpeyerl " dcbf 0,%[kaddr];" /* flush cache */
449 1.46 hpeyerl " addi %[kaddr],%[kaddr],0x1;"
450 1.46 hpeyerl " sync; isync;"
451 1.46 hpeyerl " b 3b;"
452 1.46 hpeyerl "10:mtpid %[pid]; mtmsr %[msr]; sync; isync;" /* Restore PID and MSR */
453 1.46 hpeyerl : [msr] "=&r" (msr), [pid] "=&r" (pid), [tmp] "=&r" (tmp)
454 1.46 hpeyerl : [udaddr] "b" (udaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr), [len] "b" (len), [count] "b" (count));
455 1.1 simonb
456 1.55 chs curpcb->pcb_onfault = NULL;
457 1.1 simonb return 0;
458 1.1 simonb }
459 1.1 simonb
460 1.1 simonb static int
461 1.1 simonb bigcopyin(const void *udaddr, void *kaddr, size_t len)
462 1.1 simonb {
463 1.1 simonb const char *up;
464 1.1 simonb char *kp = kaddr;
465 1.10 thorpej struct lwp *l = curlwp;
466 1.10 thorpej struct proc *p;
467 1.55 chs struct faultbuf env;
468 1.1 simonb int error;
469 1.1 simonb
470 1.10 thorpej p = l->l_proc;
471 1.10 thorpej
472 1.1 simonb /*
473 1.7 simonb * Stolen from physio():
474 1.1 simonb */
475 1.37 chs error = uvm_vslock(p->p_vmspace, __UNCONST(udaddr), len, VM_PROT_READ);
476 1.1 simonb if (error) {
477 1.55 chs return error;
478 1.1 simonb }
479 1.1 simonb up = (char *)vmaprange(p, (vaddr_t)udaddr, len, VM_PROT_READ);
480 1.1 simonb
481 1.55 chs if ((error = setfault(&env)) == 0) {
482 1.55 chs memcpy(kp, up, len);
483 1.55 chs }
484 1.55 chs
485 1.55 chs curpcb->pcb_onfault = NULL;
486 1.1 simonb vunmaprange((vaddr_t)up, len);
487 1.37 chs uvm_vsunlock(p->p_vmspace, __UNCONST(udaddr), len);
488 1.1 simonb
489 1.55 chs return error;
490 1.1 simonb }
491 1.1 simonb
492 1.1 simonb int
493 1.1 simonb copyout(const void *kaddr, void *udaddr, size_t len)
494 1.1 simonb {
495 1.1 simonb struct pmap *pm = curproc->p_vmspace->vm_map.pmap;
496 1.55 chs int rv, msr, pid, tmp, ctx, count = 0;
497 1.11 matt struct faultbuf env;
498 1.1 simonb
499 1.1 simonb /* For big copies use more efficient routine */
500 1.46 hpeyerl if (len > 1024)
501 1.25 simonb return (bigcopyout(kaddr, udaddr, len));
502 1.1 simonb
503 1.55 chs if ((rv = setfault(&env))) {
504 1.55 chs curpcb->pcb_onfault = NULL;
505 1.55 chs return rv;
506 1.1 simonb }
507 1.1 simonb
508 1.1 simonb if (!(ctx = pm->pm_ctx)) {
509 1.1 simonb /* No context -- assign it one */
510 1.1 simonb ctx_alloc(pm);
511 1.1 simonb ctx = pm->pm_ctx;
512 1.1 simonb }
513 1.1 simonb
514 1.46 hpeyerl __asm volatile(
515 1.46 hpeyerl " mfmsr %[msr];" /* Save MSR */ \
516 1.46 hpeyerl " li %[pid],0x20; " \
517 1.46 hpeyerl " andc %[pid],%[msr],%[pid]; mtmsr %[pid];" /* Disable IMMU */ \
518 1.46 hpeyerl " mfpid %[pid];" /* Save old PID */ \
519 1.46 hpeyerl " sync; isync;"
520 1.46 hpeyerl
521 1.46 hpeyerl " srwi. %[count],%[len],0x2;" /* How many words? */
522 1.46 hpeyerl " beq- 2f;" /* No words. Go do bytes */
523 1.46 hpeyerl " mtctr %[count];"
524 1.46 hpeyerl "1: mtpid %[pid];sync;"
525 1.47 simonb " lswi %[tmp],%[kaddr],4;" /* Load kernel word */
526 1.46 hpeyerl " addi %[kaddr],%[kaddr],0x4;" /* next kaddr word */
527 1.46 hpeyerl " sync; isync;"
528 1.46 hpeyerl " mtpid %[ctx]; sync;"
529 1.47 simonb " stswi %[tmp],%[udaddr],4;" /* Store user word */
530 1.46 hpeyerl " dcbf 0,%[udaddr];" /* flush cache */
531 1.46 hpeyerl " addi %[udaddr],%[udaddr],0x4;" /* next udaddr word */
532 1.46 hpeyerl " sync; isync;"
533 1.46 hpeyerl " bdnz 1b;" /* repeat */
534 1.46 hpeyerl
535 1.46 hpeyerl "2: andi. %[count],%[len],0x3;" /* How many remaining bytes? */
536 1.46 hpeyerl " addi %[count],%[count],0x1;"
537 1.46 hpeyerl " mtctr %[count];"
538 1.46 hpeyerl "3: bdz 10f;" /* while count */
539 1.46 hpeyerl " mtpid %[pid];sync;"
540 1.46 hpeyerl " lbz %[tmp],0(%[kaddr]);" /* Load kernel byte */
541 1.46 hpeyerl " addi %[kaddr],%[kaddr],0x1;" /* next kaddr byte */
542 1.46 hpeyerl " sync; isync;"
543 1.46 hpeyerl " mtpid %[ctx]; sync;"
544 1.46 hpeyerl " stb %[tmp],0(%[udaddr]);" /* Store user byte */
545 1.46 hpeyerl " dcbf 0,%[udaddr];" /* flush cache */
546 1.46 hpeyerl " addi %[udaddr],%[udaddr],0x1;"
547 1.46 hpeyerl " sync; isync;"
548 1.46 hpeyerl " b 3b;"
549 1.46 hpeyerl "10:mtpid %[pid]; mtmsr %[msr]; sync; isync;" /* Restore PID and MSR */
550 1.46 hpeyerl : [msr] "=&r" (msr), [pid] "=&r" (pid), [tmp] "=&r" (tmp)
551 1.63 kiyohara : [udaddr] "b" (udaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr), [len] "b" (len), [count] "b" (count));
552 1.1 simonb
553 1.55 chs curpcb->pcb_onfault = NULL;
554 1.1 simonb return 0;
555 1.1 simonb }
556 1.1 simonb
557 1.1 simonb static int
558 1.1 simonb bigcopyout(const void *kaddr, void *udaddr, size_t len)
559 1.1 simonb {
560 1.1 simonb char *up;
561 1.26 scw const char *kp = (const char *)kaddr;
562 1.10 thorpej struct lwp *l = curlwp;
563 1.10 thorpej struct proc *p;
564 1.55 chs struct faultbuf env;
565 1.1 simonb int error;
566 1.1 simonb
567 1.10 thorpej p = l->l_proc;
568 1.10 thorpej
569 1.1 simonb /*
570 1.7 simonb * Stolen from physio():
571 1.1 simonb */
572 1.37 chs error = uvm_vslock(p->p_vmspace, udaddr, len, VM_PROT_WRITE);
573 1.1 simonb if (error) {
574 1.55 chs return error;
575 1.1 simonb }
576 1.7 simonb up = (char *)vmaprange(p, (vaddr_t)udaddr, len,
577 1.13 simonb VM_PROT_READ | VM_PROT_WRITE);
578 1.1 simonb
579 1.55 chs if ((error = setfault(&env)) == 0) {
580 1.55 chs memcpy(up, kp, len);
581 1.55 chs }
582 1.55 chs
583 1.55 chs curpcb->pcb_onfault = NULL;
584 1.1 simonb vunmaprange((vaddr_t)up, len);
585 1.37 chs uvm_vsunlock(p->p_vmspace, udaddr, len);
586 1.1 simonb
587 1.55 chs return error;
588 1.1 simonb }
589 1.1 simonb
590 1.1 simonb /*
591 1.1 simonb * kcopy(const void *src, void *dst, size_t len);
592 1.1 simonb *
593 1.1 simonb * Copy len bytes from src to dst, aborting if we encounter a fatal
594 1.1 simonb * page fault.
595 1.1 simonb *
596 1.1 simonb * kcopy() _must_ save and restore the old fault handler since it is
597 1.1 simonb * called by uiomove(), which may be in the path of servicing a non-fatal
598 1.1 simonb * page fault.
599 1.1 simonb */
600 1.1 simonb int
601 1.1 simonb kcopy(const void *src, void *dst, size_t len)
602 1.1 simonb {
603 1.11 matt struct faultbuf env, *oldfault;
604 1.55 chs int rv;
605 1.1 simonb
606 1.1 simonb oldfault = curpcb->pcb_onfault;
607 1.55 chs if ((rv = setfault(&env))) {
608 1.1 simonb curpcb->pcb_onfault = oldfault;
609 1.55 chs return rv;
610 1.1 simonb }
611 1.1 simonb
612 1.2 wiz memcpy(dst, src, len);
613 1.1 simonb
614 1.1 simonb curpcb->pcb_onfault = oldfault;
615 1.1 simonb return 0;
616 1.1 simonb }
617 1.1 simonb
618 1.1 simonb int
619 1.1 simonb badaddr(void *addr, size_t size)
620 1.1 simonb {
621 1.1 simonb
622 1.1 simonb return badaddr_read(addr, size, NULL);
623 1.1 simonb }
624 1.1 simonb
625 1.1 simonb int
626 1.1 simonb badaddr_read(void *addr, size_t size, int *rptr)
627 1.1 simonb {
628 1.11 matt struct faultbuf env;
629 1.1 simonb int x;
630 1.1 simonb
631 1.1 simonb /* Get rid of any stale machine checks that have been waiting. */
632 1.28 perry __asm volatile ("sync; isync");
633 1.1 simonb
634 1.11 matt if (setfault(&env)) {
635 1.55 chs curpcb->pcb_onfault = NULL;
636 1.28 perry __asm volatile ("sync");
637 1.1 simonb return 1;
638 1.1 simonb }
639 1.1 simonb
640 1.28 perry __asm volatile ("sync");
641 1.1 simonb
642 1.1 simonb switch (size) {
643 1.1 simonb case 1:
644 1.1 simonb x = *(volatile int8_t *)addr;
645 1.1 simonb break;
646 1.1 simonb case 2:
647 1.1 simonb x = *(volatile int16_t *)addr;
648 1.1 simonb break;
649 1.1 simonb case 4:
650 1.1 simonb x = *(volatile int32_t *)addr;
651 1.1 simonb break;
652 1.1 simonb default:
653 1.1 simonb panic("badaddr: invalid size (%d)", size);
654 1.1 simonb }
655 1.1 simonb
656 1.1 simonb /* Make sure we took the machine check, if we caused one. */
657 1.28 perry __asm volatile ("sync; isync");
658 1.1 simonb
659 1.55 chs curpcb->pcb_onfault = NULL;
660 1.28 perry __asm volatile ("sync"); /* To be sure. */
661 1.1 simonb
662 1.1 simonb /* Use the value to avoid reorder. */
663 1.1 simonb if (rptr)
664 1.1 simonb *rptr = x;
665 1.1 simonb
666 1.1 simonb return 0;
667 1.1 simonb }
668 1.1 simonb
669 1.1 simonb /*
670 1.1 simonb * For now, this only deals with the particular unaligned access case
671 1.1 simonb * that gcc tends to generate. Eventually it should handle all of the
672 1.1 simonb * possibilities that can happen on a 32-bit PowerPC in big-endian mode.
673 1.1 simonb */
674 1.1 simonb
675 1.1 simonb static int
676 1.58 matt fix_unaligned(struct lwp *l, struct trapframe *tf)
677 1.1 simonb {
678 1.1 simonb
679 1.1 simonb return -1;
680 1.10 thorpej }
681