trap.c revision 1.85.2.1 1 1.85.2.1 thorpej /* $NetBSD: trap.c,v 1.85.2.1 2021/04/03 22:28:34 thorpej Exp $ */
2 1.1 simonb
3 1.1 simonb /*
4 1.1 simonb * Copyright 2001 Wasabi Systems, Inc.
5 1.1 simonb * All rights reserved.
6 1.1 simonb *
7 1.1 simonb * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 1.1 simonb *
9 1.1 simonb * Redistribution and use in source and binary forms, with or without
10 1.1 simonb * modification, are permitted provided that the following conditions
11 1.1 simonb * are met:
12 1.1 simonb * 1. Redistributions of source code must retain the above copyright
13 1.1 simonb * notice, this list of conditions and the following disclaimer.
14 1.1 simonb * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 simonb * notice, this list of conditions and the following disclaimer in the
16 1.1 simonb * documentation and/or other materials provided with the distribution.
17 1.1 simonb * 3. All advertising materials mentioning features or use of this software
18 1.1 simonb * must display the following acknowledgement:
19 1.1 simonb * This product includes software developed for the NetBSD Project by
20 1.1 simonb * Wasabi Systems, Inc.
21 1.1 simonb * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1 simonb * or promote products derived from this software without specific prior
23 1.1 simonb * written permission.
24 1.1 simonb *
25 1.1 simonb * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1 simonb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 simonb * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 simonb * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1 simonb * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 simonb * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 simonb * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 simonb * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 simonb * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 simonb * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 simonb * POSSIBILITY OF SUCH DAMAGE.
36 1.1 simonb */
37 1.1 simonb
38 1.1 simonb /*
39 1.1 simonb * Copyright (C) 1995, 1996 Wolfgang Solfrank.
40 1.1 simonb * Copyright (C) 1995, 1996 TooLs GmbH.
41 1.1 simonb * All rights reserved.
42 1.1 simonb *
43 1.1 simonb * Redistribution and use in source and binary forms, with or without
44 1.1 simonb * modification, are permitted provided that the following conditions
45 1.1 simonb * are met:
46 1.1 simonb * 1. Redistributions of source code must retain the above copyright
47 1.1 simonb * notice, this list of conditions and the following disclaimer.
48 1.1 simonb * 2. Redistributions in binary form must reproduce the above copyright
49 1.1 simonb * notice, this list of conditions and the following disclaimer in the
50 1.1 simonb * documentation and/or other materials provided with the distribution.
51 1.1 simonb * 3. All advertising materials mentioning features or use of this software
52 1.1 simonb * must display the following acknowledgement:
53 1.1 simonb * This product includes software developed by TooLs GmbH.
54 1.1 simonb * 4. The name of TooLs GmbH may not be used to endorse or promote products
55 1.1 simonb * derived from this software without specific prior written permission.
56 1.1 simonb *
57 1.1 simonb * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
58 1.1 simonb * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
59 1.1 simonb * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
60 1.1 simonb * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
61 1.1 simonb * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
62 1.1 simonb * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
63 1.1 simonb * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
64 1.1 simonb * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
65 1.1 simonb * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
66 1.1 simonb * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 1.1 simonb */
68 1.14 lukem
69 1.82 rin #define __UFETCHSTORE_PRIVATE
70 1.82 rin
71 1.14 lukem #include <sys/cdefs.h>
72 1.85.2.1 thorpej __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.85.2.1 2021/04/03 22:28:34 thorpej Exp $");
73 1.1 simonb
74 1.82 rin #ifdef _KERNEL_OPT
75 1.1 simonb #include "opt_ddb.h"
76 1.44 garbled #include "opt_kgdb.h"
77 1.83 rin #include "opt_ppcarch.h"
78 1.82 rin #endif
79 1.70 thorpej
80 1.1 simonb #include <sys/param.h>
81 1.72 rin #include <sys/cpu.h>
82 1.72 rin #include <sys/kauth.h>
83 1.1 simonb #include <sys/proc.h>
84 1.85.2.1 thorpej #include <sys/ptrace.h>
85 1.1 simonb #include <sys/reboot.h>
86 1.1 simonb #include <sys/syscall.h>
87 1.1 simonb #include <sys/systm.h>
88 1.1 simonb
89 1.44 garbled #if defined(KGDB)
90 1.44 garbled #include <sys/kgdb.h>
91 1.44 garbled #endif
92 1.44 garbled
93 1.1 simonb #include <uvm/uvm_extern.h>
94 1.1 simonb
95 1.1 simonb #include <dev/cons.h>
96 1.1 simonb
97 1.1 simonb #include <machine/fpu.h>
98 1.1 simonb #include <machine/frame.h>
99 1.1 simonb #include <machine/pcb.h>
100 1.1 simonb #include <machine/psl.h>
101 1.1 simonb #include <machine/trap.h>
102 1.1 simonb
103 1.61 matt #include <powerpc/db_machdep.h>
104 1.1 simonb #include <powerpc/spr.h>
105 1.74 rin #include <powerpc/userret.h>
106 1.61 matt
107 1.61 matt #include <powerpc/ibm4xx/cpu.h>
108 1.1 simonb #include <powerpc/ibm4xx/pmap.h>
109 1.71 rin #include <powerpc/ibm4xx/spr.h>
110 1.1 simonb #include <powerpc/ibm4xx/tlb.h>
111 1.61 matt
112 1.1 simonb #include <powerpc/fpu/fpu_extern.h>
113 1.1 simonb
114 1.1 simonb /* These definitions should probably be somewhere else XXX */
115 1.1 simonb #define FIRSTARG 3 /* first argument is in reg 3 */
116 1.1 simonb #define NARGREG 8 /* 8 args are in registers */
117 1.40 christos #define MOREARGS(sp) ((void *)((int)(sp) + 8)) /* more args go here */
118 1.1 simonb
119 1.63 kiyohara static int fix_unaligned(struct lwp *l, struct trapframe *tf);
120 1.1 simonb
121 1.50 dsl void trap(struct trapframe *); /* Called from locore / trap_subr */
122 1.75 rin #if 0
123 1.75 rin /* Not currently used nor exposed externally in any header file */
124 1.50 dsl int badaddr(void *, size_t);
125 1.50 dsl int badaddr_read(void *, size_t, int *);
126 1.75 rin #endif
127 1.50 dsl int ctx_setup(int, int);
128 1.1 simonb
129 1.1 simonb #ifdef DEBUG
130 1.1 simonb #define TDB_ALL 0x1
131 1.1 simonb int trapdebug = /* TDB_ALL */ 0;
132 1.1 simonb #define DBPRINTF(x, y) if (trapdebug & (x)) printf y
133 1.1 simonb #else
134 1.1 simonb #define DBPRINTF(x, y)
135 1.1 simonb #endif
136 1.1 simonb
137 1.1 simonb void
138 1.58 matt trap(struct trapframe *tf)
139 1.1 simonb {
140 1.10 thorpej struct lwp *l = curlwp;
141 1.55 chs struct proc *p = l->l_proc;
142 1.53 rmind struct pcb *pcb;
143 1.58 matt int type = tf->tf_exc;
144 1.1 simonb int ftype, rv;
145 1.18 eeh ksiginfo_t ksi;
146 1.1 simonb
147 1.55 chs KASSERT(l->l_stat == LSONPROC);
148 1.1 simonb
149 1.58 matt if (tf->tf_srr1 & PSL_PR) {
150 1.35 ad LWP_CACHE_CREDS(l, p);
151 1.1 simonb type |= EXC_USER;
152 1.35 ad }
153 1.1 simonb
154 1.1 simonb ftype = VM_PROT_READ;
155 1.1 simonb
156 1.13 simonb DBPRINTF(TDB_ALL, ("trap(%x) at %lx from frame %p &frame %p\n",
157 1.58 matt type, tf->tf_srr0, tf, &tf));
158 1.1 simonb
159 1.1 simonb switch (type) {
160 1.1 simonb case EXC_DEBUG|EXC_USER:
161 1.85.2.1 thorpej /* We don't use hardware breakpoints for userland. */
162 1.85.2.1 thorpej goto brain_damage;
163 1.13 simonb
164 1.1 simonb case EXC_TRC|EXC_USER:
165 1.19 thorpej KSI_INIT_TRAP(&ksi);
166 1.17 matt ksi.ksi_signo = SIGTRAP;
167 1.17 matt ksi.ksi_trap = EXC_TRC;
168 1.58 matt ksi.ksi_addr = (void *)tf->tf_srr0;
169 1.17 matt trapsignal(l, &ksi);
170 1.1 simonb break;
171 1.7 simonb
172 1.1 simonb case EXC_DSI:
173 1.1 simonb /* FALLTHROUGH */
174 1.1 simonb case EXC_DTMISS:
175 1.1 simonb {
176 1.1 simonb struct vm_map *map;
177 1.1 simonb vaddr_t va;
178 1.78 rin struct faultbuf *fb;
179 1.78 rin
180 1.78 rin pcb = lwp_getpcb(l);
181 1.78 rin fb = pcb->pcb_onfault;
182 1.78 rin
183 1.78 rin if (curcpu()->ci_idepth >= 0) {
184 1.78 rin rv = EFAULT;
185 1.78 rin goto out;
186 1.78 rin }
187 1.1 simonb
188 1.58 matt va = tf->tf_dear;
189 1.58 matt if (tf->tf_pid == KERNEL_PID) {
190 1.1 simonb map = kernel_map;
191 1.1 simonb } else {
192 1.1 simonb map = &p->p_vmspace->vm_map;
193 1.1 simonb }
194 1.1 simonb
195 1.58 matt if (tf->tf_esr & (ESR_DST|ESR_DIZ))
196 1.3 chs ftype = VM_PROT_WRITE;
197 1.1 simonb
198 1.13 simonb DBPRINTF(TDB_ALL,
199 1.13 simonb ("trap(EXC_DSI) at %lx %s fault on %p esr %x\n",
200 1.58 matt tf->tf_srr0,
201 1.13 simonb (ftype & VM_PROT_WRITE) ? "write" : "read",
202 1.58 matt (void *)va, tf->tf_esr));
203 1.58 matt
204 1.55 chs pcb->pcb_onfault = NULL;
205 1.32 drochner rv = uvm_fault(map, trunc_page(va), ftype);
206 1.55 chs pcb->pcb_onfault = fb;
207 1.1 simonb if (rv == 0)
208 1.68 rin return;
209 1.78 rin out:
210 1.55 chs if (fb != NULL) {
211 1.58 matt tf->tf_pid = KERNEL_PID;
212 1.58 matt tf->tf_srr0 = fb->fb_pc;
213 1.58 matt tf->tf_srr1 |= PSL_IR; /* Re-enable IMMU */
214 1.58 matt tf->tf_cr = fb->fb_cr;
215 1.58 matt tf->tf_fixreg[1] = fb->fb_sp;
216 1.58 matt tf->tf_fixreg[2] = fb->fb_r2;
217 1.79 rin tf->tf_fixreg[3] = rv;
218 1.58 matt memcpy(&tf->tf_fixreg[13], fb->fb_fixreg,
219 1.11 matt sizeof(fb->fb_fixreg));
220 1.68 rin return;
221 1.1 simonb }
222 1.1 simonb }
223 1.1 simonb goto brain_damage;
224 1.7 simonb
225 1.1 simonb case EXC_DSI|EXC_USER:
226 1.1 simonb /* FALLTHROUGH */
227 1.1 simonb case EXC_DTMISS|EXC_USER:
228 1.58 matt if (tf->tf_esr & (ESR_DST|ESR_DIZ))
229 1.3 chs ftype = VM_PROT_WRITE;
230 1.1 simonb
231 1.13 simonb DBPRINTF(TDB_ALL,
232 1.13 simonb ("trap(EXC_DSI|EXC_USER) at %lx %s fault on %lx %x\n",
233 1.58 matt tf->tf_srr0, (ftype & VM_PROT_WRITE) ? "write" : "read",
234 1.58 matt tf->tf_dear, tf->tf_esr));
235 1.13 simonb KASSERT(l == curlwp && (l->l_stat == LSONPROC));
236 1.55 chs // KASSERT(curpcb->pcb_onfault == NULL);
237 1.58 matt rv = uvm_fault(&p->p_vmspace->vm_map, trunc_page(tf->tf_dear),
238 1.32 drochner ftype);
239 1.1 simonb if (rv == 0) {
240 1.13 simonb break;
241 1.1 simonb }
242 1.19 thorpej KSI_INIT_TRAP(&ksi);
243 1.17 matt ksi.ksi_trap = EXC_DSI;
244 1.58 matt ksi.ksi_addr = (void *)tf->tf_dear;
245 1.80 rin vm_signal:
246 1.80 rin switch (rv) {
247 1.80 rin case EINVAL:
248 1.80 rin ksi.ksi_signo = SIGBUS;
249 1.80 rin ksi.ksi_code = BUS_ADRERR;
250 1.80 rin break;
251 1.80 rin case EACCES:
252 1.80 rin ksi.ksi_signo = SIGSEGV;
253 1.80 rin ksi.ksi_code = SEGV_ACCERR;
254 1.80 rin break;
255 1.80 rin case ENOMEM:
256 1.17 matt ksi.ksi_signo = SIGKILL;
257 1.80 rin printf("UVM: pid %d.%d (%s), uid %d killed: "
258 1.80 rin "out of swap\n", p->p_pid, l->l_lid, p->p_comm,
259 1.80 rin l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
260 1.80 rin break;
261 1.80 rin default:
262 1.80 rin ksi.ksi_signo = SIGSEGV;
263 1.80 rin ksi.ksi_code = SEGV_MAPERR;
264 1.80 rin break;
265 1.1 simonb }
266 1.17 matt trapsignal(l, &ksi);
267 1.1 simonb break;
268 1.15 chs
269 1.1 simonb case EXC_ITMISS|EXC_USER:
270 1.1 simonb case EXC_ISI|EXC_USER:
271 1.15 chs ftype = VM_PROT_EXECUTE;
272 1.13 simonb DBPRINTF(TDB_ALL,
273 1.15 chs ("trap(EXC_ISI|EXC_USER) at %lx execute fault tf %p\n",
274 1.58 matt tf->tf_srr0, tf));
275 1.55 chs // KASSERT(curpcb->pcb_onfault == NULL);
276 1.58 matt rv = uvm_fault(&p->p_vmspace->vm_map, trunc_page(tf->tf_srr0),
277 1.32 drochner ftype);
278 1.1 simonb if (rv == 0) {
279 1.13 simonb break;
280 1.1 simonb }
281 1.85 rin isi:
282 1.19 thorpej KSI_INIT_TRAP(&ksi);
283 1.17 matt ksi.ksi_trap = EXC_ISI;
284 1.58 matt ksi.ksi_addr = (void *)tf->tf_srr0;
285 1.80 rin goto vm_signal;
286 1.1 simonb break;
287 1.1 simonb
288 1.1 simonb case EXC_AST|EXC_USER:
289 1.62 matt cpu_ast(l, curcpu());
290 1.1 simonb break;
291 1.1 simonb
292 1.1 simonb case EXC_ALI|EXC_USER:
293 1.58 matt if (fix_unaligned(l, tf) != 0) {
294 1.19 thorpej KSI_INIT_TRAP(&ksi);
295 1.17 matt ksi.ksi_signo = SIGBUS;
296 1.17 matt ksi.ksi_trap = EXC_ALI;
297 1.58 matt ksi.ksi_addr = (void *)tf->tf_dear;
298 1.17 matt trapsignal(l, &ksi);
299 1.17 matt } else
300 1.58 matt tf->tf_srr0 += 4;
301 1.1 simonb break;
302 1.1 simonb
303 1.1 simonb case EXC_PGM|EXC_USER:
304 1.57 matt curcpu()->ci_data.cpu_ntrap++;
305 1.53 rmind
306 1.84 rin KSI_INIT_TRAP(&ksi);
307 1.84 rin ksi.ksi_trap = EXC_PGM;
308 1.84 rin ksi.ksi_addr = (void *)tf->tf_srr0;
309 1.1 simonb
310 1.84 rin if (tf->tf_esr & ESR_PTR) {
311 1.85.2.1 thorpej vaddr_t va;
312 1.84 rin sigtrap:
313 1.85.2.1 thorpej va = (vaddr_t)tf->tf_srr0;
314 1.85.2.1 thorpej /*
315 1.85.2.1 thorpej * Restore original instruction and clear BP.
316 1.85.2.1 thorpej */
317 1.85.2.1 thorpej if (p->p_md.md_ss_addr[0] == va ||
318 1.85.2.1 thorpej p->p_md.md_ss_addr[1] == va) {
319 1.85.2.1 thorpej rv = ppc_sstep(l, 0);
320 1.85.2.1 thorpej if (rv != 0)
321 1.85.2.1 thorpej goto vm_signal;
322 1.85.2.1 thorpej ksi.ksi_code = TRAP_TRACE;
323 1.85.2.1 thorpej } else
324 1.85.2.1 thorpej ksi.ksi_code = TRAP_BRKPT;
325 1.84 rin if (p->p_raslist != NULL &&
326 1.85.2.1 thorpej ras_lookup(p, (void *)va) != (void *)-1) {
327 1.85.2.1 thorpej tf->tf_srr0 += (ksi.ksi_code == TRAP_TRACE) ?
328 1.85.2.1 thorpej 0 : 4;
329 1.65 matt break;
330 1.84 rin }
331 1.84 rin ksi.ksi_signo = SIGTRAP;
332 1.85 rin } else if (tf->tf_esr & ESR_PPR) {
333 1.85 rin uint32_t opcode;
334 1.85 rin
335 1.85 rin rv = copyin((void *)tf->tf_srr0, &opcode,
336 1.85 rin sizeof(opcode));
337 1.85 rin if (rv)
338 1.85 rin goto isi;
339 1.85 rin if (emulate_mxmsr(l, tf, opcode)) {
340 1.85 rin tf->tf_srr0 += 4;
341 1.85 rin break;
342 1.85 rin }
343 1.85 rin
344 1.85 rin ksi.ksi_code = ILL_PRVOPC;
345 1.85 rin ksi.ksi_signo = SIGILL;
346 1.65 matt } else {
347 1.84 rin pcb = lwp_getpcb(l);
348 1.84 rin
349 1.84 rin if (__predict_false(!fpu_used_p(l))) {
350 1.84 rin memset(&pcb->pcb_fpu, 0, sizeof(pcb->pcb_fpu));
351 1.84 rin fpu_mark_used(l);
352 1.84 rin }
353 1.84 rin
354 1.84 rin if (fpu_emulate(tf, &pcb->pcb_fpu, &ksi)) {
355 1.84 rin if (ksi.ksi_signo == 0) /* was emulated */
356 1.84 rin break;
357 1.84 rin else if (ksi.ksi_signo == SIGTRAP)
358 1.84 rin goto sigtrap; /* XXX H/W bug? */
359 1.84 rin } else {
360 1.84 rin ksi.ksi_code = ILL_ILLOPC;
361 1.84 rin ksi.ksi_signo = SIGILL;
362 1.84 rin }
363 1.1 simonb }
364 1.65 matt
365 1.65 matt trapsignal(l, &ksi);
366 1.1 simonb break;
367 1.1 simonb
368 1.1 simonb case EXC_MCHK:
369 1.1 simonb {
370 1.11 matt struct faultbuf *fb;
371 1.1 simonb
372 1.53 rmind pcb = lwp_getpcb(l);
373 1.53 rmind if ((fb = pcb->pcb_onfault) != NULL) {
374 1.58 matt tf->tf_pid = KERNEL_PID;
375 1.58 matt tf->tf_srr0 = fb->fb_pc;
376 1.58 matt tf->tf_srr1 |= PSL_IR; /* Re-enable IMMU */
377 1.58 matt tf->tf_fixreg[1] = fb->fb_sp;
378 1.58 matt tf->tf_fixreg[2] = fb->fb_r2;
379 1.58 matt tf->tf_fixreg[3] = 1; /* Return TRUE */
380 1.58 matt tf->tf_cr = fb->fb_cr;
381 1.58 matt memcpy(&tf->tf_fixreg[13], fb->fb_fixreg,
382 1.11 matt sizeof(fb->fb_fixreg));
383 1.68 rin return;
384 1.1 simonb }
385 1.1 simonb }
386 1.1 simonb goto brain_damage;
387 1.68 rin
388 1.1 simonb default:
389 1.68 rin brain_damage:
390 1.58 matt printf("trap type 0x%x at 0x%lx\n", type, tf->tf_srr0);
391 1.44 garbled #if defined(DDB) || defined(KGDB)
392 1.58 matt if (kdb_trap(type, tf))
393 1.68 rin return;
394 1.1 simonb #endif
395 1.1 simonb #ifdef TRAP_PANICWAIT
396 1.1 simonb printf("Press a key to panic.\n");
397 1.1 simonb cngetc();
398 1.1 simonb #endif
399 1.1 simonb panic("trap");
400 1.1 simonb }
401 1.1 simonb
402 1.73 rin /* Invoke powerpc userret code */
403 1.73 rin userret(l, tf);
404 1.1 simonb }
405 1.1 simonb
406 1.1 simonb int
407 1.1 simonb ctx_setup(int ctx, int srr1)
408 1.1 simonb {
409 1.1 simonb volatile struct pmap *pm;
410 1.1 simonb
411 1.1 simonb /* Update PID if we're returning to user mode. */
412 1.1 simonb if (srr1 & PSL_PR) {
413 1.1 simonb pm = curproc->p_vmspace->vm_map.pmap;
414 1.1 simonb if (!pm->pm_ctx) {
415 1.26 scw ctx_alloc(__UNVOLATILE(pm));
416 1.1 simonb }
417 1.1 simonb ctx = pm->pm_ctx;
418 1.1 simonb }
419 1.1 simonb else if (!ctx) {
420 1.1 simonb ctx = KERNEL_PID;
421 1.1 simonb }
422 1.1 simonb return (ctx);
423 1.1 simonb }
424 1.1 simonb
425 1.1 simonb /*
426 1.1 simonb * Used by copyin()/copyout()
427 1.1 simonb */
428 1.50 dsl extern vaddr_t vmaprange(struct proc *, vaddr_t, vsize_t, int);
429 1.50 dsl extern void vunmaprange(vaddr_t, vsize_t);
430 1.50 dsl static int bigcopyin(const void *, void *, size_t );
431 1.50 dsl static int bigcopyout(const void *, void *, size_t );
432 1.1 simonb
433 1.1 simonb int
434 1.1 simonb copyin(const void *udaddr, void *kaddr, size_t len)
435 1.1 simonb {
436 1.1 simonb struct pmap *pm = curproc->p_vmspace->vm_map.pmap;
437 1.55 chs int rv, msr, pid, tmp, ctx, count = 0;
438 1.11 matt struct faultbuf env;
439 1.1 simonb
440 1.1 simonb /* For bigger buffers use the faster copy */
441 1.46 hpeyerl if (len > 1024)
442 1.25 simonb return (bigcopyin(udaddr, kaddr, len));
443 1.1 simonb
444 1.55 chs if ((rv = setfault(&env))) {
445 1.55 chs curpcb->pcb_onfault = NULL;
446 1.55 chs return rv;
447 1.1 simonb }
448 1.1 simonb
449 1.1 simonb if (!(ctx = pm->pm_ctx)) {
450 1.1 simonb /* No context -- assign it one */
451 1.1 simonb ctx_alloc(pm);
452 1.1 simonb ctx = pm->pm_ctx;
453 1.1 simonb }
454 1.1 simonb
455 1.46 hpeyerl __asm volatile(
456 1.76 rin " mfmsr %[msr];" /* Save MSR */
457 1.76 rin " li %[pid],0x20;"
458 1.76 rin " andc %[pid],%[msr],%[pid]; mtmsr %[pid];" /* Disable IMMU */
459 1.81 rin " isync;"
460 1.76 rin " mfpid %[pid];" /* Save old PID */
461 1.46 hpeyerl
462 1.76 rin " srwi. %[count],%[len],0x2;" /* How many words? */
463 1.76 rin " beq- 2f;" /* No words. Go do bytes */
464 1.46 hpeyerl " mtctr %[count];"
465 1.81 rin "1: mtpid %[ctx]; isync;"
466 1.77 rin #ifdef PPC_IBM403
467 1.76 rin " lswi %[tmp],%[udaddr],4;" /* Load user word */
468 1.77 rin #else
469 1.77 rin " lwz %[tmp],0(%[udaddr]);"
470 1.77 rin #endif
471 1.76 rin " addi %[udaddr],%[udaddr],0x4;" /* next udaddr word */
472 1.81 rin " sync;"
473 1.81 rin " mtpid %[pid]; isync;"
474 1.77 rin #ifdef PPC_IBM403
475 1.76 rin " stswi %[tmp],%[kaddr],4;" /* Store kernel word */
476 1.77 rin #else
477 1.77 rin " stw %[tmp],0(%[kaddr]);"
478 1.77 rin #endif
479 1.77 rin " dcbst 0,%[kaddr];" /* flush cache */
480 1.76 rin " addi %[kaddr],%[kaddr],0x4;" /* next udaddr word */
481 1.81 rin " sync;"
482 1.76 rin " bdnz 1b;" /* repeat */
483 1.46 hpeyerl
484 1.76 rin "2: andi. %[count],%[len],0x3;" /* How many remaining bytes? */
485 1.46 hpeyerl " addi %[count],%[count],0x1;"
486 1.46 hpeyerl " mtctr %[count];"
487 1.76 rin "3: bdz 10f;" /* while count */
488 1.81 rin " mtpid %[ctx]; isync;"
489 1.76 rin " lbz %[tmp],0(%[udaddr]);" /* Load user byte */
490 1.76 rin " addi %[udaddr],%[udaddr],0x1;" /* next udaddr byte */
491 1.81 rin " sync;"
492 1.81 rin " mtpid %[pid]; isync;"
493 1.76 rin " stb %[tmp],0(%[kaddr]);" /* Store kernel byte */
494 1.77 rin " dcbst 0,%[kaddr];" /* flush cache */
495 1.46 hpeyerl " addi %[kaddr],%[kaddr],0x1;"
496 1.81 rin " sync;"
497 1.46 hpeyerl " b 3b;"
498 1.81 rin "10:mtpid %[pid]; mtmsr %[msr]; isync;"
499 1.76 rin /* Restore PID and MSR */
500 1.46 hpeyerl : [msr] "=&r" (msr), [pid] "=&r" (pid), [tmp] "=&r" (tmp)
501 1.76 rin : [udaddr] "b" (udaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr),
502 1.76 rin [len] "b" (len), [count] "b" (count));
503 1.1 simonb
504 1.55 chs curpcb->pcb_onfault = NULL;
505 1.1 simonb return 0;
506 1.1 simonb }
507 1.1 simonb
508 1.1 simonb static int
509 1.1 simonb bigcopyin(const void *udaddr, void *kaddr, size_t len)
510 1.1 simonb {
511 1.1 simonb const char *up;
512 1.1 simonb char *kp = kaddr;
513 1.10 thorpej struct lwp *l = curlwp;
514 1.10 thorpej struct proc *p;
515 1.55 chs struct faultbuf env;
516 1.1 simonb int error;
517 1.1 simonb
518 1.10 thorpej p = l->l_proc;
519 1.10 thorpej
520 1.1 simonb /*
521 1.7 simonb * Stolen from physio():
522 1.1 simonb */
523 1.37 chs error = uvm_vslock(p->p_vmspace, __UNCONST(udaddr), len, VM_PROT_READ);
524 1.1 simonb if (error) {
525 1.55 chs return error;
526 1.1 simonb }
527 1.1 simonb up = (char *)vmaprange(p, (vaddr_t)udaddr, len, VM_PROT_READ);
528 1.1 simonb
529 1.55 chs if ((error = setfault(&env)) == 0) {
530 1.55 chs memcpy(kp, up, len);
531 1.55 chs }
532 1.55 chs
533 1.55 chs curpcb->pcb_onfault = NULL;
534 1.1 simonb vunmaprange((vaddr_t)up, len);
535 1.37 chs uvm_vsunlock(p->p_vmspace, __UNCONST(udaddr), len);
536 1.1 simonb
537 1.55 chs return error;
538 1.1 simonb }
539 1.1 simonb
540 1.1 simonb int
541 1.1 simonb copyout(const void *kaddr, void *udaddr, size_t len)
542 1.1 simonb {
543 1.1 simonb struct pmap *pm = curproc->p_vmspace->vm_map.pmap;
544 1.55 chs int rv, msr, pid, tmp, ctx, count = 0;
545 1.11 matt struct faultbuf env;
546 1.1 simonb
547 1.1 simonb /* For big copies use more efficient routine */
548 1.46 hpeyerl if (len > 1024)
549 1.25 simonb return (bigcopyout(kaddr, udaddr, len));
550 1.1 simonb
551 1.55 chs if ((rv = setfault(&env))) {
552 1.55 chs curpcb->pcb_onfault = NULL;
553 1.55 chs return rv;
554 1.1 simonb }
555 1.1 simonb
556 1.1 simonb if (!(ctx = pm->pm_ctx)) {
557 1.1 simonb /* No context -- assign it one */
558 1.1 simonb ctx_alloc(pm);
559 1.1 simonb ctx = pm->pm_ctx;
560 1.1 simonb }
561 1.1 simonb
562 1.46 hpeyerl __asm volatile(
563 1.76 rin " mfmsr %[msr];" /* Save MSR */
564 1.76 rin " li %[pid],0x20;"
565 1.76 rin " andc %[pid],%[msr],%[pid]; mtmsr %[pid];" /* Disable IMMU */
566 1.81 rin " isync;"
567 1.76 rin " mfpid %[pid];" /* Save old PID */
568 1.46 hpeyerl
569 1.76 rin " srwi. %[count],%[len],0x2;" /* How many words? */
570 1.76 rin " beq- 2f;" /* No words. Go do bytes */
571 1.46 hpeyerl " mtctr %[count];"
572 1.81 rin "1: mtpid %[pid]; isync;"
573 1.77 rin #ifdef PPC_IBM403
574 1.76 rin " lswi %[tmp],%[kaddr],4;" /* Load kernel word */
575 1.77 rin #else
576 1.77 rin " lwz %[tmp],0(%[kaddr]);"
577 1.77 rin #endif
578 1.76 rin " addi %[kaddr],%[kaddr],0x4;" /* next kaddr word */
579 1.81 rin " sync;"
580 1.81 rin " mtpid %[ctx]; isync;"
581 1.77 rin #ifdef PPC_IBM403
582 1.76 rin " stswi %[tmp],%[udaddr],4;" /* Store user word */
583 1.77 rin #else
584 1.77 rin " stw %[tmp],0(%[udaddr]);"
585 1.77 rin #endif
586 1.77 rin " dcbst 0,%[udaddr];" /* flush cache */
587 1.76 rin " addi %[udaddr],%[udaddr],0x4;" /* next udaddr word */
588 1.81 rin " sync;"
589 1.76 rin " bdnz 1b;" /* repeat */
590 1.46 hpeyerl
591 1.76 rin "2: andi. %[count],%[len],0x3;" /* How many remaining bytes? */
592 1.46 hpeyerl " addi %[count],%[count],0x1;"
593 1.46 hpeyerl " mtctr %[count];"
594 1.76 rin "3: bdz 10f;" /* while count */
595 1.81 rin " mtpid %[pid]; isync;"
596 1.76 rin " lbz %[tmp],0(%[kaddr]);" /* Load kernel byte */
597 1.76 rin " addi %[kaddr],%[kaddr],0x1;" /* next kaddr byte */
598 1.81 rin " sync;"
599 1.81 rin " mtpid %[ctx]; isync;"
600 1.76 rin " stb %[tmp],0(%[udaddr]);" /* Store user byte */
601 1.77 rin " dcbst 0,%[udaddr];" /* flush cache */
602 1.46 hpeyerl " addi %[udaddr],%[udaddr],0x1;"
603 1.81 rin " sync;"
604 1.46 hpeyerl " b 3b;"
605 1.81 rin "10:mtpid %[pid]; mtmsr %[msr]; isync;"
606 1.76 rin /* Restore PID and MSR */
607 1.46 hpeyerl : [msr] "=&r" (msr), [pid] "=&r" (pid), [tmp] "=&r" (tmp)
608 1.76 rin : [udaddr] "b" (udaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr),
609 1.76 rin [len] "b" (len), [count] "b" (count));
610 1.1 simonb
611 1.55 chs curpcb->pcb_onfault = NULL;
612 1.1 simonb return 0;
613 1.1 simonb }
614 1.1 simonb
615 1.1 simonb static int
616 1.1 simonb bigcopyout(const void *kaddr, void *udaddr, size_t len)
617 1.1 simonb {
618 1.1 simonb char *up;
619 1.26 scw const char *kp = (const char *)kaddr;
620 1.10 thorpej struct lwp *l = curlwp;
621 1.10 thorpej struct proc *p;
622 1.55 chs struct faultbuf env;
623 1.1 simonb int error;
624 1.1 simonb
625 1.10 thorpej p = l->l_proc;
626 1.10 thorpej
627 1.1 simonb /*
628 1.7 simonb * Stolen from physio():
629 1.1 simonb */
630 1.37 chs error = uvm_vslock(p->p_vmspace, udaddr, len, VM_PROT_WRITE);
631 1.1 simonb if (error) {
632 1.55 chs return error;
633 1.1 simonb }
634 1.7 simonb up = (char *)vmaprange(p, (vaddr_t)udaddr, len,
635 1.13 simonb VM_PROT_READ | VM_PROT_WRITE);
636 1.1 simonb
637 1.55 chs if ((error = setfault(&env)) == 0) {
638 1.55 chs memcpy(up, kp, len);
639 1.55 chs }
640 1.55 chs
641 1.55 chs curpcb->pcb_onfault = NULL;
642 1.1 simonb vunmaprange((vaddr_t)up, len);
643 1.37 chs uvm_vsunlock(p->p_vmspace, udaddr, len);
644 1.1 simonb
645 1.55 chs return error;
646 1.1 simonb }
647 1.1 simonb
648 1.1 simonb /*
649 1.1 simonb * kcopy(const void *src, void *dst, size_t len);
650 1.1 simonb *
651 1.1 simonb * Copy len bytes from src to dst, aborting if we encounter a fatal
652 1.1 simonb * page fault.
653 1.1 simonb *
654 1.1 simonb * kcopy() _must_ save and restore the old fault handler since it is
655 1.1 simonb * called by uiomove(), which may be in the path of servicing a non-fatal
656 1.1 simonb * page fault.
657 1.1 simonb */
658 1.1 simonb int
659 1.1 simonb kcopy(const void *src, void *dst, size_t len)
660 1.1 simonb {
661 1.11 matt struct faultbuf env, *oldfault;
662 1.55 chs int rv;
663 1.1 simonb
664 1.1 simonb oldfault = curpcb->pcb_onfault;
665 1.55 chs if ((rv = setfault(&env))) {
666 1.1 simonb curpcb->pcb_onfault = oldfault;
667 1.55 chs return rv;
668 1.1 simonb }
669 1.1 simonb
670 1.2 wiz memcpy(dst, src, len);
671 1.1 simonb
672 1.1 simonb curpcb->pcb_onfault = oldfault;
673 1.1 simonb return 0;
674 1.1 simonb }
675 1.1 simonb
676 1.75 rin #if 0
677 1.1 simonb int
678 1.1 simonb badaddr(void *addr, size_t size)
679 1.1 simonb {
680 1.1 simonb
681 1.1 simonb return badaddr_read(addr, size, NULL);
682 1.1 simonb }
683 1.1 simonb
684 1.1 simonb int
685 1.1 simonb badaddr_read(void *addr, size_t size, int *rptr)
686 1.1 simonb {
687 1.11 matt struct faultbuf env;
688 1.1 simonb int x;
689 1.1 simonb
690 1.1 simonb /* Get rid of any stale machine checks that have been waiting. */
691 1.28 perry __asm volatile ("sync; isync");
692 1.1 simonb
693 1.11 matt if (setfault(&env)) {
694 1.55 chs curpcb->pcb_onfault = NULL;
695 1.28 perry __asm volatile ("sync");
696 1.1 simonb return 1;
697 1.1 simonb }
698 1.1 simonb
699 1.28 perry __asm volatile ("sync");
700 1.1 simonb
701 1.1 simonb switch (size) {
702 1.1 simonb case 1:
703 1.1 simonb x = *(volatile int8_t *)addr;
704 1.1 simonb break;
705 1.1 simonb case 2:
706 1.1 simonb x = *(volatile int16_t *)addr;
707 1.1 simonb break;
708 1.1 simonb case 4:
709 1.1 simonb x = *(volatile int32_t *)addr;
710 1.1 simonb break;
711 1.1 simonb default:
712 1.1 simonb panic("badaddr: invalid size (%d)", size);
713 1.1 simonb }
714 1.1 simonb
715 1.1 simonb /* Make sure we took the machine check, if we caused one. */
716 1.28 perry __asm volatile ("sync; isync");
717 1.1 simonb
718 1.55 chs curpcb->pcb_onfault = NULL;
719 1.28 perry __asm volatile ("sync"); /* To be sure. */
720 1.1 simonb
721 1.1 simonb /* Use the value to avoid reorder. */
722 1.1 simonb if (rptr)
723 1.1 simonb *rptr = x;
724 1.1 simonb
725 1.1 simonb return 0;
726 1.1 simonb }
727 1.75 rin #endif
728 1.1 simonb
729 1.1 simonb /*
730 1.1 simonb * For now, this only deals with the particular unaligned access case
731 1.1 simonb * that gcc tends to generate. Eventually it should handle all of the
732 1.1 simonb * possibilities that can happen on a 32-bit PowerPC in big-endian mode.
733 1.1 simonb */
734 1.1 simonb
735 1.1 simonb static int
736 1.58 matt fix_unaligned(struct lwp *l, struct trapframe *tf)
737 1.1 simonb {
738 1.1 simonb
739 1.1 simonb return -1;
740 1.10 thorpej }
741 1.70 thorpej
742 1.70 thorpej /*
743 1.70 thorpej * XXX Extremely lame implementations of _ufetch_* / _ustore_*. IBM 4xx
744 1.70 thorpej * experts should make versions that are good.
745 1.70 thorpej */
746 1.70 thorpej
747 1.70 thorpej #define UFETCH(sz) \
748 1.70 thorpej int \
749 1.70 thorpej _ufetch_ ## sz(const uint ## sz ## _t *uaddr, uint ## sz ## _t *valp) \
750 1.70 thorpej { \
751 1.70 thorpej return copyin(uaddr, valp, sizeof(*valp)); \
752 1.70 thorpej }
753 1.70 thorpej
754 1.70 thorpej UFETCH(8)
755 1.70 thorpej UFETCH(16)
756 1.70 thorpej UFETCH(32)
757 1.70 thorpej
758 1.70 thorpej #define USTORE(sz) \
759 1.70 thorpej int \
760 1.70 thorpej _ustore_ ## sz(uint ## sz ## _t *uaddr, uint ## sz ## _t val) \
761 1.70 thorpej { \
762 1.70 thorpej return copyout(&val, uaddr, sizeof(val)); \
763 1.70 thorpej }
764 1.70 thorpej
765 1.70 thorpej USTORE(8)
766 1.70 thorpej USTORE(16)
767 1.70 thorpej USTORE(32)
768