trap.c revision 1.96 1 1.96 rin /* $NetBSD: trap.c,v 1.96 2022/09/12 06:19:14 rin Exp $ */
2 1.1 simonb
3 1.1 simonb /*
4 1.1 simonb * Copyright 2001 Wasabi Systems, Inc.
5 1.1 simonb * All rights reserved.
6 1.1 simonb *
7 1.1 simonb * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 1.1 simonb *
9 1.1 simonb * Redistribution and use in source and binary forms, with or without
10 1.1 simonb * modification, are permitted provided that the following conditions
11 1.1 simonb * are met:
12 1.1 simonb * 1. Redistributions of source code must retain the above copyright
13 1.1 simonb * notice, this list of conditions and the following disclaimer.
14 1.1 simonb * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 simonb * notice, this list of conditions and the following disclaimer in the
16 1.1 simonb * documentation and/or other materials provided with the distribution.
17 1.1 simonb * 3. All advertising materials mentioning features or use of this software
18 1.1 simonb * must display the following acknowledgement:
19 1.1 simonb * This product includes software developed for the NetBSD Project by
20 1.1 simonb * Wasabi Systems, Inc.
21 1.1 simonb * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1 simonb * or promote products derived from this software without specific prior
23 1.1 simonb * written permission.
24 1.1 simonb *
25 1.1 simonb * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1 simonb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 simonb * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 simonb * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1 simonb * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 simonb * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 simonb * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 simonb * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 simonb * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 simonb * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 simonb * POSSIBILITY OF SUCH DAMAGE.
36 1.1 simonb */
37 1.1 simonb
38 1.1 simonb /*
39 1.1 simonb * Copyright (C) 1995, 1996 Wolfgang Solfrank.
40 1.1 simonb * Copyright (C) 1995, 1996 TooLs GmbH.
41 1.1 simonb * All rights reserved.
42 1.1 simonb *
43 1.1 simonb * Redistribution and use in source and binary forms, with or without
44 1.1 simonb * modification, are permitted provided that the following conditions
45 1.1 simonb * are met:
46 1.1 simonb * 1. Redistributions of source code must retain the above copyright
47 1.1 simonb * notice, this list of conditions and the following disclaimer.
48 1.1 simonb * 2. Redistributions in binary form must reproduce the above copyright
49 1.1 simonb * notice, this list of conditions and the following disclaimer in the
50 1.1 simonb * documentation and/or other materials provided with the distribution.
51 1.1 simonb * 3. All advertising materials mentioning features or use of this software
52 1.1 simonb * must display the following acknowledgement:
53 1.1 simonb * This product includes software developed by TooLs GmbH.
54 1.1 simonb * 4. The name of TooLs GmbH may not be used to endorse or promote products
55 1.1 simonb * derived from this software without specific prior written permission.
56 1.1 simonb *
57 1.1 simonb * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
58 1.1 simonb * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
59 1.1 simonb * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
60 1.1 simonb * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
61 1.1 simonb * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
62 1.1 simonb * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
63 1.1 simonb * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
64 1.1 simonb * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
65 1.1 simonb * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
66 1.1 simonb * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 1.1 simonb */
68 1.14 lukem
69 1.82 rin #define __UFETCHSTORE_PRIVATE
70 1.82 rin
71 1.14 lukem #include <sys/cdefs.h>
72 1.96 rin __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.96 2022/09/12 06:19:14 rin Exp $");
73 1.1 simonb
74 1.82 rin #ifdef _KERNEL_OPT
75 1.1 simonb #include "opt_ddb.h"
76 1.44 garbled #include "opt_kgdb.h"
77 1.83 rin #include "opt_ppcarch.h"
78 1.87 rin #include "opt_ppcopts.h"
79 1.82 rin #endif
80 1.70 thorpej
81 1.1 simonb #include <sys/param.h>
82 1.72 rin #include <sys/cpu.h>
83 1.72 rin #include <sys/kauth.h>
84 1.1 simonb #include <sys/proc.h>
85 1.86 rin #include <sys/ptrace.h>
86 1.1 simonb #include <sys/reboot.h>
87 1.1 simonb #include <sys/syscall.h>
88 1.1 simonb #include <sys/systm.h>
89 1.1 simonb
90 1.44 garbled #if defined(KGDB)
91 1.44 garbled #include <sys/kgdb.h>
92 1.44 garbled #endif
93 1.44 garbled
94 1.1 simonb #include <uvm/uvm_extern.h>
95 1.1 simonb
96 1.1 simonb #include <dev/cons.h>
97 1.1 simonb
98 1.1 simonb #include <machine/fpu.h>
99 1.1 simonb #include <machine/frame.h>
100 1.1 simonb #include <machine/pcb.h>
101 1.1 simonb #include <machine/psl.h>
102 1.1 simonb #include <machine/trap.h>
103 1.1 simonb
104 1.61 matt #include <powerpc/db_machdep.h>
105 1.1 simonb #include <powerpc/spr.h>
106 1.74 rin #include <powerpc/userret.h>
107 1.61 matt
108 1.61 matt #include <powerpc/ibm4xx/cpu.h>
109 1.1 simonb #include <powerpc/ibm4xx/pmap.h>
110 1.71 rin #include <powerpc/ibm4xx/spr.h>
111 1.1 simonb #include <powerpc/ibm4xx/tlb.h>
112 1.61 matt
113 1.1 simonb #include <powerpc/fpu/fpu_extern.h>
114 1.1 simonb
115 1.1 simonb /* These definitions should probably be somewhere else XXX */
116 1.1 simonb #define FIRSTARG 3 /* first argument is in reg 3 */
117 1.1 simonb #define NARGREG 8 /* 8 args are in registers */
118 1.40 christos #define MOREARGS(sp) ((void *)((int)(sp) + 8)) /* more args go here */
119 1.1 simonb
120 1.50 dsl void trap(struct trapframe *); /* Called from locore / trap_subr */
121 1.75 rin #if 0
122 1.75 rin /* Not currently used nor exposed externally in any header file */
123 1.50 dsl int badaddr(void *, size_t);
124 1.50 dsl int badaddr_read(void *, size_t, int *);
125 1.75 rin #endif
126 1.50 dsl int ctx_setup(int, int);
127 1.1 simonb
128 1.87 rin #ifndef PPC_NO_UNALIGNED
129 1.87 rin static bool fix_unaligned(struct trapframe *, ksiginfo_t *);
130 1.87 rin #endif
131 1.87 rin
132 1.1 simonb #ifdef DEBUG
133 1.1 simonb #define TDB_ALL 0x1
134 1.1 simonb int trapdebug = /* TDB_ALL */ 0;
135 1.1 simonb #define DBPRINTF(x, y) if (trapdebug & (x)) printf y
136 1.1 simonb #else
137 1.1 simonb #define DBPRINTF(x, y)
138 1.1 simonb #endif
139 1.1 simonb
140 1.1 simonb void
141 1.58 matt trap(struct trapframe *tf)
142 1.1 simonb {
143 1.10 thorpej struct lwp *l = curlwp;
144 1.55 chs struct proc *p = l->l_proc;
145 1.53 rmind struct pcb *pcb;
146 1.58 matt int type = tf->tf_exc;
147 1.1 simonb int ftype, rv;
148 1.18 eeh ksiginfo_t ksi;
149 1.1 simonb
150 1.55 chs KASSERT(l->l_stat == LSONPROC);
151 1.1 simonb
152 1.58 matt if (tf->tf_srr1 & PSL_PR) {
153 1.35 ad LWP_CACHE_CREDS(l, p);
154 1.1 simonb type |= EXC_USER;
155 1.35 ad }
156 1.1 simonb
157 1.1 simonb ftype = VM_PROT_READ;
158 1.1 simonb
159 1.13 simonb DBPRINTF(TDB_ALL, ("trap(%x) at %lx from frame %p &frame %p\n",
160 1.58 matt type, tf->tf_srr0, tf, &tf));
161 1.1 simonb
162 1.1 simonb switch (type) {
163 1.1 simonb case EXC_DEBUG|EXC_USER:
164 1.86 rin /* We don't use hardware breakpoints for userland. */
165 1.86 rin goto brain_damage;
166 1.13 simonb
167 1.1 simonb case EXC_TRC|EXC_USER:
168 1.19 thorpej KSI_INIT_TRAP(&ksi);
169 1.17 matt ksi.ksi_signo = SIGTRAP;
170 1.17 matt ksi.ksi_trap = EXC_TRC;
171 1.58 matt ksi.ksi_addr = (void *)tf->tf_srr0;
172 1.17 matt trapsignal(l, &ksi);
173 1.1 simonb break;
174 1.7 simonb
175 1.1 simonb case EXC_DSI:
176 1.1 simonb /* FALLTHROUGH */
177 1.1 simonb case EXC_DTMISS:
178 1.1 simonb {
179 1.1 simonb struct vm_map *map;
180 1.1 simonb vaddr_t va;
181 1.78 rin struct faultbuf *fb;
182 1.78 rin
183 1.78 rin pcb = lwp_getpcb(l);
184 1.78 rin fb = pcb->pcb_onfault;
185 1.78 rin
186 1.78 rin if (curcpu()->ci_idepth >= 0) {
187 1.78 rin rv = EFAULT;
188 1.78 rin goto out;
189 1.78 rin }
190 1.1 simonb
191 1.58 matt va = tf->tf_dear;
192 1.58 matt if (tf->tf_pid == KERNEL_PID) {
193 1.1 simonb map = kernel_map;
194 1.1 simonb } else {
195 1.1 simonb map = &p->p_vmspace->vm_map;
196 1.1 simonb }
197 1.1 simonb
198 1.58 matt if (tf->tf_esr & (ESR_DST|ESR_DIZ))
199 1.3 chs ftype = VM_PROT_WRITE;
200 1.1 simonb
201 1.13 simonb DBPRINTF(TDB_ALL,
202 1.13 simonb ("trap(EXC_DSI) at %lx %s fault on %p esr %x\n",
203 1.58 matt tf->tf_srr0,
204 1.13 simonb (ftype & VM_PROT_WRITE) ? "write" : "read",
205 1.58 matt (void *)va, tf->tf_esr));
206 1.58 matt
207 1.55 chs pcb->pcb_onfault = NULL;
208 1.32 drochner rv = uvm_fault(map, trunc_page(va), ftype);
209 1.55 chs pcb->pcb_onfault = fb;
210 1.1 simonb if (rv == 0)
211 1.68 rin return;
212 1.78 rin out:
213 1.55 chs if (fb != NULL) {
214 1.58 matt tf->tf_pid = KERNEL_PID;
215 1.58 matt tf->tf_srr0 = fb->fb_pc;
216 1.58 matt tf->tf_srr1 |= PSL_IR; /* Re-enable IMMU */
217 1.58 matt tf->tf_cr = fb->fb_cr;
218 1.58 matt tf->tf_fixreg[1] = fb->fb_sp;
219 1.58 matt tf->tf_fixreg[2] = fb->fb_r2;
220 1.79 rin tf->tf_fixreg[3] = rv;
221 1.58 matt memcpy(&tf->tf_fixreg[13], fb->fb_fixreg,
222 1.11 matt sizeof(fb->fb_fixreg));
223 1.68 rin return;
224 1.1 simonb }
225 1.1 simonb }
226 1.1 simonb goto brain_damage;
227 1.7 simonb
228 1.1 simonb case EXC_DSI|EXC_USER:
229 1.1 simonb /* FALLTHROUGH */
230 1.1 simonb case EXC_DTMISS|EXC_USER:
231 1.58 matt if (tf->tf_esr & (ESR_DST|ESR_DIZ))
232 1.3 chs ftype = VM_PROT_WRITE;
233 1.1 simonb
234 1.13 simonb DBPRINTF(TDB_ALL,
235 1.13 simonb ("trap(EXC_DSI|EXC_USER) at %lx %s fault on %lx %x\n",
236 1.58 matt tf->tf_srr0, (ftype & VM_PROT_WRITE) ? "write" : "read",
237 1.58 matt tf->tf_dear, tf->tf_esr));
238 1.13 simonb KASSERT(l == curlwp && (l->l_stat == LSONPROC));
239 1.55 chs // KASSERT(curpcb->pcb_onfault == NULL);
240 1.58 matt rv = uvm_fault(&p->p_vmspace->vm_map, trunc_page(tf->tf_dear),
241 1.32 drochner ftype);
242 1.1 simonb if (rv == 0) {
243 1.13 simonb break;
244 1.1 simonb }
245 1.19 thorpej KSI_INIT_TRAP(&ksi);
246 1.17 matt ksi.ksi_trap = EXC_DSI;
247 1.58 matt ksi.ksi_addr = (void *)tf->tf_dear;
248 1.80 rin vm_signal:
249 1.80 rin switch (rv) {
250 1.80 rin case EINVAL:
251 1.80 rin ksi.ksi_signo = SIGBUS;
252 1.80 rin ksi.ksi_code = BUS_ADRERR;
253 1.80 rin break;
254 1.80 rin case EACCES:
255 1.80 rin ksi.ksi_signo = SIGSEGV;
256 1.80 rin ksi.ksi_code = SEGV_ACCERR;
257 1.80 rin break;
258 1.80 rin case ENOMEM:
259 1.17 matt ksi.ksi_signo = SIGKILL;
260 1.80 rin printf("UVM: pid %d.%d (%s), uid %d killed: "
261 1.80 rin "out of swap\n", p->p_pid, l->l_lid, p->p_comm,
262 1.80 rin l->l_cred ? kauth_cred_geteuid(l->l_cred) : -1);
263 1.80 rin break;
264 1.80 rin default:
265 1.80 rin ksi.ksi_signo = SIGSEGV;
266 1.80 rin ksi.ksi_code = SEGV_MAPERR;
267 1.80 rin break;
268 1.1 simonb }
269 1.17 matt trapsignal(l, &ksi);
270 1.1 simonb break;
271 1.15 chs
272 1.1 simonb case EXC_ITMISS|EXC_USER:
273 1.1 simonb case EXC_ISI|EXC_USER:
274 1.15 chs ftype = VM_PROT_EXECUTE;
275 1.13 simonb DBPRINTF(TDB_ALL,
276 1.15 chs ("trap(EXC_ISI|EXC_USER) at %lx execute fault tf %p\n",
277 1.58 matt tf->tf_srr0, tf));
278 1.55 chs // KASSERT(curpcb->pcb_onfault == NULL);
279 1.58 matt rv = uvm_fault(&p->p_vmspace->vm_map, trunc_page(tf->tf_srr0),
280 1.32 drochner ftype);
281 1.1 simonb if (rv == 0) {
282 1.13 simonb break;
283 1.1 simonb }
284 1.85 rin isi:
285 1.19 thorpej KSI_INIT_TRAP(&ksi);
286 1.17 matt ksi.ksi_trap = EXC_ISI;
287 1.58 matt ksi.ksi_addr = (void *)tf->tf_srr0;
288 1.80 rin goto vm_signal;
289 1.1 simonb break;
290 1.1 simonb
291 1.1 simonb case EXC_AST|EXC_USER:
292 1.62 matt cpu_ast(l, curcpu());
293 1.1 simonb break;
294 1.1 simonb
295 1.1 simonb case EXC_ALI|EXC_USER:
296 1.87 rin if (fix_unaligned(tf, &ksi))
297 1.17 matt trapsignal(l, &ksi);
298 1.1 simonb break;
299 1.1 simonb
300 1.1 simonb case EXC_PGM|EXC_USER:
301 1.57 matt curcpu()->ci_data.cpu_ntrap++;
302 1.53 rmind
303 1.84 rin KSI_INIT_TRAP(&ksi);
304 1.84 rin ksi.ksi_trap = EXC_PGM;
305 1.84 rin ksi.ksi_addr = (void *)tf->tf_srr0;
306 1.1 simonb
307 1.84 rin if (tf->tf_esr & ESR_PTR) {
308 1.86 rin vaddr_t va;
309 1.84 rin sigtrap:
310 1.86 rin va = (vaddr_t)tf->tf_srr0;
311 1.86 rin /*
312 1.86 rin * Restore original instruction and clear BP.
313 1.86 rin */
314 1.86 rin if (p->p_md.md_ss_addr[0] == va ||
315 1.86 rin p->p_md.md_ss_addr[1] == va) {
316 1.86 rin rv = ppc_sstep(l, 0);
317 1.86 rin if (rv != 0)
318 1.86 rin goto vm_signal;
319 1.86 rin ksi.ksi_code = TRAP_TRACE;
320 1.86 rin } else
321 1.86 rin ksi.ksi_code = TRAP_BRKPT;
322 1.84 rin if (p->p_raslist != NULL &&
323 1.86 rin ras_lookup(p, (void *)va) != (void *)-1) {
324 1.86 rin tf->tf_srr0 += (ksi.ksi_code == TRAP_TRACE) ?
325 1.86 rin 0 : 4;
326 1.65 matt break;
327 1.84 rin }
328 1.84 rin ksi.ksi_signo = SIGTRAP;
329 1.85 rin } else if (tf->tf_esr & ESR_PPR) {
330 1.85 rin uint32_t opcode;
331 1.85 rin
332 1.85 rin rv = copyin((void *)tf->tf_srr0, &opcode,
333 1.85 rin sizeof(opcode));
334 1.85 rin if (rv)
335 1.85 rin goto isi;
336 1.85 rin if (emulate_mxmsr(l, tf, opcode)) {
337 1.85 rin tf->tf_srr0 += 4;
338 1.85 rin break;
339 1.85 rin }
340 1.85 rin
341 1.85 rin ksi.ksi_code = ILL_PRVOPC;
342 1.85 rin ksi.ksi_signo = SIGILL;
343 1.65 matt } else {
344 1.84 rin pcb = lwp_getpcb(l);
345 1.84 rin
346 1.84 rin if (__predict_false(!fpu_used_p(l))) {
347 1.84 rin memset(&pcb->pcb_fpu, 0, sizeof(pcb->pcb_fpu));
348 1.84 rin fpu_mark_used(l);
349 1.84 rin }
350 1.84 rin
351 1.84 rin if (fpu_emulate(tf, &pcb->pcb_fpu, &ksi)) {
352 1.84 rin if (ksi.ksi_signo == 0) /* was emulated */
353 1.84 rin break;
354 1.84 rin else if (ksi.ksi_signo == SIGTRAP)
355 1.84 rin goto sigtrap; /* XXX H/W bug? */
356 1.84 rin } else {
357 1.84 rin ksi.ksi_code = ILL_ILLOPC;
358 1.84 rin ksi.ksi_signo = SIGILL;
359 1.84 rin }
360 1.1 simonb }
361 1.65 matt
362 1.65 matt trapsignal(l, &ksi);
363 1.1 simonb break;
364 1.1 simonb
365 1.1 simonb case EXC_MCHK:
366 1.1 simonb {
367 1.11 matt struct faultbuf *fb;
368 1.1 simonb
369 1.53 rmind pcb = lwp_getpcb(l);
370 1.53 rmind if ((fb = pcb->pcb_onfault) != NULL) {
371 1.58 matt tf->tf_pid = KERNEL_PID;
372 1.58 matt tf->tf_srr0 = fb->fb_pc;
373 1.58 matt tf->tf_srr1 |= PSL_IR; /* Re-enable IMMU */
374 1.58 matt tf->tf_fixreg[1] = fb->fb_sp;
375 1.58 matt tf->tf_fixreg[2] = fb->fb_r2;
376 1.58 matt tf->tf_fixreg[3] = 1; /* Return TRUE */
377 1.58 matt tf->tf_cr = fb->fb_cr;
378 1.58 matt memcpy(&tf->tf_fixreg[13], fb->fb_fixreg,
379 1.11 matt sizeof(fb->fb_fixreg));
380 1.68 rin return;
381 1.1 simonb }
382 1.1 simonb }
383 1.1 simonb goto brain_damage;
384 1.68 rin
385 1.1 simonb default:
386 1.68 rin brain_damage:
387 1.58 matt printf("trap type 0x%x at 0x%lx\n", type, tf->tf_srr0);
388 1.44 garbled #if defined(DDB) || defined(KGDB)
389 1.58 matt if (kdb_trap(type, tf))
390 1.68 rin return;
391 1.1 simonb #endif
392 1.1 simonb #ifdef TRAP_PANICWAIT
393 1.1 simonb printf("Press a key to panic.\n");
394 1.1 simonb cngetc();
395 1.1 simonb #endif
396 1.1 simonb panic("trap");
397 1.1 simonb }
398 1.1 simonb
399 1.73 rin /* Invoke powerpc userret code */
400 1.73 rin userret(l, tf);
401 1.1 simonb }
402 1.1 simonb
403 1.1 simonb int
404 1.1 simonb ctx_setup(int ctx, int srr1)
405 1.1 simonb {
406 1.1 simonb volatile struct pmap *pm;
407 1.1 simonb
408 1.1 simonb /* Update PID if we're returning to user mode. */
409 1.1 simonb if (srr1 & PSL_PR) {
410 1.1 simonb pm = curproc->p_vmspace->vm_map.pmap;
411 1.1 simonb if (!pm->pm_ctx) {
412 1.26 scw ctx_alloc(__UNVOLATILE(pm));
413 1.1 simonb }
414 1.1 simonb ctx = pm->pm_ctx;
415 1.1 simonb }
416 1.1 simonb else if (!ctx) {
417 1.1 simonb ctx = KERNEL_PID;
418 1.1 simonb }
419 1.1 simonb return (ctx);
420 1.1 simonb }
421 1.1 simonb
422 1.1 simonb /*
423 1.1 simonb * Used by copyin()/copyout()
424 1.1 simonb */
425 1.50 dsl extern vaddr_t vmaprange(struct proc *, vaddr_t, vsize_t, int);
426 1.50 dsl extern void vunmaprange(vaddr_t, vsize_t);
427 1.50 dsl static int bigcopyin(const void *, void *, size_t );
428 1.50 dsl static int bigcopyout(const void *, void *, size_t );
429 1.1 simonb
430 1.1 simonb int
431 1.88 rin copyin(const void *uaddr, void *kaddr, size_t len)
432 1.1 simonb {
433 1.1 simonb struct pmap *pm = curproc->p_vmspace->vm_map.pmap;
434 1.55 chs int rv, msr, pid, tmp, ctx, count = 0;
435 1.11 matt struct faultbuf env;
436 1.1 simonb
437 1.1 simonb /* For bigger buffers use the faster copy */
438 1.46 hpeyerl if (len > 1024)
439 1.88 rin return (bigcopyin(uaddr, kaddr, len));
440 1.1 simonb
441 1.55 chs if ((rv = setfault(&env))) {
442 1.55 chs curpcb->pcb_onfault = NULL;
443 1.55 chs return rv;
444 1.1 simonb }
445 1.1 simonb
446 1.1 simonb if (!(ctx = pm->pm_ctx)) {
447 1.1 simonb /* No context -- assign it one */
448 1.1 simonb ctx_alloc(pm);
449 1.1 simonb ctx = pm->pm_ctx;
450 1.1 simonb }
451 1.1 simonb
452 1.46 hpeyerl __asm volatile(
453 1.89 rin "mfmsr %[msr];" /* Save MSR */
454 1.91 rin "li %[tmp],0x20;" /* Disable IMMU */
455 1.91 rin "andc %[tmp],%[msr],%[tmp];"
456 1.91 rin "mtmsr %[tmp];"
457 1.89 rin "isync;"
458 1.89 rin "mfpid %[pid];" /* Save old PID */
459 1.89 rin
460 1.89 rin "srwi. %[count],%[len],0x2;" /* How many words? */
461 1.89 rin "beq- 2f;" /* No words. Go do bytes */
462 1.89 rin "mtctr %[count];"
463 1.89 rin
464 1.89 rin "1:" "mtpid %[ctx];"
465 1.89 rin "isync;"
466 1.77 rin #ifdef PPC_IBM403
467 1.89 rin "lswi %[tmp],%[uaddr],4;" /* Load user word */
468 1.77 rin #else
469 1.89 rin "lwz %[tmp],0(%[uaddr]);"
470 1.77 rin #endif
471 1.89 rin "addi %[uaddr],%[uaddr],0x4;" /* next uaddr word */
472 1.89 rin "sync;"
473 1.89 rin
474 1.89 rin "mtpid %[pid];"
475 1.89 rin "isync;"
476 1.77 rin #ifdef PPC_IBM403
477 1.89 rin "stswi %[tmp],%[kaddr],4;" /* Store kernel word */
478 1.77 rin #else
479 1.89 rin "stw %[tmp],0(%[kaddr]);"
480 1.77 rin #endif
481 1.89 rin "dcbst 0,%[kaddr];" /* flush cache */
482 1.90 rin "addi %[kaddr],%[kaddr],0x4;" /* next kaddr word */
483 1.89 rin "sync;"
484 1.89 rin "bdnz 1b;" /* repeat */
485 1.89 rin
486 1.89 rin "2:" "andi. %[count],%[len],0x3;" /* How many remaining bytes? */
487 1.92 rin "beq 10f;"
488 1.94 rin "mtxer %[count];"
489 1.89 rin
490 1.89 rin "mtpid %[ctx];"
491 1.89 rin "isync;"
492 1.94 rin "lswx %[tmp],0,%[uaddr];" /* Load user bytes */
493 1.89 rin "sync;"
494 1.89 rin
495 1.89 rin "mtpid %[pid];"
496 1.89 rin "isync;"
497 1.95 rin "stswx %[tmp],0,%[kaddr];" /* Store kernel bytes */
498 1.89 rin "dcbst 0,%[kaddr];" /* flush cache */
499 1.89 rin "sync;"
500 1.89 rin
501 1.96 rin "10:" "mtmsr %[msr];" /* Restore MSR */
502 1.89 rin "isync;"
503 1.89 rin
504 1.46 hpeyerl : [msr] "=&r" (msr), [pid] "=&r" (pid), [tmp] "=&r" (tmp)
505 1.88 rin : [uaddr] "b" (uaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr),
506 1.93 rin [len] "b" (len), [count] "b" (count)
507 1.94 rin : "cr0", "ctr", "xer");
508 1.1 simonb
509 1.55 chs curpcb->pcb_onfault = NULL;
510 1.1 simonb return 0;
511 1.1 simonb }
512 1.1 simonb
513 1.1 simonb static int
514 1.88 rin bigcopyin(const void *uaddr, void *kaddr, size_t len)
515 1.1 simonb {
516 1.1 simonb const char *up;
517 1.1 simonb char *kp = kaddr;
518 1.10 thorpej struct lwp *l = curlwp;
519 1.10 thorpej struct proc *p;
520 1.55 chs struct faultbuf env;
521 1.1 simonb int error;
522 1.1 simonb
523 1.10 thorpej p = l->l_proc;
524 1.10 thorpej
525 1.1 simonb /*
526 1.7 simonb * Stolen from physio():
527 1.1 simonb */
528 1.88 rin error = uvm_vslock(p->p_vmspace, __UNCONST(uaddr), len, VM_PROT_READ);
529 1.1 simonb if (error) {
530 1.55 chs return error;
531 1.1 simonb }
532 1.88 rin up = (char *)vmaprange(p, (vaddr_t)uaddr, len, VM_PROT_READ);
533 1.1 simonb
534 1.55 chs if ((error = setfault(&env)) == 0) {
535 1.55 chs memcpy(kp, up, len);
536 1.55 chs }
537 1.55 chs
538 1.55 chs curpcb->pcb_onfault = NULL;
539 1.1 simonb vunmaprange((vaddr_t)up, len);
540 1.88 rin uvm_vsunlock(p->p_vmspace, __UNCONST(uaddr), len);
541 1.1 simonb
542 1.55 chs return error;
543 1.1 simonb }
544 1.1 simonb
545 1.1 simonb int
546 1.88 rin copyout(const void *kaddr, void *uaddr, size_t len)
547 1.1 simonb {
548 1.1 simonb struct pmap *pm = curproc->p_vmspace->vm_map.pmap;
549 1.55 chs int rv, msr, pid, tmp, ctx, count = 0;
550 1.11 matt struct faultbuf env;
551 1.1 simonb
552 1.1 simonb /* For big copies use more efficient routine */
553 1.46 hpeyerl if (len > 1024)
554 1.88 rin return (bigcopyout(kaddr, uaddr, len));
555 1.1 simonb
556 1.55 chs if ((rv = setfault(&env))) {
557 1.55 chs curpcb->pcb_onfault = NULL;
558 1.55 chs return rv;
559 1.1 simonb }
560 1.1 simonb
561 1.1 simonb if (!(ctx = pm->pm_ctx)) {
562 1.1 simonb /* No context -- assign it one */
563 1.1 simonb ctx_alloc(pm);
564 1.1 simonb ctx = pm->pm_ctx;
565 1.1 simonb }
566 1.1 simonb
567 1.46 hpeyerl __asm volatile(
568 1.89 rin "mfmsr %[msr];" /* Save MSR */
569 1.91 rin "li %[tmp],0x20;" /* Disable IMMU */
570 1.91 rin "andc %[tmp],%[msr],%[tmp];"
571 1.91 rin "mtmsr %[tmp];"
572 1.89 rin "isync;"
573 1.89 rin "mfpid %[pid];" /* Save old PID */
574 1.89 rin
575 1.89 rin "srwi. %[count],%[len],0x2;" /* How many words? */
576 1.89 rin "beq- 2f;" /* No words. Go do bytes */
577 1.89 rin "mtctr %[count];"
578 1.89 rin
579 1.94 rin "1:"
580 1.77 rin #ifdef PPC_IBM403
581 1.89 rin "lswi %[tmp],%[kaddr],4;" /* Load kernel word */
582 1.77 rin #else
583 1.89 rin "lwz %[tmp],0(%[kaddr]);"
584 1.77 rin #endif
585 1.89 rin "addi %[kaddr],%[kaddr],0x4;" /* next kaddr word */
586 1.89 rin "sync;"
587 1.89 rin
588 1.89 rin "mtpid %[ctx];"
589 1.89 rin "isync;"
590 1.77 rin #ifdef PPC_IBM403
591 1.89 rin "stswi %[tmp],%[uaddr],4;" /* Store user word */
592 1.77 rin #else
593 1.89 rin "stw %[tmp],0(%[uaddr]);"
594 1.77 rin #endif
595 1.89 rin "dcbst 0,%[uaddr];" /* flush cache */
596 1.89 rin "addi %[uaddr],%[uaddr],0x4;" /* next uaddr word */
597 1.89 rin "sync;"
598 1.94 rin
599 1.94 rin "mtpid %[pid];"
600 1.94 rin "isync;"
601 1.89 rin "bdnz 1b;" /* repeat */
602 1.89 rin
603 1.89 rin "2:" "andi. %[count],%[len],0x3;" /* How many remaining bytes? */
604 1.92 rin "beq 10f;"
605 1.94 rin "mtxer %[count];"
606 1.89 rin
607 1.94 rin "lswx %[tmp],0,%[kaddr];" /* Load kernel bytes */
608 1.89 rin "sync;"
609 1.89 rin
610 1.89 rin "mtpid %[ctx];"
611 1.89 rin "isync;"
612 1.94 rin "stswx %[tmp],0,%[uaddr];" /* Store user bytes */
613 1.89 rin "dcbst 0,%[uaddr];" /* flush cache */
614 1.89 rin "sync;"
615 1.89 rin
616 1.94 rin "mtpid %[pid];" /* Restore PID and MSR */
617 1.94 rin "10:" "mtmsr %[msr];"
618 1.89 rin "isync;"
619 1.89 rin
620 1.46 hpeyerl : [msr] "=&r" (msr), [pid] "=&r" (pid), [tmp] "=&r" (tmp)
621 1.88 rin : [uaddr] "b" (uaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr),
622 1.93 rin [len] "b" (len), [count] "b" (count)
623 1.94 rin : "cr0", "ctr", "xer");
624 1.1 simonb
625 1.55 chs curpcb->pcb_onfault = NULL;
626 1.1 simonb return 0;
627 1.1 simonb }
628 1.1 simonb
629 1.1 simonb static int
630 1.88 rin bigcopyout(const void *kaddr, void *uaddr, size_t len)
631 1.1 simonb {
632 1.1 simonb char *up;
633 1.26 scw const char *kp = (const char *)kaddr;
634 1.10 thorpej struct lwp *l = curlwp;
635 1.10 thorpej struct proc *p;
636 1.55 chs struct faultbuf env;
637 1.1 simonb int error;
638 1.1 simonb
639 1.10 thorpej p = l->l_proc;
640 1.10 thorpej
641 1.1 simonb /*
642 1.7 simonb * Stolen from physio():
643 1.1 simonb */
644 1.88 rin error = uvm_vslock(p->p_vmspace, uaddr, len, VM_PROT_WRITE);
645 1.1 simonb if (error) {
646 1.55 chs return error;
647 1.1 simonb }
648 1.88 rin up = (char *)vmaprange(p, (vaddr_t)uaddr, len,
649 1.13 simonb VM_PROT_READ | VM_PROT_WRITE);
650 1.1 simonb
651 1.55 chs if ((error = setfault(&env)) == 0) {
652 1.55 chs memcpy(up, kp, len);
653 1.55 chs }
654 1.55 chs
655 1.55 chs curpcb->pcb_onfault = NULL;
656 1.1 simonb vunmaprange((vaddr_t)up, len);
657 1.88 rin uvm_vsunlock(p->p_vmspace, uaddr, len);
658 1.1 simonb
659 1.55 chs return error;
660 1.1 simonb }
661 1.1 simonb
662 1.1 simonb /*
663 1.1 simonb * kcopy(const void *src, void *dst, size_t len);
664 1.1 simonb *
665 1.1 simonb * Copy len bytes from src to dst, aborting if we encounter a fatal
666 1.1 simonb * page fault.
667 1.1 simonb *
668 1.1 simonb * kcopy() _must_ save and restore the old fault handler since it is
669 1.1 simonb * called by uiomove(), which may be in the path of servicing a non-fatal
670 1.1 simonb * page fault.
671 1.1 simonb */
672 1.1 simonb int
673 1.1 simonb kcopy(const void *src, void *dst, size_t len)
674 1.1 simonb {
675 1.11 matt struct faultbuf env, *oldfault;
676 1.55 chs int rv;
677 1.1 simonb
678 1.1 simonb oldfault = curpcb->pcb_onfault;
679 1.55 chs if ((rv = setfault(&env))) {
680 1.1 simonb curpcb->pcb_onfault = oldfault;
681 1.55 chs return rv;
682 1.1 simonb }
683 1.1 simonb
684 1.2 wiz memcpy(dst, src, len);
685 1.1 simonb
686 1.1 simonb curpcb->pcb_onfault = oldfault;
687 1.1 simonb return 0;
688 1.1 simonb }
689 1.1 simonb
690 1.75 rin #if 0
691 1.1 simonb int
692 1.1 simonb badaddr(void *addr, size_t size)
693 1.1 simonb {
694 1.1 simonb
695 1.1 simonb return badaddr_read(addr, size, NULL);
696 1.1 simonb }
697 1.1 simonb
698 1.1 simonb int
699 1.1 simonb badaddr_read(void *addr, size_t size, int *rptr)
700 1.1 simonb {
701 1.11 matt struct faultbuf env;
702 1.1 simonb int x;
703 1.1 simonb
704 1.1 simonb /* Get rid of any stale machine checks that have been waiting. */
705 1.28 perry __asm volatile ("sync; isync");
706 1.1 simonb
707 1.11 matt if (setfault(&env)) {
708 1.55 chs curpcb->pcb_onfault = NULL;
709 1.28 perry __asm volatile ("sync");
710 1.1 simonb return 1;
711 1.1 simonb }
712 1.1 simonb
713 1.28 perry __asm volatile ("sync");
714 1.1 simonb
715 1.1 simonb switch (size) {
716 1.1 simonb case 1:
717 1.1 simonb x = *(volatile int8_t *)addr;
718 1.1 simonb break;
719 1.1 simonb case 2:
720 1.1 simonb x = *(volatile int16_t *)addr;
721 1.1 simonb break;
722 1.1 simonb case 4:
723 1.1 simonb x = *(volatile int32_t *)addr;
724 1.1 simonb break;
725 1.1 simonb default:
726 1.1 simonb panic("badaddr: invalid size (%d)", size);
727 1.1 simonb }
728 1.1 simonb
729 1.1 simonb /* Make sure we took the machine check, if we caused one. */
730 1.28 perry __asm volatile ("sync; isync");
731 1.1 simonb
732 1.55 chs curpcb->pcb_onfault = NULL;
733 1.28 perry __asm volatile ("sync"); /* To be sure. */
734 1.1 simonb
735 1.1 simonb /* Use the value to avoid reorder. */
736 1.1 simonb if (rptr)
737 1.1 simonb *rptr = x;
738 1.1 simonb
739 1.1 simonb return 0;
740 1.1 simonb }
741 1.75 rin #endif
742 1.1 simonb
743 1.87 rin #ifndef PPC_NO_UNALIGNED
744 1.87 rin static bool
745 1.87 rin fix_unaligned(struct trapframe *tf, ksiginfo_t *ksi)
746 1.1 simonb {
747 1.1 simonb
748 1.87 rin KSI_INIT_TRAP(ksi);
749 1.87 rin ksi->ksi_signo = SIGBUS;
750 1.87 rin ksi->ksi_trap = EXC_ALI;
751 1.87 rin ksi->ksi_addr = (void *)tf->tf_dear;
752 1.87 rin return true;
753 1.10 thorpej }
754 1.87 rin #endif
755 1.70 thorpej
756 1.70 thorpej /*
757 1.70 thorpej * XXX Extremely lame implementations of _ufetch_* / _ustore_*. IBM 4xx
758 1.70 thorpej * experts should make versions that are good.
759 1.70 thorpej */
760 1.70 thorpej
761 1.70 thorpej #define UFETCH(sz) \
762 1.70 thorpej int \
763 1.70 thorpej _ufetch_ ## sz(const uint ## sz ## _t *uaddr, uint ## sz ## _t *valp) \
764 1.70 thorpej { \
765 1.70 thorpej return copyin(uaddr, valp, sizeof(*valp)); \
766 1.70 thorpej }
767 1.70 thorpej
768 1.70 thorpej UFETCH(8)
769 1.70 thorpej UFETCH(16)
770 1.70 thorpej UFETCH(32)
771 1.70 thorpej
772 1.70 thorpej #define USTORE(sz) \
773 1.70 thorpej int \
774 1.70 thorpej _ustore_ ## sz(uint ## sz ## _t *uaddr, uint ## sz ## _t val) \
775 1.70 thorpej { \
776 1.70 thorpej return copyout(&val, uaddr, sizeof(val)); \
777 1.70 thorpej }
778 1.70 thorpej
779 1.70 thorpej USTORE(8)
780 1.70 thorpej USTORE(16)
781 1.70 thorpej USTORE(32)
782