trap_subr.S revision 1.21 1 1.21 kiyohara /* $NetBSD: trap_subr.S,v 1.21 2011/12/15 11:13:25 kiyohara Exp $ */
2 1.1 simonb
3 1.1 simonb /*
4 1.1 simonb * Copyright 2001 Wasabi Systems, Inc.
5 1.1 simonb * All rights reserved.
6 1.1 simonb *
7 1.1 simonb * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 1.1 simonb *
9 1.1 simonb * Redistribution and use in source and binary forms, with or without
10 1.1 simonb * modification, are permitted provided that the following conditions
11 1.1 simonb * are met:
12 1.1 simonb * 1. Redistributions of source code must retain the above copyright
13 1.1 simonb * notice, this list of conditions and the following disclaimer.
14 1.1 simonb * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 simonb * notice, this list of conditions and the following disclaimer in the
16 1.1 simonb * documentation and/or other materials provided with the distribution.
17 1.1 simonb * 3. All advertising materials mentioning features or use of this software
18 1.1 simonb * must display the following acknowledgement:
19 1.1 simonb * This product includes software developed for the NetBSD Project by
20 1.1 simonb * Wasabi Systems, Inc.
21 1.1 simonb * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1 simonb * or promote products derived from this software without specific prior
23 1.1 simonb * written permission.
24 1.1 simonb *
25 1.1 simonb * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1 simonb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 simonb * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 simonb * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1 simonb * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 simonb * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 simonb * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 simonb * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 simonb * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 simonb * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 simonb * POSSIBILITY OF SUCH DAMAGE.
36 1.1 simonb */
37 1.1 simonb
38 1.1 simonb /*
39 1.1 simonb * Copyright (C) 1995, 1996 Wolfgang Solfrank.
40 1.1 simonb * Copyright (C) 1995, 1996 TooLs GmbH.
41 1.1 simonb * All rights reserved.
42 1.1 simonb *
43 1.1 simonb * Redistribution and use in source and binary forms, with or without
44 1.1 simonb * modification, are permitted provided that the following conditions
45 1.1 simonb * are met:
46 1.1 simonb * 1. Redistributions of source code must retain the above copyright
47 1.1 simonb * notice, this list of conditions and the following disclaimer.
48 1.1 simonb * 2. Redistributions in binary form must reproduce the above copyright
49 1.1 simonb * notice, this list of conditions and the following disclaimer in the
50 1.1 simonb * documentation and/or other materials provided with the distribution.
51 1.1 simonb * 3. All advertising materials mentioning features or use of this software
52 1.1 simonb * must display the following acknowledgement:
53 1.1 simonb * This product includes software developed by TooLs GmbH.
54 1.1 simonb * 4. The name of TooLs GmbH may not be used to endorse or promote products
55 1.1 simonb * derived from this software without specific prior written permission.
56 1.1 simonb *
57 1.1 simonb * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
58 1.1 simonb * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
59 1.1 simonb * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
60 1.1 simonb * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
61 1.1 simonb * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
62 1.1 simonb * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
63 1.1 simonb * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
64 1.1 simonb * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
65 1.1 simonb * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
66 1.1 simonb * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 1.1 simonb */
68 1.1 simonb
69 1.1 simonb /*
70 1.1 simonb * NOTICE: This is not a standalone file. to use it, #include it in
71 1.1 simonb * your port's locore.S, like so:
72 1.1 simonb *
73 1.5 chs * #include <powerpc/ibm4xx/trap_subr.S>
74 1.1 simonb */
75 1.1 simonb
76 1.1 simonb /*
77 1.1 simonb * XXX Interrupt and spill stacks need to be per-CPU.
78 1.1 simonb */
79 1.1 simonb
80 1.4 simonb #define GET_PCB(rX) \
81 1.1 simonb GET_CPUINFO(rX); \
82 1.1 simonb lwz rX,CI_CURPCB(rX)
83 1.1 simonb
84 1.19 kiyohara #define STANDARD_PROLOG(savearea) \
85 1.12 matt mtsprg1 %r1; /* save SP */ \
86 1.13 matt GET_CPUINFO(%r1); \
87 1.19 kiyohara stmw %r28,(savearea+CPUSAVE_R28)(%r1); /* free r28-r31 */ \
88 1.12 matt mflr %r28; /* save LR */ \
89 1.12 matt mfcr %r29; /* save CR */ \
90 1.13 matt mfsrr0 %r30; \
91 1.13 matt mfsrr1 %r31; /* Test whether we already had PR set */ \
92 1.13 matt stmw %r30,(savearea+CPUSAVE_SRR0)(%r1); /* save srr0/srr1 */ \
93 1.14 kiyohara mfsprg1 %r1; /* restore SP */ \
94 1.13 matt mtcr %r31; \
95 1.15 matt bf MSR_PR,1f; /* branch if MSR[PR] is clear */ \
96 1.14 kiyohara GET_PCB(%r1); \
97 1.13 matt addi %r1,%r1,USPACE-CALLFRAMELEN; /* stack is top of user struct */ \
98 1.13 matt 1:
99 1.13 matt
100 1.13 matt #define ACCESS_PROLOG(savearea) \
101 1.19 kiyohara mtsprg1 %r1; /* save SP temporalily */ \
102 1.13 matt GET_CPUINFO(%r1); \
103 1.19 kiyohara stmw %r28,(savearea+CPUSAVE_R28)(%r1); /* free r28-r31 */ \
104 1.13 matt mflr %r28; /* save LR */ \
105 1.13 matt mfcr %r29; /* save CR */ \
106 1.13 matt mfdear %r30; \
107 1.13 matt mfesr %r31; \
108 1.13 matt stmw %r30,(savearea+CPUSAVE_DEAR)(%r1); \
109 1.13 matt mfsrr0 %r30; \
110 1.12 matt mfsrr1 %r31; /* Test whether we already had PR set */ \
111 1.13 matt stmw %r30,(savearea+CPUSAVE_SRR0)(%r1); /* save srr0/srr1 */ \
112 1.14 kiyohara mfsprg1 %r1; /* restore SP */ \
113 1.12 matt mtcr %r31; \
114 1.15 matt bf MSR_PR,1f; /* branch if MSR[PR] is clear */ \
115 1.14 kiyohara GET_PCB(%r1); \
116 1.13 matt addi %r1,%r1,USPACE-CALLFRAMELEN; /* stack is top of user struct */ \
117 1.1 simonb 1:
118 1.4 simonb
119 1.13 matt #define CRITICAL_PROLOG(savearea) \
120 1.12 matt mtsprg1 %r1; /* save SP */ \
121 1.14 kiyohara GET_CPUINFO(%r1); \
122 1.19 kiyohara stmw %r28,(savearea+CPUSAVE_R28)(%r1); /* free r28-r31 */ \
123 1.12 matt mflr %r28; /* save LR */ \
124 1.12 matt mfcr %r29; /* save CR */ \
125 1.12 matt mfsrr2 %r30; /* Fake a standard trap */ \
126 1.12 matt mfsrr3 %r31; /* Test whether we already had PR set */ \
127 1.13 matt stmw %r30,(savearea+CPUSAVE_SRR0)(%r1); /* save srr0/srr1 */ \
128 1.14 kiyohara mfsprg1 %r1; /* restore SP */ \
129 1.12 matt mtcr %r31; \
130 1.15 matt bf MSR_PR,1f; /* branch if MSR[PR] is clear */ \
131 1.14 kiyohara GET_PCB(%r1); \
132 1.13 matt addi %r1,%r1,USPACE-CALLFRAMELEN; /* stack is top of user struct */ \
133 1.1 simonb 1:
134 1.1 simonb
135 1.1 simonb
136 1.4 simonb /* Standard handler saves r1,r28-31,LR,CR, sets up the stack and calls s_trap */
137 1.1 simonb #define STANDARD_EXC_HANDLER(name)\
138 1.1 simonb .globl _C_LABEL(name ## trap),_C_LABEL(name ## size) ; \
139 1.1 simonb _C_LABEL(name ## trap): \
140 1.13 matt STANDARD_PROLOG(CI_TEMPSAVE); \
141 1.19 kiyohara bla s_trap; \
142 1.1 simonb _C_LABEL(name ## size) = .-_C_LABEL(name ## trap)
143 1.1 simonb
144 1.4 simonb /* Access exceptions also need DEAR and ESR saved */
145 1.1 simonb #define ACCESS_EXC_HANDLER(name)\
146 1.1 simonb .globl _C_LABEL(name ## trap),_C_LABEL(name ## size) ; \
147 1.1 simonb _C_LABEL(name ## trap): \
148 1.13 matt ACCESS_PROLOG(CI_TEMPSAVE); \
149 1.19 kiyohara bla s_trap; \
150 1.1 simonb _C_LABEL(name ## size) = .-_C_LABEL(name ## trap)
151 1.1 simonb
152 1.1 simonb /* Maybe this should call ddb.... */
153 1.1 simonb #define CRITICAL_EXC_HANDLER(name)\
154 1.1 simonb .globl _C_LABEL(name ## trap),_C_LABEL(name ## size) ; \
155 1.1 simonb _C_LABEL(name ## trap): \
156 1.13 matt CRITICAL_PROLOG(CI_TEMPSAVE); \
157 1.19 kiyohara bla s_trap; \
158 1.1 simonb _C_LABEL(name ## size) = .-_C_LABEL(name ## trap)
159 1.4 simonb
160 1.13 matt #define INTR_PROLOG(tempsave) \
161 1.13 matt mtsprg1 %r1; /* save SP */ \
162 1.13 matt GET_CPUINFO(%r1); \
163 1.13 matt stmw %r28,(tempsave+CPUSAVE_R28)(%r1); /* free r28-r31 */ \
164 1.13 matt mflr %r28; /* save LR */ \
165 1.13 matt mfcr %r29; /* save CR */ \
166 1.13 matt mfxer %r30; /* save XER */ \
167 1.13 matt lwz %r31,CI_IDEPTH(%r1); /* already running on intstk? */ \
168 1.13 matt addic. %r31,%r31,1; \
169 1.13 matt stw %r31,CI_IDEPTH(%r1); \
170 1.13 matt lwz %r1,CI_INTSTK(%r1); /* get intstk */ \
171 1.13 matt beq 1f; \
172 1.13 matt mfsprg1 %r1; /* yes, get old SP */ \
173 1.13 matt 1:
174 1.13 matt
175 1.1 simonb /*
176 1.1 simonb * This code gets copied to all the trap vectors
177 1.4 simonb * (except ISI/DSI, ALI, the interrupts, and possibly the debugging
178 1.1 simonb * traps when using IPKDB).
179 1.1 simonb */
180 1.1 simonb .text
181 1.1 simonb STANDARD_EXC_HANDLER(default)
182 1.1 simonb ACCESS_EXC_HANDLER(ali)
183 1.1 simonb ACCESS_EXC_HANDLER(dsi)
184 1.1 simonb ACCESS_EXC_HANDLER(isi)
185 1.1 simonb STANDARD_EXC_HANDLER(debug)
186 1.3 eeh CRITICAL_EXC_HANDLER(mchk)
187 1.1 simonb
188 1.1 simonb /*
189 1.1 simonb * This one for the external interrupt handler.
190 1.1 simonb */
191 1.1 simonb .globl _C_LABEL(extint),_C_LABEL(extsize)
192 1.1 simonb _C_LABEL(extint):
193 1.13 matt INTR_PROLOG(CI_TEMPSAVE)
194 1.1 simonb ba extintr
195 1.1 simonb _C_LABEL(extsize) = .-_C_LABEL(extint)
196 1.1 simonb
197 1.4 simonb
198 1.11 garbled #if defined(DDB) || defined(KGDB)
199 1.1 simonb /*
200 1.1 simonb * In case of DDB we want a separate trap catcher for it
201 1.1 simonb */
202 1.13 matt .lcomm ddbstk,INTSTK,16 /* ddb stack */
203 1.1 simonb
204 1.1 simonb .globl _C_LABEL(ddblow),_C_LABEL(ddbsize)
205 1.1 simonb _C_LABEL(ddblow):
206 1.12 matt mtsprg1 %r1 /* save SP */
207 1.13 matt GET_CPUINFO(%r1)
208 1.13 matt stmw %r28,CI_DDBSAVE(%r1) /* free r28-r31 */
209 1.12 matt mflr %r28 /* save LR */
210 1.12 matt mfcr %r29 /* save CR */
211 1.19 kiyohara mfsrr0 %r30
212 1.19 kiyohara mfsrr1 %r31
213 1.19 kiyohara stmw %r30,(CI_DDBSAVE+CPUSAVE_SRR0)(%r1) /* save srr0/srr1 */
214 1.13 matt lis %r1,ddbstk+INTSTK-CALLFRAMELEN@ha /* get new SP */
215 1.13 matt addi %r1,%r1,ddbstk+INTSTK-CALLFRAMELEN@l
216 1.1 simonb bla ddbtrap
217 1.1 simonb _C_LABEL(ddbsize) = .-_C_LABEL(ddblow)
218 1.11 garbled #endif /* DDB || KGDB */
219 1.1 simonb
220 1.1 simonb #ifdef IPKDB
221 1.1 simonb /*
222 1.1 simonb * In case of IPKDB we want a separate trap catcher for it
223 1.1 simonb */
224 1.1 simonb
225 1.13 matt .lcomm ipkdbstk,INTSTK,16 /* ipkdb stack */
226 1.1 simonb
227 1.1 simonb .globl _C_LABEL(ipkdblow),_C_LABEL(ipkdbsize)
228 1.1 simonb _C_LABEL(ipkdblow):
229 1.12 matt mtsprg1 %r1 /* save SP */
230 1.13 matt GET_CPUINFO(%r1)
231 1.13 matt stmw %r28,CI_IPKDBSAVE(%r1) /* free r28-r31 */
232 1.12 matt mflr %r28 /* save LR */
233 1.12 matt mfcr %r29 /* save CR */
234 1.19 kiyohara mfsrr0 %r30
235 1.19 kiyohara mfsrr1 %r31
236 1.19 kiyohara stmw %r30,(CI_IPKDBSAVE+CPUSAVE_SRR0)(%r1) /* save srr0/srr1 */
237 1.13 matt lis %r1,ipkdbstk+INTSTK-CALLFRAMELEN@ha /* get new SP */
238 1.13 matt addi %r1,%r1,ipkdbstk+INTSTK-CALLFRAMELEN@l
239 1.1 simonb bla ipkdbtrap
240 1.1 simonb _C_LABEL(ipkdbsize) = .-_C_LABEL(ipkdblow)
241 1.1 simonb #endif /* IPKDB */
242 1.1 simonb
243 1.1 simonb #ifdef DEBUG
244 1.1 simonb #define TRAP_IF_ZERO(r) tweqi r,0
245 1.1 simonb #else
246 1.1 simonb #define TRAP_IF_ZERO(r)
247 1.1 simonb #endif
248 1.4 simonb
249 1.13 matt #define ENABLE_TRANSLATION(pidreg,tmpreg) \
250 1.13 matt mfpid pidreg; \
251 1.19 kiyohara li tmpreg,KERNEL_PID; \
252 1.13 matt mtpid tmpreg; \
253 1.13 matt mfmsr tmpreg; \
254 1.13 matt ori tmpreg,tmpreg,(PSL_DR|PSL_IR)@l; \
255 1.13 matt mtmsr tmpreg; \
256 1.13 matt isync
257 1.13 matt
258 1.1 simonb /*
259 1.1 simonb * FRAME_SETUP assumes:
260 1.12 matt * SPRG1 SP (r1)
261 1.13 matt * savearea r28-r31,DEAR,ESR,SRR0,SRR1 (DEAR & ESR only for DSI traps)
262 1.13 matt * %r28 LR
263 1.13 matt * %r29 CR
264 1.13 matt * %r1 kernel stack
265 1.1 simonb * LR trap type
266 1.1 simonb */
267 1.1 simonb #define FRAME_SETUP(savearea) \
268 1.1 simonb /* Have to enable translation to allow access of kernel stack: */ \
269 1.13 matt ENABLE_TRANSLATION(%r30,%r31); \
270 1.12 matt mfsprg1 %r31; \
271 1.12 matt stwu %r31,-FRAMELEN(%r1); \
272 1.13 matt stw %r30,FRAME_PID(%r1); \
273 1.13 matt stw %r0,FRAME_R0(%r1); \
274 1.13 matt stw %r31,FRAME_R1(%r1); \
275 1.13 matt stw %r2,FRAME_R2(%r1); \
276 1.13 matt GET_CPUINFO(%r2); \
277 1.13 matt stw %r28,FRAME_LR(%r1); \
278 1.13 matt stw %r29,FRAME_CR(%r1); \
279 1.13 matt lmw %r28,(savearea+CPUSAVE_R28)(%r2); \
280 1.13 matt stmw %r3,FRAME_R3(%r1); \
281 1.13 matt lmw %r28,(savearea+CPUSAVE_DEAR)(%r2); \
282 1.15 matt lwz %r13,CI_CURLWP(%r2); \
283 1.12 matt mfxer %r3; \
284 1.12 matt mfctr %r4; \
285 1.12 matt mflr %r5; \
286 1.12 matt andi. %r5,%r5,0xff00; \
287 1.13 matt stw %r3,FRAME_XER(%r1); \
288 1.13 matt stw %r4,FRAME_CTR(%r1); \
289 1.13 matt stw %r5,FRAME_EXC(%r1); \
290 1.13 matt stw %r28,FRAME_DEAR(%r1); \
291 1.13 matt stw %r29,FRAME_ESR(%r1); \
292 1.13 matt stw %r30,FRAME_SRR0(%r1); \
293 1.13 matt stw %r31,FRAME_SRR1(%r1)
294 1.13 matt
295 1.13 matt #define FRAME_SAVE_CALLEE \
296 1.19 kiyohara stmw %r14,FRAME_R14(%r1)
297 1.13 matt
298 1.13 matt #define FRAME_RESTORE \
299 1.13 matt lwz %r6,FRAME_LR(%r1); \
300 1.13 matt lwz %r7,FRAME_CR(%r1); \
301 1.13 matt lwz %r8,FRAME_XER(%r1); \
302 1.13 matt lwz %r9,FRAME_CTR(%r1); \
303 1.13 matt lwz %r10,FRAME_SRR0(%r1); \
304 1.13 matt lwz %r11,FRAME_SRR1(%r1); \
305 1.13 matt mtlr %r6; \
306 1.13 matt mtcr %r7; \
307 1.13 matt mtxer %r8; \
308 1.13 matt mtctr %r9; \
309 1.13 matt mtsrr0 %r10; \
310 1.13 matt mtsrr1 %r11; \
311 1.15 matt lwz %r13,FRAME_R13(%r1); \
312 1.13 matt lwz %r12,FRAME_R12(%r1); \
313 1.13 matt lwz %r11,FRAME_R11(%r1); \
314 1.13 matt lwz %r10,FRAME_R10(%r1); \
315 1.13 matt lwz %r9,FRAME_R9(%r1); \
316 1.13 matt lwz %r8,FRAME_R8(%r1); \
317 1.13 matt lwz %r7,FRAME_R7(%r1); \
318 1.13 matt lwz %r6,FRAME_R6(%r1); \
319 1.13 matt lwz %r5,FRAME_R5(%r1); \
320 1.13 matt lwz %r4,FRAME_R4(%r1); \
321 1.13 matt lwz %r3,FRAME_R3(%r1); \
322 1.13 matt lwz %r2,FRAME_R2(%r1); \
323 1.13 matt lwz %r0,FRAME_R1(%r1); \
324 1.13 matt mtsprg1 %r0; \
325 1.13 matt lwz %r0,FRAME_R0(%r1)
326 1.13 matt
327 1.1 simonb /*
328 1.1 simonb * Now the common trap catching code.
329 1.1 simonb */
330 1.1 simonb s_trap:
331 1.13 matt FRAME_SETUP(CI_TEMPSAVE)
332 1.13 matt /* R31 = SRR1 */
333 1.1 simonb /* Now we can recover interrupts again: */
334 1.1 simonb trapagain:
335 1.13 matt wrtee %r31 /* reenable interrupts */
336 1.1 simonb /* Call C trap code: */
337 1.13 matt addi %r3,%r1,FRAME_TF
338 1.1 simonb bl _C_LABEL(trap)
339 1.2 simonb .globl _C_LABEL(trapexit)
340 1.2 simonb _C_LABEL(trapexit):
341 1.1 simonb /* Disable interrupts: */
342 1.1 simonb wrteei 0
343 1.13 matt
344 1.1 simonb /* Test AST pending: */
345 1.13 matt mtcr %r31
346 1.15 matt bf MSR_PR,trapleave_to_kernel /* branch if MSR[PR] is false */
347 1.13 matt
348 1.15 matt lwz %r4,L_MD_ASTPENDING(%r13)
349 1.12 matt andi. %r4,%r4,1
350 1.13 matt beq trapleave_to_user
351 1.13 matt
352 1.12 matt li %r6,EXC_AST
353 1.13 matt stw %r6,FRAME_EXC(%r1)
354 1.1 simonb b trapagain
355 1.13 matt
356 1.13 matt trapleave_to_kernel:
357 1.15 matt lmw %r14, FRAME_R14(%r1) /* restore callee registers */
358 1.13 matt
359 1.13 matt intrleave_to_kernel:
360 1.13 matt FRAME_RESTORE /* old SP is now in sprg1 */
361 1.21 kiyohara
362 1.21 kiyohara mtsprg2 %r30
363 1.21 kiyohara mtsprg3 %r31
364 1.21 kiyohara mfmsr %r30
365 1.21 kiyohara li %r31,(PSL_DR|PSL_IR)@l
366 1.21 kiyohara andc %r30,%r30,%r31
367 1.21 kiyohara lwz %r31,FRAME_PID(%r1)
368 1.21 kiyohara TRAP_IF_ZERO(%r31)
369 1.13 matt /*
370 1.13 matt * Now that we are done with the trapframe, we can load the original SP
371 1.13 matt */
372 1.13 matt mfsprg1 %r1
373 1.21 kiyohara mtmsr %r30 /* disable translation */
374 1.21 kiyohara isync
375 1.21 kiyohara mtpid %r31
376 1.21 kiyohara mfsprg3 %r31
377 1.21 kiyohara mfsprg2 %r30
378 1.13 matt rfi
379 1.13 matt ba . /* Protect against prefetch */
380 1.13 matt
381 1.13 matt trapleave_to_user:
382 1.19 kiyohara lmw %r14, FRAME_R14(%r1) /* restore callee registers */
383 1.13 matt
384 1.13 matt intrleave_to_user:
385 1.13 matt /* Now restore regs: */
386 1.13 matt lwz %r3,FRAME_PID(%r1)
387 1.13 matt lwz %r4,FRAME_SRR1(%r1)
388 1.13 matt bl _C_LABEL(ctx_setup)
389 1.13 matt TRAP_IF_ZERO(%r3)
390 1.13 matt stw %r3,FRAME_PID(%r1)
391 1.13 matt
392 1.13 matt FRAME_RESTORE /* old SP is now in sprg1 */
393 1.13 matt
394 1.13 matt /*
395 1.13 matt * We are returning to userspace so we need to switch PIDs.
396 1.13 matt * Since the kernel executes out of what would be userspace,
397 1.13 matt * we need to turn off translation before we set the PID.
398 1.13 matt *
399 1.13 matt * Alterantively, we could map a kernel page at 0xfffff000
400 1.13 matt * that had the mtpid code in it and branch to it and avoid
401 1.13 matt * all this. (ba foo; foo: mtpid %r31; mfsprg3 %r31; rfi;)
402 1.13 matt */
403 1.20 kiyohara mtsprg2 %r30
404 1.20 kiyohara mtsprg3 %r31
405 1.13 matt mfmsr %r30
406 1.13 matt li %r31,(PSL_DR|PSL_IR)@l
407 1.13 matt andc %r30,%r30,%r31
408 1.13 matt lwz %r31,FRAME_PID(%r1)
409 1.13 matt TRAP_IF_ZERO(%r31)
410 1.13 matt /*
411 1.13 matt * Now that we are done with the trapframe, we can load the original SP
412 1.13 matt */
413 1.13 matt mfsprg1 %r1
414 1.13 matt mtmsr %r30 /* disable translation */
415 1.13 matt isync
416 1.13 matt mtpid %r31
417 1.13 matt mfsprg3 %r31
418 1.13 matt mfsprg2 %r30
419 1.1 simonb rfi
420 1.1 simonb ba . /* Protect against prefetch */
421 1.5 chs
422 1.5 chs
423 1.8 matt .globl _C_LABEL(sctrap),_C_LABEL(scsize),_C_LABEL(sctrapexit)
424 1.5 chs _C_LABEL(sctrap):
425 1.13 matt STANDARD_PROLOG(CI_TEMPSAVE)
426 1.5 chs bla s_sctrap
427 1.5 chs _C_LABEL(scsize) = .-_C_LABEL(sctrap)
428 1.5 chs
429 1.5 chs s_sctrap:
430 1.13 matt FRAME_SETUP(CI_TEMPSAVE)
431 1.5 chs /* Now we can recover interrupts again: */
432 1.5 chs wrteei 1 /* Enable interrupts */
433 1.5 chs /* Call the appropriate syscall handler: */
434 1.13 matt addi %r3,%r1,FRAME_TF
435 1.15 matt lwz %r4,L_PROC(%r13)
436 1.12 matt lwz %r4,P_MD_SYSCALL(%r4)
437 1.12 matt mtctr %r4
438 1.5 chs bctrl
439 1.8 matt _C_LABEL(sctrapexit):
440 1.13 matt b trapexit
441 1.5 chs
442 1.1 simonb /*
443 1.1 simonb * External interrupt second level handler
444 1.1 simonb */
445 1.4 simonb
446 1.13 matt #define INTR_SAVE(tempsave) \
447 1.1 simonb /* Save non-volatile registers: */ \
448 1.13 matt stwu %r1,-FRAMELEN(%r1); /* temporarily */ \
449 1.13 matt stw %r0,FRAME_R0(%r1); \
450 1.12 matt mfsprg1 %r0; /* get original SP */ \
451 1.13 matt stw %r0,FRAME_R1(%r1); /* and store it */ \
452 1.13 matt stw %r2,FRAME_R2(%r1); \
453 1.13 matt stw %r3,FRAME_R3(%r1); \
454 1.13 matt stw %r4,FRAME_R4(%r1); \
455 1.13 matt stw %r5,FRAME_R5(%r1); \
456 1.13 matt stw %r6,FRAME_R6(%r1); \
457 1.13 matt stw %r7,FRAME_R7(%r1); \
458 1.13 matt stw %r8,FRAME_R8(%r1); \
459 1.13 matt stw %r9,FRAME_R9(%r1); \
460 1.13 matt stw %r10,FRAME_R10(%r1); \
461 1.13 matt stw %r11,FRAME_R11(%r1); \
462 1.13 matt stw %r12,FRAME_R12(%r1); \
463 1.16 cliff stw %r13,FRAME_R13(%r1); \
464 1.13 matt mfctr %r31; \
465 1.13 matt stmw %r28,FRAME_LR(%r1); /* save LR, CR, XER, CTR */ \
466 1.12 matt GET_CPUINFO(%r5); \
467 1.13 matt lmw %r28,(tempsave+CPUSAVE_R28)(%r5); /* restore r28-r31 */ \
468 1.15 matt lwz %r13,CI_CURLWP(%r5); \
469 1.13 matt lwz %r5,CI_IDEPTH(%r5); \
470 1.12 matt mfsrr0 %r4; \
471 1.12 matt mfsrr1 %r3; \
472 1.13 matt stw %r5,FRAME_IDEPTH(%r1); \
473 1.13 matt stw %r4,FRAME_SRR0(%r1); \
474 1.13 matt stw %r3,FRAME_SRR1(%r1); \
475 1.1 simonb /* interrupts are recoverable here, and enable translation */ \
476 1.13 matt ENABLE_TRANSLATION(%r0,%r5); \
477 1.19 kiyohara stw %r0,FRAME_PID(%r1);
478 1.1 simonb
479 1.1 simonb .globl _C_LABEL(extint_call)
480 1.1 simonb extintr:
481 1.13 matt INTR_SAVE(CI_TEMPSAVE)
482 1.1 simonb _C_LABEL(extint_call):
483 1.1 simonb bl _C_LABEL(extint_call) /* to be filled in later */
484 1.1 simonb
485 1.1 simonb intr_exit:
486 1.13 matt /* Disable interrupts */
487 1.1 simonb wrteei 0
488 1.1 simonb isync
489 1.13 matt GET_CPUINFO(%r5)
490 1.13 matt lwz %r4,CI_IDEPTH(%r5)
491 1.13 matt addi %r4,%r4,-1 /* adjust reentrancy count */
492 1.13 matt stw %r4,CI_IDEPTH(%r5)
493 1.4 simonb
494 1.15 matt lwz %r4,FRAME_SRR1(%r1)
495 1.1 simonb /* Returning to user mode? */
496 1.15 matt mtcr %r4 /* saved SRR1 */
497 1.15 matt bf MSR_PR,intrleave_to_kernel /* branch if MSR[PR] is false */
498 1.13 matt
499 1.15 matt lwz %r4,L_MD_ASTPENDING(%r13)/* Test AST pending */
500 1.13 matt andi. %r4,%r4,1
501 1.13 matt beq intrleave_to_user
502 1.13 matt
503 1.13 matt FRAME_SAVE_CALLEE /* save rest of callee registers */
504 1.12 matt li %r6,EXC_AST
505 1.13 matt stw %r6,FRAME_EXC(%r1)
506 1.13 matt mr %r31,%r5 /* move SRR1 to R31 */
507 1.13 matt b trapagain
508 1.4 simonb
509 1.1 simonb /*
510 1.1 simonb * PIT interrupt handler.
511 1.1 simonb */
512 1.1 simonb .align 5
513 1.1 simonb _C_LABEL(pitint):
514 1.13 matt INTR_PROLOG(CI_TEMPSAVE)
515 1.13 matt INTR_SAVE(CI_TEMPSAVE)
516 1.16 cliff addi %r3,%r1,FRAME_CF /* clock frame */
517 1.1 simonb bl _C_LABEL(decr_intr)
518 1.1 simonb b intr_exit
519 1.1 simonb
520 1.1 simonb /*
521 1.1 simonb * FIT interrupt handler.
522 1.1 simonb */
523 1.1 simonb .align 5
524 1.13 matt _C_LABEL(fitint):
525 1.13 matt INTR_PROLOG(CI_TEMPSAVE)
526 1.13 matt INTR_SAVE(CI_TEMPSAVE)
527 1.16 cliff addi %r3,%r1,FRAME_CF /* clock frame */
528 1.1 simonb bl _C_LABEL(stat_intr)
529 1.1 simonb b intr_exit
530 1.1 simonb
531 1.11 garbled #if defined(DDB) || defined(KGDB)
532 1.1 simonb /*
533 1.1 simonb * Deliberate entry to ddbtrap
534 1.1 simonb */
535 1.1 simonb .globl _C_LABEL(ddb_trap)
536 1.1 simonb _C_LABEL(ddb_trap):
537 1.12 matt mtsprg1 %r1
538 1.13 matt GET_CPUINFO(%r4)
539 1.12 matt mfmsr %r3
540 1.18 kiyohara stw %r3,(CI_DDBSAVE+CPUSAVE_SRR1)(%r4)
541 1.1 simonb wrteei 0 /* disable interrupts */
542 1.1 simonb isync
543 1.17 kiyohara stmw %r28,CI_DDBSAVE(%r4)
544 1.12 matt mflr %r28
545 1.18 kiyohara stw %r28,(CI_DDBSAVE+CPUSAVE_SRR0)(%r4)
546 1.12 matt li %r29,EXC_BPT
547 1.12 matt mtlr %r29
548 1.12 matt mfcr %r29
549 1.1 simonb
550 1.1 simonb /*
551 1.11 garbled * Now the ddb/kgdb trap catching code.
552 1.1 simonb */
553 1.1 simonb ddbtrap:
554 1.13 matt FRAME_SETUP(CI_DDBSAVE)
555 1.1 simonb /* Call C trap code: */
556 1.13 matt addi %r3,%r1,FRAME_TF
557 1.1 simonb bl _C_LABEL(ddb_trap_glue)
558 1.12 matt or. %r3,%r3,%r3
559 1.13 matt beq trapagain
560 1.13 matt b trapexit
561 1.11 garbled #endif /* DDB || KGDB */
562 1.1 simonb
563 1.1 simonb #ifdef IPKDB
564 1.1 simonb /*
565 1.1 simonb * Deliberate entry to ipkdbtrap
566 1.1 simonb */
567 1.1 simonb .globl _C_LABEL(ipkdb_trap)
568 1.1 simonb _C_LABEL(ipkdb_trap):
569 1.12 matt mtsprg1 %r1
570 1.13 matt GET_CPUINFO(%r4)
571 1.12 matt mfmsr %r3
572 1.13 matt stw %r3,(CI_IPKDBSAVE+CPUSAVE_SRR1)(%r4)
573 1.1 simonb wrteei 0 /* disable interrupts */
574 1.1 simonb isync
575 1.13 matt stmw %r28,CI_IPKDBSAVE(%r4)
576 1.12 matt mflr %r28
577 1.13 matt stw %r28,(CI_IPKDBSAVE+CPUSAVE_SRR0)(%r4)
578 1.12 matt li %r29,EXC_BPT
579 1.12 matt mtlr %r29
580 1.12 matt mfcr %r29
581 1.1 simonb
582 1.1 simonb /*
583 1.1 simonb * Now the ipkdb trap catching code.
584 1.1 simonb */
585 1.1 simonb ipkdbtrap:
586 1.13 matt FRAME_SETUP(CI_IPKDBSAVE)
587 1.1 simonb /* Call C trap code: */
588 1.13 matt addi %r3,%r1,FRAME_TF
589 1.1 simonb bl _C_LABEL(ipkdb_trap_glue)
590 1.12 matt or. %r3,%r3,%r3
591 1.13 matt beq trapagain
592 1.13 matt b trapexit
593 1.1 simonb
594 1.1 simonb ipkdbfault:
595 1.1 simonb ba _ipkdbfault
596 1.1 simonb _ipkdbfault:
597 1.12 matt mfsrr0 %r3
598 1.12 matt addi %r3,%r3,4
599 1.12 matt mtsrr0 %r3
600 1.12 matt li %r3,-1
601 1.1 simonb rfi
602 1.1 simonb ba . /* Protect against prefetch */
603 1.1 simonb
604 1.1 simonb /*
605 1.1 simonb * int ipkdbfbyte(unsigned char *p)
606 1.1 simonb */
607 1.1 simonb .globl _C_LABEL(ipkdbfbyte)
608 1.1 simonb _C_LABEL(ipkdbfbyte):
609 1.12 matt li %r9,EXC_DSI /* establish new fault routine */
610 1.12 matt lwz %r5,0(%r9)
611 1.12 matt lis %r6,ipkdbfault@ha
612 1.12 matt lwz %r6,ipkdbfault@l(%r6)
613 1.12 matt stw %r6,0(%r9)
614 1.1 simonb #ifdef IPKDBUSERHACK
615 1.1 simonb #ifndef PPC_IBM4XX
616 1.12 matt lis %r8,_C_LABEL(ipkdbsr)@ha
617 1.12 matt lwz %r8,_C_LABEL(ipkdbsr)@l(%r8)
618 1.12 matt mtsr USER_SR,%r8
619 1.1 simonb isync
620 1.4 simonb #endif
621 1.1 simonb #endif
622 1.12 matt dcbst %r0,%r9 /* flush data... */
623 1.1 simonb sync
624 1.12 matt icbi %r0,%r9 /* and instruction caches */
625 1.12 matt lbz %r3,0(%r3) /* fetch data */
626 1.12 matt stw %r5,0(%r9) /* restore previous fault handler */
627 1.12 matt dcbst %r0,%r9 /* and flush data... */
628 1.1 simonb sync
629 1.12 matt icbi %r0,%r9 /* and instruction caches */
630 1.1 simonb blr
631 1.1 simonb
632 1.1 simonb /*
633 1.1 simonb * int ipkdbsbyte(unsigned char *p, int c)
634 1.1 simonb */
635 1.1 simonb .globl _C_LABEL(ipkdbsbyte)
636 1.1 simonb _C_LABEL(ipkdbsbyte):
637 1.12 matt li %r9,EXC_DSI /* establish new fault routine */
638 1.12 matt lwz %r5,0(%r9)
639 1.12 matt lis %r6,ipkdbfault@ha
640 1.12 matt lwz %r6,ipkdbfault@l(%r6)
641 1.12 matt stw %r6,0(%r9)
642 1.1 simonb #ifdef IPKDBUSERHACK
643 1.1 simonb #ifndef PPC_IBM4XX
644 1.12 matt lis %r8,_C_LABEL(ipkdbsr)@ha
645 1.12 matt lwz %r8,_C_LABEL(ipkdbsr)@l(%r8)
646 1.12 matt mtsr USER_SR,%r8
647 1.1 simonb isync
648 1.4 simonb #endif
649 1.1 simonb #endif
650 1.12 matt dcbst %r0,%r9 /* flush data... */
651 1.1 simonb sync
652 1.12 matt icbi %r0,%r9 /* and instruction caches */
653 1.12 matt mr %r6,%r3
654 1.12 matt xor %r3,%r3,%r3
655 1.12 matt stb %r4,0(%r6)
656 1.12 matt dcbst %r0,%r6 /* Now do appropriate flushes
657 1.1 simonb to data... */
658 1.1 simonb sync
659 1.12 matt icbi %r0,%r6 /* and instruction caches */
660 1.12 matt stw %r5,0(%r9) /* restore previous fault handler */
661 1.12 matt dcbst %r0,%r9 /* and flush data... */
662 1.1 simonb sync
663 1.12 matt icbi %r0,%r9 /* and instruction caches */
664 1.1 simonb blr
665 1.1 simonb #endif /* IPKDB */
666