cpuvar.h revision 1.6
1 /* $NetBSD: cpuvar.h,v 1.6 2011/06/05 16:52:25 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _POWERPC_BOOKE_CPUVAR_H_ 38 #define _POWERPC_BOOKE_CPUVAR_H_ 39 40 #include <machine/bus.h> 41 #include <prop/proplib.h> 42 43 struct cpunode_softc { 44 device_t sc_dev; 45 u_int sc_children; 46 }; 47 48 struct cpu_softc { 49 struct cpu_info *cpu_ci; 50 struct evcnt *cpu_evcnt_intrs; 51 bus_space_tag_t cpu_bst; 52 bus_space_tag_t cpu_le_bst; 53 bus_space_handle_t cpu_bsh; 54 bus_addr_t cpu_clock_gtbcr; 55 56 paddr_t cpu_highmem; 57 58 u_int cpu_pcpls[5]; 59 struct evcnt cpu_evcnt_spurious_intr; 60 struct lwp *cpu_softlwps[SOFTINT_COUNT]; 61 62 struct evcnt cpu_ev_late_clock; 63 u_long cpu_ticks_per_clock_intr; 64 struct evcnt cpu_ev_exec_trap_sync; 65 }; 66 67 struct cpunode_locators { 68 const char *cnl_name; 69 bus_addr_t cnl_addr; 70 bus_size_t cnl_size; 71 uint8_t cnl_instance; 72 uint8_t cnl_nintr; 73 uint8_t cnl_intrs[4]; 74 uint32_t cnl_flags; 75 uint16_t cnl_ids[6]; 76 }; 77 78 struct cpunode_attach_args { 79 const char *cna_busname; 80 bus_space_tag_t cna_memt; 81 bus_space_tag_t cna_le_memt; 82 bus_dma_tag_t cna_dmat; 83 struct cpunode_locators cna_locs; 84 u_int cna_childmask; 85 }; 86 87 struct mainbus_attach_args { 88 const char *ma_name; 89 bus_space_tag_t ma_memt; 90 bus_space_tag_t ma_le_memt; 91 bus_dma_tag_t ma_dmat; 92 int ma_node; 93 }; 94 95 struct generic_attach_args { 96 const char *ga_name; 97 bus_space_tag_t ga_bst; 98 bus_dma_tag_t ga_dmat; 99 bus_addr_t ga_addr; 100 bus_size_t ga_size; 101 int ga_cs; 102 int ga_irq; 103 }; 104 105 struct tlbmask; 106 107 struct tlb_md_ops { 108 /* 109 * We need mapiodev to be first so we can easily override it in 110 * early boot by doing cpu_md_ops.tlb_md_ops = (const struct 111 * tlb_md_ops *) &<variable containing mapiodev pointer>. 112 */ 113 void *(*md_tlb_mapiodev)(paddr_t, psize_t); 114 void (*md_tlb_unmapiodev)(vaddr_t, vsize_t); 115 void (*md_tlb_set_asid)(uint32_t); 116 uint32_t (*md_tlb_get_asid)(void); 117 void (*md_tlb_invalidate_all)(void); 118 void (*md_tlb_invalidate_globals)(void); 119 void (*md_tlb_invalidate_asids)(uint32_t, uint32_t); 120 void (*md_tlb_invalidate_addr)(vaddr_t, uint32_t); 121 bool (*md_tlb_update_addr)(vaddr_t, uint32_t, uint32_t, bool); 122 void (*md_tlb_read_entry)(size_t, struct tlbmask *); 123 u_int (*md_tlb_record_asids)(u_long *, uint32_t); 124 int (*md_tlb_ioreserve)(vaddr_t, vsize_t, uint32_t); 125 int (*md_tlb_iorelease)(vaddr_t); 126 void (*md_tlb_dump)(void (*)(const char *, ...)); 127 void (*md_tlb_walk)(void *, bool (*)(void *, vaddr_t, uint32_t, 128 uint32_t)); 129 }; 130 131 struct cpu_md_ops { 132 const struct cpunode_locators *md_cpunode_locs; 133 void (*md_cpu_attach)(device_t, u_int); 134 135 void (*md_device_register)(device_t, void *); 136 void (*md_cpu_startup)(void); 137 void (*md_cpu_reset)(void); 138 void (*md_cpunode_attach)(device_t, device_t, void *); 139 140 const struct tlb_md_ops *md_tlb_ops; 141 }; 142 143 144 #ifdef _KERNEL 145 146 static inline register_t 147 wrtee(register_t msr) 148 { 149 register_t old_msr; 150 __asm("mfmsr\t%0" : "=r"(old_msr)); 151 152 if (__builtin_constant_p(msr)) { 153 __asm __volatile("wrteei\t%0" :: "n"((msr & PSL_EE) ? 1 : 0)); 154 } else { 155 __asm __volatile("wrtee\t%0" :: "r"(msr)); 156 } 157 return old_msr; 158 } 159 160 uint32_t ufetch_32(const void *); 161 162 struct trapframe; 163 void booke_sstep(struct trapframe *); 164 165 void booke_fixup_stubs(void); 166 void booke_cpu_startup(const char *); /* model name */ 167 struct powerpc_bus_dma_tag booke_bus_dma_tag; 168 169 extern struct cpu_info cpu_info[]; 170 171 void cpu_evcnt_attach(struct cpu_info *); 172 uint32_t cpu_read_4(bus_size_t); 173 uint8_t cpu_read_1(bus_size_t); 174 void cpu_write_4(bus_size_t, uint32_t); 175 void cpu_write_1(bus_size_t, uint8_t); 176 177 void calc_delayconst(void); 178 179 struct intrsw; 180 void exception_init(const struct intrsw *); 181 182 uint32_t tlb_get_asid(void); 183 void tlb_set_asid(uint32_t); 184 void tlb_invalidate_all(void); 185 void tlb_invalidate_globals(void); 186 void tlb_invalidate_asids(uint32_t, uint32_t); 187 void tlb_invalidate_addr(vaddr_t, uint32_t); 188 bool tlb_update_addr(vaddr_t, uint32_t, uint32_t, bool); 189 u_int tlb_record_asids(u_long *, uint32_t); 190 void tlb_enter_addr(size_t, const struct tlbmask *); 191 void tlb_read_entry(size_t, struct tlbmask *); 192 void *tlb_mapiodev(paddr_t, psize_t); 193 void tlb_unmapiodev(vaddr_t, vsize_t); 194 int tlb_ioreserve(vaddr_t, vsize_t, uint32_t); 195 int tlb_iorelease(vaddr_t); 196 void tlb_dump(void (*)(const char *, ...)); 197 void tlb_walk(void *, bool (*)(void *, vaddr_t, uint32_t, uint32_t)); 198 199 extern struct cpu_md_ops cpu_md_ops; 200 201 void board_info_init(void); 202 void board_info_add_number(const char *, uint64_t); 203 void board_info_add_data(const char *, const void *, size_t); 204 void board_info_add_string(const char *, const char *); 205 void board_info_add_bool(const char *); 206 void board_info_add_object(const char *, void *); 207 uint64_t board_info_get_number(const char *); 208 bool board_info_get_bool(const char *); 209 void *board_info_get_object(const char *); 210 const void * 211 board_info_get_data(const char *, size_t *); 212 213 extern paddr_t msgbuf_paddr; 214 extern prop_dictionary_t board_properties; 215 extern psize_t pmemsize; 216 #endif 217 218 #endif /* !_POWERPC_BOOKE_CPUVAR_H_ */ 219
Indexes created Tue Oct 14 08:09:56 GMT 2025